From patchwork Mon Dec 13 12:09:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 48865 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8218D385841C for ; Mon, 13 Dec 2021 12:09:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 887FD385840C for ; Mon, 13 Dec 2021 12:09:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 887FD385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=kymjEMLE6zh6rNvbNb7XmwIVxbFy6z9uJwLHLgx3pqc=; b=TDD5rIP2W/ULO7fq+845JQhv+N 8pIhwnRKDmHZLS5rs0kWBYm4S6hIJrDrhk8Q9w58jpOZbrDKhc0AI6N+fE9RTc5KWXSmMnxIGuYm+ 5L+TwuAc5ZWvUBJYYH5gzgSGDlljYo8X1K1ipXXME9RHHf0Oyl8F7YNSIwSCSPPuWMquRLRaGIO1d 0gg375LssQtAf34ibWXyze/mtwTWk/Z+uD+JNxwZFH8f3OOPBtJzBQy1LsdzLTP2ozXbPsk6Eh655 6cmWc+juW3CfshYiWc+J4UvIJDnQHBaTcFjwdcFQg00WT8CPqP/QUUmf7HcuuQPSRaCE5STqN8WM0 2B6zfCsg==; Received: from host86-160-23-130.range86-160.btcentralplus.com ([86.160.23.130]:54478 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mwk8f-0005Qi-TD; Mon, 13 Dec 2021 07:09:06 -0500 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH] PR target/103611: Avoid generating orb $0, %ah on x86. Date: Mon, 13 Dec 2021 12:09:04 -0000 Message-ID: <006d01d7f01a$39d204c0$ad760e40$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Content-Language: en-gb Thread-Index: AdfwGW4dGxvTlqvnQrqgLJNQBO2WQg== X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" I'll post my proposed fix for PR target/103611 shortly, but this patch fixes another missed optimization opportunity revealed by that PR. Occasionally, reload materializes integer constants during register allocation sometimes resulting in unnecessary instructions such as: (insn 23 31 24 2 (parallel [ (set (reg:SI 0 ax [99]) (ior:SI (reg:SI 0 ax [99]) (const_int 0 [0]))) (clobber (reg:CC 17 flags)) ]) "pr103611.c":18:73 550 {*iorsi_1} (nil)) These then get "optimized" during the split2 pass, which realizes that no bits outside of 0xff00 are set, so this operation can be implemented by operating on just the highpart of a QIreg_operand, i.e. %ah, %bh, %ch etc., which leads to the useless "orb $0, %ah" seen in the reported PR. This fix catches the case of const0_rtx in relevant splitter, either eliminating the instruction or turning it into a simple move. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without "--target_board='unix{-m32}'" with no new failures. OK for mainline? 2021-12-13 Roger Sayle gcc/ChangeLog * config/i386/i386.md (define_split any_or:SWI248 -> orb %?h): Optimize the case where the integer constant operand is zero. gcc/testsuite/ChangeLog * gcc.target/i386/pr103611-1.c: New test case. Thanks in advance, Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9d7d116..f6d9c4b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10542,6 +10542,15 @@ (match_dup 2)) 0)) (clobber (reg:CC FLAGS_REG))])] { + /* Handle the case where INTVAL (operands[2]) == 0. */ + if (operands[2] == const0_rtx) + { + if (!rtx_equal_p (operands[0], operands[1])) + emit_move_insn (operands[0], operands[1]); + else + emit_note (NOTE_INSN_DELETED); + DONE; + } operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_int_mode (INTVAL (operands[2]) >> 8, QImode); diff --git a/gcc/testsuite/gcc.target/i386/pr103611-1.c b/gcc/testsuite/gcc.target/i386/pr103611-1.c new file mode 100644 index 0000000..1fae91d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103611-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-m32 -O2 -msse4" } */ +typedef int __v4si __attribute__ ((__vector_size__ (16))); + +long long ior_1(__v4si v) { + unsigned int loVal = (unsigned int)v[0]; + unsigned int hiVal = (unsigned int)v[1]; + return (long long)(loVal) | ((long long)(hiVal) << 32); +} + +long long ior_2(__v4si v) { + unsigned int loVal = (unsigned int)v[2]; + unsigned int hiVal = (unsigned int)v[3]; + return (long long)(loVal) | ((long long)(hiVal) << 32); +} + +long long xor_1(__v4si v) { + unsigned int loVal = (unsigned int)v[0]; + unsigned int hiVal = (unsigned int)v[1]; + return (long long)(loVal) ^ ((long long)(hiVal) << 32); +} + +long long xor_2(__v4si v) { + unsigned int loVal = (unsigned int)v[2]; + unsigned int hiVal = (unsigned int)v[3]; + return (long long)(loVal) ^ ((long long)(hiVal) << 32); +} +/* { dg-final { scan-assembler-not "\torb\t\\\$0," } } */ +/* { dg-final { scan-assembler-not "\txorb\t\\\$0," } } */ +