From patchwork Fri Dec 10 11:58:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 48774 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3BB4C385780A for ; Fri, 10 Dec 2021 11:58:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id B44F53858D35 for ; Fri, 10 Dec 2021 11:58:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B44F53858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=UPCxJHIms8TR9CrdWaoeSJtZ2wjLwFoYtYPgUrA4gP0=; b=c57K/py0HCzhC0pwdm6UZX6zhy 2s8h77sJsO7hf4ggvsqkkZxOHXxIjCOoCFq75am6j7ys9KpcWgYX2XqGTdJn/UD/cihT7s9DANmGZ 27MR3zVFDC7WmZYZ/FpjTJ8LipXlvULelpcAAR6r/qURE3pkLOauOI5v+Jtw1/4z2RIl3vgZSb3HF 186+O4kYQoiG1n6+TpGp0VL55KBtXYitGWMz/btYIdiYvasTc1HzIiOqMFEOj2OvuCCMJSRQ8DHnT W6SXRwIzSjTQp9iFD//jdR9/PIZEWne0JYfCDtyBq6CmaFKLKN/R7w8n0IJWI3LAWdiM5179KoBjp zqButtCA==; Received: from [185.62.158.67] (port=60077 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mveXu-0005za-7m; Fri, 10 Dec 2021 06:58:38 -0500 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH] x86_64: Improve code expanded for highpart multiplications. Date: Fri, 10 Dec 2021 11:58:37 -0000 Message-ID: <004d01d7edbd$4471a7a0$cd54f6e0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdftvFAW5WxDQj5aQjmlc0kI2ir7Gg== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" While working on a middle-end patch to more aggressively use highpart multiplications on targets that support them, I noticed that the RTL expanded by the x86 backend interacts poorly with register allocation leading to suboptimal code. For the testcase, typedef int __attribute ((mode(TI))) ti_t; long foo(long x) { return ((ti_t)x * 19065) >> 64; } we'd like to avoid: foo: movq %rdi, %rax movl $19065, %edx imulq %rdx movq %rdx, %rax ret and would prefer: foo: movl $19065, %eax imulq %rdi movq %rdx, %rax ret This patch provides a pair of peephole2 transformations to tweak the spills generated by reload, and at the same time replaces the current define_expand with define_insn patterns using the new [su]mul_highpart RTX codes. I've left the old-style patterns in the machine description for the time being, but plan to remove these once my planned middle-end improvements make them obsolete. This patch has been tested on x86_64-pc-linux-gnu (both with and without the middle-end changes) by make bootstrap and make -k check with no new failures. The new test case, which currently passes, ensures that the code we generate isn't adversely affected by changes outside the backend. Ok for mainline? 2021-12-10 Roger Sayle gcc/ChangeLog * config/i386/i386.md (any_mul_highpart): New code iterator. (sgnprefix, s): Add attribute support for [su]mul_highpart. (mul3_highpart): Delete expander. (muldi3_highpart, mulsi3_highpart, mulsi32_highpart_zext): New define_insn patterns. (define_peephole2): Tweak the register allocation for the above instructions after reload. gcc/testsuite/ChangeLog * gcc.target/i386/smuldi3_highpart.c: New test case. Thanks in advance, Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 4e9fae8..fc79146 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -992,11 +992,16 @@ ;; Mapping of extend operators (define_code_iterator any_extend [sign_extend zero_extend]) +;; Mapping of highpart multiply operators +(define_code_iterator any_mul_highpart [smul_highpart umul_highpart]) + ;; Prefix for insn menmonic. (define_code_attr sgnprefix [(sign_extend "i") (zero_extend "") + (smul_highpart "i") (umul_highpart "") (div "i") (udiv "")]) ;; Prefix for define_insn -(define_code_attr s [(sign_extend "s") (zero_extend "u")]) +(define_code_attr s [(sign_extend "s") (zero_extend "u") + (smul_highpart "s") (umul_highpart "u")]) (define_code_attr u [(sign_extend "") (zero_extend "u") (div "") (udiv "u")]) (define_code_attr u_bool [(sign_extend "false") (zero_extend "true") @@ -8426,20 +8431,64 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "QI")]) -(define_expand "mul3_highpart" - [(parallel [(set (match_operand:DWIH 0 "register_operand") - (truncate:DWIH - (lshiftrt: - (mult: - (any_extend: - (match_operand:DWIH 1 "nonimmediate_operand")) - (any_extend: - (match_operand:DWIH 2 "register_operand"))) - (match_dup 3)))) - (clobber (scratch:DWIH)) - (clobber (reg:CC FLAGS_REG))])] +;; Highpart multiplication patterns +(define_insn "muldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=d") + (any_mul_highpart:DI + (match_operand:DI 1 "register_operand" "%a") + (match_operand:DI 2 "nonimmediate_operand" "rm"))) + (clobber (match_scratch:DI 3 "=1")) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT" + "mul{q}\t%2" + [(set_attr "type" "imul") + (set_attr "length_immediate" "0") + (set (attr "athlon_decode") + (if_then_else (eq_attr "cpu" "athlon") + (const_string "vector") + (const_string "double"))) + (set_attr "amdfam10_decode" "double") + (set_attr "bdver1_decode" "direct") + (set_attr "mode" "DI")]) + +(define_insn "*mulsi3_highpart_zext" + [(set (match_operand:DI 0 "register_operand" "=d") + (zero_extend:DI + (any_mul_highpart:SI + (match_operand:SI 1 "register_operand" "%a") + (match_operand:SI 2 "nonimmediate_operand" "rm")))) + (clobber (match_scratch:SI 3 "=1")) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT" + "mul{l}\t%2" + [(set_attr "type" "imul") + (set_attr "length_immediate" "0") + (set (attr "athlon_decode") + (if_then_else (eq_attr "cpu" "athlon") + (const_string "vector") + (const_string "double"))) + (set_attr "amdfam10_decode" "double") + (set_attr "bdver1_decode" "direct") + (set_attr "mode" "SI")]) + +(define_insn "*mulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (any_mul_highpart:SI + (match_operand:SI 1 "register_operand" "%a") + (match_operand:SI 2 "nonimmediate_operand" "rm"))) + (clobber (match_scratch:SI 3 "=1")) + (clobber (reg:CC FLAGS_REG))] "" - "operands[3] = GEN_INT (GET_MODE_BITSIZE (mode));") + "mul{l}\t%2" + [(set_attr "type" "imul") + (set_attr "length_immediate" "0") + (set (attr "athlon_decode") + (if_then_else (eq_attr "cpu" "athlon") + (const_string "vector") + (const_string "double"))) + (set_attr "amdfam10_decode" "double") + (set_attr "bdver1_decode" "direct") + (set_attr "mode" "SI")]) (define_insn "*muldi3_highpart_1" [(set (match_operand:DI 0 "register_operand" "=d") @@ -8460,8 +8509,8 @@ (set_attr "length_immediate" "0") (set (attr "athlon_decode") (if_then_else (eq_attr "cpu" "athlon") - (const_string "vector") - (const_string "double"))) + (const_string "vector") + (const_string "double"))) (set_attr "amdfam10_decode" "double") (set_attr "bdver1_decode" "direct") (set_attr "mode" "DI")]) @@ -8484,8 +8533,8 @@ (set_attr "length_immediate" "0") (set (attr "athlon_decode") (if_then_else (eq_attr "cpu" "athlon") - (const_string "vector") - (const_string "double"))) + (const_string "vector") + (const_string "double"))) (set_attr "amdfam10_decode" "double") (set_attr "bdver1_decode" "direct") (set_attr "mode" "SI")]) @@ -8508,12 +8557,54 @@ (set_attr "length_immediate" "0") (set (attr "athlon_decode") (if_then_else (eq_attr "cpu" "athlon") - (const_string "vector") - (const_string "double"))) + (const_string "vector") + (const_string "double"))) (set_attr "amdfam10_decode" "double") (set_attr "bdver1_decode" "direct") (set_attr "mode" "SI")]) +;; Highpart multiplication peephole2s to tweak register allocation. +;; mov %rdx,imm; mov %rax,%rdi; imulq %rdx -> mov %rax,imm; imulq %rdi +(define_peephole2 + [(set (match_operand:SWI48 0 "general_reg_operand") + (match_operand:SWI48 1 "immediate_operand")) + (set (match_operand:SWI48 2 "general_reg_operand") + (match_operand:SWI48 3 "general_reg_operand")) + (parallel [(set (match_operand:SWI48 4 "general_reg_operand") + (any_mul_highpart:SWI48 (match_dup 2) (match_dup 0))) + (clobber (match_dup 2)) + (clobber (reg:CC FLAGS_REG))])] + "REGNO (operands[0]) != REGNO (operands[2]) + && REGNO (operands[0]) != REGNO (operands[3]) + && (REGNO (operands[0]) == REGNO (operands[4]) + || peep2_reg_dead_p (3, operands[0]))" + [(set (match_dup 2) (match_dup 1)) + (parallel [(set (match_dup 4) + (any_mul_highpart:SWI48 (match_dup 2) (match_dup 3))) + (clobber (match_dup 2)) + (clobber (reg:CC FLAGS_REG))])]) + +(define_peephole2 + [(set (match_operand:SI 0 "general_reg_operand") + (match_operand:SI 1 "immediate_operand")) + (set (match_operand:SI 2 "general_reg_operand") + (match_operand:SI 3 "general_reg_operand")) + (parallel [(set (match_operand:DI 4 "general_reg_operand") + (zero_extend:DI + (any_mul_highpart:SI (match_dup 2) (match_dup 0)))) + (clobber (match_dup 2)) + (clobber (reg:CC FLAGS_REG))])] + "REGNO (operands[0]) != REGNO (operands[2]) + && REGNO (operands[0]) != REGNO (operands[3]) + && (REGNO (operands[0]) == REGNO (operands[4]) + || peep2_reg_dead_p (3, operands[0]))" + [(set (match_dup 2) (match_dup 1)) + (parallel [(set (match_dup 4) + (zero_extend:DI + (any_mul_highpart:SI (match_dup 2) (match_dup 3)))) + (clobber (match_dup 2)) + (clobber (reg:CC FLAGS_REG))])]) + ;; The patterns that match these are at the end of this file. (define_expand "mulxf3" diff --git a/gcc/testsuite/gcc.target/i386/smuldi3_highpart.c b/gcc/testsuite/gcc.target/i386/smuldi3_highpart.c new file mode 100644 index 0000000..8bbd5f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/smuldi3_highpart.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2" } */ +typedef int __attribute ((mode(TI))) ti_t; + +long foo(long x) +{ + return ((ti_t)x * 19065) >> 72; +} + +/* { dg-final { scan-assembler "movl\[ \\t]+\\\$19065, %eax" } } */ +/* { dg-final { scan-assembler-times "movq" 1 } } */