From patchwork Tue Dec 7 02:09:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 48568 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D047D3858D28 for ; Tue, 7 Dec 2021 02:10:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D047D3858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1638843030; bh=rbouMEQ2qg6vfJfTj5amVFruqHzy117HxkXkDLIw1i0=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=mOqv3eUi7euhWQKmgF+LQ2Vqx09BdmXzllJ2h09KgHlrMDAhlnCwAbyFOow+y+Aq3 usXdWBN+5Bf7jzA8gI/iYdkSFaoNXJoxOsJ3geaYZxb52/FHFx3wJsnyXH2qWSRrpE V0YdArGOfjOFD4Y2jobkGL4QUF7ek/zcA6w8ZamQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 1BC7E3858D28 for ; Tue, 7 Dec 2021 02:10:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1BC7E3858D28 X-IronPort-AV: E=McAfee;i="6200,9189,10190"; a="234977153" X-IronPort-AV: E=Sophos;i="5.87,293,1631602800"; d="scan'208";a="234977153" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2021 18:09:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,293,1631602800"; d="scan'208";a="515235418" Received: from scymds02.sc.intel.com ([10.82.73.244]) by fmsmga007.fm.intel.com with ESMTP; 06 Dec 2021 18:09:59 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds02.sc.intel.com with ESMTP id 1B729vZt017626; Mon, 6 Dec 2021 18:09:58 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386]Add combine splitter to transform vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0 Date: Tue, 7 Dec 2021 10:09:57 +0800 Message-Id: <20211207020957.93540-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: hongtao.liu@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds combine splitter to transform vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0. OK for trunk? BRs, Haochen gcc/ChangeLog: PR target/100738 * config/i386/sse.md (*_blendv_not_ltint): Add new define_insn_and_split. gcc/testsuite/ChangeLog: PR target/100738 * g++.target/i386/pr100738-1.C: New test. --- gcc/config/i386/sse.md | 28 ++++++++++++++++++++++ gcc/testsuite/g++.target/i386/pr100738-1.C | 19 +++++++++++++++ 2 files changed, 47 insertions(+) create mode 100755 gcc/testsuite/g++.target/i386/pr100738-1.C diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 08bdcddc111..db3506c78d7 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -20659,6 +20659,34 @@ (set_attr "btver2_decode" "vector,vector,vector") (set_attr "mode" "")]) +;; PR target/100738: Transform vpcmpeqd + vpxor + vblendvps to vblendvps for inverted mask; +(define_insn_and_split "*_blendv_not_ltint" + [(set (match_operand: 0 "register_operand") + (unspec: + [(match_operand: 1 "register_operand") + (match_operand: 2 "vector_operand") + (subreg: + (lt:VI48_AVX + (subreg:VI48_AVX + (not: + (match_operand: 3 "register_operand")) 0) + (match_operand:VI48_AVX 4 "const0_operand")) 0)] + UNSPEC_BLENDV))] + "TARGET_SSE4_1 && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec: + [(match_dup 2) (match_dup 1) (match_dup 3)] UNSPEC_BLENDV))] +{ + operands[0] = gen_lowpart (mode, operands[0]); + operands[1] = gen_lowpart (mode, operands[1]); + operands[2] = gen_lowpart (mode, operands[2]); + operands[3] = gen_lowpart (mode, operands[3]); + if (MEM_P (operands[2])) + operands[2] = force_reg (mode, operands[2]); +}) + (define_insn "_dp" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 diff --git a/gcc/testsuite/g++.target/i386/pr100738-1.C b/gcc/testsuite/g++.target/i386/pr100738-1.C new file mode 100755 index 00000000000..5a04c5b031f --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr100738-1.C @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -mavx2" } */ +/* { dg-final {scan-assembler-times "vblendvps\[ \\t\]" 2 } } */ +/* { dg-final {scan-assembler-not "vpcmpeqd\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpxor\[ \\t\]" } } */ + +typedef int v4si __attribute__((vector_size(16))); +typedef char v16qi __attribute__((vector_size(16))); +v4si +foo_1 (v16qi a, v4si b, v4si c, v4si d) +{ + return ((v4si)~a) < 0 ? c : d; +} + +v4si +foo_2 (v16qi a, v4si b, v4si c, v4si d) +{ + return ((v4si)~a) >= 0 ? c : d; +}