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Sat, 06 Dec 2025 16:10:42 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:42 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: claziss@gmail.com Subject: [PATCH V2 01/20] doc, arc: Clean up ARC option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:11 -0700 Message-Id: <20251207001030.1024365-2-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org The ARC front end presently has a large number of options that are explicitly deprecated, either by the "Warn" option or by being documented as such in the GCC manual. The manual text has documented a long list of obsolete options with a warning that they will be removed completely in a future release since at least GCC 5, 10+ years ago. Some of documented options have, in fact, already been deleted. This patch does *not* delete the remaining obsolete options, but only marks them as "Undocumented" in the .opt file and removes the documentation to reduce clutter in the manual. I've also added missing index entries for the remaining options to the manual. gcc/ChangeLog PR other/122243 * config/arc/arc.opt: Mark -mbig-endian, -mlittle-endian, -mmixed-code, -mno-mpy, -margonaut, -munalign-prob-threshold=, -mannotate-align, -malign-call, -mRcq, -mRcw, -mbbit-peephole, -mcompact-casesi, -mq-class, -mexpand-adddi, -mcrc, -mdsp-packa, -mdvbf, -mtelephony, -mrtsc, -EB, -EL, -mrla, -mEA, and -multcost= as "Undocumented". Add fixme for -mno-brcc. * doc/invoke.texi: Remove documentation for the above options. plus -mmac-d16 and -mmac-24 (which were already marked as "Undocumented"). Likewise remove documentation for -mbarrel_shifter, -mdpfp_compact, -mdpfp_fast, -mdsp_packa, -mmac_24, -mmac_d16, -mspfp_compact, and -mspfp_fast, which had already been deleted from arc.opt at some point. Add index entries for the -mno- forms of remaining options that have them. --- gcc/config/arc/arc.opt | 60 ++++++----- gcc/doc/invoke.texi | 232 ++++++++++------------------------------- 2 files changed, 88 insertions(+), 204 deletions(-) diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 9bd04f15737..a3dc410682b 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -21,12 +21,14 @@ HeaderInclude config/arc/arc-opts.h +; Formerly documented as deprecated; use configure options instead. mbig-endian -Target RejectNegative Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Undocumented Compile code for big endian mode. +; Formerly documented as deprecated; use configure options instead. mlittle-endian -Target RejectNegative InverseMask(BIG_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN) Undocumented Compile code for little endian mode. This is the default. mno-cond-exec @@ -136,7 +138,7 @@ Target Mask(CODE_DENSITY) Enable code density instructions for ARCv2. mmixed-code -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. ; We use an explict definition for the negative form because that is the @@ -166,7 +168,7 @@ Target Mask(MUL64_SET) Generate mul64 and mulu64 instructions. mno-mpy -Target Mask(NOMPY_SET) Warn(%qs is deprecated) +Target Mask(NOMPY_SET) Undocumented Warn(%qs is deprecated) Do not generate mpy instructions for ARC700. mea @@ -181,9 +183,11 @@ mlong-calls Target Mask(LONG_CALLS_SET) Generate call insns as register indirect calls. +; FIXME: should either be RejectNegative or listed in the positive form +; with InverseMask, otherwise we have -mno-no-brcc. mno-brcc Target Mask(NO_BRCC_SET) -Do no generate BRcc instructions in arc_reorg. +Do not generate BRcc instructions in arc_reorg. msdata Target InverseMask(NO_SDATA_SET) @@ -205,8 +209,9 @@ mspfp-fast Target Mask(SPFP_FAST_SET) FPX: Generate Single Precision FPX (fast) instructions. +; Formerly documented as deprecated, "obsolete FPX" margonaut -Target Mask(ARGONAUT_SET) +Target Mask(ARGONAUT_SET) Undocumented FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. mdpfp @@ -221,6 +226,7 @@ mdpfp-fast Target Mask(DPFP_FAST_SET) FPX: Generate Double Precision FPX (fast) instructions. +; Should be RejectNegative? mno-dpfp-lrsr Target Mask(DPFP_DISABLE_LRSR) Disable LR and SR instructions from using FPX extension aux registers. @@ -292,7 +298,7 @@ Target Mask(MULMAC_32BY16_SET) Generate 32x16 multiply and mac instructions. munalign-prob-threshold= -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. mmedium-calls @@ -300,20 +306,20 @@ Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) Don't use less than 25 bit addressing range for calls. mannotate-align -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. malign-call -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. mRcq -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. mRcw -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. @@ -322,7 +328,7 @@ Target Var(TARGET_EARLY_CBRANCHSI) Enable pre-reload use of cbranchsi pattern. mbbit-peephole -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. mcase-vector-pcrel @@ -330,30 +336,30 @@ Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) Use pc-relative switch case tables - this enables case table shortening. mcompact-casesi -Target Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) Enable compact casesi pattern. mq-class -Target Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) Enable 'q' instruction alternatives. mexpand-adddi -Target Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. ; Flags used by the assembler, but for which we define preprocessor ; macro symbols as well. mcrc -Target Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) Enable variable polynomial CRC extension. mdsp-packa -Target Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) Enable DSP 3.1 Pack A extensions. mdvbf -Target Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) Enable dual viterbi butterfly extension. mmac-d16 @@ -363,7 +369,7 @@ mmac-24 Target Undocumented Warn(%qs is deprecated) mtelephony -Target RejectNegative Warn(%qs is deprecated) +Target RejectNegative Undocumented Warn(%qs is deprecated) Enable Dual and Single Operand Instructions for Telephony. mxy @@ -380,15 +386,17 @@ Target Enable swap byte ordering extension instruction. mrtsc -Target Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) Enable 64-bit Time-Stamp Counter extension instruction. +; Formerly documented as deprecated. EB -Target +Target Undocumented Pass -EB option through to linker. +; Formerly documented as deprecated. EL -Target +Target Undocumented Pass -EL option through to linker. marclinux @@ -399,9 +407,8 @@ marclinux_prof Target Pass -marclinux_prof option through to linker. -;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. mlra -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. mlra-priority-none @@ -419,10 +426,11 @@ Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS mEA -Target +Target Undocumented multcost= -Target RejectNegative Joined +Target RejectNegative Joined Undocumented + matomic Target Mask(ATOMIC) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a6d2b54cc7f..51f5ef1ca6c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -926,20 +926,20 @@ Objective-C and Objective-C++ Dialects}. @gccoptlist{-mbarrel-shifter -mjli-always -mcpu=@var{cpu} -mA6 -mARC600 -mA7 -mARC700 -mdpfp -mdpfp-compact -mdpfp-fast -mno-dpfp-lrsr --mea -mno-mpy -mmul32x16 -mmul64 -matomic +-mea -mmul32x16 -mmul64 -matomic -mnorm -mspfp -mspfp-compact -mspfp-fast -msimd -msoft-float -mswap --mcrc -mdsp-packa -mdvbf -mlock -mmac-d16 -mmac-24 -mrtsc -mswape --mtelephony -mxy -misize -mannotate-align -marclinux -marclinux_prof +-mlock -mswape +-mxy -misize -marclinux -marclinux_prof -mlong-calls -mmedium-calls -msdata -mirq-ctrl-saved -mrgf-banked-regs -mlpc-width=@var{width} -G @var{num} -mvolatile-cache -mtp-regno=@var{regno} --malign-call -mauto-modify-reg -mbbit-peephole -mno-brcc --mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi --mexpand-adddi -mindexed-loads -mlra -mlra-priority-none +-mauto-modify-reg -mno-brcc +-mcase-vector-pcrel -mno-cond-exec -mearly-cbranchsi +-mindexed-loads -mlra-priority-none -mlra-priority-compact -mlra-priority-noncompact -mmillicode --mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} +-msize-level=@var{level} -mtune=@var{cpu} -mmultcost=@var{num} -mcode-density-frame --munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} +-mmpy-option=@var{multo} -mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16 -mbranch-index} @emph{ARM Options} (@ref{ARM Options}) @@ -23481,11 +23481,13 @@ is being compiled: @table @gcctabopt @opindex mbarrel-shifter +@opindex mno-barrel-shifter @item -mbarrel-shifter Generate instructions supported by barrel shifter. This is the default unless @option{-mcpu=ARC601} or @samp{-mcpu=ARCEM} is in effect. @opindex mjli-always +@opindex mno-mjli-always @item -mjli-always Force to call a function using jli_s instruction. This option is valid only for ARCv2 architecture. @@ -23590,13 +23592,16 @@ set. @end table @opindex mdpfp +@opindex mno-dpfp @opindex mdpfp-compact +@opindex mno-dpfp-compact @item -mdpfp @itemx -mdpfp-compact Generate double-precision FPX instructions, tuned for the compact implementation. @opindex mdpfp-fast +@opindex mno-dpfp-fast @item -mdpfp-fast Generate double-precision FPX instructions, tuned for the fast implementation. @@ -23607,44 +23612,46 @@ Disable @code{lr} and @code{sr} instructions from using FPX extension aux registers. @opindex mea +@opindex mno-ea @item -mea Generate extended arithmetic instructions. Currently only @code{divaw}, @code{adds}, @code{subs}, and @code{sat16} are supported. Only valid for @option{-mcpu=ARC700}. -@opindex mno-mpy -@opindex mmpy -@item -mno-mpy -Do not generate @code{mpy}-family instructions for ARC700. This option is -deprecated. - @opindex mmul32x16 +@opindex mno-mul32x16 @item -mmul32x16 Generate 32x16-bit multiply and multiply-accumulate instructions. @opindex mmul64 +@opindex mno-mul64 @item -mmul64 Generate @code{mul64} and @code{mulu64} instructions. Only valid for @option{-mcpu=ARC600}. @opindex mnorm +@opindex mno-norm @item -mnorm Generate @code{norm} instructions. This is the default if @option{-mcpu=ARC700} is in effect. @opindex mspfp +@opindex mno-spfp @opindex mspfp-compact +@opindex mno-spfp-compact @item -mspfp @itemx -mspfp-compact Generate single-precision FPX instructions, tuned for the compact implementation. @opindex mspfp-fast +@opindex mno-spfp-fast @item -mspfp-fast Generate single-precision FPX instructions, tuned for the fast implementation. @opindex msimd +@opindex mno-simd @item -msimd Enable generation of ARC SIMD instructions via target-specific builtins. Only valid for @option{-mcpu=ARC700}. @@ -23658,25 +23665,31 @@ can overridden by FPX options; @option{-mspfp}, @option{-mspfp-compact}, or @option{-mdpfp-compact}, or @option{-mdpfp-fast} for double precision. @opindex mswap +@opindex mno-swap @item -mswap Generate @code{swap} instructions. @opindex matomic +@opindex mno-atomic @item -matomic This enables use of the locked load/store conditional extension to implement atomic memory built-in functions. Not available for ARC 6xx or ARC EM cores. @opindex mdiv-rem +@opindex mno-div-rem @item -mdiv-rem Enable @code{div} and @code{rem} instructions for ARCv2 cores. @opindex mcode-density +@opindex mno-code-density @item -mcode-density +@itemx -mno-code-density Enable code density instructions for ARC EM. This option is on by default for ARC HS. @opindex mll64 +@opindex mno-ll64 @item -mll64 Enable double load/store operations for ARC HS cores. @@ -23847,12 +23860,14 @@ loop mechanism for various needs. This option defines macro @code{__ARC_LPC_WIDTH__} with the value of @var{width}. @opindex mrf16 +@opindex mno-rf16 @item -mrf16 This option instructs the compiler to generate code for a 16-entry register file. This option defines the @code{__ARC_RF16__} preprocessor macro. @opindex mbranch-index +@opindex mno-branch-index @item -mbranch-index Enable use of @code{bi} or @code{bih} instructions to implement jump tables. @@ -23865,56 +23880,25 @@ define preprocessor macro symbols. @c Flags used by the assembler, but for which we define preprocessor @c macro symbols as well. @table @gcctabopt -@opindex mdsp-packa -@item -mdsp-packa -Passed down to the assembler to enable the DSP Pack A extensions. -Also sets the preprocessor symbol @code{__Xdsp_packa}. This option is -deprecated. - -@opindex mdvbf -@item -mdvbf -Passed down to the assembler to enable the dual Viterbi butterfly -extension. Also sets the preprocessor symbol @code{__Xdvbf}. This -option is deprecated. @c ARC700 4.10 extension instruction @opindex mlock +@opindex mno-lock @item -mlock Passed down to the assembler to enable the locked load/store conditional extension. Also sets the preprocessor symbol @code{__Xlock}. -@opindex mmac-d16 -@item -mmac-d16 -Passed down to the assembler. Also sets the preprocessor symbol -@code{__Xxmac_d16}. This option is deprecated. - -@opindex mmac-24 -@item -mmac-24 -Passed down to the assembler. Also sets the preprocessor symbol -@code{__Xxmac_24}. This option is deprecated. - -@c ARC700 4.10 extension instruction -@opindex mrtsc -@item -mrtsc -Passed down to the assembler to enable the 64-bit time-stamp counter -extension instruction. Also sets the preprocessor symbol -@code{__Xrtsc}. This option is deprecated. - @c ARC700 4.10 extension instruction @opindex mswape +@opindex mno-swape @item -mswape Passed down to the assembler to enable the swap byte ordering extension instruction. Also sets the preprocessor symbol @code{__Xswape}. -@opindex mtelephony -@item -mtelephony -Passed down to the assembler to enable dual- and single-operand -instructions for telephony. Also sets the preprocessor symbol -@code{__Xtelephony}. This option is deprecated. - @opindex mxy +@opindex mno-xy @item -mxy Passed down to the assembler to enable the XY memory extension. Also sets the preprocessor symbol @code{__Xxy}. @@ -23926,13 +23910,10 @@ The following options control how the assembly code is annotated: @c Assembly annotation options @table @gcctabopt @opindex misize +@opindex mno-isize @item -misize Annotate assembler instructions with estimated addresses. -@opindex mannotate-align -@item -mannotate-align -Does nothing. Preserved for backward compatibility. - @end table The following options are passed through to the linker: @@ -23940,14 +23921,18 @@ The following options are passed through to the linker: @c options passed through to the linker @table @gcctabopt @opindex marclinux +@opindex mno-arclinux @item -marclinux +@itemx -mno-arclinux Passed through to the linker, to specify use of the @code{arclinux} emulation. This option is enabled by default in tool chains built for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets when profiling is not requested. @opindex marclinux_prof +@opindex mno-arclinux_prof @item -marclinux_prof +@itemx -mno-arclinux_prof Passed through to the linker, to specify use of the @code{arclinux_prof} emulation. This option is enabled by default in tool chains built for @w{@code{arc-linux-uclibc}} and @@ -23960,12 +23945,15 @@ The following options control the semantics of generated code: @c semantically relevant code generation options @table @gcctabopt @opindex mlong-calls +@opindex mno-long-calls @item -mlong-calls Generate calls as register indirect calls, thus providing access to the full 32-bit address range. @opindex mmedium-calls +@opindex mno-medium-calls @item -mmedium-calls +@itemx -mno-medium-calls Don't use less than 25-bit addressing range for calls, which is the offset available for an unconditional branch-and-link instruction. Conditional execution of function calls is suppressed, to @@ -23988,32 +23976,26 @@ built for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets. @opindex mvolatile-cache -@item -mvolatile-cache -Use ordinarily cached memory accesses for volatile references. This is the -default. - @opindex mno-volatile-cache -@opindex mvolatile-cache -@item -mno-volatile-cache -Enable cache bypass for volatile references. +@item -mvolatile-cache +@itemx -mno-volatile-cache + +Control how volatile references are accessed. +The default is @option{-mvolatile-cache}, which uses ordinary +cached memory accesses for volatile references. +Use @option{-mno-volatile-cache} to +enable cache bypass for volatile references. @end table The following options fine tune code generation: @c code generation tuning options @table @gcctabopt -@opindex malign-call -@item -malign-call -Does nothing. Preserved for backward compatibility. - @opindex mauto-modify-reg +@opindex mno-auto-modify-reg @item -mauto-modify-reg Enable the use of pre/post modify with register displacement. -@opindex mbbit-peephole -@item -mbbit-peephole -Does nothing. Preserved for backward compatibility. - @opindex mno-brcc @item -mno-brcc This option disables a target-specific pass in @file{arc_reorg} to @@ -24022,15 +24004,11 @@ It has no effect on generation of these instructions driven by the combiner pass. @opindex mcase-vector-pcrel +@opindex mno-case-vector-pcrel @item -mcase-vector-pcrel Use PC-relative switch case tables to enable case table shortening. This is the default for @option{-Os}. -@opindex mcompact-casesi -@item -mcompact-casesi -Enable compact @code{casesi} pattern. This is the default for @option{-Os}, -and only available for ARCv1 cores. This option is deprecated. - @opindex mno-cond-exec @item -mno-cond-exec Disable the ARCompact-specific pass to generate conditional @@ -24049,24 +24027,17 @@ offset range because they are conditionalized, you should consider using @option{-mmedium-calls} instead. @opindex mearly-cbranchsi +@opindex mno-early-cbranchsi @item -mearly-cbranchsi Enable pre-reload use of the @code{cbranchsi} pattern. -@opindex mexpand-adddi -@item -mexpand-adddi -Expand @code{adddi3} and @code{subdi3} at RTL generation time into -@code{add.f}, @code{adc} etc. This option is deprecated. - @opindex mindexed-loads +@opindex mno-indexed-loads @item -mindexed-loads Enable the use of indexed loads. This can be problematic because some optimizers then assume that indexed stores exist, which is not the case. -@opindex mlra -@item -mlra -Does nothing. Preserved for backward compatibility. - @opindex mlra-priority-none @item -mlra-priority-none Don't indicate any priority for target registers. @@ -24080,6 +24051,7 @@ Indicate target register priority for r0..r3 / r12..r15. Reduce target register priority for r0..r3 / r12..r15. @opindex mmillicode +@opindex mno-millicode @item -mmillicode When optimizing for size (using @option{-Os}), prologues and epilogues that have to save or restore a large number of registers are often @@ -24090,28 +24062,12 @@ nonstandard way, this option is provided to turn on or off millicode call generation. @opindex mcode-density-frame +@opindex mno-code-density-frame @item -mcode-density-frame This option enable the compiler to emit @code{enter} and @code{leave} instructions. These instructions are only valid for CPUs with code-density feature. -@opindex mmixed-code -@item -mmixed-code -Does nothing. Preserved for backward compatibility. - -@opindex mq-class -@item -mq-class -Ths option is deprecated. Enable @samp{q} instruction alternatives. -This is the default for @option{-Os}. - -@opindex mRcq -@item -mRcq -Does nothing. Preserved for backward compatibility. - -@opindex mRcw -@item -mRcw -Does nothing. Preserved for backward compatibility. - @opindex msize-level @item -msize-level=@var{level} Fine-tune size optimization with regards to instruction lengths and alignment. @@ -24174,86 +24130,6 @@ Tune for ARC4x release 3.10a. Cost to assume for a multiply instruction, with @samp{4} being equal to a normal instruction. -@opindex munalign-prob-threshold -@item -munalign-prob-threshold=@var{probability} -Does nothing. Preserved for backward compatibility. - -@end table - -The following options are maintained for backward compatibility, but -are now deprecated and will be removed in a future release: - -@c Deprecated options -@table @gcctabopt - -@opindex margonaut -@item -margonaut -Obsolete FPX. - -@opindex mbig-endian -@opindex EB -@item -mbig-endian -@itemx -EB -Compile code for big-endian targets. Use of these options is now -deprecated. Big-endian code is supported by configuring GCC to build -@w{@code{arceb-elf32}} and @w{@code{arceb-linux-uclibc}} targets, -for which big endian is the default. - -@opindex mlittle-endian -@opindex EL -@item -mlittle-endian -@itemx -EL -Compile code for little-endian targets. Use of these options is now -deprecated. Little-endian code is supported by configuring GCC to build -@w{@code{arc-elf32}} and @w{@code{arc-linux-uclibc}} targets, -for which little endian is the default. - -@opindex mbarrel_shifter -@item -mbarrel_shifter -Replaced by @option{-mbarrel-shifter}. - -@opindex mdpfp_compact -@item -mdpfp_compact -Replaced by @option{-mdpfp-compact}. - -@opindex mdpfp_fast -@item -mdpfp_fast -Replaced by @option{-mdpfp-fast}. - -@opindex mdsp_packa -@item -mdsp_packa -Replaced by @option{-mdsp-packa}. - -@opindex mEA -@item -mEA -Replaced by @option{-mea}. - -@opindex mmac_24 -@item -mmac_24 -Replaced by @option{-mmac-24}. - -@opindex mmac_d16 -@item -mmac_d16 -Replaced by @option{-mmac-d16}. - -@opindex mspfp_compact -@item -mspfp_compact -Replaced by @option{-mspfp-compact}. - -@opindex mspfp_fast -@item -mspfp_fast -Replaced by @option{-mspfp-fast}. - -@opindex mtune -@item -mtune=@var{cpu} -Values @samp{arc600}, @samp{arc601}, @samp{arc700} and -@samp{arc700-xmac} for @var{cpu} are replaced by @samp{ARC600}, -@samp{ARC601}, @samp{ARC700} and @samp{ARC700-xmac} respectively. - -@opindex multcost -@item -multcost=@var{num} -Replaced by @option{-mmultcost}. - @end table @node ARM Options From patchwork Sun Dec 7 00:10:12 2025 Content-Type: text/plain; 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Sat, 06 Dec 2025 16:10:43 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:43 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com Subject: [PATCH V2 02/20] doc, h8300: Clean up H8/300 option and attribute documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:12 -0700 Message-Id: <20251207001030.1024365-3-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Comparing the documentation in invoke.texi with hs8300.opt, I spotted a few options in the latter that were missing documentation, and added it. I wanted to add a link to the "monitor" attribute referenced in the existing docs for this option, but found that was also missing, along with docs for the "OS_Task" attribute; so I fixed those problems while I was at it. gcc/ChangeLog PR other/122243 * config/h8300/h8300.opt (mexr, mno-exr): Add FIXME re ambiguity for -mno-exr semantics. * doc/extend.texi (H8/300 Function Attributes): Document monitor and OS_Task attributes. * doc/invoke.texi (Option Summary) X-Patchwork-Id: 126073 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5A862442384B for ; Sun, 7 Dec 2025 00:16:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5A862442384B Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=YB3WMwmJ X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-f67.google.com (mail-ot1-f67.google.com [209.85.210.67]) by sourceware.org (Postfix) with ESMTPS id A270A4143731 for ; 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Sat, 06 Dec 2025 16:10:45 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:45 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, dave.anglin@bell.net Subject: [PATCH 03/20] doc, pa: HPPA option documentation cleanup [PR122243] Date: Sat, 6 Dec 2025 17:10:13 -0700 Message-Id: <20251207001030.1024365-4-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Note that the default for the -mlra option on HPPA was recently changed from 0 to 1. This option has never been documented for this target and reload is supposed to be going away entirely soon, so I see no reason to document it now. gcc/ChangeLog PR other/122243 * config/pa/pa.opt (mbig-switch): Mark obsolete option as "Undocumented". (mjump-in-delay): Likewise. (mlra): Likewise. (mnosnake, msnake): Likewise. * doc/invoke.texi (Option Summary) : Remove deliberately undocumented options from list. Remove redundant negative/positive forms from list. Fix formatting so there is uniformly two spaces between options on the same line. (HPPA Options): Remove documentation for obsolete options. Add @opindex for negative forms. Properly list -mwsio instead of just referring to it in the -msio docs. Light copy-editing to fix markup, jargon, etc. --- gcc/config/pa/pa.opt | 10 ++++---- gcc/doc/invoke.texi | 57 ++++++++++++++++++++++++-------------------- 2 files changed, 36 insertions(+), 31 deletions(-) diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt index e90c4cacbd5..7efb01c8982 100644 --- a/gcc/config/pa/pa.opt +++ b/gcc/config/pa/pa.opt @@ -42,7 +42,7 @@ Target Var(TARGET_ATOMIC_LIBCALLS) Init(1) Generate libcalls for atomic loads and stores when sync libcalls are disabled. mbig-switch -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. mcaller-copies @@ -74,7 +74,7 @@ Target Mask(GAS) Assume code will be assembled by GAS. mjump-in-delay -Target Ignore +Target Ignore Undocumented Does nothing. Preserved for backward compatibility. ;; Not used by gcc @@ -87,7 +87,7 @@ Target Mask(LONG_CALLS) Always generate long calls. mlra -Target Var(pa_lra_p) Init(1) +Target Var(pa_lra_p) Init(1) Undocumented Use LRA instead of reload (transitional). mlong-load-store @@ -95,7 +95,7 @@ Target Mask(LONG_LOAD_STORE) Emit long load/store sequences. mnosnake -Target RejectNegative +Target RejectNegative Undocumented Generate PA1.0 code. mno-space-regs @@ -156,7 +156,7 @@ Target Mask(SOFT_MULT) Use software integer multiplication. msnake -Target RejectNegative +Target RejectNegative Undocumented Generate PA1.1 code. mspace-regs diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0afdaad8eb5..4439683cbd5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1113,18 +1113,15 @@ Objective-C and Objective-C++ Dialects}. @emph{HPPA Options} (@ref{HPPA Options}) @gccoptlist{-march=@var{architecture-type} --matomic-libcalls -mbig-switch +-mno-atomic-libcalls -mcaller-copies -mdisable-fpregs -mdisable-indexing -mordered -mfast-indirect-calls -mgas -mgnu-ld -mhp-ld -mfixed-range=@var{register-range} --mcoherent-ldcw -mjump-in-delay -mlinker-opt -mlong-calls --mlong-load-store -mno-atomic-libcalls -mno-disable-fpregs --mno-disable-indexing -mno-fast-indirect-calls -mno-gas --mno-jump-in-delay -mno-long-load-store --mno-portable-runtime -mno-soft-float +-mcoherent-ldcw -mlinker-opt -mlong-calls +-mlong-load-store -mno-space-regs -msoft-float -mpa-risc-1-0 -mpa-risc-1-1 -mpa-risc-2-0 -mportable-runtime --mschedule=@var{cpu-type} -mspace-regs -msoft-mult -msio -mwsio +-mschedule=@var{cpu-type} -msoft-mult -msio -mwsio -munix=@var{unix-std} -nolibdld -static -threads} @emph{IA-64 Options} (@ref{IA-64 Options}) @@ -28066,11 +28063,13 @@ other way around. @item -mpa-risc-1-0 @itemx -mpa-risc-1-1 @itemx -mpa-risc-2-0 -Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively. +Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0}, +respectively. @opindex matomic-libcalls @opindex mno-atomic-libcalls @item -matomic-libcalls +@itemx -mno-atomic-libcalls Generate libcalls for atomic loads and stores when sync libcalls are disabled. This option is enabled by default. It only affects the generation of atomic libcalls by the HPPA backend. @@ -28091,11 +28090,8 @@ This option generates @code{__atomic_exchange} calls for atomic stores. It also provides special handling for atomic DImode accesses on 32-bit targets. -@opindex mbig-switch -@item -mbig-switch -Does nothing. Preserved for backward compatibility. - @opindex mcaller-copies +@opindex mno-caller-copies @item -mcaller-copies The caller copies function arguments passed by hidden reference. This option should be used with care as it is not compatible with the default @@ -28104,19 +28100,23 @@ passed by hidden reference and the option provides better compatibility with OpenMP. @opindex mcoherent-ldcw +@opindex mno-coherent-ldcw @item -mcoherent-ldcw Use ldcw/ldcd coherent cache-control hint. @opindex mdisable-fpregs +@opindex -mno-disable-fpregs @item -mdisable-fpregs -Disable floating-point registers. Equivalent to @code{-msoft-float}. +Disable floating-point registers. Equivalent to @option{-msoft-float}. @opindex mdisable-indexing +@opindex mno-disable-indexing @item -mdisable-indexing Prevent the compiler from using indexing address modes. This avoids some rather obscure problems when compiling MIG generated code under MACH@. @opindex mfast-indirect-calls +@opindex mno-fast-indirect-calls @item -mfast-indirect-calls Generate code that assumes calls never cross space boundaries. This allows GCC to emit code that performs faster indirect calls. @@ -28133,6 +28133,7 @@ two registers separated by a dash. Multiple register ranges can be specified separated by a comma. @opindex mgas +@opindex -mno-gas @item -mgas Enable the use of assembler directives only GAS understands. @@ -28179,7 +28180,7 @@ long calls only when the distance from the call site to the beginning of the function or translation unit, as the case may be, exceeds a predefined limit set by the branch type being used. The limits for normal calls are 7,600,000 and 240,000 bytes, respectively for the -PA 2.0 and PA 1.X architectures. Sibcalls are always limited at +PA 2.0 and PA 1.X architectures. Sibling calls are always limited at 240,000 bytes. Distances are measured from the beginning of functions when using the @@ -28193,21 +28194,18 @@ particularly when partial linking is used to build the application. The types of long calls used depends on the capabilities of the assembler and linker, and the type of code being generated. The -impact on systems that support long absolute calls, and long pic -symbol-difference or pc-relative calls should be relatively small. -However, an indirect call is used on 32-bit ELF systems in pic code +impact on systems that support long absolute calls, and long PIC +symbol-difference or PC-relative calls should be relatively small. +However, an indirect call is used on 32-bit ELF systems in PIC code and it is quite long. @opindex mlong-load-store +@opindex mno-long-load-store @item -mlong-load-store Generate 3-instruction load and store sequences as sometimes required by the HP-UX 10 linker. This is equivalent to the @samp{+k} option to the HP compilers. -@opindex mjump-in-delay -@item -mjump-in-delay -This option is ignored and provided for compatibility purposes only. - @opindex mno-space-regs @opindex mspace-regs @item -mno-space-regs @@ -28217,10 +28215,12 @@ GCC to generate faster indirect calls and use unscaled index address modes. Such code is suitable for level 0 PA systems and kernels. @opindex mordered +@opindex mno-ordered @item -mordered Assume memory references are ordered and barriers are not needed. @opindex mportable-runtime +@opindex mno-portable-runtime @item -mportable-runtime Use the portable calling conventions proposed by HP for ELF systems. @@ -28234,13 +28234,17 @@ proper scheduling option for your machine. The default scheduling is @samp{8000}. @opindex msio +@opindex mwsio @item -msio -Generate the predefine, @code{_SIO}, for server IO@. The default is +@itemx -mwsio +The @option{-msio} generates the predefine, @code{_SIO}, for server IO@. +The default is @option{-mwsio}. This generates the predefines, @code{__hp9000s700}, @code{__hp9000s700__} and @code{_WSIO}, for workstation IO@. These options are available under HP-UX and HI-UX@. @opindex msoft-float +@opindex mno-soft-float @item -msoft-float Generate output containing library calls for floating point. @strong{Warning:} the requisite libraries are not available for all HPPA @@ -28256,6 +28260,7 @@ library that comes with GCC, with @option{-msoft-float} in order for this to work. @opindex msoft-mult +@opindex mno-soft-mult @item -msoft-mult Use software integer multiplication. @@ -28289,18 +28294,18 @@ as appropriate. Most GNU software doesn't provide this capability. @opindex nolibdld @item -nolibdld -Suppress the generation of link options to search libdld.sl when the +Suppress the generation of link options to search @file{libdld.sl} when the @option{-static} option is specified on HP-UX 10 and later. @opindex static @item -static -The HP-UX implementation of setlocale in libc has a dependency on -libdld.sl. There isn't an archive version of libdld.sl. Thus, +The HP-UX C library implementation of @code{setlocale} has a dependency on +@file{libdld.sl}. There isn't an archive version of @file{libdld.sl}. Thus, when the @option{-static} option is specified, special link options are needed to resolve this dependency. On HP-UX 10 and later, the GCC driver adds the necessary options to -link with libdld.sl when the @option{-static} option is specified. +link with @file{libdld.sl} when the @option{-static} option is specified. This causes the resulting binary to be dynamic. On the 64-bit port, the linkers generate dynamic binaries by default in any case. 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Sat, 06 Dec 2025 16:10:47 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:46 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Subject: [PATCH 04/20] doc, ia64: Clean up documentation of IA-64 options [PR122243] Date: Sat, 6 Dec 2025 17:10:14 -0700 Message-Id: <20251207001030.1024365-5-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org This backend is no longer maintained and was supposed to have been deleted as of GCC 15, but since it is still part of GCC and documented in the manual, I have gone ahead and fixed up its options documentation for consistency with other active targets. gcc/ChangeLog PR other/122243 * config/ia64/ia64.opt (msched-prefer-data-spec-insns): Mark as explicitly "Undocumented". (msched-prefer-non-control-spec-insns): Likewise. * doc/invoke.texi (Option Summary) : Remove explicitly undocumented and redundant mno- forms from the list. (IA-64 Options): Remove documentation for already-deleted option -mfused-add and the two explicitly undocumented options. Add @opindex for negative forms and explicitly list the -mno-forms of options that are enabled by default. --- gcc/config/ia64/ia64.opt | 4 ++-- gcc/doc/invoke.texi | 44 ++++++++++++++-------------------------- 2 files changed, 17 insertions(+), 31 deletions(-) diff --git a/gcc/config/ia64/ia64.opt b/gcc/config/ia64/ia64.opt index 1d34f1092bd..3a0a1938a18 100644 --- a/gcc/config/ia64/ia64.opt +++ b/gcc/config/ia64/ia64.opt @@ -164,10 +164,10 @@ Target Var(mflag_sched_spec_control_ldc) Init(0) Use simple data speculation check for control speculation. msched-prefer-non-data-spec-insns -Target WarnRemoved +Target WarnRemoved Undocumented msched-prefer-non-control-spec-insns -Target WarnRemoved +Target WarnRemoved Undocumented msched-count-spec-in-critical-path Target Var(mflag_sched_count_spec_in_critical_path) Init(0) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4439683cbd5..c08d84d9bdc 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1126,8 +1126,8 @@ Objective-C and Objective-C++ Dialects}. @emph{IA-64 Options} (@ref{IA-64 Options}) @gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic --mvolatile-asm-stop -mregister-names -msdata -mno-sdata --mconstant-gp -mauto-pic -mfused-madd +-mvolatile-asm-stop -mregister-names -msdata +-mconstant-gp -mauto-pic -minline-float-divide-min-latency -minline-float-divide-max-throughput -mno-inline-float-divide @@ -1142,7 +1142,6 @@ Objective-C and Objective-C++ Dialects}. -msched-br-data-spec -msched-ar-data-spec -msched-control-spec -msched-br-in-data-spec -msched-ar-in-data-spec -msched-in-control-spec -msched-spec-ldc -msched-spec-control-ldc --msched-prefer-non-data-spec-insns -msched-prefer-non-control-spec-insns -msched-stop-bits-after-every-cycle -msched-count-spec-in-critical-path -msel-sched-dont-check-control-spec -msched-fp-mem-deps-zero-cost -msched-max-memory-insns-hard-limit -msched-max-memory-insns=@var{max-insns}} @@ -28429,13 +28428,6 @@ using the maximum throughput algorithm. @item -mno-inline-sqrt Do not generate inline code for @code{sqrt}. -@opindex mfused-madd -@opindex mno-fused-madd -@item -mfused-madd -@itemx -mno-fused-madd -Do (don't) generate code that uses the fused multiply/add or multiply/subtract -instructions. The default is to use these instructions. - @opindex mno-dwarf2-asm @opindex mdwarf2-asm @item -mno-dwarf2-asm @@ -28534,24 +28526,6 @@ are dependent on the control speculative loads. This is effective only with @option{-msched-control-spec} enabled. The default setting is enabled. -@opindex mno-sched-prefer-non-data-spec-insns -@opindex msched-prefer-non-data-spec-insns -@item -mno-sched-prefer-non-data-spec-insns -@itemx -msched-prefer-non-data-spec-insns -If enabled, data-speculative instructions are chosen for schedule -only if there are no other choices at the moment. This makes -the use of the data speculation much more conservative. -The default setting is disabled. - -@opindex mno-sched-prefer-non-control-spec-insns -@opindex msched-prefer-non-control-spec-insns -@item -mno-sched-prefer-non-control-spec-insns -@itemx -msched-prefer-non-control-spec-insns -If enabled, control-speculative instructions are chosen for schedule -only if there are no other choices at the moment. This makes -the use of the control speculation much more conservative. -The default setting is disabled. - @opindex mno-sched-count-spec-in-critical-path @opindex msched-count-spec-in-critical-path @item -mno-sched-count-spec-in-critical-path @@ -28562,26 +28536,36 @@ speculation a bit more conservative. The default setting is disabled. @opindex msched-spec-ldc +@opindex mno-sched-spec-ldc @item -msched-spec-ldc +@itemx -mno-sched-spec-ldc Use a simple data speculation check. This option is on by default. -@opindex msched-spec-ldc +@opindex msched-spec-control-ldc +@opindex mno-sched-spec-control-ldc @item -msched-control-spec-ldc +@itemx -mno-sched-control-spec-ldc Use a simple check for control speculation. This option is on by default. @opindex msched-stop-bits-after-every-cycle +@opindex mno-sched-stop-bits-after-every-cycle @item -msched-stop-bits-after-every-cycle +@itemx -mno-sched-stop-bits-after-every-cycle Place a stop bit after every cycle when scheduling. This option is on by default. @opindex msched-fp-mem-deps-zero-cost +@opindex mno-sched-fp-mem-deps-zero-cost @item -msched-fp-mem-deps-zero-cost +@itemx -mno-sched-fp-mem-deps-zero-cost Assume that floating-point stores and loads are not likely to cause a conflict when placed into the same instruction group. This option is disabled by default. @opindex msel-sched-dont-check-control-spec +@opindex mno-sel-sched-dont-check-control-spec @item -msel-sched-dont-check-control-spec +@itemx -mno-sel-sched-dont-check-control-spec Generate checks for control speculation in selective scheduling. This flag is disabled by default. @@ -28593,7 +28577,9 @@ instruction group. Frequently useful to prevent cache bank conflicts. The default value is 1. @opindex msched-max-memory-insns-hard-limit +@opindex mno-sched-max-memory-insns-hard-limit @item -msched-max-memory-insns-hard-limit +@itemx -mno-sched-max-memory-insns-hard-limit Makes the limit specified by @option{msched-max-memory-insns} a hard limit, disallowing more than that number in an instruction group. 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Sat, 06 Dec 2025 16:10:48 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:48 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: sebastien@milkymist.org Subject: [PATCH 05/20] doc, lm32: Clean up LM32 option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:15 -0700 Message-Id: <20251207001030.1024365-6-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * doc/invoke.texi (LM32 Options): Add @opindex entries for negative option forms. --- gcc/doc/invoke.texi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c08d84d9bdc..c93cfd666ec 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -28596,22 +28596,27 @@ These @option{-m} options are defined for the LatticeMico32 architecture: @table @gcctabopt @opindex mbarrel-shift-enabled +@opindex mno-barrel-shift-enabled @item -mbarrel-shift-enabled Enable barrel-shift instructions. @opindex mdivide-enabled +@opindex mno-divide-enabled @item -mdivide-enabled Enable divide and modulus instructions. -@opindex multiply-enabled +@opindex mmultiply-enabled +@opindex mno-multiply-enabled @item -mmultiply-enabled Enable multiply instructions. @opindex msign-extend-enabled +@opindex mno-sign-extend-enabled @item -msign-extend-enabled Enable sign extend instructions. @opindex muser-enabled +@opindex mno-user-enabled @item -muser-enabled Enable user-defined instructions. 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Sat, 06 Dec 2025 16:10:50 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:50 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH 06/20] doc, loongarch: Clean up LoongArch option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:16 -0700 Message-Id: <20251207001030.1024365-7-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, PROLO_LEO1, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * doc/invoke.texi (Option Summary) : Remove redundant -mno forms from list. Fix formatting so that there is uniformly two spaces between options on the same line. (LoongArch Options): Copy-editing for grammar, etc. Add @opindex for negative forms. --- gcc/doc/invoke.texi | 115 ++++++++++++++++++++++++-------------------- 1 file changed, 64 insertions(+), 51 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c93cfd666ec..5fff5c022c4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1151,22 +1151,21 @@ Objective-C and Objective-C++ Dialects}. -msign-extend-enabled -muser-enabled} @emph{LoongArch Options} (@ref{LoongArch Options}) -@gccoptlist{-march=@var{arch-type} -mtune=@var{tune-type} -mabi=@var{base-abi-type} --mfpu=@var{fpu-type} -msimd=@var{simd-type} --msoft-float -msingle-float -mdouble-float -mlsx -mno-lsx -mlasx -mno-lasx --mbranch-cost=@var{n} -maddr-reg-reg-cost=@var{n} -mcheck-zero-division --mno-check-zero-division -mbreak-code=@var{code} --mcond-move-int -mno-cond-move-int --mcond-move-float -mno-cond-move-float --memcpy -mno-memcpy -mstrict-align -mno-strict-align -G @var{num} +@gccoptlist{-march=@var{arch-type} -mtune=@var{tune-type} -mabi=@var{base-abi-type} +-mfpu=@var{fpu-type} -msimd=@var{simd-type} +-msoft-float -msingle-float -mdouble-float -mlsx -mlasx +-mbranch-cost=@var{n} -maddr-reg-reg-cost=@var{n} -mcheck-zero-division +-mbreak-code=@var{code} +-mcond-move-int -mcond-move-float +-memcpy -mstrict-align -G @var{num} -mmax-inline-memcpy-size=@var{n} --mexplicit-relocs=@var{style} -mexplicit-relocs -mno-explicit-relocs --mdirect-extern-access -mno-direct-extern-access --mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as --mrecip -mrecip=@var{opt} -mfrecipe -mno-frecipe -mdiv32 -mno-div32 --mlam-bh -mno-lam-bh -mlamcas -mno-lamcas -mld-seq-sa -mno-ld-seq-sa --mscq -mno-scq -mtls-dialect=@var{opt} --mannotate-tablejump -mno-annotate-tablejump} +-mexplicit-relocs=@var{style} -mexplicit-relocs -mno-explicit-relocs +-mdirect-extern-access +-mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as +-mrecip -mrecip=@var{opt} -mfrecipe -mdiv32 +-mlam-bh -mlamcas -mld-seq-sa +-mscq -mtls-dialect=@var{opt} +-mannotate-tablejump} @emph{M32C Options} (@ref{M32C Options}) @gccoptlist{-mcpu=@var{cpu} -msim -memregs=@var{number}} @@ -28727,7 +28726,7 @@ No LoongArch SIMD instruction may be generated. @opindex msoft-float @item -msoft-float -Force @option{-mfpu=none} and prevents the use of floating-point +Force @option{-mfpu=none} and prevent the use of floating-point registers for parameter passing. This option may change the target ABI. @@ -28743,18 +28742,22 @@ Force @option{-mfpu=64} and allow the use of 32/64-bit floating-point registers for parameter passing. This option may change the target ABI. -@opindex ml[a]sx +@opindex mlasx +@opindex mno-lasx +@opindex mlsx +@opindex mno-lsx @item -mlasx @itemx -mno-lasx @item -mlsx @itemx -mno-lsx Incrementally adjust the scope of the SIMD extensions (none / LSX / LASX) that can be used by the compiler for code generation. Enabling LASX with -@option{mlasx} automatically enables LSX, and diabling LSX with @option{mno-lsx} +@option{-mlasx} automatically enables LSX, +and disabling LSX with @option{-mno-lsx} automatically disables LASX. These driver-only options act upon the final -@option{msimd} configuration state and make incremental changes in the order +@option{-msimd} configuration state and make incremental changes in the order they appear on the GCC driver's command line, deriving the final / canonicalized -@option{msimd} option that is passed to the compiler proper. +@option{-msimd} option that is passed to the compiler proper. @opindex mbranch-cost @item -mbranch-cost=@var{n} @@ -28765,6 +28768,7 @@ Set the cost of branches to roughly @var{n} instructions. Set the cost of ADDRESS_REG_REG to the value calculated by @var{n}. @opindex mcheck-zero-division +@opindex mno-check-zero-division @item -mcheck-zero-division @itemx -mno-check-zero-divison Trap (do not trap) on integer division by zero. The default is @@ -28783,18 +28787,21 @@ or greater than 32767. The default is -1, meaning to use the @code{amswap.w} instruction. @opindex mcond-move-int +@opindex mno-cond-move-int @item -mcond-move-int @itemx -mno-cond-move-int Conditional moves for integral data in general-purpose registers are enabled (disabled). The default is @option{-mcond-move-int}. @opindex mcond-move-float +@opindex mno-cond-move-float @item -mcond-move-float @itemx -mno-cond-move-float Conditional moves for floating-point registers are enabled (disabled). The default is @option{-mcond-move-float}. @opindex mmemcpy +@opindex mno-memcpy @item -mmemcpy @itemx -mno-memcpy Force (do not force) the use of @code{memcpy} for non-trivial block moves. @@ -28805,6 +28812,7 @@ behavior if explicitly specified, regardless of the order these options on the command line. @opindex mstrict-align +@opindex mno-strict-align @item -mstrict-align @itemx -mno-strict-align Avoid or allow generating memory accesses that may not be aligned on a natural @@ -28845,15 +28853,21 @@ The @option{-mcmodel=extreme} option is incompatible with @option{-fplt} and/or @option{-mexplicit-relocs=none}. @end table +@opindex mexplicit-relocs +@opindex mno-explicit-relocs @item -mexplicit-relocs=@var{style} +@itemx -mexplicit-relocs +@itemx -mno-explicit-relocs Set when to use assembler relocation operators when dealing with symbolic addresses. The alternative is to use assembler macros instead, which may limit instruction scheduling but allow linker relaxation. -with @option{-mexplicit-relocs=none} the assembler macros are always used, -with @option{-mexplicit-relocs=always} the assembler relocation operators -are always used, with @option{-mexplicit-relocs=auto} the compiler will -use the relocation operators where the linker relaxation is impossible to -improve the code quality, and macros elsewhere. The default +With @option{-mexplicit-relocs=none}, the assembler macros are always used; +with @option{-mexplicit-relocs=always}, the assembler relocation operators +are always used; and with @option{-mexplicit-relocs=auto} the compiler uses +the relocation operators where linker relaxation is impossible to +improve the code quality, and macros elsewhere. + +The default value for the option is determined with the assembler capability detected during GCC build-time and the setting of @option{-mrelax}: @option{-mexplicit-relocs=none} if the assembler does not support @@ -28863,22 +28877,18 @@ operators but @option{-mrelax} is not enabled, @option{-mexplicit-relocs=auto} if the assembler supports relocation operators and @option{-mrelax} is enabled. -@opindex mexplicit-relocs -@item -mexplicit-relocs -An alias of @option{-mexplicit-relocs=always} for backward compatibility. - -@opindex mno-explicit-relocs -@item -mno-explicit-relocs -An alias of @option{-mexplicit-relocs=none} for backward compatibility. +For backward compatibility, @option{-mexplicit-relocs} is equivalent to +@option{-mexplicit-relocs=always}, while @option{-mno-explicit-relocs} is +equivalent to @option{-mexplicit-relocs=none}. @opindex mdirect-extern-access @item -mdirect-extern-access @itemx -mno-direct-extern-access -Do not use or use GOT to access external symbols. The default is -@option{-mno-direct-extern-access}: GOT is used for external symbols with +Control use of the GOT to access external symbols. The default is +@option{-mno-direct-extern-access}: the GOT is used for external symbols with default visibility, but not used for other external symbols. -With @option{-mdirect-extern-access}, GOT is not used and all external +With @option{-mdirect-extern-access}, the GOT is not used and all external symbols are PC-relatively addressed. It is @strong{only} suitable for environments where no dynamic link is performed, like firmwares, OS kernels, executables linked with @option{-static} or @option{-static-pie}. @@ -28921,7 +28931,7 @@ These instructions are generated only when @option{-funsafe-math-optimizations} is enabled together with @option{-ffinite-math-only} and @option{-fno-trapping-math}. This option is off by default. Before you can use this option, you must sure the -target CPU supports frecipe and frsqrte instructions. +target CPU supports the @code{frecipe} and @code{frsqrte} instructions. Note that while the throughput of the sequence is higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). @@ -28969,31 +28979,33 @@ all of the reciprocal approximations, except for scalar square root. @item -mfrecipe @itemx -mno-frecipe Use (do not use) @code{frecipe.@{s/d@}} and @code{frsqrte.@{s/d@}} -instructions. When build with @option{-march=la664}, it is enabled by default. -The default is @option{-mno-frecipe}. +instructions. When compiling with @option{-march=la664}, +it is enabled by default. Otherwise the default is @option{-mno-frecipe}. @opindex mdiv32 @opindex mno-div32 @item -mdiv32 @itemx -mno-div32 Use (do not use) @code{div.w[u]} and @code{mod.w[u]} instructions with input -not sign-extended. When build with @option{-march=la664}, it is enabled by -default. The default is @option{-mno-div32}. +not sign-extended. When compiling with @option{-march=la664}, it is enabled by +default. Otherwise the default is @option{-mno-div32}. @opindex mlam-bh @opindex mno-lam-bh @item -mlam-bh @itemx -mno-lam-bh -Use (do not use) @code{am@{swap/add@}[_db].@{b/h@}} instructions. When build -with @option{-march=la664}, it is enabled by default. The default is -@option{-mno-lam-bh}. +Use (do not use) @code{am@{swap/add@}[_db].@{b/h@}} instructions. +When compiling +with @option{-march=la664}, it is enabled by default. Otherwise +the default is @option{-mno-lam-bh}. @opindex mlamcas @opindex mno-lamcas @item -mlamcas @itemx -mno-lamcas -Use (do not use) @code{amcas[_db].@{b/h/w/d@}} instructions. When build with -@option{-march=la664}, it is enabled by default. The default is +Use (do not use) @code{amcas[_db].@{b/h/w/d@}} instructions. +When compiling with +@option{-march=la664}, it is enabled by default. Otherwise the default is @option{-mno-lamcas}. @opindex mld-seq-sa @@ -29001,7 +29013,8 @@ Use (do not use) @code{amcas[_db].@{b/h/w/d@}} instructions. When build with @item -mld-seq-sa @itemx -mno-ld-seq-sa Whether a same-address load-load barrier (@code{dbar 0x700}) is needed. When -build with @option{-march=la664}, it is enabled by default. The default is +compiling with @option{-march=la664}, it is enabled by default. +Otherwise the default is @option{-mno-ld-seq-sa}, the load-load barrier is needed. @opindex mscq @@ -29014,8 +29027,8 @@ The default is @option{-mscq} if the machine type specified with @opindex mtls-dialect @item -mtls-dialect=@var{opt} -This option controls which tls dialect may be used for general dynamic and -local dynamic TLS models. +This option controls which TLS dialect may be used for general dynamic and +local dynamic TLS models. The @var{opt} argument can be one of: @table @samp @item trad @@ -29033,13 +29046,13 @@ Create an annotation section @code{.discard.tablejump_annotate} to correlate the @code{jirl} instruction and the jump table when a jump table is used to optimize the @code{switch} statement. Some external tools, for example @file{objtool} of the Linux kernel building system, -need the annotation to analysis the control flow. The default is +need the annotation to analyze the control flow. The default is @option{-mno-annotate-tablejump}. @item --param loongarch-vect-unroll-limit=@var{n} -The vectorizer will use available tuning information to determine whether it +The vectorizer uses available tuning information to determine whether it would be beneficial to unroll the main vectorized loop and by how much. This -parameter set's the upper bound of how much the vectorizer will unroll the main +parameter sets the upper bound of how much the vectorizer unrolls the main loop. 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(M32R/D Options): Regularize form of @opindex entries for various options of the form -mfoo=@var{value}. Combine the documentation for -malign-loops and -mno-align-loops. --- gcc/doc/invoke.texi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3c9d004790f..2ce6462c66d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1173,7 +1173,7 @@ Objective-C and Objective-C++ Dialects}. @emph{M32R/D Options} (@ref{M32R/D Options}) @gccoptlist{-m32r2 -m32rx -m32r -mdebug --malign-loops -mno-align-loops +-malign-loops -missue-rate=@var{number} -mbranch-cost=@var{number} -mmodel=@var{code-size-model-type} @@ -29110,6 +29110,7 @@ Generate code for the M32R/X@. @item -m32r Generate code for the M32R@. This is the default. +@opindex mmodel @opindex mmodel=small @item -mmodel=small Assume all objects live in the lower 16MB of memory (so that their addresses @@ -29134,6 +29135,7 @@ assume subroutines may not be reachable with the @code{bl} instruction (the compiler generates the much slower @code{seth/add3/jl} instruction sequence). +@opindex msdata @opindex msdata=none @item -msdata=none Disable use of the small data area. Variables are put into @@ -29175,24 +29177,22 @@ Makes the M32R-specific code in the compiler display some statistics that might help in debugging programs. @opindex malign-loops -@item -malign-loops -Align all loops to a 32-byte boundary. - @opindex mno-align-loops -@item -mno-align-loops -Do not enforce a 32-byte alignment for loops. This is the default. +@item -malign-loops +@itemx -mno-align-loops +Align all loops to a 32-byte boundary. This option is disabled by default. -@opindex missue-rate=@var{number} +@opindex missue-rate @item -missue-rate=@var{number} Issue @var{number} instructions per cycle. @var{number} can only be 1 or 2. -@opindex mbranch-cost=@var{number} +@opindex mbranch-cost @item -mbranch-cost=@var{number} @var{number} can only be 1 or 2. If it is 1 then branches are preferred over conditional code, if it is 2, then the opposite applies. -@opindex mflush-trap=@var{number} +@opindex mflush-trap @item -mflush-trap=@var{number} Specifies the trap number to use to flush the cache. The default is 12. Valid numbers are between 0 and 15 inclusive. @@ -29201,7 +29201,7 @@ Specifies the trap number to use to flush the cache. The default is @item -mno-flush-trap Specifies that the cache cannot be flushed by using a trap. -@opindex mflush-func=@var{name} +@opindex mflush-func @item -mflush-func=@var{name} Specifies the name of the operating system function to call to flush the cache. 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Sat, 06 Dec 2025 16:10:55 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:55 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, schwab@linux-m68k.org Subject: [PATCH 09/20] doc, m68k: Clean up M680x0 option documentation [PR122243] [PR119404] Date: Sat, 6 Dec 2025 17:10:19 -0700 Message-Id: <20251207001030.1024365-10-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 PR target/119404 * config/m68k/m68k.opt (mlra): Fix typo in help string. * doc/invoke.texi (Option Summary) : Remove redundant -mno- forms from the list. (M680x0 Options): Combine documentation for -mshort, mbitfield, -msep-data, -mid-shared-library with that for their respective negatives that were formerly separately listed. Add missing @opindex entries. --- gcc/config/m68k/m68k.opt | 2 +- gcc/doc/invoke.texi | 65 +++++++++++++++++++++------------------- 2 files changed, 36 insertions(+), 31 deletions(-) diff --git a/gcc/config/m68k/m68k.opt b/gcc/config/m68k/m68k.opt index 35f86ba11ff..afd1b494eef 100644 --- a/gcc/config/m68k/m68k.opt +++ b/gcc/config/m68k/m68k.opt @@ -148,7 +148,7 @@ Use 32-bit offsets in jump tables rather than 16-bit offsets. mlra Target Var(m68k_lra_p) Undocumented -Usa LRA for reload instead of the old reload framework. This option is +Use LRA for reload instead of the old reload framework. This option is experimental, and it may be removed in future versions of the compiler. mnobitfield diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2ce6462c66d..d5c8b411474 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1186,12 +1186,12 @@ Objective-C and Objective-C++ Dialects}. @gccoptlist{-march=@var{arch} -mcpu=@var{cpu} -mtune=@var{tune} -m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 -m68060 -mcpu32 -m5200 -m5206e -m528x -m5307 -m5407 --mcfv4e -mbitfield -mno-bitfield -mc68000 -mc68020 --mnobitfield -mrtd -mno-rtd -mdiv -mno-div -mshort --mno-short -mhard-float -m68881 -msoft-float -mpcrel --malign-int -mstrict-align -msep-data -mno-sep-data --mshared-library-id=n -mid-shared-library -mno-id-shared-library --mxgot -mno-xgot -mlong-jump-table-offsets} +-mcfv4e -mbitfield -mc68000 -mc68020 +-mrtd -mdiv -mshort +-mhard-float -m68881 -msoft-float -mpcrel +-malign-int -mstrict-align -msep-data +-mshared-library-id=@var{n} -mid-shared-library +-mxgot -mlong-jump-table-offsets} @emph{MCore Options} (@ref{MCore Options}) @gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @@ -29457,31 +29457,30 @@ example, the default is ``off'' for @option{-mcpu=5206} and ``on'' for GCC defines the macro @code{__mcfhwdiv__} when this option is enabled. @opindex mshort +@opindex mno-short @item -mshort +@itemx -mno-short Consider type @code{int} to be 16 bits wide, like @code{short int}. Additionally, parameters passed on the stack are also aligned to a 16-bit boundary even on targets whose API mandates promotion to 32-bit. - -@opindex mno-short -@item -mno-short -Do not consider type @code{int} to be 16 bits wide. This is the default. - -@opindex mnobitfield -@opindex mno-bitfield -@item -mnobitfield -@itemx -mno-bitfield -Do not use the bit-field instructions. The @option{-m68000}, @option{-mcpu32} -and @option{-m5200} options imply @w{@option{-mnobitfield}}. +This option is disabled by default. @opindex mbitfield +@opindex mno-bitfield +@opindex mnobitfield @item -mbitfield -Do use the bit-field instructions. The @option{-m68020} option implies -@option{-mbitfield}. This is the default if you use a configuration -designed for a 68020. +@itemx -mno-bitfield +@itemx -mnobitfield +Control use of the bit-field instructions. +The @option{-m68000}, @option{-mcpu32} +and @option{-m5200} options imply @w{@option{-mnobitfield}}; +the @option{-m68020} option implies @option{-mbitfield}. @opindex mrtd +@opindex mno-rtd @item -mrtd -Use a different function-calling convention, in which functions +@itemx -mno-rtd +Control use of a different function-calling convention, in which functions that take a fixed number of arguments return with the @code{rtd} instruction, which pops their arguments while returning. This saves one instruction in the caller since there is no need to pop @@ -29533,26 +29532,32 @@ not presently supported with @option{-mpcrel}, though this could be supported fo Do not (do) assume that unaligned memory references are handled by the system. +@opindex msep-data +@opindex mno-sep-data @item -msep-data -Generate code that allows the data segment to be located in a different +@itemx -mno-sep-data +With @option{-msep-data}, +generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute-in-place in an environment without virtual memory management. This option implies @option{-fPIC}. -@item -mno-sep-data -Generate code that assumes that the data segment follows the text segment. -This is the default. +This option is disabled by default; GCC +generates code that assumes that the data segment follows the text segment. +@opindex mid-shared-library +@opindex mno-id-shared-libary @item -mid-shared-library -Generate code that supports shared libraries via the library ID method. +@itemx -mno-id-shared-library +If enabled, generate code that supports shared libraries via the +library ID method. This allows for execute-in-place and shared libraries in an environment without virtual memory management. This option implies @option{-fPIC}. -@item -mno-id-shared-library -Generate code that doesn't assume ID-based shared libraries are being used. -This is the default. +This option is disabled by default. -@item -mshared-library-id=n +@opindex mshared-library-id +@item -mshared-library-id=@var{n} Specifies the identification number of the ID-based shared library being compiled. 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(MCore Options): Disambiguate documentation for -mbig-endian/-mlittle-endian and -m210/-m340. --- gcc/doc/invoke.texi | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d5c8b411474..4ff7c2deef3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1194,10 +1194,10 @@ Objective-C and Objective-C++ Dialects}. -mxgot -mlong-jump-table-offsets} @emph{MCore Options} (@ref{MCore Options}) -@gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates --mno-relax-immediates -mwide-bitfields -mno-wide-bitfields --m4byte-functions -mno-4byte-functions -mcallgraph-data --mno-callgraph-data -mslow-bytes -mno-slow-bytes -mno-lsim +@gccoptlist{-mhardlit -mdiv -mrelax-immediates +-mwide-bitfields +-m4byte-functions -mcallgraph-data +-mslow-bytes -mno-lsim -mlittle-endian -mbig-endian -m210 -m340 -mstack-increment} @emph{MicroBlaze Options} (@ref{MicroBlaze Options}) @@ -29658,14 +29658,18 @@ Prefer word access when reading byte quantities. @opindex mbig-endian @item -mlittle-endian @itemx -mbig-endian -Generate code for a little-endian target. +Generate code for a little- or big-endian target, respectively. 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Sat, 06 Dec 2025 16:10:59 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:10:59 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: eager@eagercon.com Subject: [PATCH 11/20] doc, microblaze: Clean up MicroBlaze option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:21 -0700 Message-Id: <20251207001030.1024365-12-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * config/microblaze/microblaze.opt (Zxl-mode-bootstrap): Mark as "Undocumented". (Zxl-mode-executable): Likewise. (Zxl-mode-novectors): Likewise. (Zxl-mode-xilkernel): Likewise. (Zxl-mode-xmdstub): Likewise. (mxl-stack-check): Likewise. (mno-clearbss): Likewise. (mxl-mode-executable): Make help string more useful. (mxl-mode-xmdstub): Likewise. (mxl-mode-bootstrap): Likewise. (mxl-mode-novectors): Likewise. (mxl-mode-xilkernel): Mark as "Undocumented". * doc/invoke.texi (Option Summary) : Delete entries for obsolete options now explicitly undocumented, and add missing -mxl-prefetch option. (MicroBlaze Options): Add missing @opindex entries for negative option forms and list negative forms explicitly when appropriate. Delete documentation for obsolete/deprecated options. Add missing @opindex entries for the m[no-]xml-mode- options. Add missing documentation for -mxl-prefetch. --- gcc/config/microblaze/microblaze.opt | 24 ++++++++-------- gcc/doc/invoke.texi | 43 +++++++++++++++++++--------- 2 files changed, 41 insertions(+), 26 deletions(-) diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt index 639557721fb..8a2aa6ea411 100644 --- a/gcc/config/microblaze/microblaze.opt +++ b/gcc/config/microblaze/microblaze.opt @@ -21,19 +21,19 @@ ; . */ Zxl-mode-bootstrap -Driver +Driver Undocumented Zxl-mode-executable -Driver +Driver Undocumented Zxl-mode-novectors -Driver +Driver Undocumented Zxl-mode-xilkernel -Driver +Driver Undocumented Zxl-mode-xmdstub -Driver +Driver Undocumented msoft-float Target RejectNegative Mask(SOFT_FLOAT) @@ -84,7 +84,7 @@ Target Mask(PATTERN_COMPARE) Use pattern compare instructions. mxl-stack-check -Target Mask(STACK_CHECK) Warn(%qs is deprecated; use -fstack-check) +Target Mask(STACK_CHECK) Warn(%qs is deprecated; use -fstack-check) Undocumented Check for stack overflow at runtime. mxl-gp-opt @@ -92,7 +92,7 @@ Target Mask(XLGPOPT) Use GP relative sdata/sbss sections. mno-clearbss -Target RejectNegative Var(flag_zero_initialized_in_bss, 0) Warn(%qs is deprecated; use -fno-zero-initialized-in-bss) +Target RejectNegative Var(flag_zero_initialized_in_bss, 0) Warn(%qs is deprecated; use -fno-zero-initialized-in-bss) Undocumented Clear the BSS to zero and place zero initialized in BSS. mxl-multiply-high @@ -109,19 +109,19 @@ Use hardware floating point square root instruction. mxl-mode-executable Target Mask(XL_MODE_EXECUTABLE) -Description for mxl-mode-executable. +Build application as normal executable. mxl-mode-xmdstub Target Mask(XL_MODE_XMDSTUB) -Description for mxl-mode-xmdstub. +Build application for use with xmdstub debug agent. mxl-mode-bootstrap Target Mask(XL_MODE_BOOTSTRAP) -Description for mxl-mode-bootstrap. +Build application to be loaded using a bootloader. mxl-mode-novectors Target Mask(XL_MODE_NOVECTORS) -Description for mxl-mode-novectors. +Build application without any of the MicroBlaze vectors. mxl-prefetch Target Mask(PREFETCH) @@ -132,4 +132,4 @@ Target Mask(PIC_DATA_TEXT_REL) Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE). mxl-mode-xilkernel -Target +Target Undocumented diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4ff7c2deef3..6a0c2e57ad8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1203,10 +1203,10 @@ Objective-C and Objective-C++ Dialects}. @emph{MicroBlaze Options} (@ref{MicroBlaze Options}) @gccoptlist{-msoft-float -mhard-float -msmall-divides -mcpu=@var{cpu} -mmemcpy -mxl-soft-mul -mxl-soft-div -mxl-barrel-shift --mxl-pattern-compare -mxl-stack-check -mxl-gp-opt -mno-clearbss +-mxl-pattern-compare -mxl-gp-opt -mxl-multiply-high -mxl-float-convert -mxl-float-sqrt -mbig-endian -mlittle-endian -mxl-reorder -mxl-mode-@var{app-model} --mpic-data-is-text-relative} +-mxl-prefetch -mpic-data-is-text-relative} @emph{MIPS Options} (@ref{MIPS Options}) @gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @@ -29700,13 +29700,10 @@ Use software emulation for floating point (default). Use hardware floating-point instructions. @opindex mmemcpy +@opindex mno-memcpy @item -mmemcpy Do not optimize block moves, use @code{memcpy}. -@opindex mno-clearbss -@item -mno-clearbss -This option is deprecated. Use @option{-fno-zero-initialized-in-bss} instead. - @opindex mcpu= @item -mcpu=@var{cpu-type} Use features of, and schedule code for, the given CPU. @@ -29716,42 +29713,49 @@ where @var{X} is a major version, @var{YY} is the minor version, and @samp{v4.00.b}, @samp{v5.00.a}, @samp{v5.00.b}, @samp{v6.00.a}. @opindex mxl-soft-mul +@opindex mno-xl-soft-mul @item -mxl-soft-mul -Use software multiply emulation (default). +@itemx -mno-xl-soft-mul +Use software multiply emulation. This is enabled by default. @opindex mxl-soft-div +@opindex mno-xl-soft-div @item -mxl-soft-div -Use software emulation for divides (default). +@itemx -mno-xl-soft-div +Use software emulation for divides. This is enabled by default. @opindex mxl-barrel-shift +@opindex mno-xl-barrel-shift @item -mxl-barrel-shift Use the hardware barrel shifter. @opindex mxl-pattern-compare +@opindex mno-xl-pattern-compare @item -mxl-pattern-compare Use pattern compare instructions. @opindex msmall-divides +@opindex mno-small-divides @item -msmall-divides Use table lookup optimization for small signed integer divisions. -@opindex mxl-stack-check -@item -mxl-stack-check -This option is deprecated. Use @option{-fstack-check} instead. - @opindex mxl-gp-opt +@opindex mno-xl-gp-opt @item -mxl-gp-opt Use GP-relative @code{.sdata}/@code{.sbss} sections. @opindex mxl-multiply-high +@opindex mno-xl-multiply-high @item -mxl-multiply-high Use multiply high instructions for high part of 32x32 multiply. @opindex mxl-float-convert +@opindex mno-xl-float-convert @item -mxl-float-convert Use hardware floating-point conversion instructions. @opindex mxl-float-sqrt +@opindex mno-xl-float-sqrt @item -mxl-float-sqrt Use hardware floating-point square root instruction. @@ -29767,6 +29771,14 @@ Generate code for a little-endian target. @item -mxl-reorder Use reorder instructions (swap and byte reversed load/store). +@opindex mxl-mode-executable +@opindex mno-xl-mode-executable +@opindex mxl-mode-xmdstub +@opindex mno-xl-mode-xmdstub +@opindex mxl-mode-bootstrap +@opindex mno-xl-mode-bootstrap +@opindex mxl-mode-novectors +@opindex mno-xl-mode-novectors @item -mxl-mode-@var{app-model} Select application model @var{app-model}. Valid models are @table @samp @@ -29790,10 +29802,13 @@ MicroBlaze vectors. This option may be useful for applications running within a monitoring application. This model uses @file{crt3.o} as a startup file. @end table -Option @option{-xl-mode-@var{app-model}} is a deprecated alias for -@option{-mxl-mode-@var{app-model}}. +@opindex mxl-prefetch +@opindex mno-xl-prefetch +@item -mxl-prefetch +Enable insertion of prefetch (@code{wic}) instructions at call sites. @opindex mpic-data-is-text-relative +@opindex mno-pic-data-is-text-relative @item -mpic-data-is-text-relative Assume that the displacement between the text and data segments is fixed at static link time. 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Sat, 06 Dec 2025 16:11:00 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:00 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: syq@gcc.gnu.org Subject: [PATCH 12/20] doc, mips: Clean up MIPS option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:22 -0700 Message-Id: <20251207001030.1024365-13-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * config/mips/mips.opt (mfix4300): Mark as "Undocumented". (mnoasmopt): Likewise. * doc/invoke.texi (Option Summary) : Add missing entries for -mel/-meb. Only list one of -mfoo/-mno-foo. (MIPS Options): Document -meb/-mel as synonyms for -EB/-EL. Add missing @opindex entries. Document -mmsa. Minor copy-editing for grammar and jargon issues. --- gcc/config/mips/mips.opt | 4 +- gcc/doc/invoke.texi | 127 ++++++++++++++++++++------------------- 2 files changed, 67 insertions(+), 64 deletions(-) diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index f07db5ad7f4..b2c715220e1 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -211,7 +211,7 @@ Target Var(TARGET_FIX_VR4130) Work around VR4130 mflo/mfhi errata. mfix4300 -Target Var(TARGET_4300_MUL_FIX) +Target Var(TARGET_4300_MUL_FIX) Undocumented Work around an early 4300 hardware bug. mfp-exceptions @@ -478,7 +478,7 @@ Target Var(TARGET_FRAME_GROWS_DOWNWARDS) Init(1) Undocumented Change the behaviour to grow the frame downwards. noasmopt -Driver +Driver Undocumented mload-store-pairs Target Var(TARGET_LOAD_STORE_PAIRS) Init(1) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6a0c2e57ad8..ba58398e7c3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1209,64 +1209,39 @@ Objective-C and Objective-C++ Dialects}. -mxl-prefetch -mpic-data-is-text-relative} @emph{MIPS Options} (@ref{MIPS Options}) -@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} +@gccoptlist{-EL -EB -mel -meb -march=@var{arch} -mtune=@var{arch} -mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips32r3 -mips32r5 -mips32r6 -mips64 -mips64r2 -mips64r3 -mips64r5 -mips64r6 --mips16 -mno-mips16 -mflip-mips16 --minterlink-compressed -mno-interlink-compressed --minterlink-mips16 -mno-interlink-mips16 --mabi=@var{abi} -mabicalls -mno-abicalls --mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot +-mips16 -mmips16e2 -mflip-mips16 +-minterlink-compressed -minterlink-mips16 +-mabi=@var{abi} -mabicalls -mshared -mplt -mxgot -mgp32 -mgp64 -mfp32 -mfpxx -mfp64 -mhard-float -msoft-float --mno-float -msingle-float -mdouble-float --modd-spreg -mno-odd-spreg +-mno-float -msingle-float -mdouble-float -modd-spreg -mabs=@var{mode} -mnan=@var{encoding} --mdsp -mno-dsp -mdspr2 -mno-dspr2 --mmcu -mmno-mcu --meva -mno-eva --mvirt -mno-virt --mxpa -mno-xpa --mcrc -mno-crc --mginv -mno-ginv --mmicromips -mno-micromips --mmsa -mno-msa --mloongson-mmi -mno-loongson-mmi --mloongson-ext -mno-loongson-ext --mloongson-ext2 -mno-loongson-ext2 +-mdsp -mdspr2 -mmcu -meva -mvirt -mxpa -mcrc -mginv +-mmicromips -mmsa +-mloongson-mmi -mloongson-ext -mloongson-ext2 -mfpu=@var{fpu-type} --msmartmips -mno-smartmips --mpaired-single -mno-paired-single -mdmx -mno-mdmx --mips3d -mno-mips3d -mmt -mno-mt -mllsc -mno-llsc --mlong64 -mlong32 -msym32 -mno-sym32 --G@var{num} -mlocal-sdata -mno-local-sdata --mextern-sdata -mno-extern-sdata -mgpopt -mno-gopt --membedded-data -mno-embedded-data --muninit-const-in-rodata -mno-uninit-const-in-rodata +-msmartmips -mpaired-single -mdmx -mips3d -mmt -mllsc +-mlong64 -mlong32 -msym32 +-G@var{num} -mno-local-sdata -mno-extern-sdata -mno-gopt +-membedded-data -muninit-const-in-rodata -mcode-readable=@var{setting} --msplit-addresses -mno-split-addresses --mexplicit-relocs -mno-explicit-relocs --mexplicit-relocs=@var{release} --mcheck-zero-division -mno-check-zero-division --mdivide-traps -mdivide-breaks --mload-store-pairs -mno-load-store-pairs --mstrict-align -mno-strict-align --mno-unaligned-access -munaligned-access --mmemcpy -mno-memcpy -mlong-calls -mno-long-calls --mmad -mno-mad -mimadd -mno-imadd -mfused-madd -mno-fused-madd -nocpp --mfix-24k -mno-fix-24k --mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 --mfix-r5900 -mno-fix-r5900 --mfix-r10000 -mno-fix-r10000 -mfix-rm7000 -mno-fix-rm7000 --mfix-vr4120 -mno-fix-vr4120 --mfix-vr4130 -mno-fix-vr4130 -mfix-sb1 -mno-fix-sb1 +-msplit-addresses -mexplicit-relocs -mexplicit-relocs=@var{release} +-mno-check-zero-division -mdivide-traps -mdivide-breaks +-mno-load-store-pairs +-mstrict-align -mno-unaligned-access +-mmemcpy -mlong-calls +-mmad -mimadd -mno-fused-madd -nocpp +-mfix-24k -mfix-r4000 -mfix-r4400 -mfix-r5900 +-mfix-r10000 -mfix-rm7000 -mfix-vr4120 -mfix-vr4130 -mfix-sb1 +-mr10k-cache-barrier=@var{setting} -mflush-func=@var{func} -mno-flush-func --mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely +-mbranch-cost=@var{num} -mbranch-likely -mcompact-branches=@var{policy} --mfp-exceptions -mno-fp-exceptions --mvr4130-align -mno-vr4130-align -msynci -mno-synci --mlxc1-sxc1 -mno-lxc1-sxc1 -mmadd4 -mno-madd4 --mrelax-pic-calls -mno-relax-pic-calls -mmcount-ra-address --mframe-header-opt -mno-frame-header-opt} +-mno-fp-exceptions -mvr4130-align -msynci -mno-lxc1-sxc1 -mno-madd4 +-mno-relax-pic-calls -mmcount-ra-address +-mframe-header-opt} @emph{MMIX Options} (@ref{MMIX Options}) @gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @@ -29823,11 +29798,16 @@ text address instead of GOT since PC-relative addressing is not supported. @table @gcctabopt @opindex EB +@opindex meb +@opindex mno-el @item -EB +@itemx -meb Generate big-endian code. @opindex EL +@opindex mel @item -EL +@itemx -mel Generate little-endian code. This is the default for @samp{mips*el-*-*} configurations. @@ -29995,7 +29975,9 @@ Use (do not use) the MIPS16e2 ASE. This option modifies the behavior of the @option{-mips16} option such that it targets the MIPS16e2 ASE@. @opindex mflip-mips16 +@opindex mno-flip-mips16 @item -mflip-mips16 +@itemx -mflip-mips16 Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code. @@ -30069,6 +30051,8 @@ Generate (do not generate) code that is suitable for SVR4-style dynamic objects. @option{-mabicalls} is the default for SVR4-based systems. +@opindex mshared +@opindex mno-shared @item -mshared @itemx -mno-shared Generate (do not generate) code that is fully position-independent, @@ -30349,6 +30333,12 @@ Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions. @itemx -mno-ginv Use (do not use) the MIPS Global INValidate (GINV) instructions. +@opindex mmsa +@opindex mno-msa +@item -mmsa +@itemx -mno-msa +Use (do not use) the MIPS MSA extension instructions. + @opindex mloongson-mmi @opindex mno-loongson-mmi @item -mloongson-mmi @@ -30564,10 +30554,11 @@ to support bonding. @itemx -munaligned-access @itemx -mno-unaligned-access Disable (enable) direct unaligned access for MIPS Release 6. -MIPSr6 requires load/store unaligned-access support, by hardware or -trap&emulate. So @option{-mstrict-align} may be needed by kernel. The +MIPSr6 requires load/store unaligned-access support, either by hardware or +by trapping and emulation. In the latter case @option{-mstrict-align} +may be needed by the operating system kernel. The options @option{-munaligned-access} and @option{-mno-unaligned-access} -are obsoleted, and only for backward-compatible. +are obsolete, and only provided for backward compatibility. @opindex mmemcpy @opindex mno-memcpy @@ -30676,6 +30667,7 @@ branch-likely instructions. @option{-mfix-r10000} is the default when otherwise. @opindex mfix-r5900 +@opindex mno-fix-r5900 @item -mfix-r5900 @itemx -mno-fix-r5900 Do not attempt to schedule the preceding instruction into the delay slot @@ -30686,12 +30678,14 @@ execute only once or twice, due to a hardware bug in the R5900 chip. The workaround is implemented by the assembler rather than by GCC@. @opindex mfix-rm7000 +@opindex mno-fix-rm7000 @item -mfix-rm7000 @itemx -mno-fix-rm7000 Work around the RM7000 @code{dmult}/@code{dmultu} errata. The workarounds are implemented by the assembler rather than by GCC@. @opindex mfix-vr4120 +@opindex mno-fix-vr4120 @item -mfix-vr4120 @itemx -mno-fix-vr4120 Work around certain VR4120 errata: @@ -30710,7 +30704,9 @@ Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself. @opindex mfix-vr4130 +@opindex mno-fix-vr4130 @item -mfix-vr4130 +@itemx -mno-fix-vr4130 Work around the VR4130 @code{mflo}/@code{mfhi} errata. The workarounds are implemented by the assembler rather than by GCC, although GCC avoids using @code{mflo} and @code{mfhi} if the @@ -30718,6 +30714,7 @@ VR4130 @code{macc}, @code{macchi}, @code{dmacc} and @code{dmacchi} instructions are available instead. @opindex mfix-sb1 +@opindex mno-fix-sb1 @item -mfix-sb1 @itemx -mno-fix-sb1 Work around certain SB-1 CPU core errata. @@ -30828,27 +30825,28 @@ and MIPS64 architectures specifically deprecate their use. @item -mcompact-branches=never @itemx -mcompact-branches=optimal @itemx -mcompact-branches=always -These options control which form of branches will be generated. The +These options control which form of branches are generated. The default is @option{-mcompact-branches=optimal}. The @option{-mcompact-branches=never} option ensures that compact branch -instructions will never be generated. +instructions are never generated. The @option{-mcompact-branches=always} option ensures that a compact -branch instruction will be generated if available for MIPS Release 6 onwards. +branch instruction is generated if available for MIPS Release 6 onwards. If a compact branch instruction is not available (or pre-R6), -a delay slot form of the branch will be used instead. +a delay slot form of the branch is used instead. -If it is used for MIPS16/microMIPS targets, it will be just ignored now. +If it is used for MIPS16/microMIPS targets, it is just ignored now. The behavior for MIPS16/microMIPS may change in future, since they do have some compact branch instructions. -The @option{-mcompact-branches=optimal} option will cause a delay slot +The @option{-mcompact-branches=optimal} option causes a delay slot branch to be used if one is available in the current ISA and the delay slot is successfully filled. If the delay slot is not filled, a compact -branch will be chosen if one is available. +branch is chosen if one is available. @opindex mfp-exceptions +@opindex mno-fp-exceptions @item -mfp-exceptions @itemx -mno-fp-exceptions Specifies whether FP exceptions are enabled. This affects how @@ -30873,6 +30871,7 @@ It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level @option{-O3}. @opindex msynci +@opindex mno-synci @item -msynci @itemx -mno-synci Enable (disable) generation of @code{synci} instructions on @@ -30889,6 +30888,7 @@ does not invalidate the instruction caches on all cores and may lead to undefined behavior. @opindex mrelax-pic-calls +@opindex mno-relax-pic-calls @item -mrelax-pic-calls @itemx -mno-relax-pic-calls Try to turn PIC calls that are normally dispatched via register @@ -30923,23 +30923,26 @@ if @var{ra-address} is nonnull. The default is @option{-mno-mcount-ra-address}. @opindex mframe-header-opt +@opindex mno-frame-header-opt @item -mframe-header-opt @itemx -mno-frame-header-opt Enable (disable) frame header optimization in the o32 ABI. When using the -o32 ABI, calling functions will allocate 16 bytes on the stack for the called +o32 ABI, calling functions allocates 16 bytes on the stack for the called function to write out register arguments. When enabled, this optimization -will suppress the allocation of the frame header if it can be determined that +suppresses the allocation of the frame header if it can be determined that it is unused. This optimization is off by default at all optimization levels. @opindex mlxc1-sxc1 +@opindex mno-lxc1-sxc1 @item -mlxc1-sxc1 @itemx -mno-lxc1-sxc1 When applicable, enable (disable) the generation of @code{lwxc1}, @code{swxc1}, @code{ldxc1}, @code{sdxc1} instructions. Enabled by default. @opindex mmadd4 +@opindex mno-madd4 @item -mmadd4 @itemx -mno-madd4 When applicable, enable (disable) the generation of 4-operand @code{madd.s}, From patchwork Sun Dec 7 00:10:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandra Loosemore X-Patchwork-Id: 126079 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B242C4B812D0 for ; Sun, 7 Dec 2025 00:22:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B242C4B812D0 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=vx8x6amv X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-f65.google.com (mail-ot1-f65.google.com [209.85.210.65]) by sourceware.org (Postfix) with ESMTPS id 5D15D41436C5 for ; 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Sat, 06 Dec 2025 16:11:04 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:03 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, aoliva@gcc.gnu.org Subject: [PATCH 14/20] doc, mn10300: Clean up MN10300 option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:24 -0700 Message-Id: <20251207001030.1024365-15-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * doc/invoke.texi (Option Summary) : Remove redundant -mno- forms from the list. (MN10300 Options): Combine the documentation for -mmult-bug, -mam33, -mliw, and -msetlb with the entries for the respective negative forms. List and index the negative forms -mno-am33-2, -mno-am34, -mno-return-pointer-on-d0, -mno-mul.x. --- gcc/doc/invoke.texi | 71 +++++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 35 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b8787f1f408..20947fd5e30 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1251,10 +1251,10 @@ Objective-C and Objective-C++ Dialects}. @emph{MN10300 Options} (@ref{MN10300 Options}) @gccoptlist{-mmult-bug -mno-mult-bug --mno-am33 -mam33 -mam33-2 -mam34 +-mam33 -mam33-2 -mam34 -mtune=@var{cpu-type} --mreturn-pointer-on-d0 --mno-crt0 -mrelax -mliw -msetlb} +-mno-return-pointer-on-d0 +-mno-crt0 -mrelax -mno-liw -mno-setlb} @emph{Moxie Options} (@ref{Moxie Options}) @gccoptlist{-meb -mel -mmul.x -mno-crt0} @@ -31044,31 +31044,32 @@ These @option{-m} options are defined for Matsushita MN10300 architectures: @table @gcctabopt @opindex mmult-bug -@item -mmult-bug -Generate code to avoid bugs in the multiply instructions for the MN10300 -processors. This is the default. - @opindex mno-mult-bug -@item -mno-mult-bug -Do not generate code to avoid bugs in the multiply instructions for the -MN10300 processors. +@item -mmult-bug +@itemx -mno-mult-bug +When enabled, generate code to avoid bugs in the multiply instructions +for the MN10300 processors. This is the default. @opindex mam33 -@item -mam33 -Generate code using features specific to the AM33 processor. - @opindex mno-am33 -@item -mno-am33 -Do not generate code using features specific to the AM33 processor. This -is the default. +@item -mam33 +@itemx -mno-am33 +Generate code using features specific to the AM33 processor. +The default is @option{-mno-am33}. @opindex mam33-2 +@opindex mno-am33-2 @item -mam33-2 +@itemx -mno-am33-2 Generate code using features specific to the AM33/2.0 processor. +The default is @option{-mno-am33-2}. @opindex mam34 +@opindex mno-am34 @item -mam34 +@itemx -mno-am34 Generate code using features specific to the AM34 processor. +The default is @option{-mno-am34}. @opindex mtune @item -mtune=@var{cpu-type} @@ -31078,7 +31079,9 @@ type. The CPU type must be one of @samp{mn10300}, @samp{am33}, @samp{am33-2} or @samp{am34}. @opindex mreturn-pointer-on-d0 +@opindex mno-return-pointer-on-d0 @item -mreturn-pointer-on-d0 +@itemx -mno-return-pointer-on-d0 When generating a function that returns a pointer, return the pointer in both @code{a0} and @code{d0}. Otherwise, the pointer is returned only in @code{a0}, and attempts to call such functions without a prototype @@ -31098,28 +31101,24 @@ has an effect when used on the command line for the final link step. This option makes symbolic debugging impossible. @opindex mliw -@item -mliw -Allow the compiler to generate @emph{Long Instruction Word} -instructions if the target is the @samp{AM33} or later. This is the -default. This option defines the preprocessor macro @code{__LIW__}. - @opindex mno-liw -@item -mno-liw -Do not allow the compiler to generate @emph{Long Instruction Word} -instructions. This option defines the preprocessor macro -@code{__NO_LIW__}. +@item -mliw +@itemx -mno-liw +Allow the compiler to generate @emph{Long Instruction Word} +instructions if the target is the @samp{AM33} or later. This option is +enabled by default. +@option{-mliw} defines the preprocessor macro @code{__LIW__}; +@option{-mno-liw} defines the preprocessor macro @code{__NO_LIW__}. @opindex msetlb -@item -msetlb -Allow the compiler to generate the @emph{SETLB} and @emph{Lcc} -instructions if the target is the @samp{AM33} or later. This is the -default. This option defines the preprocessor macro @code{__SETLB__}. - @opindex mno-setlb -@item -mno-setlb -Do not allow the compiler to generate @emph{SETLB} or @emph{Lcc} -instructions. This option defines the preprocessor macro -@code{__NO_SETLB__}. +@item -msetlb +@itemx -mno-setlb +Allow the compiler to generate the @emph{SETLB} and @emph{Lcc} +instructions if the target is the @samp{AM33} or later. This option is +enabled by default. +@option{-msetlb} defines the preprocessor macro @code{__SETLB__}; +@option{-mno-setlb} defines the preprocessor macro @code{__NO_SETLB__}. @end table @@ -31139,8 +31138,10 @@ configurations. Generate little-endian code. @opindex mmul.x +@opindex mno-mul.x @item -mmul.x -Generate mul.x and umul.x instructions. This is the default for +@itemx -mno-mul.x +Generate mul.x and umul.x instructions. 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Sat, 06 Dec 2025 16:11:05 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:04 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: nickc@redhat.com Subject: [PATCH 15/20] doc, msp430: Clean up MSP430 option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:25 -0700 Message-Id: <20251207001030.1024365-16-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * config/msp430/msp32.opt (mcpu): Mark deprecated option as "Undocumented". (mdevices-csv-loc=): Mark option not intended to be used by users as "Undocumented". * doc/invoke.texi (Option Summary) : Fill in argument syntax for options of the form -mfoo=@var{arg}. Don't list deprecated option -mcpu=. Add missing entries for -mwarn-devices-csv and -muse-lower-region-prefix. (MSP430 Options): Similarly document argument syntax in the table @item entries. Add @opindex entries for negative forms. Delete documentation of deprecated -mcpu= option. Add documentation for -muse-lower-region-prefix. Markup and copy-editing fixes throughout the section. --- gcc/config/msp430/msp430.opt | 4 +- gcc/doc/invoke.texi | 102 +++++++++++++++++++---------------- 2 files changed, 58 insertions(+), 48 deletions(-) diff --git a/gcc/config/msp430/msp430.opt b/gcc/config/msp430/msp430.opt index 56dc996f9d9..3767b31d5b0 100644 --- a/gcc/config/msp430/msp430.opt +++ b/gcc/config/msp430/msp430.opt @@ -23,7 +23,7 @@ Target Var(msp430_warn_devices_csv) Init(1) Warn if devices.csv is not found or there are problem parsing it (default: on). mcpu= -Target Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT) +Target Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT) Undocumented Specify the ISA to build for: msp430, msp430x, msp430xv2. Enum @@ -127,7 +127,7 @@ Target Joined RejectNegative ToLower Passes on a request to the assembler to warn about various silicon errata. mdevices-csv-loc= -Target Joined Var(msp430_devices_csv_loc) RejectNegative +Target Joined Var(msp430_devices_csv_loc) RejectNegative Undocumented The path to devices.csv. The GCC driver can normally locate devices.csv itself and pass this option to the compiler, so the user shouldn't need to pass this. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 20947fd5e30..28c4035da6b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1260,11 +1260,13 @@ Objective-C and Objective-C++ Dialects}. @gccoptlist{-meb -mel -mmul.x -mno-crt0} @emph{MSP430 Options} (@ref{MSP430 Options}) -@gccoptlist{-msim -masm-hex -mmcu= -mcpu= -mlarge -msmall -mrelax --mwarn-mcu --mcode-region= -mdata-region= --msilicon-errata= -msilicon-errata-warn= --mhwmult= -minrt -mtiny-printf -mmax-inline-shift=} +@gccoptlist{-msim -masm-hex -mmcu=@var{name} -mlarge -msmall -mrelax +-mwarn-mcu -mwarn-devices-csv +-mcode-region=@var{where} -mdata-region=@var{where} +-muse-lower-region-prefix +-msilicon-errata=@var{name}@r{[},@var{name}@dots{}@r{]} +-msilicon-errata-warn=@var{name}@r{[},@var{name}@dots{}@r{]} +-mhwmult=@var{type} -minrt -mtiny-printf -mmax-inline-shift=@var{n}} @emph{NDS32 Options} (@ref{NDS32 Options}) @gccoptlist{-mbig-endian -mlittle-endian @@ -31159,13 +31161,14 @@ These options are defined for the MSP430: @table @gcctabopt @opindex masm-hex +@opindex mno-asm-hex @item -masm-hex Force assembly output to always use hex constants. Normally such constants are signed decimals, but this option is available for testsuite and/or aesthetic purposes. @opindex mmcu= -@item -mmcu= +@item -mmcu=@var{name} Select the MCU to target. This is used to create a C preprocessor symbol based upon the MCU name, converted to upper case and pre- and post-fixed with @samp{__}. This in turn is used by the @@ -31185,37 +31188,38 @@ command line defines the C preprocessor symbol @code{__XXX__} and cause the linker to search for a script called @file{xxx.ld}. The ISA and hardware multiply supported for the different MCUs is hard-coded -into GCC. However, an external @samp{devices.csv} file can be used to +into GCC. However, an external @file{devices.csv} file can be used to extend device support beyond those that have been hard-coded. -GCC searches for the @samp{devices.csv} file using the following methods in the +GCC searches for the @file{devices.csv} file using the following methods in the given precedence order, where the first method takes precedence over the second which takes precedence over the third. @table @asis -@item Include path specified with @code{-I} and @code{-L} -@samp{devices.csv} is searched for in each of the directories specified by +@item Include path specified with @option{-I} and @option{-L} +@file{devices.csv} is searched for in each of the directories specified by include paths and linker library search paths. -@item Path specified by the environment variable @samp{MSP430_GCC_INCLUDE_DIR} +@item Path specified by the environment variable @env{MSP430_GCC_INCLUDE_DIR} Define the value of the global environment variable -@samp{MSP430_GCC_INCLUDE_DIR} -to the full path to the directory containing devices.csv, and GCC will search -this directory for devices.csv. If devices.csv is found, this directory is +@env{MSP430_GCC_INCLUDE_DIR} +to the full path to the directory containing @file{devices.csv}, +and GCC will search +this directory for @file{devices.csv}. +If @file{devices.csv} is found, this directory is also registered as an include path and linker library path. Header files and linker scripts in this directory can therefore be used without manually -specifying @code{-I} and @code{-L} on the command line. -@item The @samp{msp430-elf@{,bare@}/include/devices} directory -Finally, GCC examines @samp{msp430-elf@{,bare@}/include/devices} from the +specifying @option{-I} and @option{-L} on the command line. +@item The @file{msp430-elf@{,bare@}/include/devices} directory +Finally, GCC examines @file{msp430-elf@{,bare@}/include/devices} from the toolchain root directory. This directory does not exist in a default -installation, but if the user has created it and copied @samp{devices.csv} +installation, but if you have created it and copied @file{devices.csv} there, then the MCU data is read. As above, this directory is also registered as an include path and linker library path. @end table -If none of the above search methods find @samp{devices.csv}, then the +If none of the above search methods find @file{devices.csv}, then the hard-coded MCU data is used. - @opindex mwarn-mcu @opindex mno-warn-mcu @item -mwarn-mcu @@ -31226,13 +31230,8 @@ MCU name specified by the @option{-mmcu} option and the ISA set by the @option{-mhwmult} option. It also toggles warnings about unrecognized MCU names. This option is on by default. -@opindex mcpu= -@item -mcpu= -Specifies the ISA to use. Accepted values are @samp{msp430}, -@samp{msp430x} and @samp{msp430xv2}. This option is deprecated. The -@option{-mmcu=} option should be used to select the ISA. - @opindex msim +@opindex -mno-sim @item -msim Link to the simulator runtime libraries and linker script. Overrides any scripts that would be selected by the @option{-mmcu=} option. @@ -31246,22 +31245,24 @@ Use large-model addressing (20-bit pointers, 20-bit @code{size_t}). Use small-model addressing (16-bit pointers, 16-bit @code{size_t}). @opindex mrelax +@opindex mno-relax @item -mrelax This option is passed to the assembler and linker, and allows the linker to perform certain optimizations that cannot be done until the final link. -@opindex mhwmult= -@item mhwmult= +@opindex mhwmult +@item mhwmult=@var{type} Describes the type of hardware multiply supported by the target. -Accepted values are @samp{none} for no hardware multiply, @samp{16bit} +Accepted values for @var{type} are @samp{none} for no hardware multiply, +@samp{16bit} for the original 16-bit-only multiply supported by early MCUs. @samp{32bit} for the 16/32-bit multiply supported by later MCUs and @samp{f5series} for the 16/32-bit multiply supported by F5-series MCUs. A value of @samp{auto} can also be given. This tells GCC to deduce the hardware multiply support based upon the MCU name provided by the @option{-mmcu} option. If no @option{-mmcu} option is specified or if -the MCU name is not recognized then no hardware multiply support is +the MCU name is not recognized, then no hardware multiply support is assumed. @code{auto} is the default setting. Hardware multiplies are normally performed by calling a library @@ -31275,27 +31276,28 @@ them safe to use inside interrupt handlers as well as in normal code. @opindex minrt @item -minrt -Enable the use of a minimum runtime environment - no static +Enable the use of a minimum runtime environment without support for static initializers or constructors. This is intended for memory-constrained devices. The compiler includes special symbols in some objects that tell the linker and runtime which code fragments are required. @opindex mtiny-printf +@opindex mno-tiny-printf @item -mtiny-printf Enable reduced code size @code{printf} and @code{puts} library functions. The @samp{tiny} implementations of these functions are not reentrant, so must be used with caution in multi-threaded applications. -Support for streams has been removed and the string to be printed will -always be sent to stdout via the @code{write} syscall. The string is not +Support for streams has been removed and the string to be printed are +always sent to stdout via the @code{write} syscall. The string is not buffered before it is sent to write. This option requires Newlib Nano IO, so GCC must be configured with @samp{--enable-newlib-nano-formatted-io}. @opindex mmax-inline-shift= -@item -mmax-inline-shift= -This option takes an integer between 0 and 64 inclusive, and sets +@item -mmax-inline-shift=@var{n} +This option takes an integer @var{n} between 0 and 64 inclusive, and sets the maximum number of inline shift instructions which should be emitted to perform a shift operation by a constant amount. When this value needs to be exceeded, an mspabi helper function is used instead. The default value is 4. @@ -31308,32 +31310,40 @@ this option is divided by 2 and the resulting value used instead. @opindex mcode-region @opindex mdata-region -@item -mcode-region= -@itemx -mdata-region= +@item -mcode-region=@var{where} +@itemx -mdata-region=@var{where} These options tell the compiler where to place functions and data that do not have one of the @code{lower}, @code{upper}, @code{either} or -@code{section} attributes. Possible values are @code{lower}, -@code{upper}, @code{either} or @code{any}. The first three behave -like the corresponding attribute. The fourth possible value - -@code{any} - is the default. It leaves placement entirely up to the +@code{section} attributes. Possible values for @var{where} are @samp{lower}, +@samp{upper}, @samp{either} or @samp{any}. The first three behave +like the corresponding attribute. The fourth possible value, +@samp{any}, is the default. It leaves placement entirely up to the linker script and how it assigns the standard sections (@code{.text}, @code{.data}, etc) to the memory regions. +@opindex muse-lower-region-prefix +@opindex mno-use-lower-region-prefix +@item -muse-lower-region-prefix +Add the @samp{.lower} prefix to section names when compiling with +@option{-mcode-region=lower} or @option{-mdata-region=lower}. Disabled +by default. + @opindex msilicon-errata -@item -msilicon-errata= +@item -msilicon-errata=@var{name}@r{[},@var{name}@dots{}@r{]} This option passes on a request to assembler to enable the fixes for -the named silicon errata. +the named silicon errata. Refer to the assembler documentation for details. @opindex msilicon-errata-warn -@item -msilicon-errata-warn= +@item -msilicon-errata-warn=@var{name}@r{[},@var{name}@dots{}@r{]} This option passes on a request to the assembler to enable warning -messages when a silicon errata might need to be applied. +messages when a named silicon errata might need to be applied. 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(NDS32 Options): Consolidate separate entries for positive and negative forms of the same option. Document missing negative forms in the same style. --- gcc/doc/invoke.texi | 64 ++++++++++++++++++--------------------------- 1 file changed, 26 insertions(+), 38 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 28c4035da6b..77ba685d560 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1271,12 +1271,8 @@ Objective-C and Objective-C++ Dialects}. @emph{NDS32 Options} (@ref{NDS32 Options}) @gccoptlist{-mbig-endian -mlittle-endian -mreduced-regs -mfull-regs --mcmov -mno-cmov --mext-perf -mno-ext-perf --mext-perf2 -mno-ext-perf2 --mext-string -mno-ext-string --mv3push -mno-v3push --m16bit -mno-16bit +-mcmov -mext-perf -mext-perf2 +-mext-string -mv3push -m16bit -misr-vector-size=@var{num} -mcache-block-size=@var{num} -march=@var{arch} @@ -31373,52 +31369,40 @@ Use reduced-set registers for register allocation. Use full-set registers for register allocation. @opindex mcmov -@item -mcmov -Generate conditional move instructions. - @opindex mno-cmov -@item -mno-cmov -Do not generate conditional move instructions. +@item -mcmov +@itemx -mno-cmov +Enable/disable generation of conditional move instructions. @opindex mext-perf -@item -mext-perf -Generate performance extension instructions. - @opindex mno-ext-perf -@item -mno-ext-perf -Do not generate performance extension instructions. +@item -mext-perf +@itemx -mno-ext-perf +Enable/disable generation of performance extension instructions. @opindex mext-perf2 -@item -mext-perf2 -Generate performance extension 2 instructions. - @opindex mno-ext-perf2 -@item -mno-ext-perf2 -Do not generate performance extension 2 instructions. +@item -mext-perf2 +@itemx -mno-ext-perf2 +Enable/disable generation of performance extension 2 instructions. @opindex mext-string -@item -mext-string -Generate string extension instructions. - @opindex mno-ext-string -@item -mno-ext-string -Do not generate string extension instructions. +@item -mext-string +@itemx -mno-ext-string +Enable/disable generation of string extension instructions. @opindex mv3push -@item -mv3push -Generate v3 push25/pop25 instructions. - @opindex mno-v3push -@item -mno-v3push -Do not generate v3 push25/pop25 instructions. +@item -mv3push +@itemx -mno-v3push +Enable/disable generation of v3 push25/pop25 instructions. @opindex m16-bit -@item -m16-bit -Generate 16-bit instructions. - @opindex mno-16-bit -@item -mno-16-bit -Do not generate 16-bit instructions. +@item -m16-bit +@itemx -mno-16-bit +Enable/disable generation of 16-bit instructions. @opindex misr-vector-size @item -misr-vector-size=@var{num} @@ -31449,12 +31433,16 @@ All the text and data segments can be within 4GB addressing space. @end table @opindex mctor-dtor +@opindex mno-ctor-dtor @item -mctor-dtor -Enable constructor/destructor feature. +@itemx -mno-ctor-dtor +Enable/disable constructor/destructor feature. @opindex mrelax +@opindex mno-relax @item -mrelax -Guide linker to relax instructions. +@itemx -mno-relax +Enable/disable linker option to relax instructions. @end table From patchwork Sun Dec 7 00:10:27 2025 Content-Type: text/plain; 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Sat, 06 Dec 2025 16:11:08 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:08 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: tdevries@suse.de, tschwinge@baylibre.com Subject: [PATCH 17/20] doc, nvptx: Clean up documentation of Nvidia PDX Options [PR122243] Date: Sat, 6 Dec 2025 17:10:27 -0700 Message-Id: <20251207001030.1024365-18-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * doc/invoke.texi (Option Summary) : Add several missing options. (Nvidia PTX Options): Correct index entry for -march-map. List negative forms of -moptimize, muniform-simt, and -mgomp. Fix some Texinfo markup issues. --- gcc/doc/invoke.texi | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 77ba685d560..62afc5a66dd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1280,7 +1280,9 @@ Objective-C and Objective-C++ Dialects}. -mctor-dtor -mrelax} @emph{Nvidia PTX Options} (@ref{Nvidia PTX Options}) -@gccoptlist{-m64 -mmainkernel -moptimize} +@gccoptlist{-m64 -march=@var{arch} -misa=@var{arch} -march-map=@var{arch} +-mptx=@var{version} +-mmainkernel -moptimize -msoft-stack -muniform-simt -mgomp} @emph{OpenRISC Options} (@ref{OpenRISC Options}) @gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @@ -31480,7 +31482,7 @@ This option sets the value of the preprocessor macro @item -misa=@var{architecture-string} Alias of @option{-march=}. -@opindex march +@opindex march-map @item -march-map=@var{architecture-string} Select the closest available @option{-march=} value that is not more capable. For instance, for @option{-march-map=sm_50} select @@ -31511,9 +31513,11 @@ Link in code for a __main kernel. This is for stand-alone instead of offloading execution. @opindex moptimize +@opindex mno-optimize @item -moptimize -Apply partitioned execution optimizations. This is the default when any -level of optimization is selected. +@itemx -mno-optimize +Enable/disable partitioned execution optimizations. This option is enabled by +default when any level of optimization is selected. @opindex msoft-stack @opindex mno-soft-stack @@ -31539,11 +31543,15 @@ of testing the compiler; to generate code suitable for linking into programs using OpenMP offloading, use option @option{-mgomp}. @opindex muniform-simt +@opindex mno-uniform-simt @item -muniform-simt -Switch to code generation variant that allows to execute all threads in each +@itemx -mno-uniform-simt +Enable/disable code generation variant that allows execution of +all threads in each warp, while maintaining memory state and side effects as if only one thread in each warp was active outside of OpenMP SIMD regions. All atomic operations -and calls to runtime (malloc, free, vprintf) are conditionally executed (iff +and calls to runtime (@code{malloc}, @code{free}, @code{vprintf}) +are conditionally executed (iff current lane index equals the master lane index), and the register being assigned is copied via a shuffle instruction from the master lane. Outside of SIMD regions lane 0 is the master; inside, each thread sees itself as the @@ -31553,9 +31561,12 @@ regions). Each thread can bitwise-and the bitmask at position @code{tid.y} with current lane index to compute the master lane index. @opindex mgomp +@opindex mno-gomp @item -mgomp -Generate code for use in OpenMP offloading: enables @option{-msoft-stack} and -@option{-muniform-simt} options, and selects corresponding multilib variant. +@itemx -mno-gomp +Enable/disable generation of code for use in OpenMP offloading. +@option{-mgomp} enables @option{-msoft-stack} and +@option{-muniform-simt} options, and selects a corresponding multilib variant. @end table From patchwork Sun Dec 7 00:10:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandra Loosemore X-Patchwork-Id: 126082 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 270AD4077A6C for ; Sun, 7 Dec 2025 00:24:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-f68.google.com (mail-ot1-f68.google.com [209.85.210.68]) by sourceware.org (Postfix) with ESMTPS id 8E6A041436E1 for ; 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Sat, 06 Dec 2025 16:11:09 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:09 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: shorne@gmail.com Subject: [PATCH 18/20] doc, or1k: Clean up OpenRISC option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:28 -0700 Message-Id: <20251207001030.1024365-19-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org I'm not sure what the rationale is for having "RejectNegative" on all of the options that control instruction usage except for -mdouble-float, but with this patch the documentation matches what is in the .opt files. gcc/ChangeLog PR other/122243 * config/or1k/elf.opt (mnewlib): Mark obsolete option as "Undocumented". * config/or1k/or1k.opt (mcmov): Don't use future tense in doc string. (msfimm): Likewise. (mshftimm): Likewise. * doc/invoke.texi (Option Summary) : Don't document -mnewlib. (OpenRISC Options): Likewise. Add @opindex entry for -mno-double-float. Fix more instances of incorrect use of future tense. --- gcc/config/or1k/elf.opt | 2 +- gcc/config/or1k/or1k.opt | 6 +++--- gcc/doc/invoke.texi | 16 ++++++---------- 3 files changed, 10 insertions(+), 14 deletions(-) diff --git a/gcc/config/or1k/elf.opt b/gcc/config/or1k/elf.opt index 28e960ed208..578aba3ba04 100644 --- a/gcc/config/or1k/elf.opt +++ b/gcc/config/or1k/elf.opt @@ -28,6 +28,6 @@ Target RejectNegative Joined Configure the newlib board specific runtime. The default is or1ksim. mnewlib -Target RejectNegative +Target RejectNegative Undocumented This option is ignored; it is provided for compatibility purposes only. This used to select linker and preprocessor options for use with newlib. diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt index d252de08204..9ce8b800ed5 100644 --- a/gcc/config/or1k/or1k.opt +++ b/gcc/config/or1k/or1k.opt @@ -85,7 +85,7 @@ Enum(or1k_cmodel_type) String(large) Value(CMODEL_LARGE) mcmov Target RejectNegative Mask(CMOV) Enable generation of conditional move (l.cmov) instructions. By default the -equivalent will be generated using set and branch. +equivalents are generated using set and branch. mror Target RejectNegative Mask(ROR) @@ -106,11 +106,11 @@ loads are used to perform sign extension. msfimm Target RejectNegative Mask(SFIMM) Enable generation of compare and set flag with immediate (l.sf*i) instructions. -By default extra instructions will be generated to store the immediate to a +By default extra instructions are generated to store the immediate to a register first. mshftimm Target RejectNegative Mask(SHFTIMM) Enable generation of shift with immediate (l.srai, l.srli, l.slli) instructions. -By default extra instructions will be generated to store the immediate to a +By default extra instructions are generated to store the immediate to a register first. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 62afc5a66dd..f403d20bc0b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1285,7 +1285,7 @@ Objective-C and Objective-C++ Dialects}. -mmainkernel -moptimize -msoft-stack -muniform-simt -mgomp} @emph{OpenRISC Options} (@ref{OpenRISC Options}) -@gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div +@gccoptlist{-mboard=@var{name} -mhard-mul -mhard-div -msoft-mul -msoft-div -msoft-float -mhard-float -mdouble-float -munordered-float -mcmov -mror -mrori -msext -msfimm -mshftimm @@ -31580,14 +31580,9 @@ These options are defined for OpenRISC: @opindex mboard @item -mboard=@var{name} -Configure a board specific runtime. This will be passed to the linker for +Configure a board specific runtime. This is passed to the linker for newlib board library linking. The default is @code{or1ksim}. -@opindex mnewlib -@item -mnewlib -This option is ignored; it is for compatibility purposes only. This used to -select linker and preprocessor options for use with newlib. - @opindex msoft-div @opindex mhard-div @item -msoft-div @@ -31610,6 +31605,7 @@ Select software or hardware for floating point operations. The default is software. @opindex mdouble-float +@opindex mno-double-float @item -mdouble-float When @option{-mhard-float} is selected, enables generation of double-precision floating point instructions. By default functions from @file{libgcc} are used @@ -31625,7 +31621,7 @@ compare and set flag operations. @opindex mcmov @item -mcmov Enable generation of conditional move (@code{l.cmov}) instructions. By -default the equivalent will be generated using set and branch. +default the equivalents are generated using set and branch. @opindex mror @item -mror @@ -31646,13 +31642,13 @@ memory loads are used to perform sign extension. @opindex msfimm @item -msfimm Enable generation of compare and set flag with immediate (@code{l.sf*i}) -instructions. By default extra instructions will be generated to store the +instructions. By default extra instructions are generated to store the immediate to a register first. @opindex mshftimm @item -mshftimm Enable generation of shift with immediate (@code{l.srai}, @code{l.srli}, -@code{l.slli}) instructions. By default extra instructions will be generated +@code{l.slli}) instructions. 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Sat, 06 Dec 2025 16:11:11 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:10 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: ni1d@arrl.net Subject: [PATCH 19/20] doc, pdp11: Clean up PDP-11 documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:29 -0700 Message-Id: <20251207001030.1024365-20-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org While working on this patch I saw that this target has an -mlra option that still defaults to off. Although the LRA support was added in 2018 apparently it wasn't robust enough to enable by default. We are supposed to be deleting reload support and all targets that don't use LRA by default in GCC 16, so this target may be declared obsolete very soon, but I've made the documentation of other options consistent with the .opt files and conventions used for other targets anyway in case either somebody who can build/test for this target switches the default (see PR target/113947) or the reload removal is postponed. gcc/ChangeLog PR other/122243 * doc/invoke.texi (Option Summary) : Remove redundant -mno- forms from the list. (PDP-11 Options): Fix some markup issues. Merge documentation of positive and negative forms of -mac0. Index negative forms of -m40, -m45, -msplit, -mlra. --- gcc/doc/invoke.texi | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f403d20bc0b..413259f2fe3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1292,8 +1292,8 @@ Objective-C and Objective-C++ Dialects}. -mcmodel=@var{code-model}} @emph{PDP-11 Options} (@ref{PDP-11 Options}) -@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 --mint32 -mno-int16 -mint16 -mno-int32 +@gccoptlist{-mfpu -msoft-float -mac0 -m40 -m45 -m10 +-mint32 -mint16 -msplit -munix-asm -mdec-asm -mgnu-asm -mlra} @emph{PowerPC Options} @@ -31675,31 +31675,35 @@ These options are defined for the PDP-11: @opindex mfpu @item -mfpu Use hardware FPP floating point. This is the default. (FIS floating -point on the PDP-11/40 is not supported.) Implies -m45. +point on the PDP-11/40 is not supported.) Implies @option{-m45}. @opindex msoft-float @item -msoft-float Do not use hardware floating point. @opindex mac0 -@item -mac0 -Return floating-point results in ac0 (fr0 in Unix assembler syntax). - @opindex mno-ac0 -@item -mno-ac0 -Return floating-point results in memory. This is the default. +@item -mac0 +@itemx -mno-ac0 +With @option{-mac0}, return floating-point results in ac0 +(fr0 in Unix assembler syntax). The default, @option{-mno-ac0}, is +to return floating-point results in memory. @opindex m40 +@opindex mno-40 @item -m40 -Generate code for a PDP-11/40. Implies -msoft-float -mno-split. +Generate code for a PDP-11/40. +Implies @option{-msoft-float} @option{-mno-split}. @opindex m45 +@opindex mno-45 @item -m45 Generate code for a PDP-11/45. This is the default. @opindex m10 @item -m10 -Generate code for a PDP-11/10. Implies -msoft-float -mno-split. +Generate code for a PDP-11/10. +Implies @option{-msoft-float} @option{-mno-split}. @opindex mint16 @opindex mno-int32 @@ -31714,8 +31718,9 @@ Use 16-bit @code{int}. This is the default. Use 32-bit @code{int}. @opindex msplit +@opindex mno-split @item -msplit -Target has split instruction and data space. Implies -m45. +Target has split instruction and data space. Implies @option{-m45}. @opindex munix-asm @item -munix-asm @@ -31730,6 +31735,7 @@ Use DEC assembler syntax. Use GNU assembler syntax. This is the default. @opindex mlra +@opindex mno-lra @item -mlra Use the new LRA register allocator. By default, the old ``reload'' allocator is used. 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Sat, 06 Dec 2025 16:11:12 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:12 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: dimitar@dinux.eu Subject: [PATCH 20/20] doc, pru: Clean up PRU option documentation [PR122243] Date: Sat, 6 Dec 2025 17:10:30 -0700 Message-Id: <20251207001030.1024365-21-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * doc/invoke.texi (Option Summary) : Fix whitespace in option list. (PRU Options): Copy-editing. Index and list negative option forms. --- gcc/doc/invoke.texi | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 413259f2fe3..fe12ee3a139 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1301,7 +1301,7 @@ See RS/6000 and PowerPC Options. @emph{PRU Options} (@ref{PRU Options}) @gccoptlist{-mmcu=@var{mcu} -minrt -mno-relax -mloop --mmul -mfillzero -mabi=@var{variant}} +-mmul -mfillzero -mabi=@var{variant}} @emph{RISC-V Options} (@ref{RISC-V Options}) @gccoptlist{-mbranch-cost=@var{N-instruction} @@ -31763,16 +31763,16 @@ are removed. This option disables support for static initializers and constructors. Beware that the compiler could still generate code with static initializers and constructors. It is up to the programmer to ensure that the source -program will not use those features. +program does not use those features. -The minimal startup code would not pass @code{argc} and @code{argv} arguments +The minimal startup code does not pass @code{argc} and @code{argv} arguments to @code{main}, so the latter must be declared as @code{int main (void)}. This is already the norm for most firmware projects. @opindex mmcu @item -mmcu=@var{mcu} -Specify the PRU hardware variant to use. A correspondingly named -spec file would be loaded, passing the memory region sizes to +Specify the PRU hardware variant to use. A correspondingly-named +spec file is loaded, passing the memory region sizes to the linker and defining hardware-specific C macros. Newlib provides only the @code{sim} spec, intended for running @@ -31786,21 +31786,27 @@ Make GCC pass the @option{--no-relax} command-line option to the linker instead of the @option{--relax} option. @opindex mloop +@opindex mno-loop @item -mloop +@itemx -mno-loop Allow (or do not allow) GCC to use the LOOP instruction. @opindex mmul +@opindex mno-mul @item -mmul +@itemx -mno-mul Allow (or do not allow) GCC to use the PRU multiplier unit. @opindex mfillzero +@opindex mno-fillzero @item -mfillzero +@itemx -mno-fillzero Allow (or do not allow) GCC to use the FILL and ZERO instructions. @opindex mabi @item -mabi=@var{variant} Specify the ABI variant to output code for. @option{-mabi=ti} selects the -unmodified TI ABI while @option{-mabi=gnu} selects a GNU variant that copes +unmodified TI ABI, while @option{-mabi=gnu} selects a GNU variant that copes more naturally with certain GCC assumptions. These are the differences: @table @samp @@ -31816,7 +31822,8 @@ GNU always passes and expects a valid return value pointer. @item Size Of Struct Containing Bit-fields TI ABI mandates that struct size is determined by the bit-field type, if it -contains any. Whereas GNU allocates the smallest amount of bytes which would +contains any. On the other hand, +GNU allocates the smallest amount of bytes which would fit the bit-field. For example, TI ABI reserves 4 bytes for this struct, whereas GNU reserves @@ -31831,7 +31838,7 @@ TI ABI mandates that volatile bit-fields are accessed using their type. In contrast, GNU ABI uses the smallest integer type fitting the bit-field. For example, TI ABI requires a single load of 4 bytes for the -following bit-field. Whereas GNU generates a load of 1 byte: +following bit-field. GNU generates a load of 1 byte: @smallexample struct S @{ volatile int i:1; @};