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client-ip=172.205.89.229; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (172.205.89.229) by AM1PEPF000252DA.mail.protection.outlook.com (10.167.16.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9412.4 via Frontend Transport; Fri, 5 Dec 2025 10:57:12 +0000 Received: from AZ-NEU-EX03.Arm.com (10.240.25.137) by AZ-NEU-EX04.Arm.com (10.240.25.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 5 Dec 2025 10:57:07 +0000 Received: from e120703.cambridge.arm.com (10.2.81.20) by mail.arm.com (10.240.25.137) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 5 Dec 2025 10:57:07 +0000 From: Srinath Parvathaneni To: CC: , , , Srinath Parvathaneni , Matthew Malcomson Subject: [PATCH v2 1/3] aarch64: Add support for POE2 instructions. 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CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(14060799003)(35042699022)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2025 10:58:21.9806 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e1548c0-425e-4231-f92e-08de33ed34dc X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C6.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR08MB7934 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_NONE, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch adds support for FEAT_S1POE2 feature enabled by "+poe2" flag along with support for following instructions. * TCHANGEB (immediate) * TCHANGEB (register) * TCHANGEF (immediate) * TCHANGEF (register) A new operand AARCH64_OPND_NOT_BALANCED is added to the code in this patch to support the new optional argument "NB" (not_balanced) which is a 1-bit field in the encoding for all the above mentioned instructions. Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath Co-authored-by: Matthew Malcomson --- gas/config/tc-aarch64.c | 29 ++++++++ gas/doc/c-aarch64.texi | 2 + gas/testsuite/gas/aarch64/poe2-invalid-1.d | 4 ++ gas/testsuite/gas/aarch64/poe2-invalid-1.l | 63 ++++++++++++++++++ gas/testsuite/gas/aarch64/poe2-invalid-1.s | 77 ++++++++++++++++++++++ gas/testsuite/gas/aarch64/poe2-invalid-2.d | 4 ++ gas/testsuite/gas/aarch64/poe2-invalid-2.l | 61 +++++++++++++++++ gas/testsuite/gas/aarch64/poe2.d | 69 +++++++++++++++++++ gas/testsuite/gas/aarch64/poe2.s | 75 +++++++++++++++++++++ include/opcode/aarch64.h | 5 ++ opcodes/aarch64-asm-2.c | 1 + opcodes/aarch64-dis-2.c | 69 +++++++++++++++---- opcodes/aarch64-opc-2.c | 1 + opcodes/aarch64-opc.c | 11 ++++ opcodes/aarch64-opc.h | 1 + opcodes/aarch64-tbl-2.h | 4 ++ opcodes/aarch64-tbl.h | 20 ++++++ 17 files changed, 482 insertions(+), 14 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/poe2-invalid-1.d create mode 100644 gas/testsuite/gas/aarch64/poe2-invalid-1.l create mode 100644 gas/testsuite/gas/aarch64/poe2-invalid-1.s create mode 100644 gas/testsuite/gas/aarch64/poe2-invalid-2.d create mode 100644 gas/testsuite/gas/aarch64/poe2-invalid-2.l create mode 100644 gas/testsuite/gas/aarch64/poe2.d create mode 100644 gas/testsuite/gas/aarch64/poe2.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 0ca54c3bd40..5eae44b1b8a 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6441,6 +6441,10 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, operand->hint_option = aarch64_hint_options + default_value; break; + case AARCH64_OPND_NOT_BALANCED: + operand->imm.value = default_value; + break; + default: break; } @@ -8173,6 +8177,20 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->barrier = aarch64_barrier_dsb_nxs_options + val; break; + case AARCH64_OPND_NOT_BALANCED: + val = parse_barrier (&str); + if (val != PARSE_FAIL) + info->imm.value = val; + else + { + set_syntax_error (_("the specified operand is not accepted in" + " TCHANGE instruction")); + /* Turn off backtrack as this optional operand is present. */ + backtrack_pos = 0; + goto failure; + } + break; + case AARCH64_OPND_PRFOP: val = parse_pldop (&str); @@ -10512,6 +10530,16 @@ md_begin (void) } } + for (i = 0; i < ARRAY_SIZE (aarch64_nb_options); i++) + { + const char *name = aarch64_nb_options[i].name; + checked_hash_insert (aarch64_barrier_opt_hsh, name, + aarch64_nb_options + i); + /* Also hash the name in the upper case. */ + checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name), + aarch64_nb_options + i); + } + for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++) { const char *name = aarch64_barrier_options[i].name; @@ -10818,6 +10846,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"sb", AARCH64_FEATURE (SB), AARCH64_NO_FEATURES}, {"predres", AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES}, {"predres2", AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)}, + {"poe2", AARCH64_FEATURE (S1POE2), AARCH64_NO_FEATURES}, {"aes", AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)}, {"sm4", AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)}, {"sha3", AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)}, diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 9683d411ce9..2064d22706b 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -267,6 +267,8 @@ automatically cause those extensions to be disabled. @tab Enable additional prediction restriction instructions. @item @code{profile} @tab @tab Enable statistical profiling extensions. +@item @code{poe2} @tab + @tab Enable Permission overlays extension 2. @item @code{ras} @tab @tab Enable the Reliability, Availability and Serviceability extension. @item @code{rasv2} @tab @code{ras} diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.d b/gas/testsuite/gas/aarch64/poe2-invalid-1.d new file mode 100644 index 00000000000..7aa529ce244 --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.d @@ -0,0 +1,4 @@ +#name: Invalid poe2 TCHANGE instructions. +#source: poe2-invalid-1.s +#as: -march=armv8-a+poe2 +#error_output: poe2-invalid-1.l diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.l b/gas/testsuite/gas/aarch64/poe2-invalid-1.l new file mode 100644 index 00000000000..df536613fde --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.l @@ -0,0 +1,63 @@ +.*: Assembler messages: +.*: Error: constant expression required at operand 2 -- `tchangef x0,x31' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,x3' +.*: Error: comma expected between operands at operand 2 -- `tchangef x7' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x15,x30,' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x30,x0,x10' +.*: Error: comma expected between operands at operand 2 -- `tchangef x10 x0' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef #1,#100' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef #10,x0' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x0,x1,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangef x1,x3 nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x3,x7,n' +.*: Error: unexpected characters following instruction at operand 3 -- `tchangef x7,x15,nb,nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x15,x30,Nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x30,x0,nB' +.*: Error: constant expression required at operand 2 -- `tchangef x10,NB,NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,NB' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#128' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x1,#3111' +.*: Error: missing immediate expression at operand 2 -- `tchangef x3,#' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#15' +.*: Error: constant expression required at operand 2 -- `tchangef x10,nb,#127' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10,nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x0,#1,nB' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x1,#3,Nb' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x3,#777,nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x7,#15,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangef x15,#31 NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#63,nb' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,#127' +.*: Error: constant expression required at operand 2 -- `tchangef x10,NB,#128' +.*: Error: constant expression required at operand 2 -- `tchangeb x0,x31' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,x3' +.*: Error: comma expected between operands at operand 2 -- `tchangeb x7' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x15,x30,' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x30,x0,x10' +.*: Error: comma expected between operands at operand 2 -- `tchangeb x10 x0' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb #1,#100' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb #10,x0' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x0,x1,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangeb x1,x3 nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x3,x7,n' +.*: Error: unexpected characters following instruction at operand 3 -- `tchangeb x7,x15,nb,nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x15,x30,Nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x30,x0,nB' +.*: Error: constant expression required at operand 2 -- `tchangeb x10,NB,NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,NB' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#128' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x1,#3111' +.*: Error: missing immediate expression at operand 2 -- `tchangeb x3,#' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#15' +.*: Error: constant expression required at operand 2 -- `tchangeb x10,nb,#127' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10,nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x0,#1,nB' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x1,#3,Nb' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x3,#777,nb' +.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x7,#15,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangeb x15,#31 NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#63,nb' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,#127' +.*: Error: constant expression required at operand 2 -- `tchangeb x10,NB,#128' diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.s b/gas/testsuite/gas/aarch64/poe2-invalid-1.s new file mode 100644 index 00000000000..8c214466b52 --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.s @@ -0,0 +1,77 @@ +#TCHANGEF (register) instructions + tchangef x0, x31 + tchangef x31, x3 + tchangef x7 + tchangef x15, x30, + tchangef x30, x0, x10 + tchangef x10 x0 + tchangef #1, #100 + tchangef #10, x0 + +#TCHANGEF (register) instructions with not_balanced + tchangef x0, x1, nbb + tchangef x1, x3 nb + tchangef x3, x7, n + tchangef x7, x15, nb, nb + tchangef x15, x30, Nb + tchangef x30, x0, nB + tchangef x10, NB, NB + tchangef NB, x10, NB + +#TCHANGEF (immediate) instructions + tchangef x0, #-10 + tchangef x0, #128 + tchangef x1, #3111 + tchangef x3, # + tchangef x31, #15 + tchangef x10, nb, #127 + +#TCHANGEF (immediate) instructions with not_balanced + tchangef x0, #-10, nb + tchangef x0, #1, nB + tchangef x1, #3, Nb + tchangef x3, #777, nb + tchangef x7, #15, nbb + tchangef x15, #31 NB + tchangef x31, #63, nb + tchangef NB, x10, #127 + tchangef x10, NB, #128 + +#TCHANGEB (register) instructions + tchangeb x0, x31 + tchangeb x31, x3 + tchangeb x7 + tchangeb x15, x30, + tchangeb x30, x0, x10 + tchangeb x10 x0 + tchangeb #1, #100 + tchangeb #10, x0 + +#TCHANGEB (register) instructions with not_balanced + tchangeb x0, x1, nbb + tchangeb x1, x3 nb + tchangeb x3, x7, n + tchangeb x7, x15, nb, nb + tchangeb x15, x30, Nb + tchangeb x30, x0, nB + tchangeb x10, NB, NB + tchangeb NB, x10, NB + +#TCHANGEB (immediate) instructions + tchangeb x0, #-10 + tchangeb x0, #128 + tchangeb x1, #3111 + tchangeb x3, # + tchangeb x31, #15 + tchangeb x10, nb, #127 + +#TCHANGEB (immediate) instructions with not_balanced + tchangeb x0, #-10, nb + tchangeb x0, #1, nB + tchangeb x1, #3, Nb + tchangeb x3, #777, nb + tchangeb x7, #15, nbb + tchangeb x15, #31 NB + tchangeb x31, #63, nb + tchangeb NB, x10, #127 + tchangeb x10, NB, #128 diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-2.d b/gas/testsuite/gas/aarch64/poe2-invalid-2.d new file mode 100644 index 00000000000..e6ac680b2a3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-2.d @@ -0,0 +1,4 @@ +#name: TCHANGE instructions without +poe2 flag. +#source: poe2.s +#as: -march=armv8-a +#error_output: poe2-invalid-2.l diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-2.l b/gas/testsuite/gas/aarch64/poe2-invalid-2.l new file mode 100644 index 00000000000..c88442521be --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-2.l @@ -0,0 +1,61 @@ +.*: Assembler messages: +.*: Error: selected processor does not support `tchangef x0,x1' +.*: Error: selected processor does not support `tchangef x1,x3' +.*: Error: selected processor does not support `tchangef x3,x7' +.*: Error: selected processor does not support `tchangef x7,x15' +.*: Error: selected processor does not support `tchangef x15,x30' +.*: Error: selected processor does not support `tchangef x30,x0' +.*: Error: selected processor does not support `tchangef x10,x5' +.*: Error: selected processor does not support `tchangef x0,x1,nb' +.*: Error: selected processor does not support `tchangef x1,x3,nb' +.*: Error: selected processor does not support `tchangef x3,x7,nb' +.*: Error: selected processor does not support `tchangef x7,x15,nb' +.*: Error: selected processor does not support `tchangef x15,x30,NB' +.*: Error: selected processor does not support `tchangef x30,x0,nb' +.*: Error: selected processor does not support `tchangef x10,x5,NB' +.*: Error: selected processor does not support `tchangef x0,#0' +.*: Error: selected processor does not support `tchangef x0,#1' +.*: Error: selected processor does not support `tchangef x1,#3' +.*: Error: selected processor does not support `tchangef x3,#7' +.*: Error: selected processor does not support `tchangef x7,#15' +.*: Error: selected processor does not support `tchangef x15,#31' +.*: Error: selected processor does not support `tchangef x30,#63' +.*: Error: selected processor does not support `tchangef x10,#127' +.*: Error: selected processor does not support `tchangef x0,#0,nb' +.*: Error: selected processor does not support `tchangef x0,#1,nb' +.*: Error: selected processor does not support `tchangef x1,#3,nb' +.*: Error: selected processor does not support `tchangef x3,#7,nb' +.*: Error: selected processor does not support `tchangef x7,#15,nb' +.*: Error: selected processor does not support `tchangef x15,#31,NB' +.*: Error: selected processor does not support `tchangef x30,#63,nb' +.*: Error: selected processor does not support `tchangef x10,#127,NB' +.*: Error: selected processor does not support `tchangeb x0,x1' +.*: Error: selected processor does not support `tchangeb x1,x3' +.*: Error: selected processor does not support `tchangeb x3,x7' +.*: Error: selected processor does not support `tchangeb x7,x15' +.*: Error: selected processor does not support `tchangeb x15,x30' +.*: Error: selected processor does not support `tchangeb x30,x0' +.*: Error: selected processor does not support `tchangeb x10,x5' +.*: Error: selected processor does not support `tchangeb x0,x1,nb' +.*: Error: selected processor does not support `tchangeb x1,x3,nb' +.*: Error: selected processor does not support `tchangeb x3,x7,nb' +.*: Error: selected processor does not support `tchangeb x7,x15,nb' +.*: Error: selected processor does not support `tchangeb x15,x30,NB' +.*: Error: selected processor does not support `tchangeb x30,x0,nb' +.*: Error: selected processor does not support `tchangeb x10,x5,NB' +.*: Error: selected processor does not support `tchangeb x0,#0' +.*: Error: selected processor does not support `tchangeb x0,#1' +.*: Error: selected processor does not support `tchangeb x1,#3' +.*: Error: selected processor does not support `tchangeb x3,#7' +.*: Error: selected processor does not support `tchangeb x7,#15' +.*: Error: selected processor does not support `tchangeb x15,#31' +.*: Error: selected processor does not support `tchangeb x30,#63' +.*: Error: selected processor does not support `tchangeb x10,#127' +.*: Error: selected processor does not support `tchangeb x0,#0,nb' +.*: Error: selected processor does not support `tchangeb x0,#1,nb' +.*: Error: selected processor does not support `tchangeb x1,#3,nb' +.*: Error: selected processor does not support `tchangeb x3,#7,nb' +.*: Error: selected processor does not support `tchangeb x7,#15,nb' +.*: Error: selected processor does not support `tchangeb x15,#31,NB' +.*: Error: selected processor does not support `tchangeb x30,#63,nb' +.*: Error: selected processor does not support `tchangeb x10,#127,NB' diff --git a/gas/testsuite/gas/aarch64/poe2.d b/gas/testsuite/gas/aarch64/poe2.d new file mode 100644 index 00000000000..709565729e1 --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2.d @@ -0,0 +1,69 @@ +#objdump: -dr +#as: -march=armv8-a+poe2 + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5800020 tchangef x0, x1 +.*: d5800061 tchangef x1, x3 +.*: d58000e3 tchangef x3, x7 +.*: d58001e7 tchangef x7, x15 +.*: d58003cf tchangef x15, x30 +.*: d580001e tchangef x30, x0 +.*: d58000aa tchangef x10, x5 +.*: d5820020 tchangef x0, x1, nb +.*: d5820061 tchangef x1, x3, nb +.*: d58200e3 tchangef x3, x7, nb +.*: d58201e7 tchangef x7, x15, nb +.*: d58203cf tchangef x15, x30, nb +.*: d582001e tchangef x30, x0, nb +.*: d58200aa tchangef x10, x5, nb +.*: d5900000 tchangef x0, #0x0 +.*: d5900020 tchangef x0, #0x1 +.*: d5900061 tchangef x1, #0x3 +.*: d59000e3 tchangef x3, #0x7 +.*: d59001e7 tchangef x7, #0xf +.*: d59003ef tchangef x15, #0x1f +.*: d59007fe tchangef x30, #0x3f +.*: d5900fea tchangef x10, #0x7f +.*: d5920000 tchangef x0, #0x0, nb +.*: d5920020 tchangef x0, #0x1, nb +.*: d5920061 tchangef x1, #0x3, nb +.*: d59200e3 tchangef x3, #0x7, nb +.*: d59201e7 tchangef x7, #0xf, nb +.*: d59203ef tchangef x15, #0x1f, nb +.*: d59207fe tchangef x30, #0x3f, nb +.*: d5920fea tchangef x10, #0x7f, nb +.*: d5840020 tchangeb x0, x1 +.*: d5840061 tchangeb x1, x3 +.*: d58400e3 tchangeb x3, x7 +.*: d58401e7 tchangeb x7, x15 +.*: d58403cf tchangeb x15, x30 +.*: d584001e tchangeb x30, x0 +.*: d58400aa tchangeb x10, x5 +.*: d5860020 tchangeb x0, x1, nb +.*: d5860061 tchangeb x1, x3, nb +.*: d58600e3 tchangeb x3, x7, nb +.*: d58601e7 tchangeb x7, x15, nb +.*: d58603cf tchangeb x15, x30, nb +.*: d586001e tchangeb x30, x0, nb +.*: d58600aa tchangeb x10, x5, nb +.*: d5940000 tchangeb x0, #0x0 +.*: d5940020 tchangeb x0, #0x1 +.*: d5940061 tchangeb x1, #0x3 +.*: d59400e3 tchangeb x3, #0x7 +.*: d59401e7 tchangeb x7, #0xf +.*: d59403ef tchangeb x15, #0x1f +.*: d59407fe tchangeb x30, #0x3f +.*: d5940fea tchangeb x10, #0x7f +.*: d5960000 tchangeb x0, #0x0, nb +.*: d5960020 tchangeb x0, #0x1, nb +.*: d5960061 tchangeb x1, #0x3, nb +.*: d59600e3 tchangeb x3, #0x7, nb +.*: d59601e7 tchangeb x7, #0xf, nb +.*: d59603ef tchangeb x15, #0x1f, nb +.*: d59607fe tchangeb x30, #0x3f, nb +.*: d5960fea tchangeb x10, #0x7f, nb diff --git a/gas/testsuite/gas/aarch64/poe2.s b/gas/testsuite/gas/aarch64/poe2.s new file mode 100644 index 00000000000..3b9353c5c98 --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2.s @@ -0,0 +1,75 @@ +#TCHANGEF (register) instructions + tchangef x0, x1 + tchangef x1, x3 + tchangef x3, x7 + tchangef x7, x15 + tchangef x15, x30 + tchangef x30, x0 + tchangef x10, x5 + +#TCHANGEF (register) instructions with not_balanced + tchangef x0, x1, nb + tchangef x1, x3, nb + tchangef x3, x7, nb + tchangef x7, x15, nb + tchangef x15, x30, NB + tchangef x30, x0, nb + tchangef x10, x5, NB + +#TCHANGEF (immediate) instructions + tchangef x0, #0 + tchangef x0, #1 + tchangef x1, #3 + tchangef x3, #7 + tchangef x7, #15 + tchangef x15, #31 + tchangef x30, #63 + tchangef x10, #127 + +#TCHANGEF (immediate) instructions with not_balanced + tchangef x0, #0, nb + tchangef x0, #1, nb + tchangef x1, #3, nb + tchangef x3, #7, nb + tchangef x7, #15, nb + tchangef x15, #31, NB + tchangef x30, #63, nb + tchangef x10, #127, NB + +#TCHANGEB (register) instructions + tchangeb x0, x1 + tchangeb x1, x3 + tchangeb x3, x7 + tchangeb x7, x15 + tchangeb x15, x30 + tchangeb x30, x0 + tchangeb x10, x5 + +#TCHANGEB (register) instructions with not_balanced + tchangeb x0, x1, nb + tchangeb x1, x3, nb + tchangeb x3, x7, nb + tchangeb x7, x15, nb + tchangeb x15, x30, NB + tchangeb x30, x0, nb + tchangeb x10, x5, NB + +#TCHANGEB (immediate) instructions + tchangeb x0, #0 + tchangeb x0, #1 + tchangeb x1, #3 + tchangeb x3, #7 + tchangeb x7, #15 + tchangeb x15, #31 + tchangeb x30, #63 + tchangeb x10, #127 + +#TCHANGEB (immediate) instructions with not_balanced + tchangeb x0, #0, nb + tchangeb x0, #1, nb + tchangeb x1, #3, nb + tchangeb x3, #7, nb + tchangeb x7, #15, nb + tchangeb x15, #31, NB + tchangeb x30, #63, nb + tchangeb x10, #127, NB diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 68a181c531f..e7c6ed601b1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -263,6 +263,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_TMOP, /* SME MOP4 instructions. */ AARCH64_FEATURE_SME_MOP4, + /* POE2 instructions. */ + AARCH64_FEATURE_S1POE2, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -673,6 +675,7 @@ enum aarch64_opnd AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ + AARCH64_OPND_NOT_BALANCED, /* a 1-bit not_balanced optional operand. */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for each condition flag. */ @@ -1132,6 +1135,7 @@ enum aarch64_insn_class lse128_atomic, movewide, pcreladdr, + s1poe2, ic_system, sme_fp_sd, sme_int_sd, @@ -1599,6 +1603,7 @@ struct aarch64_name_value_pair }; extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; +extern const struct aarch64_name_value_pair aarch64_nb_options [1]; extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4]; extern const struct aarch64_name_value_pair aarch64_prfops [32]; diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index b0611654ead..c93447742f8 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -930,6 +930,7 @@ aarch64_insert_operand (const aarch64_operand *self, case AARCH64_OPND_UNDEFINED: case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: + case AARCH64_OPND_NOT_BALANCED: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_PCREL9: case AARCH64_OPND_ADDR_PCREL14: diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index ecaea2d2fdb..657e1ec4f37 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -26541,28 +26541,68 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - if (((word >> 25) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1010101x00xxxxxxxxxxxxxxxxxxxxx. */ - return A64_OPID_d500403f_xaflag; + if (((word >> 25) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010101000xxxxxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d500403f_xaflag; + } + else + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010111000xxxxxxxxxx0xxxxxxxxxx. */ + return A64_OPID_d71f0800_braa_Rn_Rd_SP; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010111000xxxxxxxxxx1xxxxxxxxxx. */ + return A64_OPID_d71f0c00_brab_Rn_Rd_SP; + } + } } else { - if (((word >> 10) & 0x1) == 0) + if (((word >> 18) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1010111x00xxxxxxxxxx0xxxxxxxxxx. */ - return A64_OPID_d71f0800_braa_Rn_Rd_SP; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11000x0xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5800000_tchangef_Rd_Rn_NOT_BALANCED; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11001x0xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5900000_tchangef_Rd_UIMM7_NOT_BALANCED; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1010111x00xxxxxxxxxx1xxxxxxxxxx. */ - return A64_OPID_d71f0c00_brab_Rn_Rd_SP; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11000x1xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5840000_tchangeb_Rd_Rn_NOT_BALANCED; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11001x1xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5940000_tchangeb_Rd_UIMM7_NOT_BALANCED; + } } } } @@ -37357,6 +37397,7 @@ aarch64_extract_operand (const aarch64_operand *self, case AARCH64_OPND_UNDEFINED: case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: + case AARCH64_OPND_NOT_BALANCED: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_ADRP: case AARCH64_OPND_ADDR_PCREL9: diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 7f3b25eae38..fc88fe82ed3 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -104,6 +104,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_0}, "a 16-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_17}, "a 1-bit not_balanced optional operand"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index c501b9b35e5..623fd7a4272 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -361,6 +361,7 @@ const aarch64_field aarch64_fields[] = AARCH64_FIELD (14, 1), /* imm1_14: general immediate in bits [14]. */ AARCH64_FIELD (15, 1), /* imm1_15: general immediate in bits [15]. */ AARCH64_FIELD (16, 1), /* imm1_16: general immediate in bits [16]. */ + AARCH64_FIELD (17, 1), /* imm1_17: op1[0] in the TCHANGE instruction. */ AARCH64_FIELD ( 0, 2), /* imm2_0: general immediate in bits [1:0]. */ AARCH64_FIELD ( 1, 2), /* imm2_1: general immediate in bits [2:1]. */ AARCH64_FIELD ( 2, 2), /* imm2_2: general immediate in bits [3:2]. */ @@ -559,6 +560,11 @@ aarch64_shift_operator_p (enum aarch64_modifier_kind kind) return kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL; } +const struct aarch64_name_value_pair aarch64_nb_options[1] = +{ + { "nb", 1 }, +}; + const struct aarch64_name_value_pair aarch64_barrier_options[16] = { { "#0x00", 0x0 }, @@ -5153,6 +5159,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "%s", style_sub_mnem (styler, "dsync")); break; + case AARCH64_OPND_NOT_BALANCED: + if (opnd->imm.value) + snprintf (buf, size, "%s", style_sub_mnem (styler, "nb")); + break; + case AARCH64_OPND_BTI_TARGET: if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0) snprintf (buf, size, "%s", diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 5d544d53baf..376aacb8312 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -165,6 +165,7 @@ enum aarch64_field_kind FLD_imm1_14, FLD_imm1_15, FLD_imm1_16, + FLD_imm1_17, FLD_imm2_0, FLD_imm2_1, FLD_imm2_2, diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h index 1263f1f9bd8..16b3448c828 100644 --- a/opcodes/aarch64-tbl-2.h +++ b/opcodes/aarch64-tbl-2.h @@ -3995,5 +3995,9 @@ enum aarch64_opcode_idx A64_OPID_a1c00018_usmop4s_SME_ZAda_3b_SME_Zn_6_3_SME_Zm_17_3, A64_OPID_a1c00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zm_17_3, A64_OPID_a1d00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zmx2_17_3, + A64_OPID_d5800000_tchangef_Rd_Rn_NOT_BALANCED, + A64_OPID_d5900000_tchangef_Rd_UIMM7_NOT_BALANCED, + A64_OPID_d5840000_tchangeb_Rd_Rn_NOT_BALANCED, + A64_OPID_d5940000_tchangeb_Rd_UIMM7_NOT_BALANCED, A64_OPID_MAX, }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 2fc69c27791..572385621db 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -64,6 +64,12 @@ QLF2(X,NIL), \ } +/* e.g. TCHANGEF , #{, }. */ +#define QL_DST_X1 \ +{ \ + QLF3(X,NIL,NIL), \ +} + /* e.g. MRRS , , . */ #define QL_DST_X2 \ { \ @@ -2808,6 +2814,7 @@ { \ QLF3(V_4S, V_8H, S_H), \ } + /* Opcode table. */ @@ -3057,6 +3064,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_f8f32 = AARCH64_FEATURES (2, SME_MOP4, SME_F8F32); static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 = AARCH64_FEATURES (2, SME_MOP4, SME_I16I64); +static const aarch64_feature_set aarch64_feature_s1poe2 = + AARCH64_FEATURE (S1POE2); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -3181,6 +3190,7 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 = #define SME_MOP4_F8F16 &aarch64_feature_sme_mop4_f8f16 #define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32 #define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64 +#define S1POE2 &aarch64_feature_s1poe2 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } @@ -3510,6 +3520,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 = #define SME_MOP4_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_I16I64, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } +#define S1POE2_INSN(NAME,OPCODE,MASK,OPS,QUALS, FLAGS) \ + { NAME, OPCODE, MASK, s1poe2, 0, S1POE2, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -7738,6 +7750,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0), SME_MOP4_I16I64_INSN ("usmop4s", 0xa1d00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zmx2_17_3), OP_SVE_DHH, 0, 0), + /* POE2 instructions. */ + S1POE2_INSN("tchangef", 0xd5800000, 0xfffdfc00, OP3 (Rd, Rn, NOT_BALANCED), QL_DST_X2, F_OPD2_OPT | F_DEFAULT (0x0)), + S1POE2_INSN("tchangef", 0xd5900000, 0xfffdf000, OP3 (Rd, UIMM7, NOT_BALANCED), QL_DST_X1, F_OPD2_OPT | F_DEFAULT (0x0)), + S1POE2_INSN("tchangeb", 0xd5840000, 0xfffdfc00, OP3 (Rd, Rn, NOT_BALANCED), QL_DST_X2, F_OPD2_OPT | F_DEFAULT (0x0)), + S1POE2_INSN("tchangeb", 0xd5940000, 0xfffdf000, OP3 (Rd, UIMM7, NOT_BALANCED), QL_DST_X1, F_OPD2_OPT | F_DEFAULT (0x0)), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -7890,6 +7908,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 5-bit unsigned immediate") \ Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ "a 5-bit signed immediate") \ + Y(IMMEDIATE, imm, "NOT_BALANCED", 0, F(FLD_imm1_17), \ + "a 1-bit not_balanced optional operand") \ Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ "a flag bit specifier giving an alternative value for each flag") \ Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ From patchwork Fri Dec 5 10:57:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 125969 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 958594BC894E for ; Fri, 5 Dec 2025 11:04:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 958594BC894E Authentication-Results: sourceware.org; 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CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(35042699022)(36860700013)(14060799003)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2025 10:58:23.9216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f79c73f1-a6cf-4fa7-a8a5-08de33ed3602 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C713.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9069 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_NONE, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch adds support for following system registers which are available by default, however if guarding restrictions are enabled using -menable-sysreg-checking than "+poe2" option need to specified to the -march. * AFGDTpn_ELx system registers * AFGDTpn_ELx system registers * DPOTBRn_ELx system registers * TPIDR3_ELx system registers * IRTBRp_ELx system registers * LDSTT_ELx system registers * STINDEX_ELx system registers * TINDEX_ELx system registers * TTTBRp_ELx system registers * DPOCR_EL0 system registers * VNCCR_EL2 system register example: $cat tmp.s .text msr afgdtp0_el1, x0 By default, "afgdtp0_el1" available with following command line. $ aarch64-none-elf-as tmp.s -march=armv8-a On enabling guarding restrictions, "afgdtp0_el1" available with following command line. $ aarch64-none-elf-as tmp.s -menable-sysreg-checking -march=armv8-a+poe2 Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath Co-authored-by: Matthew Malcomson --- .../gas/aarch64/sysreg/poe2-sysreg-1.d | 535 +++++++++++++++++ .../gas/aarch64/sysreg/poe2-sysreg-1.s | 90 +++ .../gas/aarch64/sysreg/poe2-sysreg-2.d | 536 ++++++++++++++++++ .../aarch64/sysreg/poe2-sysreg-invalid-1.d | 4 + .../aarch64/sysreg/poe2-sysreg-invalid-1.l | 527 +++++++++++++++++ opcodes/aarch64-sys-regs.def | 263 +++++++++ 6 files changed, 1955 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.d create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.l diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d new file mode 100644 index 00000000000..4d21649c2a8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d @@ -0,0 +1,535 @@ +#as: -menable-sysreg-checking -I$srcdir/$subdir -march=armv8-a+poe2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183620 msr afgdtp1_el1, x0 +.*: d5383620 mrs x0, afgdtp1_el1 +.*: d5183640 msr afgdtp2_el1, x0 +.*: d5383640 mrs x0, afgdtp2_el1 +.*: d5183660 msr afgdtp3_el1, x0 +.*: d5383660 mrs x0, afgdtp3_el1 +.*: d5183680 msr afgdtp4_el1, x0 +.*: d5383680 mrs x0, afgdtp4_el1 +.*: d51836a0 msr afgdtp5_el1, x0 +.*: d53836a0 mrs x0, afgdtp5_el1 +.*: d51836c0 msr afgdtp6_el1, x0 +.*: d53836c0 mrs x0, afgdtp6_el1 +.*: d51836e0 msr afgdtp7_el1, x0 +.*: d53836e0 mrs x0, afgdtp7_el1 +.*: d5183700 msr afgdtp8_el1, x0 +.*: d5383700 mrs x0, afgdtp8_el1 +.*: d5183720 msr afgdtp9_el1, x0 +.*: d5383720 mrs x0, afgdtp9_el1 +.*: d5183740 msr afgdtp10_el1, x0 +.*: d5383740 mrs x0, afgdtp10_el1 +.*: d5183760 msr afgdtp11_el1, x0 +.*: d5383760 mrs x0, afgdtp11_el1 +.*: d5183780 msr afgdtp12_el1, x0 +.*: d5383780 mrs x0, afgdtp12_el1 +.*: d51837a0 msr afgdtp13_el1, x0 +.*: d53837a0 mrs x0, afgdtp13_el1 +.*: d51837c0 msr afgdtp14_el1, x0 +.*: d53837c0 mrs x0, afgdtp14_el1 +.*: d51837e0 msr afgdtp15_el1, x0 +.*: d53837e0 mrs x0, afgdtp15_el1 +.*: d51d3600 msr afgdtp0_el12, x0 +.*: d53d3600 mrs x0, afgdtp0_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3640 msr afgdtp2_el12, x0 +.*: d53d3640 mrs x0, afgdtp2_el12 +.*: d51d3660 msr afgdtp3_el12, x0 +.*: d53d3660 mrs x0, afgdtp3_el12 +.*: d51d3680 msr afgdtp4_el12, x0 +.*: d53d3680 mrs x0, afgdtp4_el12 +.*: d51d36a0 msr afgdtp5_el12, x0 +.*: d53d36a0 mrs x0, afgdtp5_el12 +.*: d51d36c0 msr afgdtp6_el12, x0 +.*: d53d36c0 mrs x0, afgdtp6_el12 +.*: d51d36e0 msr afgdtp7_el12, x0 +.*: d53d36e0 mrs x0, afgdtp7_el12 +.*: d51d3700 msr afgdtp8_el12, x0 +.*: d53d3700 mrs x0, afgdtp8_el12 +.*: d51d3720 msr afgdtp9_el12, x0 +.*: d53d3720 mrs x0, afgdtp9_el12 +.*: d51d3740 msr afgdtp10_el12, x0 +.*: d53d3740 mrs x0, afgdtp10_el12 +.*: d51d3760 msr afgdtp11_el12, x0 +.*: d53d3760 mrs x0, afgdtp11_el12 +.*: d51d3780 msr afgdtp12_el12, x0 +.*: d53d3780 mrs x0, afgdtp12_el12 +.*: d51d37a0 msr afgdtp13_el12, x0 +.*: d53d37a0 mrs x0, afgdtp13_el12 +.*: d51d37c0 msr afgdtp14_el12, x0 +.*: d53d37c0 mrs x0, afgdtp14_el12 +.*: d51d37e0 msr afgdtp15_el12, x0 +.*: d53d37e0 mrs x0, afgdtp15_el12 +.*: d51c3600 msr afgdtp0_el2, x0 +.*: d53c3600 mrs x0, afgdtp0_el2 +.*: d51c3620 msr afgdtp1_el2, x0 +.*: d53c3620 mrs x0, afgdtp1_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3660 msr afgdtp3_el2, x0 +.*: d53c3660 mrs x0, afgdtp3_el2 +.*: d51c3680 msr afgdtp4_el2, x0 +.*: d53c3680 mrs x0, afgdtp4_el2 +.*: d51c36a0 msr afgdtp5_el2, x0 +.*: d53c36a0 mrs x0, afgdtp5_el2 +.*: d51c36c0 msr afgdtp6_el2, x0 +.*: d53c36c0 mrs x0, afgdtp6_el2 +.*: d51c36e0 msr afgdtp7_el2, x0 +.*: d53c36e0 mrs x0, afgdtp7_el2 +.*: d51c3700 msr afgdtp8_el2, x0 +.*: d53c3700 mrs x0, afgdtp8_el2 +.*: d51c3720 msr afgdtp9_el2, x0 +.*: d53c3720 mrs x0, afgdtp9_el2 +.*: d51c3740 msr afgdtp10_el2, x0 +.*: d53c3740 mrs x0, afgdtp10_el2 +.*: d51c3760 msr afgdtp11_el2, x0 +.*: d53c3760 mrs x0, afgdtp11_el2 +.*: d51c3780 msr afgdtp12_el2, x0 +.*: d53c3780 mrs x0, afgdtp12_el2 +.*: d51c37a0 msr afgdtp13_el2, x0 +.*: d53c37a0 mrs x0, afgdtp13_el2 +.*: d51c37c0 msr afgdtp14_el2, x0 +.*: d53c37c0 mrs x0, afgdtp14_el2 +.*: d51c37e0 msr afgdtp15_el2, x0 +.*: d53c37e0 mrs x0, afgdtp15_el2 +.*: d51e3600 msr afgdtp0_el3, x0 +.*: d53e3600 mrs x0, afgdtp0_el3 +.*: d51e3620 msr afgdtp1_el3, x0 +.*: d53e3620 mrs x0, afgdtp1_el3 +.*: d51e3640 msr afgdtp2_el3, x0 +.*: d53e3640 mrs x0, afgdtp2_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3680 msr afgdtp4_el3, x0 +.*: d53e3680 mrs x0, afgdtp4_el3 +.*: d51e36a0 msr afgdtp5_el3, x0 +.*: d53e36a0 mrs x0, afgdtp5_el3 +.*: d51e36c0 msr afgdtp6_el3, x0 +.*: d53e36c0 mrs x0, afgdtp6_el3 +.*: d51e36e0 msr afgdtp7_el3, x0 +.*: d53e36e0 mrs x0, afgdtp7_el3 +.*: d51e3700 msr afgdtp8_el3, x0 +.*: d53e3700 mrs x0, afgdtp8_el3 +.*: d51e3720 msr afgdtp9_el3, x0 +.*: d53e3720 mrs x0, afgdtp9_el3 +.*: d51e3740 msr afgdtp10_el3, x0 +.*: d53e3740 mrs x0, afgdtp10_el3 +.*: d51e3760 msr afgdtp11_el3, x0 +.*: d53e3760 mrs x0, afgdtp11_el3 +.*: d51e3780 msr afgdtp12_el3, x0 +.*: d53e3780 mrs x0, afgdtp12_el3 +.*: d51e37a0 msr afgdtp13_el3, x0 +.*: d53e37a0 mrs x0, afgdtp13_el3 +.*: d51e37c0 msr afgdtp14_el3, x0 +.*: d53e37c0 mrs x0, afgdtp14_el3 +.*: d51e37e0 msr afgdtp15_el3, x0 +.*: d53e37e0 mrs x0, afgdtp15_el3 +.*: d5183800 msr afgdtu0_el1, x0 +.*: d5383800 mrs x0, afgdtu0_el1 +.*: d5183820 msr afgdtu1_el1, x0 +.*: d5383820 mrs x0, afgdtu1_el1 +.*: d5183840 msr afgdtu2_el1, x0 +.*: d5383840 mrs x0, afgdtu2_el1 +.*: d5183860 msr afgdtu3_el1, x0 +.*: d5383860 mrs x0, afgdtu3_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d51838a0 msr afgdtu5_el1, x0 +.*: d53838a0 mrs x0, afgdtu5_el1 +.*: d51838c0 msr afgdtu6_el1, x0 +.*: d53838c0 mrs x0, afgdtu6_el1 +.*: d51838e0 msr afgdtu7_el1, x0 +.*: d53838e0 mrs x0, afgdtu7_el1 +.*: d5183900 msr afgdtu8_el1, x0 +.*: d5383900 mrs x0, afgdtu8_el1 +.*: d5183920 msr afgdtu9_el1, x0 +.*: d5383920 mrs x0, afgdtu9_el1 +.*: d5183940 msr afgdtu10_el1, x0 +.*: d5383940 mrs x0, afgdtu10_el1 +.*: d5183960 msr afgdtu11_el1, x0 +.*: d5383960 mrs x0, afgdtu11_el1 +.*: d5183980 msr afgdtu12_el1, x0 +.*: d5383980 mrs x0, afgdtu12_el1 +.*: d51839a0 msr afgdtu13_el1, x0 +.*: d53839a0 mrs x0, afgdtu13_el1 +.*: d51839c0 msr afgdtu14_el1, x0 +.*: d53839c0 mrs x0, afgdtu14_el1 +.*: d51839e0 msr afgdtu15_el1, x0 +.*: d53839e0 mrs x0, afgdtu15_el1 +.*: d51d3800 msr afgdtu0_el12, x0 +.*: d53d3800 mrs x0, afgdtu0_el12 +.*: d51d3820 msr afgdtu1_el12, x0 +.*: d53d3820 mrs x0, afgdtu1_el12 +.*: d51d3840 msr afgdtu2_el12, x0 +.*: d53d3840 mrs x0, afgdtu2_el12 +.*: d51d3860 msr afgdtu3_el12, x0 +.*: d53d3860 mrs x0, afgdtu3_el12 +.*: d51d3880 msr afgdtu4_el12, x0 +.*: d53d3880 mrs x0, afgdtu4_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38c0 msr afgdtu6_el12, x0 +.*: d53d38c0 mrs x0, afgdtu6_el12 +.*: d51d38e0 msr afgdtu7_el12, x0 +.*: d53d38e0 mrs x0, afgdtu7_el12 +.*: d51d3900 msr afgdtu8_el12, x0 +.*: d53d3900 mrs x0, afgdtu8_el12 +.*: d51d3920 msr afgdtu9_el12, x0 +.*: d53d3920 mrs x0, afgdtu9_el12 +.*: d51d3940 msr afgdtu10_el12, x0 +.*: d53d3940 mrs x0, afgdtu10_el12 +.*: d51d3960 msr afgdtu11_el12, x0 +.*: d53d3960 mrs x0, afgdtu11_el12 +.*: d51d3980 msr afgdtu12_el12, x0 +.*: d53d3980 mrs x0, afgdtu12_el12 +.*: d51d39a0 msr afgdtu13_el12, x0 +.*: d53d39a0 mrs x0, afgdtu13_el12 +.*: d51d39c0 msr afgdtu14_el12, x0 +.*: d53d39c0 mrs x0, afgdtu14_el12 +.*: d51d39e0 msr afgdtu15_el12, x0 +.*: d53d39e0 mrs x0, afgdtu15_el12 +.*: d51c3800 msr afgdtu0_el2, x0 +.*: d53c3800 mrs x0, afgdtu0_el2 +.*: d51c3820 msr afgdtu1_el2, x0 +.*: d53c3820 mrs x0, afgdtu1_el2 +.*: d51c3840 msr afgdtu2_el2, x0 +.*: d53c3840 mrs x0, afgdtu2_el2 +.*: d51c3860 msr afgdtu3_el2, x0 +.*: d53c3860 mrs x0, afgdtu3_el2 +.*: d51c3880 msr afgdtu4_el2, x0 +.*: d53c3880 mrs x0, afgdtu4_el2 +.*: d51c38a0 msr afgdtu5_el2, x0 +.*: d53c38a0 mrs x0, afgdtu5_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38e0 msr afgdtu7_el2, x0 +.*: d53c38e0 mrs x0, afgdtu7_el2 +.*: d51c3900 msr afgdtu8_el2, x0 +.*: d53c3900 mrs x0, afgdtu8_el2 +.*: d51c3920 msr afgdtu9_el2, x0 +.*: d53c3920 mrs x0, afgdtu9_el2 +.*: d51c3940 msr afgdtu10_el2, x0 +.*: d53c3940 mrs x0, afgdtu10_el2 +.*: d51c3960 msr afgdtu11_el2, x0 +.*: d53c3960 mrs x0, afgdtu11_el2 +.*: d51c3980 msr afgdtu12_el2, x0 +.*: d53c3980 mrs x0, afgdtu12_el2 +.*: d51c39a0 msr afgdtu13_el2, x0 +.*: d53c39a0 mrs x0, afgdtu13_el2 +.*: d51c39c0 msr afgdtu14_el2, x0 +.*: d53c39c0 mrs x0, afgdtu14_el2 +.*: d51c39e0 msr afgdtu15_el2, x0 +.*: d53c39e0 mrs x0, afgdtu15_el2 +.*: d5183200 msr fgdtp0_el1, x0 +.*: d5383200 mrs x0, fgdtp0_el1 +.*: d5183220 msr fgdtp1_el1, x0 +.*: d5383220 mrs x0, fgdtp1_el1 +.*: d5183240 msr fgdtp2_el1, x0 +.*: d5383240 mrs x0, fgdtp2_el1 +.*: d5183260 msr fgdtp3_el1, x0 +.*: d5383260 mrs x0, fgdtp3_el1 +.*: d5183280 msr fgdtp4_el1, x0 +.*: d5383280 mrs x0, fgdtp4_el1 +.*: d51832a0 msr fgdtp5_el1, x0 +.*: d53832a0 mrs x0, fgdtp5_el1 +.*: d51832c0 msr fgdtp6_el1, x0 +.*: d53832c0 mrs x0, fgdtp6_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d5183300 msr fgdtp8_el1, x0 +.*: d5383300 mrs x0, fgdtp8_el1 +.*: d5183320 msr fgdtp9_el1, x0 +.*: d5383320 mrs x0, fgdtp9_el1 +.*: d5183340 msr fgdtp10_el1, x0 +.*: d5383340 mrs x0, fgdtp10_el1 +.*: d5183360 msr fgdtp11_el1, x0 +.*: d5383360 mrs x0, fgdtp11_el1 +.*: d5183380 msr fgdtp12_el1, x0 +.*: d5383380 mrs x0, fgdtp12_el1 +.*: d51833a0 msr fgdtp13_el1, x0 +.*: d53833a0 mrs x0, fgdtp13_el1 +.*: d51833c0 msr fgdtp14_el1, x0 +.*: d53833c0 mrs x0, fgdtp14_el1 +.*: d51833e0 msr fgdtp15_el1, x0 +.*: d53833e0 mrs x0, fgdtp15_el1 +.*: d51d3200 msr fgdtp0_el12, x0 +.*: d53d3200 mrs x0, fgdtp0_el12 +.*: d51d3220 msr fgdtp1_el12, x0 +.*: d53d3220 mrs x0, fgdtp1_el12 +.*: d51d3240 msr fgdtp2_el12, x0 +.*: d53d3240 mrs x0, fgdtp2_el12 +.*: d51d3260 msr fgdtp3_el12, x0 +.*: d53d3260 mrs x0, fgdtp3_el12 +.*: d51d3280 msr fgdtp4_el12, x0 +.*: d53d3280 mrs x0, fgdtp4_el12 +.*: d51d32a0 msr fgdtp5_el12, x0 +.*: d53d32a0 mrs x0, fgdtp5_el12 +.*: d51d32c0 msr fgdtp6_el12, x0 +.*: d53d32c0 mrs x0, fgdtp6_el12 +.*: d51d32e0 msr fgdtp7_el12, x0 +.*: d53d32e0 mrs x0, fgdtp7_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3320 msr fgdtp9_el12, x0 +.*: d53d3320 mrs x0, fgdtp9_el12 +.*: d51d3340 msr fgdtp10_el12, x0 +.*: d53d3340 mrs x0, fgdtp10_el12 +.*: d51d3360 msr fgdtp11_el12, x0 +.*: d53d3360 mrs x0, fgdtp11_el12 +.*: d51d3380 msr fgdtp12_el12, x0 +.*: d53d3380 mrs x0, fgdtp12_el12 +.*: d51d33a0 msr fgdtp13_el12, x0 +.*: d53d33a0 mrs x0, fgdtp13_el12 +.*: d51d33c0 msr fgdtp14_el12, x0 +.*: d53d33c0 mrs x0, fgdtp14_el12 +.*: d51d33e0 msr fgdtp15_el12, x0 +.*: d53d33e0 mrs x0, fgdtp15_el12 +.*: d51c3200 msr fgdtp0_el2, x0 +.*: d53c3200 mrs x0, fgdtp0_el2 +.*: d51c3220 msr fgdtp1_el2, x0 +.*: d53c3220 mrs x0, fgdtp1_el2 +.*: d51c3240 msr fgdtp2_el2, x0 +.*: d53c3240 mrs x0, fgdtp2_el2 +.*: d51c3260 msr fgdtp3_el2, x0 +.*: d53c3260 mrs x0, fgdtp3_el2 +.*: d51c3280 msr fgdtp4_el2, x0 +.*: d53c3280 mrs x0, fgdtp4_el2 +.*: d51c32a0 msr fgdtp5_el2, x0 +.*: d53c32a0 mrs x0, fgdtp5_el2 +.*: d51c32c0 msr fgdtp6_el2, x0 +.*: d53c32c0 mrs x0, fgdtp6_el2 +.*: d51c32e0 msr fgdtp7_el2, x0 +.*: d53c32e0 mrs x0, fgdtp7_el2 +.*: d51c3300 msr fgdtp8_el2, x0 +.*: d53c3300 mrs x0, fgdtp8_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3340 msr fgdtp10_el2, x0 +.*: d53c3340 mrs x0, fgdtp10_el2 +.*: d51c3360 msr fgdtp11_el2, x0 +.*: d53c3360 mrs x0, fgdtp11_el2 +.*: d51c3380 msr fgdtp12_el2, x0 +.*: d53c3380 mrs x0, fgdtp12_el2 +.*: d51c33a0 msr fgdtp13_el2, x0 +.*: d53c33a0 mrs x0, fgdtp13_el2 +.*: d51c33c0 msr fgdtp14_el2, x0 +.*: d53c33c0 mrs x0, fgdtp14_el2 +.*: d51c33e0 msr fgdtp15_el2, x0 +.*: d53c33e0 mrs x0, fgdtp15_el2 +.*: d51e3200 msr fgdtp0_el3, x0 +.*: d53e3200 mrs x0, fgdtp0_el3 +.*: d51e3220 msr fgdtp1_el3, x0 +.*: d53e3220 mrs x0, fgdtp1_el3 +.*: d51e3240 msr fgdtp2_el3, x0 +.*: d53e3240 mrs x0, fgdtp2_el3 +.*: d51e3260 msr fgdtp3_el3, x0 +.*: d53e3260 mrs x0, fgdtp3_el3 +.*: d51e3280 msr fgdtp4_el3, x0 +.*: d53e3280 mrs x0, fgdtp4_el3 +.*: d51e32a0 msr fgdtp5_el3, x0 +.*: d53e32a0 mrs x0, fgdtp5_el3 +.*: d51e32c0 msr fgdtp6_el3, x0 +.*: d53e32c0 mrs x0, fgdtp6_el3 +.*: d51e32e0 msr fgdtp7_el3, x0 +.*: d53e32e0 mrs x0, fgdtp7_el3 +.*: d51e3300 msr fgdtp8_el3, x0 +.*: d53e3300 mrs x0, fgdtp8_el3 +.*: d51e3320 msr fgdtp9_el3, x0 +.*: d53e3320 mrs x0, fgdtp9_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3360 msr fgdtp11_el3, x0 +.*: d53e3360 mrs x0, fgdtp11_el3 +.*: d51e3380 msr fgdtp12_el3, x0 +.*: d53e3380 mrs x0, fgdtp12_el3 +.*: d51e33a0 msr fgdtp13_el3, x0 +.*: d53e33a0 mrs x0, fgdtp13_el3 +.*: d51e33c0 msr fgdtp14_el3, x0 +.*: d53e33c0 mrs x0, fgdtp14_el3 +.*: d51e33e0 msr fgdtp15_el3, x0 +.*: d53e33e0 mrs x0, fgdtp15_el3 +.*: d5183400 msr fgdtu0_el1, x0 +.*: d5383400 mrs x0, fgdtu0_el1 +.*: d5183420 msr fgdtu1_el1, x0 +.*: d5383420 mrs x0, fgdtu1_el1 +.*: d5183440 msr fgdtu2_el1, x0 +.*: d5383440 mrs x0, fgdtu2_el1 +.*: d5183460 msr fgdtu3_el1, x0 +.*: d5383460 mrs x0, fgdtu3_el1 +.*: d5183480 msr fgdtu4_el1, x0 +.*: d5383480 mrs x0, fgdtu4_el1 +.*: d51834a0 msr fgdtu5_el1, x0 +.*: d53834a0 mrs x0, fgdtu5_el1 +.*: d51834c0 msr fgdtu6_el1, x0 +.*: d53834c0 mrs x0, fgdtu6_el1 +.*: d51834e0 msr fgdtu7_el1, x0 +.*: d53834e0 mrs x0, fgdtu7_el1 +.*: d5183500 msr fgdtu8_el1, x0 +.*: d5383500 mrs x0, fgdtu8_el1 +.*: d5183520 msr fgdtu9_el1, x0 +.*: d5383520 mrs x0, fgdtu9_el1 +.*: d5183540 msr fgdtu10_el1, x0 +.*: d5383540 mrs x0, fgdtu10_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183580 msr fgdtu12_el1, x0 +.*: d5383580 mrs x0, fgdtu12_el1 +.*: d51835a0 msr fgdtu13_el1, x0 +.*: d53835a0 mrs x0, fgdtu13_el1 +.*: d51835c0 msr fgdtu14_el1, x0 +.*: d53835c0 mrs x0, fgdtu14_el1 +.*: d51835e0 msr fgdtu15_el1, x0 +.*: d53835e0 mrs x0, fgdtu15_el1 +.*: d51d3400 msr fgdtu0_el12, x0 +.*: d53d3400 mrs x0, fgdtu0_el12 +.*: d51d3420 msr fgdtu1_el12, x0 +.*: d53d3420 mrs x0, fgdtu1_el12 +.*: d51d3440 msr fgdtu2_el12, x0 +.*: d53d3440 mrs x0, fgdtu2_el12 +.*: d51d3460 msr fgdtu3_el12, x0 +.*: d53d3460 mrs x0, fgdtu3_el12 +.*: d51d3480 msr fgdtu4_el12, x0 +.*: d53d3480 mrs x0, fgdtu4_el12 +.*: d51d34a0 msr fgdtu5_el12, x0 +.*: d53d34a0 mrs x0, fgdtu5_el12 +.*: d51d34c0 msr fgdtu6_el12, x0 +.*: d53d34c0 mrs x0, fgdtu6_el12 +.*: d51d34e0 msr fgdtu7_el12, x0 +.*: d53d34e0 mrs x0, fgdtu7_el12 +.*: d51d3500 msr fgdtu8_el12, x0 +.*: d53d3500 mrs x0, fgdtu8_el12 +.*: d51d3520 msr fgdtu9_el12, x0 +.*: d53d3520 mrs x0, fgdtu9_el12 +.*: d51d3540 msr fgdtu10_el12, x0 +.*: d53d3540 mrs x0, fgdtu10_el12 +.*: d51d3560 msr fgdtu11_el12, x0 +.*: d53d3560 mrs x0, fgdtu11_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d35a0 msr fgdtu13_el12, x0 +.*: d53d35a0 mrs x0, fgdtu13_el12 +.*: d51d35c0 msr fgdtu14_el12, x0 +.*: d53d35c0 mrs x0, fgdtu14_el12 +.*: d51d35e0 msr fgdtu15_el12, x0 +.*: d53d35e0 mrs x0, fgdtu15_el12 +.*: d51c3400 msr fgdtu0_el2, x0 +.*: d53c3400 mrs x0, fgdtu0_el2 +.*: d51c3420 msr fgdtu1_el2, x0 +.*: d53c3420 mrs x0, fgdtu1_el2 +.*: d51c3440 msr fgdtu2_el2, x0 +.*: d53c3440 mrs x0, fgdtu2_el2 +.*: d51c3460 msr fgdtu3_el2, x0 +.*: d53c3460 mrs x0, fgdtu3_el2 +.*: d51c3480 msr fgdtu4_el2, x0 +.*: d53c3480 mrs x0, fgdtu4_el2 +.*: d51c34a0 msr fgdtu5_el2, x0 +.*: d53c34a0 mrs x0, fgdtu5_el2 +.*: d51c34c0 msr fgdtu6_el2, x0 +.*: d53c34c0 mrs x0, fgdtu6_el2 +.*: d51c34e0 msr fgdtu7_el2, x0 +.*: d53c34e0 mrs x0, fgdtu7_el2 +.*: d51c3500 msr fgdtu8_el2, x0 +.*: d53c3500 mrs x0, fgdtu8_el2 +.*: d51c3520 msr fgdtu9_el2, x0 +.*: d53c3520 mrs x0, fgdtu9_el2 +.*: d51c3540 msr fgdtu10_el2, x0 +.*: d53c3540 mrs x0, fgdtu10_el2 +.*: d51c3560 msr fgdtu11_el2, x0 +.*: d53c3560 mrs x0, fgdtu11_el2 +.*: d51c3580 msr fgdtu12_el2, x0 +.*: d53c3580 mrs x0, fgdtu12_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35c0 msr fgdtu14_el2, x0 +.*: d53c35c0 mrs x0, fgdtu14_el2 +.*: d51c35e0 msr fgdtu15_el2, x0 +.*: d53c35e0 mrs x0, fgdtu15_el2 +.*: d51820c0 msr dpotbr0_el1, x0 +.*: d53820c0 mrs x0, dpotbr0_el1 +.*: d51820e0 msr dpotbr1_el1, x0 +.*: d53820e0 mrs x0, dpotbr1_el1 +.*: d51d20c0 msr dpotbr0_el12, x0 +.*: d53d20c0 mrs x0, dpotbr0_el12 +.*: d51d20e0 msr dpotbr1_el12, x0 +.*: d53d20e0 mrs x0, dpotbr1_el12 +.*: d51c20c0 msr dpotbr0_el2, x0 +.*: d53c20c0 mrs x0, dpotbr0_el2 +.*: d51c20e0 msr dpotbr1_el2, x0 +.*: d53c20e0 mrs x0, dpotbr1_el2 +.*: d51e20c0 msr dpotbr0_el3, x0 +.*: d53e20c0 mrs x0, dpotbr0_el3 +.*: d51bd000 msr tpidr3_el0, x0 +.*: d53bd000 mrs x0, tpidr3_el0 +.*: d518d000 msr tpidr3_el1, x0 +.*: d538d000 mrs x0, tpidr3_el1 +.*: d51dd000 msr tpidr3_el12, x0 +.*: d53dd000 mrs x0, tpidr3_el12 +.*: d51cd000 msr tpidr3_el2, x0 +.*: d53cd000 mrs x0, tpidr3_el2 +.*: d51ed000 msr tpidr3_el3, x0 +.*: d53ed000 mrs x0, tpidr3_el3 +.*: d5182080 msr irtbru_el1, x0 +.*: d5382080 mrs x0, irtbru_el1 +.*: d51d2080 msr irtbru_el12, x0 +.*: d53d2080 mrs x0, irtbru_el12 +.*: d51c2080 msr irtbru_el2, x0 +.*: d53c2080 mrs x0, irtbru_el2 +.*: d51820a0 msr irtbrp_el1, x0 +.*: d53820a0 mrs x0, irtbrp_el1 +.*: d51d20a0 msr irtbrp_el12, x0 +.*: d53d20a0 mrs x0, irtbrp_el12 +.*: d51c20a0 msr irtbrp_el2, x0 +.*: d53c20a0 mrs x0, irtbrp_el2 +.*: d51e20a0 msr irtbrp_el3, x0 +.*: d53e20a0 mrs x0, irtbrp_el3 +.*: d51821e0 msr ldstt_el1, x0 +.*: d53821e0 mrs x0, ldstt_el1 +.*: d51d21e0 msr ldstt_el12, x0 +.*: d53d21e0 mrs x0, ldstt_el12 +.*: d51c21e0 msr ldstt_el2, x0 +.*: d53c21e0 mrs x0, ldstt_el2 +.*: d5184040 msr stindex_el1, x0 +.*: d5384040 mrs x0, stindex_el1 +.*: d51d4040 msr stindex_el12, x0 +.*: d53d4040 mrs x0, stindex_el12 +.*: d51c4040 msr stindex_el2, x0 +.*: d53c4040 mrs x0, stindex_el2 +.*: d51b4060 msr tindex_el0, x0 +.*: d53b4060 mrs x0, tindex_el0 +.*: d5184060 msr tindex_el1, x0 +.*: d5384060 mrs x0, tindex_el1 +.*: d51d4060 msr tindex_el12, x0 +.*: d53d4060 mrs x0, tindex_el12 +.*: d51c4060 msr tindex_el2, x0 +.*: d53c4060 mrs x0, tindex_el2 +.*: d51e4060 msr tindex_el3, x0 +.*: d53e4060 mrs x0, tindex_el3 +.*: d518a2c0 msr tttbru_el1, x0 +.*: d538a2c0 mrs x0, tttbru_el1 +.*: d51da2c0 msr tttbru_el12, x0 +.*: d53da2c0 mrs x0, tttbru_el12 +.*: d51ca2c0 msr tttbru_el2, x0 +.*: d53ca2c0 mrs x0, tttbru_el2 +.*: d518a2e0 msr tttbrp_el1, x0 +.*: d538a2e0 mrs x0, tttbrp_el1 +.*: d51da2e0 msr tttbrp_el12, x0 +.*: d53da2e0 mrs x0, tttbrp_el12 +.*: d51ca2e0 msr tttbrp_el2, x0 +.*: d53ca2e0 mrs x0, tttbrp_el2 +.*: d51ea2e0 msr tttbrp_el3, x0 +.*: d53ea2e0 mrs x0, tttbrp_el3 +.*: d51b4540 msr dpocr_el0, x0 +.*: d53b4540 mrs x0, dpocr_el0 +.*: d51c2220 msr vnccr_el2, x0 +.*: d53c2220 mrs x0, vnccr_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s new file mode 100644 index 00000000000..25856fdc991 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s @@ -0,0 +1,90 @@ +.include "sysreg-test-utils.inc" + +.text + +.altmacro + + .macro sysreg_name Base, EL, from=0, to=15 + rw_sys_reg \Base\from\()_\EL + + .if (\to - \from > 0) + sysreg_name \Base, \EL, %(\from+1), \to + .endif + .endm + + .macro sysreg_name1 Base, EL + rw_sys_reg \Base\()_\EL + .endm + +// AFGDTpn_ELx system registers + sysreg_name AFGDTP, EL1 + sysreg_name AFGDTP, EL12 + sysreg_name AFGDTP, EL2 + sysreg_name AFGDTP, EL3 + sysreg_name AFGDTU, EL1 + sysreg_name AFGDTU, EL12 + sysreg_name AFGDTU, EL2 + +// AFGDTpn_ELx system registers + sysreg_name FGDTP, EL1 + sysreg_name FGDTP, EL12 + sysreg_name FGDTP, EL2 + sysreg_name FGDTP, EL3 + sysreg_name FGDTU, EL1 + sysreg_name FGDTU, EL12 + sysreg_name FGDTU, EL2 + +// DPOTBRn_ELx system registers + sysreg_name DPOTBR, EL1, 0, 1 + sysreg_name DPOTBR, EL12, 0, 1 + sysreg_name DPOTBR, EL2, 0, 1 + sysreg_name DPOTBR, EL3, 0, 0 + +// TPIDR3_ELx system registers + sysreg_name TPIDR, EL0, 3, 3 + sysreg_name TPIDR, EL1, 3, 3 + sysreg_name TPIDR, EL12, 3, 3 + sysreg_name TPIDR, EL2, 3, 3 + sysreg_name TPIDR, EL3, 3, 3 + +// IRTBRp_ELx system registers + sysreg_name1 IRTBRU EL1 + sysreg_name1 IRTBRU EL12 + sysreg_name1 IRTBRU EL2 + sysreg_name1 IRTBRP EL1 + sysreg_name1 IRTBRP EL12 + sysreg_name1 IRTBRP EL2 + sysreg_name1 IRTBRP EL3 + +// LDSTT_ELx system registers + sysreg_name1 LDSTT EL1 + sysreg_name1 LDSTT EL12 + sysreg_name1 LDSTT EL2 + +// STINDEX_ELx system registers + sysreg_name1 STINDEX EL1 + sysreg_name1 STINDEX EL12 + sysreg_name1 STINDEX EL2 + +// TINDEX_ELx system registers + sysreg_name1 TINDEX EL0 + sysreg_name1 TINDEX EL1 + sysreg_name1 TINDEX EL12 + sysreg_name1 TINDEX EL2 + sysreg_name1 TINDEX EL3 + +// TTTBRp_ELx system registers + sysreg_name1 TTTBRU EL1 + sysreg_name1 TTTBRU EL12 + sysreg_name1 TTTBRU EL2 + sysreg_name1 TTTBRP EL1 + sysreg_name1 TTTBRP EL12 + sysreg_name1 TTTBRP EL2 + sysreg_name1 TTTBRP EL3 + +// DPOCR_EL0 system registers + sysreg_name1 DPOCR EL0 + +// VNCCR_EL2 system registers + sysreg_name1 VNCCR EL2 +.noaltmacro diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d new file mode 100644 index 00000000000..936774dfc34 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d @@ -0,0 +1,536 @@ +#as: -I$srcdir/$subdir -march=armv8-a +#source: poe2-sysreg-1.s +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183620 msr afgdtp1_el1, x0 +.*: d5383620 mrs x0, afgdtp1_el1 +.*: d5183640 msr afgdtp2_el1, x0 +.*: d5383640 mrs x0, afgdtp2_el1 +.*: d5183660 msr afgdtp3_el1, x0 +.*: d5383660 mrs x0, afgdtp3_el1 +.*: d5183680 msr afgdtp4_el1, x0 +.*: d5383680 mrs x0, afgdtp4_el1 +.*: d51836a0 msr afgdtp5_el1, x0 +.*: d53836a0 mrs x0, afgdtp5_el1 +.*: d51836c0 msr afgdtp6_el1, x0 +.*: d53836c0 mrs x0, afgdtp6_el1 +.*: d51836e0 msr afgdtp7_el1, x0 +.*: d53836e0 mrs x0, afgdtp7_el1 +.*: d5183700 msr afgdtp8_el1, x0 +.*: d5383700 mrs x0, afgdtp8_el1 +.*: d5183720 msr afgdtp9_el1, x0 +.*: d5383720 mrs x0, afgdtp9_el1 +.*: d5183740 msr afgdtp10_el1, x0 +.*: d5383740 mrs x0, afgdtp10_el1 +.*: d5183760 msr afgdtp11_el1, x0 +.*: d5383760 mrs x0, afgdtp11_el1 +.*: d5183780 msr afgdtp12_el1, x0 +.*: d5383780 mrs x0, afgdtp12_el1 +.*: d51837a0 msr afgdtp13_el1, x0 +.*: d53837a0 mrs x0, afgdtp13_el1 +.*: d51837c0 msr afgdtp14_el1, x0 +.*: d53837c0 mrs x0, afgdtp14_el1 +.*: d51837e0 msr afgdtp15_el1, x0 +.*: d53837e0 mrs x0, afgdtp15_el1 +.*: d51d3600 msr afgdtp0_el12, x0 +.*: d53d3600 mrs x0, afgdtp0_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3640 msr afgdtp2_el12, x0 +.*: d53d3640 mrs x0, afgdtp2_el12 +.*: d51d3660 msr afgdtp3_el12, x0 +.*: d53d3660 mrs x0, afgdtp3_el12 +.*: d51d3680 msr afgdtp4_el12, x0 +.*: d53d3680 mrs x0, afgdtp4_el12 +.*: d51d36a0 msr afgdtp5_el12, x0 +.*: d53d36a0 mrs x0, afgdtp5_el12 +.*: d51d36c0 msr afgdtp6_el12, x0 +.*: d53d36c0 mrs x0, afgdtp6_el12 +.*: d51d36e0 msr afgdtp7_el12, x0 +.*: d53d36e0 mrs x0, afgdtp7_el12 +.*: d51d3700 msr afgdtp8_el12, x0 +.*: d53d3700 mrs x0, afgdtp8_el12 +.*: d51d3720 msr afgdtp9_el12, x0 +.*: d53d3720 mrs x0, afgdtp9_el12 +.*: d51d3740 msr afgdtp10_el12, x0 +.*: d53d3740 mrs x0, afgdtp10_el12 +.*: d51d3760 msr afgdtp11_el12, x0 +.*: d53d3760 mrs x0, afgdtp11_el12 +.*: d51d3780 msr afgdtp12_el12, x0 +.*: d53d3780 mrs x0, afgdtp12_el12 +.*: d51d37a0 msr afgdtp13_el12, x0 +.*: d53d37a0 mrs x0, afgdtp13_el12 +.*: d51d37c0 msr afgdtp14_el12, x0 +.*: d53d37c0 mrs x0, afgdtp14_el12 +.*: d51d37e0 msr afgdtp15_el12, x0 +.*: d53d37e0 mrs x0, afgdtp15_el12 +.*: d51c3600 msr afgdtp0_el2, x0 +.*: d53c3600 mrs x0, afgdtp0_el2 +.*: d51c3620 msr afgdtp1_el2, x0 +.*: d53c3620 mrs x0, afgdtp1_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3660 msr afgdtp3_el2, x0 +.*: d53c3660 mrs x0, afgdtp3_el2 +.*: d51c3680 msr afgdtp4_el2, x0 +.*: d53c3680 mrs x0, afgdtp4_el2 +.*: d51c36a0 msr afgdtp5_el2, x0 +.*: d53c36a0 mrs x0, afgdtp5_el2 +.*: d51c36c0 msr afgdtp6_el2, x0 +.*: d53c36c0 mrs x0, afgdtp6_el2 +.*: d51c36e0 msr afgdtp7_el2, x0 +.*: d53c36e0 mrs x0, afgdtp7_el2 +.*: d51c3700 msr afgdtp8_el2, x0 +.*: d53c3700 mrs x0, afgdtp8_el2 +.*: d51c3720 msr afgdtp9_el2, x0 +.*: d53c3720 mrs x0, afgdtp9_el2 +.*: d51c3740 msr afgdtp10_el2, x0 +.*: d53c3740 mrs x0, afgdtp10_el2 +.*: d51c3760 msr afgdtp11_el2, x0 +.*: d53c3760 mrs x0, afgdtp11_el2 +.*: d51c3780 msr afgdtp12_el2, x0 +.*: d53c3780 mrs x0, afgdtp12_el2 +.*: d51c37a0 msr afgdtp13_el2, x0 +.*: d53c37a0 mrs x0, afgdtp13_el2 +.*: d51c37c0 msr afgdtp14_el2, x0 +.*: d53c37c0 mrs x0, afgdtp14_el2 +.*: d51c37e0 msr afgdtp15_el2, x0 +.*: d53c37e0 mrs x0, afgdtp15_el2 +.*: d51e3600 msr afgdtp0_el3, x0 +.*: d53e3600 mrs x0, afgdtp0_el3 +.*: d51e3620 msr afgdtp1_el3, x0 +.*: d53e3620 mrs x0, afgdtp1_el3 +.*: d51e3640 msr afgdtp2_el3, x0 +.*: d53e3640 mrs x0, afgdtp2_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3680 msr afgdtp4_el3, x0 +.*: d53e3680 mrs x0, afgdtp4_el3 +.*: d51e36a0 msr afgdtp5_el3, x0 +.*: d53e36a0 mrs x0, afgdtp5_el3 +.*: d51e36c0 msr afgdtp6_el3, x0 +.*: d53e36c0 mrs x0, afgdtp6_el3 +.*: d51e36e0 msr afgdtp7_el3, x0 +.*: d53e36e0 mrs x0, afgdtp7_el3 +.*: d51e3700 msr afgdtp8_el3, x0 +.*: d53e3700 mrs x0, afgdtp8_el3 +.*: d51e3720 msr afgdtp9_el3, x0 +.*: d53e3720 mrs x0, afgdtp9_el3 +.*: d51e3740 msr afgdtp10_el3, x0 +.*: d53e3740 mrs x0, afgdtp10_el3 +.*: d51e3760 msr afgdtp11_el3, x0 +.*: d53e3760 mrs x0, afgdtp11_el3 +.*: d51e3780 msr afgdtp12_el3, x0 +.*: d53e3780 mrs x0, afgdtp12_el3 +.*: d51e37a0 msr afgdtp13_el3, x0 +.*: d53e37a0 mrs x0, afgdtp13_el3 +.*: d51e37c0 msr afgdtp14_el3, x0 +.*: d53e37c0 mrs x0, afgdtp14_el3 +.*: d51e37e0 msr afgdtp15_el3, x0 +.*: d53e37e0 mrs x0, afgdtp15_el3 +.*: d5183800 msr afgdtu0_el1, x0 +.*: d5383800 mrs x0, afgdtu0_el1 +.*: d5183820 msr afgdtu1_el1, x0 +.*: d5383820 mrs x0, afgdtu1_el1 +.*: d5183840 msr afgdtu2_el1, x0 +.*: d5383840 mrs x0, afgdtu2_el1 +.*: d5183860 msr afgdtu3_el1, x0 +.*: d5383860 mrs x0, afgdtu3_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d51838a0 msr afgdtu5_el1, x0 +.*: d53838a0 mrs x0, afgdtu5_el1 +.*: d51838c0 msr afgdtu6_el1, x0 +.*: d53838c0 mrs x0, afgdtu6_el1 +.*: d51838e0 msr afgdtu7_el1, x0 +.*: d53838e0 mrs x0, afgdtu7_el1 +.*: d5183900 msr afgdtu8_el1, x0 +.*: d5383900 mrs x0, afgdtu8_el1 +.*: d5183920 msr afgdtu9_el1, x0 +.*: d5383920 mrs x0, afgdtu9_el1 +.*: d5183940 msr afgdtu10_el1, x0 +.*: d5383940 mrs x0, afgdtu10_el1 +.*: d5183960 msr afgdtu11_el1, x0 +.*: d5383960 mrs x0, afgdtu11_el1 +.*: d5183980 msr afgdtu12_el1, x0 +.*: d5383980 mrs x0, afgdtu12_el1 +.*: d51839a0 msr afgdtu13_el1, x0 +.*: d53839a0 mrs x0, afgdtu13_el1 +.*: d51839c0 msr afgdtu14_el1, x0 +.*: d53839c0 mrs x0, afgdtu14_el1 +.*: d51839e0 msr afgdtu15_el1, x0 +.*: d53839e0 mrs x0, afgdtu15_el1 +.*: d51d3800 msr afgdtu0_el12, x0 +.*: d53d3800 mrs x0, afgdtu0_el12 +.*: d51d3820 msr afgdtu1_el12, x0 +.*: d53d3820 mrs x0, afgdtu1_el12 +.*: d51d3840 msr afgdtu2_el12, x0 +.*: d53d3840 mrs x0, afgdtu2_el12 +.*: d51d3860 msr afgdtu3_el12, x0 +.*: d53d3860 mrs x0, afgdtu3_el12 +.*: d51d3880 msr afgdtu4_el12, x0 +.*: d53d3880 mrs x0, afgdtu4_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38c0 msr afgdtu6_el12, x0 +.*: d53d38c0 mrs x0, afgdtu6_el12 +.*: d51d38e0 msr afgdtu7_el12, x0 +.*: d53d38e0 mrs x0, afgdtu7_el12 +.*: d51d3900 msr afgdtu8_el12, x0 +.*: d53d3900 mrs x0, afgdtu8_el12 +.*: d51d3920 msr afgdtu9_el12, x0 +.*: d53d3920 mrs x0, afgdtu9_el12 +.*: d51d3940 msr afgdtu10_el12, x0 +.*: d53d3940 mrs x0, afgdtu10_el12 +.*: d51d3960 msr afgdtu11_el12, x0 +.*: d53d3960 mrs x0, afgdtu11_el12 +.*: d51d3980 msr afgdtu12_el12, x0 +.*: d53d3980 mrs x0, afgdtu12_el12 +.*: d51d39a0 msr afgdtu13_el12, x0 +.*: d53d39a0 mrs x0, afgdtu13_el12 +.*: d51d39c0 msr afgdtu14_el12, x0 +.*: d53d39c0 mrs x0, afgdtu14_el12 +.*: d51d39e0 msr afgdtu15_el12, x0 +.*: d53d39e0 mrs x0, afgdtu15_el12 +.*: d51c3800 msr afgdtu0_el2, x0 +.*: d53c3800 mrs x0, afgdtu0_el2 +.*: d51c3820 msr afgdtu1_el2, x0 +.*: d53c3820 mrs x0, afgdtu1_el2 +.*: d51c3840 msr afgdtu2_el2, x0 +.*: d53c3840 mrs x0, afgdtu2_el2 +.*: d51c3860 msr afgdtu3_el2, x0 +.*: d53c3860 mrs x0, afgdtu3_el2 +.*: d51c3880 msr afgdtu4_el2, x0 +.*: d53c3880 mrs x0, afgdtu4_el2 +.*: d51c38a0 msr afgdtu5_el2, x0 +.*: d53c38a0 mrs x0, afgdtu5_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38e0 msr afgdtu7_el2, x0 +.*: d53c38e0 mrs x0, afgdtu7_el2 +.*: d51c3900 msr afgdtu8_el2, x0 +.*: d53c3900 mrs x0, afgdtu8_el2 +.*: d51c3920 msr afgdtu9_el2, x0 +.*: d53c3920 mrs x0, afgdtu9_el2 +.*: d51c3940 msr afgdtu10_el2, x0 +.*: d53c3940 mrs x0, afgdtu10_el2 +.*: d51c3960 msr afgdtu11_el2, x0 +.*: d53c3960 mrs x0, afgdtu11_el2 +.*: d51c3980 msr afgdtu12_el2, x0 +.*: d53c3980 mrs x0, afgdtu12_el2 +.*: d51c39a0 msr afgdtu13_el2, x0 +.*: d53c39a0 mrs x0, afgdtu13_el2 +.*: d51c39c0 msr afgdtu14_el2, x0 +.*: d53c39c0 mrs x0, afgdtu14_el2 +.*: d51c39e0 msr afgdtu15_el2, x0 +.*: d53c39e0 mrs x0, afgdtu15_el2 +.*: d5183200 msr fgdtp0_el1, x0 +.*: d5383200 mrs x0, fgdtp0_el1 +.*: d5183220 msr fgdtp1_el1, x0 +.*: d5383220 mrs x0, fgdtp1_el1 +.*: d5183240 msr fgdtp2_el1, x0 +.*: d5383240 mrs x0, fgdtp2_el1 +.*: d5183260 msr fgdtp3_el1, x0 +.*: d5383260 mrs x0, fgdtp3_el1 +.*: d5183280 msr fgdtp4_el1, x0 +.*: d5383280 mrs x0, fgdtp4_el1 +.*: d51832a0 msr fgdtp5_el1, x0 +.*: d53832a0 mrs x0, fgdtp5_el1 +.*: d51832c0 msr fgdtp6_el1, x0 +.*: d53832c0 mrs x0, fgdtp6_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d5183300 msr fgdtp8_el1, x0 +.*: d5383300 mrs x0, fgdtp8_el1 +.*: d5183320 msr fgdtp9_el1, x0 +.*: d5383320 mrs x0, fgdtp9_el1 +.*: d5183340 msr fgdtp10_el1, x0 +.*: d5383340 mrs x0, fgdtp10_el1 +.*: d5183360 msr fgdtp11_el1, x0 +.*: d5383360 mrs x0, fgdtp11_el1 +.*: d5183380 msr fgdtp12_el1, x0 +.*: d5383380 mrs x0, fgdtp12_el1 +.*: d51833a0 msr fgdtp13_el1, x0 +.*: d53833a0 mrs x0, fgdtp13_el1 +.*: d51833c0 msr fgdtp14_el1, x0 +.*: d53833c0 mrs x0, fgdtp14_el1 +.*: d51833e0 msr fgdtp15_el1, x0 +.*: d53833e0 mrs x0, fgdtp15_el1 +.*: d51d3200 msr fgdtp0_el12, x0 +.*: d53d3200 mrs x0, fgdtp0_el12 +.*: d51d3220 msr fgdtp1_el12, x0 +.*: d53d3220 mrs x0, fgdtp1_el12 +.*: d51d3240 msr fgdtp2_el12, x0 +.*: d53d3240 mrs x0, fgdtp2_el12 +.*: d51d3260 msr fgdtp3_el12, x0 +.*: d53d3260 mrs x0, fgdtp3_el12 +.*: d51d3280 msr fgdtp4_el12, x0 +.*: d53d3280 mrs x0, fgdtp4_el12 +.*: d51d32a0 msr fgdtp5_el12, x0 +.*: d53d32a0 mrs x0, fgdtp5_el12 +.*: d51d32c0 msr fgdtp6_el12, x0 +.*: d53d32c0 mrs x0, fgdtp6_el12 +.*: d51d32e0 msr fgdtp7_el12, x0 +.*: d53d32e0 mrs x0, fgdtp7_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3320 msr fgdtp9_el12, x0 +.*: d53d3320 mrs x0, fgdtp9_el12 +.*: d51d3340 msr fgdtp10_el12, x0 +.*: d53d3340 mrs x0, fgdtp10_el12 +.*: d51d3360 msr fgdtp11_el12, x0 +.*: d53d3360 mrs x0, fgdtp11_el12 +.*: d51d3380 msr fgdtp12_el12, x0 +.*: d53d3380 mrs x0, fgdtp12_el12 +.*: d51d33a0 msr fgdtp13_el12, x0 +.*: d53d33a0 mrs x0, fgdtp13_el12 +.*: d51d33c0 msr fgdtp14_el12, x0 +.*: d53d33c0 mrs x0, fgdtp14_el12 +.*: d51d33e0 msr fgdtp15_el12, x0 +.*: d53d33e0 mrs x0, fgdtp15_el12 +.*: d51c3200 msr fgdtp0_el2, x0 +.*: d53c3200 mrs x0, fgdtp0_el2 +.*: d51c3220 msr fgdtp1_el2, x0 +.*: d53c3220 mrs x0, fgdtp1_el2 +.*: d51c3240 msr fgdtp2_el2, x0 +.*: d53c3240 mrs x0, fgdtp2_el2 +.*: d51c3260 msr fgdtp3_el2, x0 +.*: d53c3260 mrs x0, fgdtp3_el2 +.*: d51c3280 msr fgdtp4_el2, x0 +.*: d53c3280 mrs x0, fgdtp4_el2 +.*: d51c32a0 msr fgdtp5_el2, x0 +.*: d53c32a0 mrs x0, fgdtp5_el2 +.*: d51c32c0 msr fgdtp6_el2, x0 +.*: d53c32c0 mrs x0, fgdtp6_el2 +.*: d51c32e0 msr fgdtp7_el2, x0 +.*: d53c32e0 mrs x0, fgdtp7_el2 +.*: d51c3300 msr fgdtp8_el2, x0 +.*: d53c3300 mrs x0, fgdtp8_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3340 msr fgdtp10_el2, x0 +.*: d53c3340 mrs x0, fgdtp10_el2 +.*: d51c3360 msr fgdtp11_el2, x0 +.*: d53c3360 mrs x0, fgdtp11_el2 +.*: d51c3380 msr fgdtp12_el2, x0 +.*: d53c3380 mrs x0, fgdtp12_el2 +.*: d51c33a0 msr fgdtp13_el2, x0 +.*: d53c33a0 mrs x0, fgdtp13_el2 +.*: d51c33c0 msr fgdtp14_el2, x0 +.*: d53c33c0 mrs x0, fgdtp14_el2 +.*: d51c33e0 msr fgdtp15_el2, x0 +.*: d53c33e0 mrs x0, fgdtp15_el2 +.*: d51e3200 msr fgdtp0_el3, x0 +.*: d53e3200 mrs x0, fgdtp0_el3 +.*: d51e3220 msr fgdtp1_el3, x0 +.*: d53e3220 mrs x0, fgdtp1_el3 +.*: d51e3240 msr fgdtp2_el3, x0 +.*: d53e3240 mrs x0, fgdtp2_el3 +.*: d51e3260 msr fgdtp3_el3, x0 +.*: d53e3260 mrs x0, fgdtp3_el3 +.*: d51e3280 msr fgdtp4_el3, x0 +.*: d53e3280 mrs x0, fgdtp4_el3 +.*: d51e32a0 msr fgdtp5_el3, x0 +.*: d53e32a0 mrs x0, fgdtp5_el3 +.*: d51e32c0 msr fgdtp6_el3, x0 +.*: d53e32c0 mrs x0, fgdtp6_el3 +.*: d51e32e0 msr fgdtp7_el3, x0 +.*: d53e32e0 mrs x0, fgdtp7_el3 +.*: d51e3300 msr fgdtp8_el3, x0 +.*: d53e3300 mrs x0, fgdtp8_el3 +.*: d51e3320 msr fgdtp9_el3, x0 +.*: d53e3320 mrs x0, fgdtp9_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3360 msr fgdtp11_el3, x0 +.*: d53e3360 mrs x0, fgdtp11_el3 +.*: d51e3380 msr fgdtp12_el3, x0 +.*: d53e3380 mrs x0, fgdtp12_el3 +.*: d51e33a0 msr fgdtp13_el3, x0 +.*: d53e33a0 mrs x0, fgdtp13_el3 +.*: d51e33c0 msr fgdtp14_el3, x0 +.*: d53e33c0 mrs x0, fgdtp14_el3 +.*: d51e33e0 msr fgdtp15_el3, x0 +.*: d53e33e0 mrs x0, fgdtp15_el3 +.*: d5183400 msr fgdtu0_el1, x0 +.*: d5383400 mrs x0, fgdtu0_el1 +.*: d5183420 msr fgdtu1_el1, x0 +.*: d5383420 mrs x0, fgdtu1_el1 +.*: d5183440 msr fgdtu2_el1, x0 +.*: d5383440 mrs x0, fgdtu2_el1 +.*: d5183460 msr fgdtu3_el1, x0 +.*: d5383460 mrs x0, fgdtu3_el1 +.*: d5183480 msr fgdtu4_el1, x0 +.*: d5383480 mrs x0, fgdtu4_el1 +.*: d51834a0 msr fgdtu5_el1, x0 +.*: d53834a0 mrs x0, fgdtu5_el1 +.*: d51834c0 msr fgdtu6_el1, x0 +.*: d53834c0 mrs x0, fgdtu6_el1 +.*: d51834e0 msr fgdtu7_el1, x0 +.*: d53834e0 mrs x0, fgdtu7_el1 +.*: d5183500 msr fgdtu8_el1, x0 +.*: d5383500 mrs x0, fgdtu8_el1 +.*: d5183520 msr fgdtu9_el1, x0 +.*: d5383520 mrs x0, fgdtu9_el1 +.*: d5183540 msr fgdtu10_el1, x0 +.*: d5383540 mrs x0, fgdtu10_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183580 msr fgdtu12_el1, x0 +.*: d5383580 mrs x0, fgdtu12_el1 +.*: d51835a0 msr fgdtu13_el1, x0 +.*: d53835a0 mrs x0, fgdtu13_el1 +.*: d51835c0 msr fgdtu14_el1, x0 +.*: d53835c0 mrs x0, fgdtu14_el1 +.*: d51835e0 msr fgdtu15_el1, x0 +.*: d53835e0 mrs x0, fgdtu15_el1 +.*: d51d3400 msr fgdtu0_el12, x0 +.*: d53d3400 mrs x0, fgdtu0_el12 +.*: d51d3420 msr fgdtu1_el12, x0 +.*: d53d3420 mrs x0, fgdtu1_el12 +.*: d51d3440 msr fgdtu2_el12, x0 +.*: d53d3440 mrs x0, fgdtu2_el12 +.*: d51d3460 msr fgdtu3_el12, x0 +.*: d53d3460 mrs x0, fgdtu3_el12 +.*: d51d3480 msr fgdtu4_el12, x0 +.*: d53d3480 mrs x0, fgdtu4_el12 +.*: d51d34a0 msr fgdtu5_el12, x0 +.*: d53d34a0 mrs x0, fgdtu5_el12 +.*: d51d34c0 msr fgdtu6_el12, x0 +.*: d53d34c0 mrs x0, fgdtu6_el12 +.*: d51d34e0 msr fgdtu7_el12, x0 +.*: d53d34e0 mrs x0, fgdtu7_el12 +.*: d51d3500 msr fgdtu8_el12, x0 +.*: d53d3500 mrs x0, fgdtu8_el12 +.*: d51d3520 msr fgdtu9_el12, x0 +.*: d53d3520 mrs x0, fgdtu9_el12 +.*: d51d3540 msr fgdtu10_el12, x0 +.*: d53d3540 mrs x0, fgdtu10_el12 +.*: d51d3560 msr fgdtu11_el12, x0 +.*: d53d3560 mrs x0, fgdtu11_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d35a0 msr fgdtu13_el12, x0 +.*: d53d35a0 mrs x0, fgdtu13_el12 +.*: d51d35c0 msr fgdtu14_el12, x0 +.*: d53d35c0 mrs x0, fgdtu14_el12 +.*: d51d35e0 msr fgdtu15_el12, x0 +.*: d53d35e0 mrs x0, fgdtu15_el12 +.*: d51c3400 msr fgdtu0_el2, x0 +.*: d53c3400 mrs x0, fgdtu0_el2 +.*: d51c3420 msr fgdtu1_el2, x0 +.*: d53c3420 mrs x0, fgdtu1_el2 +.*: d51c3440 msr fgdtu2_el2, x0 +.*: d53c3440 mrs x0, fgdtu2_el2 +.*: d51c3460 msr fgdtu3_el2, x0 +.*: d53c3460 mrs x0, fgdtu3_el2 +.*: d51c3480 msr fgdtu4_el2, x0 +.*: d53c3480 mrs x0, fgdtu4_el2 +.*: d51c34a0 msr fgdtu5_el2, x0 +.*: d53c34a0 mrs x0, fgdtu5_el2 +.*: d51c34c0 msr fgdtu6_el2, x0 +.*: d53c34c0 mrs x0, fgdtu6_el2 +.*: d51c34e0 msr fgdtu7_el2, x0 +.*: d53c34e0 mrs x0, fgdtu7_el2 +.*: d51c3500 msr fgdtu8_el2, x0 +.*: d53c3500 mrs x0, fgdtu8_el2 +.*: d51c3520 msr fgdtu9_el2, x0 +.*: d53c3520 mrs x0, fgdtu9_el2 +.*: d51c3540 msr fgdtu10_el2, x0 +.*: d53c3540 mrs x0, fgdtu10_el2 +.*: d51c3560 msr fgdtu11_el2, x0 +.*: d53c3560 mrs x0, fgdtu11_el2 +.*: d51c3580 msr fgdtu12_el2, x0 +.*: d53c3580 mrs x0, fgdtu12_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35c0 msr fgdtu14_el2, x0 +.*: d53c35c0 mrs x0, fgdtu14_el2 +.*: d51c35e0 msr fgdtu15_el2, x0 +.*: d53c35e0 mrs x0, fgdtu15_el2 +.*: d51820c0 msr dpotbr0_el1, x0 +.*: d53820c0 mrs x0, dpotbr0_el1 +.*: d51820e0 msr dpotbr1_el1, x0 +.*: d53820e0 mrs x0, dpotbr1_el1 +.*: d51d20c0 msr dpotbr0_el12, x0 +.*: d53d20c0 mrs x0, dpotbr0_el12 +.*: d51d20e0 msr dpotbr1_el12, x0 +.*: d53d20e0 mrs x0, dpotbr1_el12 +.*: d51c20c0 msr dpotbr0_el2, x0 +.*: d53c20c0 mrs x0, dpotbr0_el2 +.*: d51c20e0 msr dpotbr1_el2, x0 +.*: d53c20e0 mrs x0, dpotbr1_el2 +.*: d51e20c0 msr dpotbr0_el3, x0 +.*: d53e20c0 mrs x0, dpotbr0_el3 +.*: d51bd000 msr tpidr3_el0, x0 +.*: d53bd000 mrs x0, tpidr3_el0 +.*: d518d000 msr tpidr3_el1, x0 +.*: d538d000 mrs x0, tpidr3_el1 +.*: d51dd000 msr tpidr3_el12, x0 +.*: d53dd000 mrs x0, tpidr3_el12 +.*: d51cd000 msr tpidr3_el2, x0 +.*: d53cd000 mrs x0, tpidr3_el2 +.*: d51ed000 msr tpidr3_el3, x0 +.*: d53ed000 mrs x0, tpidr3_el3 +.*: d5182080 msr irtbru_el1, x0 +.*: d5382080 mrs x0, irtbru_el1 +.*: d51d2080 msr irtbru_el12, x0 +.*: d53d2080 mrs x0, irtbru_el12 +.*: d51c2080 msr irtbru_el2, x0 +.*: d53c2080 mrs x0, irtbru_el2 +.*: d51820a0 msr irtbrp_el1, x0 +.*: d53820a0 mrs x0, irtbrp_el1 +.*: d51d20a0 msr irtbrp_el12, x0 +.*: d53d20a0 mrs x0, irtbrp_el12 +.*: d51c20a0 msr irtbrp_el2, x0 +.*: d53c20a0 mrs x0, irtbrp_el2 +.*: d51e20a0 msr irtbrp_el3, x0 +.*: d53e20a0 mrs x0, irtbrp_el3 +.*: d51821e0 msr ldstt_el1, x0 +.*: d53821e0 mrs x0, ldstt_el1 +.*: d51d21e0 msr ldstt_el12, x0 +.*: d53d21e0 mrs x0, ldstt_el12 +.*: d51c21e0 msr ldstt_el2, x0 +.*: d53c21e0 mrs x0, ldstt_el2 +.*: d5184040 msr stindex_el1, x0 +.*: d5384040 mrs x0, stindex_el1 +.*: d51d4040 msr stindex_el12, x0 +.*: d53d4040 mrs x0, stindex_el12 +.*: d51c4040 msr stindex_el2, x0 +.*: d53c4040 mrs x0, stindex_el2 +.*: d51b4060 msr tindex_el0, x0 +.*: d53b4060 mrs x0, tindex_el0 +.*: d5184060 msr tindex_el1, x0 +.*: d5384060 mrs x0, tindex_el1 +.*: d51d4060 msr tindex_el12, x0 +.*: d53d4060 mrs x0, tindex_el12 +.*: d51c4060 msr tindex_el2, x0 +.*: d53c4060 mrs x0, tindex_el2 +.*: d51e4060 msr tindex_el3, x0 +.*: d53e4060 mrs x0, tindex_el3 +.*: d518a2c0 msr tttbru_el1, x0 +.*: d538a2c0 mrs x0, tttbru_el1 +.*: d51da2c0 msr tttbru_el12, x0 +.*: d53da2c0 mrs x0, tttbru_el12 +.*: d51ca2c0 msr tttbru_el2, x0 +.*: d53ca2c0 mrs x0, tttbru_el2 +.*: d518a2e0 msr tttbrp_el1, x0 +.*: d538a2e0 mrs x0, tttbrp_el1 +.*: d51da2e0 msr tttbrp_el12, x0 +.*: d53da2e0 mrs x0, tttbrp_el12 +.*: d51ca2e0 msr tttbrp_el2, x0 +.*: d53ca2e0 mrs x0, tttbrp_el2 +.*: d51ea2e0 msr tttbrp_el3, x0 +.*: d53ea2e0 mrs x0, tttbrp_el3 +.*: d51b4540 msr dpocr_el0, x0 +.*: d53b4540 mrs x0, dpocr_el0 +.*: d51c2220 msr vnccr_el2, x0 +.*: d53c2220 mrs x0, vnccr_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.d b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.d new file mode 100644 index 00000000000..14a7762376a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.d @@ -0,0 +1,4 @@ +#name: Invalid system registers without +poe2 flag and forced checking. +#source: poe2-sysreg-1.s +#as: -menable-sysreg-checking -I$srcdir/$subdir -march=armv8-a --no-info +#error_output: poe2-sysreg-invalid-1.l diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.l b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.l new file mode 100644 index 00000000000..19cc928f89a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-invalid-1.l @@ -0,0 +1,527 @@ +.*: Assembler messages: +.*: Error: selected processor does not support system register name 'afgdtp0_el1' +.*: Error: selected processor does not support system register name 'afgdtp0_el1' +.*: Error: selected processor does not support system register name 'afgdtp1_el1' +.*: Error: selected processor does not support system register name 'afgdtp1_el1' +.*: Error: selected processor does not support system register name 'afgdtp2_el1' +.*: Error: selected processor does not support system register name 'afgdtp2_el1' +.*: Error: selected processor does not support system register name 'afgdtp3_el1' +.*: Error: selected processor does not support system register name 'afgdtp3_el1' +.*: Error: selected processor does not support system register name 'afgdtp4_el1' +.*: Error: selected processor does not support system register name 'afgdtp4_el1' +.*: Error: selected processor does not support system register name 'afgdtp5_el1' +.*: Error: selected processor does not support system register name 'afgdtp5_el1' +.*: Error: selected processor does not support system register name 'afgdtp6_el1' +.*: Error: selected processor does not support system register name 'afgdtp6_el1' +.*: Error: selected processor does not support system register name 'afgdtp7_el1' +.*: Error: selected processor does not support system register name 'afgdtp7_el1' +.*: Error: selected processor does not support system register name 'afgdtp8_el1' +.*: Error: selected processor does not support system register name 'afgdtp8_el1' +.*: Error: selected processor does not support system register name 'afgdtp9_el1' +.*: Error: selected processor does not support system register name 'afgdtp9_el1' +.*: Error: selected processor does not support system register name 'afgdtp10_el1' +.*: Error: selected processor does not support system register name 'afgdtp10_el1' +.*: Error: selected processor does not support system register name 'afgdtp11_el1' +.*: Error: selected processor does not support system register name 'afgdtp11_el1' +.*: Error: selected processor does not support system register name 'afgdtp12_el1' +.*: Error: selected processor does not support system register name 'afgdtp12_el1' +.*: Error: selected processor does not support system register name 'afgdtp13_el1' +.*: Error: selected processor does not support system register name 'afgdtp13_el1' +.*: Error: selected processor does not support system register name 'afgdtp14_el1' +.*: Error: selected processor does not support system register name 'afgdtp14_el1' +.*: Error: selected processor does not support system register name 'afgdtp15_el1' +.*: Error: selected processor does not support system register name 'afgdtp15_el1' +.*: Error: selected processor does not support system register name 'afgdtp0_el12' +.*: Error: selected processor does not support system register name 'afgdtp0_el12' +.*: Error: selected processor does not support system register name 'afgdtp1_el12' +.*: Error: selected processor does not support system register name 'afgdtp1_el12' +.*: Error: selected processor does not support system register name 'afgdtp2_el12' +.*: Error: selected processor does not support system register name 'afgdtp2_el12' +.*: Error: selected processor does not support system register name 'afgdtp3_el12' +.*: Error: selected processor does not support system register name 'afgdtp3_el12' +.*: Error: selected processor does not support system register name 'afgdtp4_el12' +.*: Error: selected processor does not support system register name 'afgdtp4_el12' +.*: Error: selected processor does not support system register name 'afgdtp5_el12' +.*: Error: selected processor does not support system register name 'afgdtp5_el12' +.*: Error: selected processor does not support system register name 'afgdtp6_el12' +.*: Error: selected processor does not support system register name 'afgdtp6_el12' +.*: Error: selected processor does not support system register name 'afgdtp7_el12' +.*: Error: selected processor does not support system register name 'afgdtp7_el12' +.*: Error: selected processor does not support system register name 'afgdtp8_el12' +.*: Error: selected processor does not support system register name 'afgdtp8_el12' +.*: Error: selected processor does not support system register name 'afgdtp9_el12' +.*: Error: selected processor does not support system register name 'afgdtp9_el12' +.*: Error: selected processor does not support system register name 'afgdtp10_el12' +.*: Error: selected processor does not support system register name 'afgdtp10_el12' +.*: Error: selected processor does not support system register name 'afgdtp11_el12' +.*: Error: selected processor does not support system register name 'afgdtp11_el12' +.*: Error: selected processor does not support system register name 'afgdtp12_el12' +.*: Error: selected processor does not support system register name 'afgdtp12_el12' +.*: Error: selected processor does not support system register name 'afgdtp13_el12' +.*: Error: selected processor does not support system register name 'afgdtp13_el12' +.*: Error: selected processor does not support system register name 'afgdtp14_el12' +.*: Error: selected processor does not support system register name 'afgdtp14_el12' +.*: Error: selected processor does not support system register name 'afgdtp15_el12' +.*: Error: selected processor does not support system register name 'afgdtp15_el12' +.*: Error: selected processor does not support system register name 'afgdtp0_el2' +.*: Error: selected processor does not support system register name 'afgdtp0_el2' +.*: Error: selected processor does not support system register name 'afgdtp1_el2' +.*: Error: selected processor does not support system register name 'afgdtp1_el2' +.*: Error: selected processor does not support system register name 'afgdtp2_el2' +.*: Error: selected processor does not support system register name 'afgdtp2_el2' +.*: Error: selected processor does not support system register name 'afgdtp3_el2' +.*: Error: selected processor does not support system register name 'afgdtp3_el2' +.*: Error: selected processor does not support system register name 'afgdtp4_el2' +.*: Error: selected processor does not support system register name 'afgdtp4_el2' +.*: Error: selected processor does not support system register name 'afgdtp5_el2' +.*: Error: selected processor does not support system register name 'afgdtp5_el2' +.*: Error: selected processor does not support system register name 'afgdtp6_el2' +.*: Error: selected processor does not support system register name 'afgdtp6_el2' +.*: Error: selected processor does not support system register name 'afgdtp7_el2' +.*: Error: selected processor does not support system register name 'afgdtp7_el2' +.*: Error: selected processor does not support system register name 'afgdtp8_el2' +.*: Error: selected processor does not support system register name 'afgdtp8_el2' +.*: Error: selected processor does not support system register name 'afgdtp9_el2' +.*: Error: selected processor does not support system register name 'afgdtp9_el2' +.*: Error: selected processor does not support system register name 'afgdtp10_el2' +.*: Error: selected processor does not support system register name 'afgdtp10_el2' +.*: Error: selected processor does not support system register name 'afgdtp11_el2' +.*: Error: selected processor does not support system register name 'afgdtp11_el2' +.*: Error: selected processor does not support system register name 'afgdtp12_el2' +.*: Error: selected processor does not support system register name 'afgdtp12_el2' +.*: Error: selected processor does not support system register name 'afgdtp13_el2' +.*: Error: selected processor does not support system register name 'afgdtp13_el2' +.*: Error: selected processor does not support system register name 'afgdtp14_el2' +.*: Error: selected processor does not support system register name 'afgdtp14_el2' +.*: Error: selected processor does not support system register name 'afgdtp15_el2' +.*: Error: selected processor does not support system register name 'afgdtp15_el2' +.*: Error: selected processor does not support system register name 'afgdtp0_el3' +.*: Error: selected processor does not support system register name 'afgdtp0_el3' +.*: Error: selected processor does not support system register name 'afgdtp1_el3' +.*: Error: selected processor does not support system register name 'afgdtp1_el3' +.*: Error: selected processor does not support system register name 'afgdtp2_el3' +.*: Error: selected processor does not support system register name 'afgdtp2_el3' +.*: Error: selected processor does not support system register name 'afgdtp3_el3' +.*: Error: selected processor does not support system register name 'afgdtp3_el3' +.*: Error: selected processor does not support system register name 'afgdtp4_el3' +.*: Error: selected processor does not support system register name 'afgdtp4_el3' +.*: Error: selected processor does not support system register name 'afgdtp5_el3' +.*: Error: selected processor does not support system register name 'afgdtp5_el3' +.*: Error: selected processor does not support system register name 'afgdtp6_el3' +.*: Error: selected processor does not support system register name 'afgdtp6_el3' +.*: Error: selected processor does not support system register name 'afgdtp7_el3' +.*: Error: selected processor does not support system register name 'afgdtp7_el3' +.*: Error: selected processor does not support system register name 'afgdtp8_el3' +.*: Error: selected processor does not support system register name 'afgdtp8_el3' +.*: Error: selected processor does not support system register name 'afgdtp9_el3' +.*: Error: selected processor does not support system register name 'afgdtp9_el3' +.*: Error: selected processor does not support system register name 'afgdtp10_el3' +.*: Error: selected processor does not support system register name 'afgdtp10_el3' +.*: Error: selected processor does not support system register name 'afgdtp11_el3' +.*: Error: selected processor does not support system register name 'afgdtp11_el3' +.*: Error: selected processor does not support system register name 'afgdtp12_el3' +.*: Error: selected processor does not support system register name 'afgdtp12_el3' +.*: Error: selected processor does not support system register name 'afgdtp13_el3' +.*: Error: selected processor does not support system register name 'afgdtp13_el3' +.*: Error: selected processor does not support system register name 'afgdtp14_el3' +.*: Error: selected processor does not support system register name 'afgdtp14_el3' +.*: Error: selected processor does not support system register name 'afgdtp15_el3' +.*: Error: selected processor does not support system register name 'afgdtp15_el3' +.*: Error: selected processor does not support system register name 'afgdtu0_el1' +.*: Error: selected processor does not support system register name 'afgdtu0_el1' +.*: Error: selected processor does not support system register name 'afgdtu1_el1' +.*: Error: selected processor does not support system register name 'afgdtu1_el1' +.*: Error: selected processor does not support system register name 'afgdtu2_el1' +.*: Error: selected processor does not support system register name 'afgdtu2_el1' +.*: Error: selected processor does not support system register name 'afgdtu3_el1' +.*: Error: selected processor does not support system register name 'afgdtu3_el1' +.*: Error: selected processor does not support system register name 'afgdtu4_el1' +.*: Error: selected processor does not support system register name 'afgdtu4_el1' +.*: Error: selected processor does not support system register name 'afgdtu5_el1' +.*: Error: selected processor does not support system register name 'afgdtu5_el1' +.*: Error: selected processor does not support system register name 'afgdtu6_el1' +.*: Error: selected processor does not support system register name 'afgdtu6_el1' +.*: Error: selected processor does not support system register name 'afgdtu7_el1' +.*: Error: selected processor does not support system register name 'afgdtu7_el1' +.*: Error: selected processor does not support system register name 'afgdtu8_el1' +.*: Error: selected processor does not support system register name 'afgdtu8_el1' +.*: Error: selected processor does not support system register name 'afgdtu9_el1' +.*: Error: selected processor does not support system register name 'afgdtu9_el1' +.*: Error: selected processor does not support system register name 'afgdtu10_el1' +.*: Error: selected processor does not support system register name 'afgdtu10_el1' +.*: Error: selected processor does not support system register name 'afgdtu11_el1' +.*: Error: selected processor does not support system register name 'afgdtu11_el1' +.*: Error: selected processor does not support system register name 'afgdtu12_el1' +.*: Error: selected processor does not support system register name 'afgdtu12_el1' +.*: Error: selected processor does not support system register name 'afgdtu13_el1' +.*: Error: selected processor does not support system register name 'afgdtu13_el1' +.*: Error: selected processor does not support system register name 'afgdtu14_el1' +.*: Error: selected processor does not support system register name 'afgdtu14_el1' +.*: Error: selected processor does not support system register name 'afgdtu15_el1' +.*: Error: selected processor does not support system register name 'afgdtu15_el1' +.*: Error: selected processor does not support system register name 'afgdtu0_el12' +.*: Error: selected processor does not support system register name 'afgdtu0_el12' +.*: Error: selected processor does not support system register name 'afgdtu1_el12' +.*: Error: selected processor does not support system register name 'afgdtu1_el12' +.*: Error: selected processor does not support system register name 'afgdtu2_el12' +.*: Error: selected processor does not support system register name 'afgdtu2_el12' +.*: Error: selected processor does not support system register name 'afgdtu3_el12' +.*: Error: selected processor does not support system register name 'afgdtu3_el12' +.*: Error: selected processor does not support system register name 'afgdtu4_el12' +.*: Error: selected processor does not support system register name 'afgdtu4_el12' +.*: Error: selected processor does not support system register name 'afgdtu5_el12' +.*: Error: selected processor does not support system register name 'afgdtu5_el12' +.*: Error: selected processor does not support system register name 'afgdtu6_el12' +.*: Error: selected processor does not support system register name 'afgdtu6_el12' +.*: Error: selected processor does not support system register name 'afgdtu7_el12' +.*: Error: selected processor does not support system register name 'afgdtu7_el12' +.*: Error: selected processor does not support system register name 'afgdtu8_el12' +.*: Error: selected processor does not support system register name 'afgdtu8_el12' +.*: Error: selected processor does not support system register name 'afgdtu9_el12' +.*: Error: selected processor does not support system register name 'afgdtu9_el12' +.*: Error: selected processor does not support system register name 'afgdtu10_el12' +.*: Error: selected processor does not support system register name 'afgdtu10_el12' +.*: Error: selected processor does not support system register name 'afgdtu11_el12' +.*: Error: selected processor does not support system register name 'afgdtu11_el12' +.*: Error: selected processor does not support system register name 'afgdtu12_el12' +.*: Error: selected processor does not support system register name 'afgdtu12_el12' +.*: Error: selected processor does not support system register name 'afgdtu13_el12' +.*: Error: selected processor does not support system register name 'afgdtu13_el12' +.*: Error: selected processor does not support system register name 'afgdtu14_el12' +.*: Error: selected processor does not support system register name 'afgdtu14_el12' +.*: Error: selected processor does not support system register name 'afgdtu15_el12' +.*: Error: selected processor does not support system register name 'afgdtu15_el12' +.*: Error: selected processor does not support system register name 'afgdtu0_el2' +.*: Error: selected processor does not support system register name 'afgdtu0_el2' +.*: Error: selected processor does not support system register name 'afgdtu1_el2' +.*: Error: selected processor does not support system register name 'afgdtu1_el2' +.*: Error: selected processor does not support system register name 'afgdtu2_el2' +.*: Error: selected processor does not support system register name 'afgdtu2_el2' +.*: Error: selected processor does not support system register name 'afgdtu3_el2' +.*: Error: selected processor does not support system register name 'afgdtu3_el2' +.*: Error: selected processor does not support system register name 'afgdtu4_el2' +.*: Error: selected processor does not support system register name 'afgdtu4_el2' +.*: Error: selected processor does not support system register name 'afgdtu5_el2' +.*: Error: selected processor does not support system register name 'afgdtu5_el2' +.*: Error: selected processor does not support system register name 'afgdtu6_el2' +.*: Error: selected processor does not support system register name 'afgdtu6_el2' +.*: Error: selected processor does not support system register name 'afgdtu7_el2' +.*: Error: selected processor does not support system register name 'afgdtu7_el2' +.*: Error: selected processor does not support system register name 'afgdtu8_el2' +.*: Error: selected processor does not support system register name 'afgdtu8_el2' +.*: Error: selected processor does not support system register name 'afgdtu9_el2' +.*: Error: selected processor does not support system register name 'afgdtu9_el2' +.*: Error: selected processor does not support system register name 'afgdtu10_el2' +.*: Error: selected processor does not support system register name 'afgdtu10_el2' +.*: Error: selected processor does not support system register name 'afgdtu11_el2' +.*: Error: selected processor does not support system register name 'afgdtu11_el2' +.*: Error: selected processor does not support system register name 'afgdtu12_el2' +.*: Error: selected processor does not support system register name 'afgdtu12_el2' +.*: Error: selected processor does not support system register name 'afgdtu13_el2' +.*: Error: selected processor does not support system register name 'afgdtu13_el2' +.*: Error: selected processor does not support system register name 'afgdtu14_el2' +.*: Error: selected processor does not support system register name 'afgdtu14_el2' +.*: Error: selected processor does not support system register name 'afgdtu15_el2' +.*: Error: selected processor does not support system register name 'afgdtu15_el2' +.*: Error: selected processor does not support system register name 'fgdtp0_el1' +.*: Error: selected processor does not support system register name 'fgdtp0_el1' +.*: Error: selected processor does not support system register name 'fgdtp1_el1' +.*: Error: selected processor does not support system register name 'fgdtp1_el1' +.*: Error: selected processor does not support system register name 'fgdtp2_el1' +.*: Error: selected processor does not support system register name 'fgdtp2_el1' +.*: Error: selected processor does not support system register name 'fgdtp3_el1' +.*: Error: selected processor does not support system register name 'fgdtp3_el1' +.*: Error: selected processor does not support system register name 'fgdtp4_el1' +.*: Error: selected processor does not support system register name 'fgdtp4_el1' +.*: Error: selected processor does not support system register name 'fgdtp5_el1' +.*: Error: selected processor does not support system register name 'fgdtp5_el1' +.*: Error: selected processor does not support system register name 'fgdtp6_el1' +.*: Error: selected processor does not support system register name 'fgdtp6_el1' +.*: Error: selected processor does not support system register name 'fgdtp7_el1' +.*: Error: selected processor does not support system register name 'fgdtp7_el1' +.*: Error: selected processor does not support system register name 'fgdtp8_el1' +.*: Error: selected processor does not support system register name 'fgdtp8_el1' +.*: Error: selected processor does not support system register name 'fgdtp9_el1' +.*: Error: selected processor does not support system register name 'fgdtp9_el1' +.*: Error: selected processor does not support system register name 'fgdtp10_el1' +.*: Error: selected processor does not support system register name 'fgdtp10_el1' +.*: Error: selected processor does not support system register name 'fgdtp11_el1' +.*: Error: selected processor does not support system register name 'fgdtp11_el1' +.*: Error: selected processor does not support system register name 'fgdtp12_el1' +.*: Error: selected processor does not support system register name 'fgdtp12_el1' +.*: Error: selected processor does not support system register name 'fgdtp13_el1' +.*: Error: selected processor does not support system register name 'fgdtp13_el1' +.*: Error: selected processor does not support system register name 'fgdtp14_el1' +.*: Error: selected processor does not support system register name 'fgdtp14_el1' +.*: Error: selected processor does not support system register name 'fgdtp15_el1' +.*: Error: selected processor does not support system register name 'fgdtp15_el1' +.*: Error: selected processor does not support system register name 'fgdtp0_el12' +.*: Error: selected processor does not support system register name 'fgdtp0_el12' +.*: Error: selected processor does not support system register name 'fgdtp1_el12' +.*: Error: selected processor does not support system register name 'fgdtp1_el12' +.*: Error: selected processor does not support system register name 'fgdtp2_el12' +.*: Error: selected processor does not support system register name 'fgdtp2_el12' +.*: Error: selected processor does not support system register name 'fgdtp3_el12' +.*: Error: selected processor does not support system register name 'fgdtp3_el12' +.*: Error: selected processor does not support system register name 'fgdtp4_el12' +.*: Error: selected processor does not support system register name 'fgdtp4_el12' +.*: Error: selected processor does not support system register name 'fgdtp5_el12' +.*: Error: selected processor does not support system register name 'fgdtp5_el12' +.*: Error: selected processor does not support system register name 'fgdtp6_el12' +.*: Error: selected processor does not support system register name 'fgdtp6_el12' +.*: Error: selected processor does not support system register name 'fgdtp7_el12' +.*: Error: selected processor does not support system register name 'fgdtp7_el12' +.*: Error: selected processor does not support system register name 'fgdtp8_el12' +.*: Error: selected processor does not support system register name 'fgdtp8_el12' +.*: Error: selected processor does not support system register name 'fgdtp9_el12' +.*: Error: selected processor does not support system register name 'fgdtp9_el12' +.*: Error: selected processor does not support system register name 'fgdtp10_el12' +.*: Error: selected processor does not support system register name 'fgdtp10_el12' +.*: Error: selected processor does not support system register name 'fgdtp11_el12' +.*: Error: selected processor does not support system register name 'fgdtp11_el12' +.*: Error: selected processor does not support system register name 'fgdtp12_el12' +.*: Error: selected processor does not support system register name 'fgdtp12_el12' +.*: Error: selected processor does not support system register name 'fgdtp13_el12' +.*: Error: selected processor does not support system register name 'fgdtp13_el12' +.*: Error: selected processor does not support system register name 'fgdtp14_el12' +.*: Error: selected processor does not support system register name 'fgdtp14_el12' +.*: Error: selected processor does not support system register name 'fgdtp15_el12' +.*: Error: selected processor does not support system register name 'fgdtp15_el12' +.*: Error: selected processor does not support system register name 'fgdtp0_el2' +.*: Error: selected processor does not support system register name 'fgdtp0_el2' +.*: Error: selected processor does not support system register name 'fgdtp1_el2' +.*: Error: selected processor does not support system register name 'fgdtp1_el2' +.*: Error: selected processor does not support system register name 'fgdtp2_el2' +.*: Error: selected processor does not support system register name 'fgdtp2_el2' +.*: Error: selected processor does not support system register name 'fgdtp3_el2' +.*: Error: selected processor does not support system register name 'fgdtp3_el2' +.*: Error: selected processor does not support system register name 'fgdtp4_el2' +.*: Error: selected processor does not support system register name 'fgdtp4_el2' +.*: Error: selected processor does not support system register name 'fgdtp5_el2' +.*: Error: selected processor does not support system register name 'fgdtp5_el2' +.*: Error: selected processor does not support system register name 'fgdtp6_el2' +.*: Error: selected processor does not support system register name 'fgdtp6_el2' +.*: Error: selected processor does not support system register name 'fgdtp7_el2' +.*: Error: selected processor does not support system register name 'fgdtp7_el2' +.*: Error: selected processor does not support system register name 'fgdtp8_el2' +.*: Error: selected processor does not support system register name 'fgdtp8_el2' +.*: Error: selected processor does not support system register name 'fgdtp9_el2' +.*: Error: selected processor does not support system register name 'fgdtp9_el2' +.*: Error: selected processor does not support system register name 'fgdtp10_el2' +.*: Error: selected processor does not support system register name 'fgdtp10_el2' +.*: Error: selected processor does not support system register name 'fgdtp11_el2' +.*: Error: selected processor does not support system register name 'fgdtp11_el2' +.*: Error: selected processor does not support system register name 'fgdtp12_el2' +.*: Error: selected processor does not support system register name 'fgdtp12_el2' +.*: Error: selected processor does not support system register name 'fgdtp13_el2' +.*: Error: selected processor does not support system register name 'fgdtp13_el2' +.*: Error: selected processor does not support system register name 'fgdtp14_el2' +.*: Error: selected processor does not support system register name 'fgdtp14_el2' +.*: Error: selected processor does not support system register name 'fgdtp15_el2' +.*: Error: selected processor does not support system register name 'fgdtp15_el2' +.*: Error: selected processor does not support system register name 'fgdtp0_el3' +.*: Error: selected processor does not support system register name 'fgdtp0_el3' +.*: Error: selected processor does not support system register name 'fgdtp1_el3' +.*: Error: selected processor does not support system register name 'fgdtp1_el3' +.*: Error: selected processor does not support system register name 'fgdtp2_el3' +.*: Error: selected processor does not support system register name 'fgdtp2_el3' +.*: Error: selected processor does not support system register name 'fgdtp3_el3' +.*: Error: selected processor does not support system register name 'fgdtp3_el3' +.*: Error: selected processor does not support system register name 'fgdtp4_el3' +.*: Error: selected processor does not support system register name 'fgdtp4_el3' +.*: Error: selected processor does not support system register name 'fgdtp5_el3' +.*: Error: selected processor does not support system register name 'fgdtp5_el3' +.*: Error: selected processor does not support system register name 'fgdtp6_el3' +.*: Error: selected processor does not support system register name 'fgdtp6_el3' +.*: Error: selected processor does not support system register name 'fgdtp7_el3' +.*: Error: selected processor does not support system register name 'fgdtp7_el3' +.*: Error: selected processor does not support system register name 'fgdtp8_el3' +.*: Error: selected processor does not support system register name 'fgdtp8_el3' +.*: Error: selected processor does not support system register name 'fgdtp9_el3' +.*: Error: selected processor does not support system register name 'fgdtp9_el3' +.*: Error: selected processor does not support system register name 'fgdtp10_el3' +.*: Error: selected processor does not support system register name 'fgdtp10_el3' +.*: Error: selected processor does not support system register name 'fgdtp11_el3' +.*: Error: selected processor does not support system register name 'fgdtp11_el3' +.*: Error: selected processor does not support system register name 'fgdtp12_el3' +.*: Error: selected processor does not support system register name 'fgdtp12_el3' +.*: Error: selected processor does not support system register name 'fgdtp13_el3' +.*: Error: selected processor does not support system register name 'fgdtp13_el3' +.*: Error: selected processor does not support system register name 'fgdtp14_el3' +.*: Error: selected processor does not support system register name 'fgdtp14_el3' +.*: Error: selected processor does not support system register name 'fgdtp15_el3' +.*: Error: selected processor does not support system register name 'fgdtp15_el3' +.*: Error: selected processor does not support system register name 'fgdtu0_el1' +.*: Error: selected processor does not support system register name 'fgdtu0_el1' +.*: Error: selected processor does not support system register name 'fgdtu1_el1' +.*: Error: selected processor does not support system register name 'fgdtu1_el1' +.*: Error: selected processor does not support system register name 'fgdtu2_el1' +.*: Error: selected processor does not support system register name 'fgdtu2_el1' +.*: Error: selected processor does not support system register name 'fgdtu3_el1' +.*: Error: selected processor does not support system register name 'fgdtu3_el1' +.*: Error: selected processor does not support system register name 'fgdtu4_el1' +.*: Error: selected processor does not support system register name 'fgdtu4_el1' +.*: Error: selected processor does not support system register name 'fgdtu5_el1' +.*: Error: selected processor does not support system register name 'fgdtu5_el1' +.*: Error: selected processor does not support system register name 'fgdtu6_el1' +.*: Error: selected processor does not support system register name 'fgdtu6_el1' +.*: Error: selected processor does not support system register name 'fgdtu7_el1' +.*: Error: selected processor does not support system register name 'fgdtu7_el1' +.*: Error: selected processor does not support system register name 'fgdtu8_el1' +.*: Error: selected processor does not support system register name 'fgdtu8_el1' +.*: Error: selected processor does not support system register name 'fgdtu9_el1' +.*: Error: selected processor does not support system register name 'fgdtu9_el1' +.*: Error: selected processor does not support system register name 'fgdtu10_el1' +.*: Error: selected processor does not support system register name 'fgdtu10_el1' +.*: Error: selected processor does not support system register name 'fgdtu11_el1' +.*: Error: selected processor does not support system register name 'fgdtu11_el1' +.*: Error: selected processor does not support system register name 'fgdtu12_el1' +.*: Error: selected processor does not support system register name 'fgdtu12_el1' +.*: Error: selected processor does not support system register name 'fgdtu13_el1' +.*: Error: selected processor does not support system register name 'fgdtu13_el1' +.*: Error: selected processor does not support system register name 'fgdtu14_el1' +.*: Error: selected processor does not support system register name 'fgdtu14_el1' +.*: Error: selected processor does not support system register name 'fgdtu15_el1' +.*: Error: selected processor does not support system register name 'fgdtu15_el1' +.*: Error: selected processor does not support system register name 'fgdtu0_el12' +.*: Error: selected processor does not support system register name 'fgdtu0_el12' +.*: Error: selected processor does not support system register name 'fgdtu1_el12' +.*: Error: selected processor does not support system register name 'fgdtu1_el12' +.*: Error: selected processor does not support system register name 'fgdtu2_el12' +.*: Error: selected processor does not support system register name 'fgdtu2_el12' +.*: Error: selected processor does not support system register name 'fgdtu3_el12' +.*: Error: selected processor does not support system register name 'fgdtu3_el12' +.*: Error: selected processor does not support system register name 'fgdtu4_el12' +.*: Error: selected processor does not support system register name 'fgdtu4_el12' +.*: Error: selected processor does not support system register name 'fgdtu5_el12' +.*: Error: selected processor does not support system register name 'fgdtu5_el12' +.*: Error: selected processor does not support system register name 'fgdtu6_el12' +.*: Error: selected processor does not support system register name 'fgdtu6_el12' +.*: Error: selected processor does not support system register name 'fgdtu7_el12' +.*: Error: selected processor does not support system register name 'fgdtu7_el12' +.*: Error: selected processor does not support system register name 'fgdtu8_el12' +.*: Error: selected processor does not support system register name 'fgdtu8_el12' +.*: Error: selected processor does not support system register name 'fgdtu9_el12' +.*: Error: selected processor does not support system register name 'fgdtu9_el12' +.*: Error: selected processor does not support system register name 'fgdtu10_el12' +.*: Error: selected processor does not support system register name 'fgdtu10_el12' +.*: Error: selected processor does not support system register name 'fgdtu11_el12' +.*: Error: selected processor does not support system register name 'fgdtu11_el12' +.*: Error: selected processor does not support system register name 'fgdtu12_el12' +.*: Error: selected processor does not support system register name 'fgdtu12_el12' +.*: Error: selected processor does not support system register name 'fgdtu13_el12' +.*: Error: selected processor does not support system register name 'fgdtu13_el12' +.*: Error: selected processor does not support system register name 'fgdtu14_el12' +.*: Error: selected processor does not support system register name 'fgdtu14_el12' +.*: Error: selected processor does not support system register name 'fgdtu15_el12' +.*: Error: selected processor does not support system register name 'fgdtu15_el12' +.*: Error: selected processor does not support system register name 'fgdtu0_el2' +.*: Error: selected processor does not support system register name 'fgdtu0_el2' +.*: Error: selected processor does not support system register name 'fgdtu1_el2' +.*: Error: selected processor does not support system register name 'fgdtu1_el2' +.*: Error: selected processor does not support system register name 'fgdtu2_el2' +.*: Error: selected processor does not support system register name 'fgdtu2_el2' +.*: Error: selected processor does not support system register name 'fgdtu3_el2' +.*: Error: selected processor does not support system register name 'fgdtu3_el2' +.*: Error: selected processor does not support system register name 'fgdtu4_el2' +.*: Error: selected processor does not support system register name 'fgdtu4_el2' +.*: Error: selected processor does not support system register name 'fgdtu5_el2' +.*: Error: selected processor does not support system register name 'fgdtu5_el2' +.*: Error: selected processor does not support system register name 'fgdtu6_el2' +.*: Error: selected processor does not support system register name 'fgdtu6_el2' +.*: Error: selected processor does not support system register name 'fgdtu7_el2' +.*: Error: selected processor does not support system register name 'fgdtu7_el2' +.*: Error: selected processor does not support system register name 'fgdtu8_el2' +.*: Error: selected processor does not support system register name 'fgdtu8_el2' +.*: Error: selected processor does not support system register name 'fgdtu9_el2' +.*: Error: selected processor does not support system register name 'fgdtu9_el2' +.*: Error: selected processor does not support system register name 'fgdtu10_el2' +.*: Error: selected processor does not support system register name 'fgdtu10_el2' +.*: Error: selected processor does not support system register name 'fgdtu11_el2' +.*: Error: selected processor does not support system register name 'fgdtu11_el2' +.*: Error: selected processor does not support system register name 'fgdtu12_el2' +.*: Error: selected processor does not support system register name 'fgdtu12_el2' +.*: Error: selected processor does not support system register name 'fgdtu13_el2' +.*: Error: selected processor does not support system register name 'fgdtu13_el2' +.*: Error: selected processor does not support system register name 'fgdtu14_el2' +.*: Error: selected processor does not support system register name 'fgdtu14_el2' +.*: Error: selected processor does not support system register name 'fgdtu15_el2' +.*: Error: selected processor does not support system register name 'fgdtu15_el2' +.*: Error: selected processor does not support system register name 'dpotbr0_el1' +.*: Error: selected processor does not support system register name 'dpotbr0_el1' +.*: Error: selected processor does not support system register name 'dpotbr1_el1' +.*: Error: selected processor does not support system register name 'dpotbr1_el1' +.*: Error: selected processor does not support system register name 'dpotbr0_el12' +.*: Error: selected processor does not support system register name 'dpotbr0_el12' +.*: Error: selected processor does not support system register name 'dpotbr1_el12' +.*: Error: selected processor does not support system register name 'dpotbr1_el12' +.*: Error: selected processor does not support system register name 'dpotbr0_el2' +.*: Error: selected processor does not support system register name 'dpotbr0_el2' +.*: Error: selected processor does not support system register name 'dpotbr1_el2' +.*: Error: selected processor does not support system register name 'dpotbr1_el2' +.*: Error: selected processor does not support system register name 'dpotbr0_el3' +.*: Error: selected processor does not support system register name 'dpotbr0_el3' +.*: Error: selected processor does not support system register name 'tpidr3_el0' +.*: Error: selected processor does not support system register name 'tpidr3_el0' +.*: Error: selected processor does not support system register name 'tpidr3_el1' +.*: Error: selected processor does not support system register name 'tpidr3_el1' +.*: Error: selected processor does not support system register name 'tpidr3_el12' +.*: Error: selected processor does not support system register name 'tpidr3_el12' +.*: Error: selected processor does not support system register name 'tpidr3_el2' +.*: Error: selected processor does not support system register name 'tpidr3_el2' +.*: Error: selected processor does not support system register name 'tpidr3_el3' +.*: Error: selected processor does not support system register name 'tpidr3_el3' +.*: Error: selected processor does not support system register name 'irtbru_el1' +.*: Error: selected processor does not support system register name 'irtbru_el1' +.*: Error: selected processor does not support system register name 'irtbru_el12' +.*: Error: selected processor does not support system register name 'irtbru_el12' +.*: Error: selected processor does not support system register name 'irtbru_el2' +.*: Error: selected processor does not support system register name 'irtbru_el2' +.*: Error: selected processor does not support system register name 'irtbrp_el1' +.*: Error: selected processor does not support system register name 'irtbrp_el1' +.*: Error: selected processor does not support system register name 'irtbrp_el12' +.*: Error: selected processor does not support system register name 'irtbrp_el12' +.*: Error: selected processor does not support system register name 'irtbrp_el2' +.*: Error: selected processor does not support system register name 'irtbrp_el2' +.*: Error: selected processor does not support system register name 'irtbrp_el3' +.*: Error: selected processor does not support system register name 'irtbrp_el3' +.*: Error: selected processor does not support system register name 'ldstt_el1' +.*: Error: selected processor does not support system register name 'ldstt_el1' +.*: Error: selected processor does not support system register name 'ldstt_el12' +.*: Error: selected processor does not support system register name 'ldstt_el12' +.*: Error: selected processor does not support system register name 'ldstt_el2' +.*: Error: selected processor does not support system register name 'ldstt_el2' +.*: Error: selected processor does not support system register name 'stindex_el1' +.*: Error: selected processor does not support system register name 'stindex_el1' +.*: Error: selected processor does not support system register name 'stindex_el12' +.*: Error: selected processor does not support system register name 'stindex_el12' +.*: Error: selected processor does not support system register name 'stindex_el2' +.*: Error: selected processor does not support system register name 'stindex_el2' +.*: Error: selected processor does not support system register name 'tindex_el0' +.*: Error: selected processor does not support system register name 'tindex_el0' +.*: Error: selected processor does not support system register name 'tindex_el1' +.*: Error: selected processor does not support system register name 'tindex_el1' +.*: Error: selected processor does not support system register name 'tindex_el12' +.*: Error: selected processor does not support system register name 'tindex_el12' +.*: Error: selected processor does not support system register name 'tindex_el2' +.*: Error: selected processor does not support system register name 'tindex_el2' +.*: Error: selected processor does not support system register name 'tindex_el3' +.*: Error: selected processor does not support system register name 'tindex_el3' +.*: Error: selected processor does not support system register name 'tttbru_el1' +.*: Error: selected processor does not support system register name 'tttbru_el1' +.*: Error: selected processor does not support system register name 'tttbru_el12' +.*: Error: selected processor does not support system register name 'tttbru_el12' +.*: Error: selected processor does not support system register name 'tttbru_el2' +.*: Error: selected processor does not support system register name 'tttbru_el2' +.*: Error: selected processor does not support system register name 'tttbrp_el1' +.*: Error: selected processor does not support system register name 'tttbrp_el1' +.*: Error: selected processor does not support system register name 'tttbrp_el12' +.*: Error: selected processor does not support system register name 'tttbrp_el12' +.*: Error: selected processor does not support system register name 'tttbrp_el2' +.*: Error: selected processor does not support system register name 'tttbrp_el2' +.*: Error: selected processor does not support system register name 'tttbrp_el3' +.*: Error: selected processor does not support system register name 'tttbrp_el3' +.*: Error: selected processor does not support system register name 'dpocr_el0' +.*: Error: selected processor does not support system register name 'dpocr_el0' +.*: Error: selected processor does not support system register name 'vnccr_el2' +.*: Error: selected processor does not support system register name 'vnccr_el2' diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 17c1c9d0c01..e1c2a624aca 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -45,6 +45,118 @@ SYSREG ("actlrmask_el1", CPENC (3,0,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */ SYSREG ("actlrmask_el12", CPENC (3,5,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */ SYSREG ("actlrmask_el2", CPENC (3,4,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */ + SYSREG ("afgdtp0_el1", CPENC (3,0,3,6,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp1_el1", CPENC (3,0,3,6,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp2_el1", CPENC (3,0,3,6,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp3_el1", CPENC (3,0,3,6,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp4_el1", CPENC (3,0,3,6,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp5_el1", CPENC (3,0,3,6,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp6_el1", CPENC (3,0,3,6,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp7_el1", CPENC (3,0,3,6,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp8_el1", CPENC (3,0,3,7,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp9_el1", CPENC (3,0,3,7,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp10_el1", CPENC (3,0,3,7,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp11_el1", CPENC (3,0,3,7,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp12_el1", CPENC (3,0,3,7,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp13_el1", CPENC (3,0,3,7,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp14_el1", CPENC (3,0,3,7,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp15_el1", CPENC (3,0,3,7,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp0_el2", CPENC (3,4,3,6,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp1_el2", CPENC (3,4,3,6,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp2_el2", CPENC (3,4,3,6,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp3_el2", CPENC (3,4,3,6,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp4_el2", CPENC (3,4,3,6,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp5_el2", CPENC (3,4,3,6,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp6_el2", CPENC (3,4,3,6,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp7_el2", CPENC (3,4,3,6,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp8_el2", CPENC (3,4,3,7,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp9_el2", CPENC (3,4,3,7,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp10_el2", CPENC (3,4,3,7,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp11_el2", CPENC (3,4,3,7,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp12_el2", CPENC (3,4,3,7,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp13_el2", CPENC (3,4,3,7,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp14_el2", CPENC (3,4,3,7,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp15_el2", CPENC (3,4,3,7,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp0_el12", CPENC (3,5,3,6,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp1_el12", CPENC (3,5,3,6,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp2_el12", CPENC (3,5,3,6,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp3_el12", CPENC (3,5,3,6,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp4_el12", CPENC (3,5,3,6,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp5_el12", CPENC (3,5,3,6,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp6_el12", CPENC (3,5,3,6,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp7_el12", CPENC (3,5,3,6,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp8_el12", CPENC (3,5,3,7,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp9_el12", CPENC (3,5,3,7,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp10_el12", CPENC (3,5,3,7,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp11_el12", CPENC (3,5,3,7,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp12_el12", CPENC (3,5,3,7,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp13_el12", CPENC (3,5,3,7,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp14_el12", CPENC (3,5,3,7,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp15_el12", CPENC (3,5,3,7,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp0_el3", CPENC (3,6,3,6,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp1_el3", CPENC (3,6,3,6,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp2_el3", CPENC (3,6,3,6,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp3_el3", CPENC (3,6,3,6,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp4_el3", CPENC (3,6,3,6,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp5_el3", CPENC (3,6,3,6,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp6_el3", CPENC (3,6,3,6,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp7_el3", CPENC (3,6,3,6,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp8_el3", CPENC (3,6,3,7,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp9_el3", CPENC (3,6,3,7,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp10_el3", CPENC (3,6,3,7,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp11_el3", CPENC (3,6,3,7,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp12_el3", CPENC (3,6,3,7,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp13_el3", CPENC (3,6,3,7,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp14_el3", CPENC (3,6,3,7,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtp15_el3", CPENC (3,6,3,7,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu0_el1", CPENC (3,0,3,8,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu1_el1", CPENC (3,0,3,8,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu2_el1", CPENC (3,0,3,8,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu3_el1", CPENC (3,0,3,8,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu4_el1", CPENC (3,0,3,8,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu5_el1", CPENC (3,0,3,8,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu6_el1", CPENC (3,0,3,8,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu7_el1", CPENC (3,0,3,8,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu8_el1", CPENC (3,0,3,9,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu9_el1", CPENC (3,0,3,9,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu10_el1", CPENC (3,0,3,9,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu11_el1", CPENC (3,0,3,9,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu12_el1", CPENC (3,0,3,9,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu13_el1", CPENC (3,0,3,9,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu14_el1", CPENC (3,0,3,9,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu15_el1", CPENC (3,0,3,9,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu0_el2", CPENC (3,4,3,8,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu1_el2", CPENC (3,4,3,8,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu2_el2", CPENC (3,4,3,8,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu3_el2", CPENC (3,4,3,8,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu4_el2", CPENC (3,4,3,8,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu5_el2", CPENC (3,4,3,8,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu6_el2", CPENC (3,4,3,8,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu7_el2", CPENC (3,4,3,8,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu8_el2", CPENC (3,4,3,9,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu9_el2", CPENC (3,4,3,9,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu10_el2", CPENC (3,4,3,9,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu11_el2", CPENC (3,4,3,9,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu12_el2", CPENC (3,4,3,9,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu13_el2", CPENC (3,4,3,9,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu14_el2", CPENC (3,4,3,9,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu15_el2", CPENC (3,4,3,9,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu0_el12", CPENC (3,5,3,8,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu1_el12", CPENC (3,5,3,8,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu2_el12", CPENC (3,5,3,8,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu3_el12", CPENC (3,5,3,8,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu4_el12", CPENC (3,5,3,8,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu5_el12", CPENC (3,5,3,8,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu6_el12", CPENC (3,5,3,8,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu7_el12", CPENC (3,5,3,8,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu8_el12", CPENC (3,5,3,9,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu9_el12", CPENC (3,5,3,9,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu10_el12", CPENC (3,5,3,9,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu11_el12", CPENC (3,5,3,9,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu12_el12", CPENC (3,5,3,9,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu13_el12", CPENC (3,5,3,9,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu14_el12", CPENC (3,5,3,9,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("afgdtu15_el12", CPENC (3,5,3,9,7), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("afsr0_el1", CPENC (3,0,5,1,0), 0, AARCH64_NO_FEATURES) SYSREG ("afsr0_el12", CPENC (3,5,5,1,0), 0, AARCH64_NO_FEATURES) SYSREG ("afsr0_el2", CPENC (3,4,5,1,0), 0, AARCH64_NO_FEATURES) @@ -391,6 +503,14 @@ SYSREG ("disr_el1", CPENC (3,0,12,1,1), 0, AARCH64_FEATURE (RAS)) SYSREG ("dit", CPENC (3,3,4,2,5), 0, AARCH64_FEATURE (V8_3A)) /* DIT */ SYSREG ("dlr_el0", CPENC (3,3,4,5,1), 0, AARCH64_NO_FEATURES) + SYSREG ("dpocr_el0", CPENC (3,3,4,5,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("dpotbr0_el1", CPENC (3,0,2,0,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("dpotbr0_el12", CPENC (3,5,2,0,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("dpotbr1_el1", CPENC (3,0,2,0,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("dpotbr1_el12", CPENC (3,5,2,0,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("dpotbr0_el2", CPENC (3,4,2,0,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("dpotbr1_el2", CPENC (3,4,2,0,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("dpotbr0_el3", CPENC (3,6,2,0,6), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("dspsr_el0", CPENC (3,3,4,5,0), 0, AARCH64_NO_FEATURES) SYSREG ("elr_el1", CPENC (3,0,4,0,1), 0, AARCH64_NO_FEATURES) SYSREG ("elr_el12", CPENC (3,5,4,0,1), 0, AARCH64_NO_FEATURES) @@ -418,6 +538,118 @@ SYSREG ("far_el12", CPENC (3,5,6,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("far_el2", CPENC (3,4,6,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("far_el3", CPENC (3,6,6,0,0), 0, AARCH64_NO_FEATURES) + SYSREG ("fgdtp0_el1", CPENC (3,0,3,2,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp1_el1", CPENC (3,0,3,2,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp2_el1", CPENC (3,0,3,2,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp3_el1", CPENC (3,0,3,2,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp4_el1", CPENC (3,0,3,2,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp5_el1", CPENC (3,0,3,2,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp6_el1", CPENC (3,0,3,2,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp7_el1", CPENC (3,0,3,2,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp8_el1", CPENC (3,0,3,3,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp9_el1", CPENC (3,0,3,3,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp10_el1", CPENC (3,0,3,3,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp11_el1", CPENC (3,0,3,3,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp12_el1", CPENC (3,0,3,3,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp13_el1", CPENC (3,0,3,3,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp14_el1", CPENC (3,0,3,3,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp15_el1", CPENC (3,0,3,3,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu0_el1", CPENC (3,0,3,4,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu1_el1", CPENC (3,0,3,4,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu2_el1", CPENC (3,0,3,4,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu3_el1", CPENC (3,0,3,4,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu4_el1", CPENC (3,0,3,4,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu5_el1", CPENC (3,0,3,4,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu6_el1", CPENC (3,0,3,4,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu7_el1", CPENC (3,0,3,4,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu8_el1", CPENC (3,0,3,5,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu9_el1", CPENC (3,0,3,5,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu10_el1", CPENC (3,0,3,5,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu11_el1", CPENC (3,0,3,5,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu12_el1", CPENC (3,0,3,5,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu13_el1", CPENC (3,0,3,5,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu14_el1", CPENC (3,0,3,5,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu15_el1", CPENC (3,0,3,5,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp0_el2", CPENC (3,4,3,2,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp1_el2", CPENC (3,4,3,2,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp2_el2", CPENC (3,4,3,2,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp3_el2", CPENC (3,4,3,2,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp4_el2", CPENC (3,4,3,2,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp5_el2", CPENC (3,4,3,2,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp6_el2", CPENC (3,4,3,2,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp7_el2", CPENC (3,4,3,2,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp8_el2", CPENC (3,4,3,3,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp9_el2", CPENC (3,4,3,3,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp10_el2", CPENC (3,4,3,3,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp11_el2", CPENC (3,4,3,3,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp12_el2", CPENC (3,4,3,3,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp13_el2", CPENC (3,4,3,3,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp14_el2", CPENC (3,4,3,3,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp15_el2", CPENC (3,4,3,3,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu0_el2", CPENC (3,4,3,4,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu1_el2", CPENC (3,4,3,4,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu2_el2", CPENC (3,4,3,4,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu3_el2", CPENC (3,4,3,4,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu4_el2", CPENC (3,4,3,4,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu5_el2", CPENC (3,4,3,4,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu6_el2", CPENC (3,4,3,4,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu7_el2", CPENC (3,4,3,4,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu8_el2", CPENC (3,4,3,5,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu9_el2", CPENC (3,4,3,5,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu10_el2", CPENC (3,4,3,5,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu11_el2", CPENC (3,4,3,5,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu12_el2", CPENC (3,4,3,5,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu13_el2", CPENC (3,4,3,5,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu14_el2", CPENC (3,4,3,5,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu15_el2", CPENC (3,4,3,5,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp0_el12", CPENC (3,5,3,2,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp1_el12", CPENC (3,5,3,2,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp2_el12", CPENC (3,5,3,2,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp3_el12", CPENC (3,5,3,2,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp4_el12", CPENC (3,5,3,2,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp5_el12", CPENC (3,5,3,2,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp6_el12", CPENC (3,5,3,2,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp7_el12", CPENC (3,5,3,2,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp8_el12", CPENC (3,5,3,3,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp9_el12", CPENC (3,5,3,3,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp10_el12", CPENC (3,5,3,3,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp11_el12", CPENC (3,5,3,3,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp12_el12", CPENC (3,5,3,3,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp13_el12", CPENC (3,5,3,3,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp14_el12", CPENC (3,5,3,3,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp15_el12", CPENC (3,5,3,3,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu0_el12", CPENC (3,5,3,4,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu1_el12", CPENC (3,5,3,4,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu2_el12", CPENC (3,5,3,4,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu3_el12", CPENC (3,5,3,4,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu4_el12", CPENC (3,5,3,4,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu5_el12", CPENC (3,5,3,4,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu6_el12", CPENC (3,5,3,4,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu7_el12", CPENC (3,5,3,4,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu8_el12", CPENC (3,5,3,5,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu9_el12", CPENC (3,5,3,5,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu10_el12", CPENC (3,5,3,5,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu11_el12", CPENC (3,5,3,5,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu12_el12", CPENC (3,5,3,5,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu13_el12", CPENC (3,5,3,5,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu14_el12", CPENC (3,5,3,5,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtu15_el12", CPENC (3,5,3,5,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp0_el3", CPENC (3,6,3,2,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp1_el3", CPENC (3,6,3,2,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp2_el3", CPENC (3,6,3,2,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp3_el3", CPENC (3,6,3,2,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp4_el3", CPENC (3,6,3,2,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp5_el3", CPENC (3,6,3,2,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp6_el3", CPENC (3,6,3,2,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp7_el3", CPENC (3,6,3,2,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp8_el3", CPENC (3,6,3,3,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp9_el3", CPENC (3,6,3,3,1), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp10_el3", CPENC (3,6,3,3,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp11_el3", CPENC (3,6,3,3,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp12_el3", CPENC (3,6,3,3,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp13_el3", CPENC (3,6,3,3,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp14_el3", CPENC (3,6,3,3,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("fgdtp15_el3", CPENC (3,6,3,3,7), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("fgwte3_el3", CPENC (3,6,1,1,5), 0, AARCH64_FEATURE (V9_4A)) /* FGWTE3 */ SYSREG ("fpcr", CPENC (3,3,4,4,0), 0, AARCH64_NO_FEATURES) SYSREG ("fpexc32_el2", CPENC (3,4,5,3,0), 0, AARCH64_NO_FEATURES) @@ -635,7 +867,17 @@ SYSREG ("id_pfr1_el1", CPENC (3,0,0,1,1), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("id_pfr2_el1", CPENC (3,0,0,3,4), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("ifsr32_el2", CPENC (3,4,5,0,1), 0, AARCH64_NO_FEATURES) + SYSREG ("irtbru_el1", CPENC (3,0,2,0,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("irtbru_el12", CPENC (3,5,2,0,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("irtbrp_el1", CPENC (3,0,2,0,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("irtbrp_el12", CPENC (3,5,2,0,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("irtbru_el2", CPENC (3,4,2,0,4), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("irtbrp_el2", CPENC (3,4,2,0,5), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("irtbrp_el3", CPENC (3,6,2,0,5), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("isr_el1", CPENC (3,0,12,1,0), F_REG_READ, AARCH64_NO_FEATURES) + SYSREG ("ldstt_el1", CPENC (3,0,2,1,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("ldstt_el12", CPENC (3,5,2,1,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("ldstt_el2", CPENC (3,4,2,1,7), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("lorc_el1", CPENC (3,0,10,4,3), 0, AARCH64_FEATURE (LOR)) SYSREG ("lorea_el1", CPENC (3,0,10,4,1), 0, AARCH64_FEATURE (LOR)) SYSREG ("lorid_el1", CPENC (3,0,10,4,7), F_REG_READ, AARCH64_FEATURE (LOR)) @@ -1072,6 +1314,9 @@ SYSREG ("spsr_svc", CPENC (3,0,4,0,0), F_DEPRECATED, AARCH64_NO_FEATURES) SYSREG ("spsr_und", CPENC (3,4,4,3,2), 0, AARCH64_NO_FEATURES) SYSREG ("ssbs", CPENC (3,3,4,2,6), 0, AARCH64_FEATURE (SSBS)) + SYSREG ("stindex_el1", CPENC (3,0,4,0,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("stindex_el2", CPENC (3,4,4,0,2), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("stindex_el12", CPENC (3,5,4,0,2), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("svcr", CPENC (3,3,4,2,2), 0, AARCH64_FEATURE (SME)) SYSREG ("tco", CPENC (3,3,4,2,7), 0, AARCH64_FEATURE (MEMTAG)) SYSREG ("tcr_el1", CPENC (3,0,2,0,2), 0, AARCH64_NO_FEATURES) @@ -1094,7 +1339,17 @@ SYSREG ("tfsr_el2", CPENC (3,4,5,6,0), 0, AARCH64_FEATURE (MEMTAG)) SYSREG ("tfsr_el3", CPENC (3,6,5,6,0), 0, AARCH64_FEATURE (MEMTAG)) SYSREG ("tfsre0_el1", CPENC (3,0,5,6,1), 0, AARCH64_FEATURE (MEMTAG)) + SYSREG ("tindex_el1", CPENC (3,0,4,0,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tindex_el0", CPENC (3,3,4,0,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tindex_el2", CPENC (3,4,4,0,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tindex_el12", CPENC (3,5,4,0,3), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tindex_el3", CPENC (3,6,4,0,3), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("tpidr2_el0", CPENC (3,3,13,0,5), 0, AARCH64_FEATURE (SME)) + SYSREG ("tpidr3_el0", CPENC (3,3,13,0,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tpidr3_el1", CPENC (3,0,13,0,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tpidr3_el12", CPENC (3,5,13,0,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tpidr3_el2", CPENC (3,4,13,0,0), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tpidr3_el3", CPENC (3,6,13,0,0), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("tpidr_el0", CPENC (3,3,13,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr_el1", CPENC (3,0,13,0,4), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr_el2", CPENC (3,4,13,0,2), 0, AARCH64_NO_FEATURES) @@ -1340,6 +1595,13 @@ SYSREG ("ttbr1_el1", CPENC (3,0,2,0,1), F_REG_128, AARCH64_NO_FEATURES) SYSREG ("ttbr1_el12", CPENC (3,5,2,0,1), F_REG_128, AARCH64_NO_FEATURES) SYSREG ("ttbr1_el2", CPENC (3,4,2,0,1), F_REG_128, AARCH64_FEATURE (V8A)) + SYSREG ("tttbru_el1", CPENC (3,0,10,2,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tttbru_el12", CPENC (3,5,10,2,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tttbrp_el1", CPENC (3,0,10,2,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tttbrp_el12", CPENC (3,5,10,2,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tttbru_el2", CPENC (3,4,10,2,6), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tttbrp_el2", CPENC (3,4,10,2,7), 0, AARCH64_FEATURE (S1POE2)) + SYSREG ("tttbrp_el3", CPENC (3,6,10,2,7), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("uao", CPENC (3,0,4,2,4), 0, AARCH64_FEATURE (V8_1A)) /* UAO */ SYSREG ("vbar_el1", CPENC (3,0,12,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("vbar_el12", CPENC (3,5,12,0,0), 0, AARCH64_NO_FEATURES) @@ -1350,6 +1612,7 @@ SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_FEATURE (V9_2A)) /* MEC */ SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_FEATURE (V9_2A)) /* MEC */ SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES) + SYSREG ("vnccr_el2", CPENC (3,4,2,2,1), 0, AARCH64_FEATURE (S1POE2)) SYSREG ("vncr_el2", CPENC (3,4,2,2,0), 0, AARCH64_FEATURE (V8_3A)) /* NV2 */ SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("vsctlr_el2", CPENC (3,4,2,0,0), 0, AARCH64_FEATURE (V8R)) From patchwork Fri Dec 5 10:57:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 125968 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 656484BC8947 for ; Fri, 5 Dec 2025 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Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath --- gas/config/tc-aarch64.c | 37 +++++++++++++++++-- gas/doc/c-aarch64.texi | 2 + gas/testsuite/gas/aarch64/poe2-invalid-1.l | 36 +++++++++--------- gas/testsuite/gas/aarch64/tev-invalid-1.d | 4 ++ gas/testsuite/gas/aarch64/tev-invalid-1.l | 21 +++++++++++ gas/testsuite/gas/aarch64/tev-invalid-1.s | 25 +++++++++++++ gas/testsuite/gas/aarch64/tev-invalid-2.d | 4 ++ gas/testsuite/gas/aarch64/tev-invalid-2.l | 20 ++++++++++ gas/testsuite/gas/aarch64/tev.d | 28 ++++++++++++++ gas/testsuite/gas/aarch64/tev.s | 26 +++++++++++++ include/opcode/aarch64.h | 6 ++- opcodes/aarch64-asm-2.c | 1 + opcodes/aarch64-dis-2.c | 43 ++++++++++++++++------ opcodes/aarch64-opc-2.c | 1 + opcodes/aarch64-opc.c | 1 + opcodes/aarch64-tbl-2.h | 2 + opcodes/aarch64-tbl.h | 11 ++++++ 17 files changed, 235 insertions(+), 33 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-1.d create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-1.l create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-1.s create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-2.d create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-2.l create mode 100644 gas/testsuite/gas/aarch64/tev.d create mode 100644 gas/testsuite/gas/aarch64/tev.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 5eae44b1b8a..24cb00e27b6 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -261,6 +261,7 @@ set_fatal_syntax_error (const char *error) return the information of the parsed result, e.g. register number, on success. */ #define PARSE_FAIL -1 +#define PARSE_FAIL2 -2 /* This is an invalid condition code that means no conditional field is present. */ @@ -4595,6 +4596,31 @@ parse_barrier (char **str) return o->value; } +/* Parse an option for instructions with not_balanced optional operands. On + sucess, return the encoding for the matched operand. On failure, return + PARSE_FAIL. However, if the instruction is TEXIT with no optional operands, + on failure return PARSE_FAIL2 instead. */ + +static int +parse_not_balanced (char **str) +{ + char *p, *q; + const struct aarch64_name_value_pair *o; + + p = q = *str; + while (ISALPHA (*q)) + q++; + + o = str_hash_find_n (aarch64_barrier_opt_hsh, p, q - p); + if ((q-p) == 0 && !o) + return PARSE_FAIL2; + else if (!o) + return PARSE_FAIL; + + *str = q; + return o->value; +} + /* Parse an option for barrier, bti and guarded control stack data synchronization instructions. Return true on matching the target options else return false. */ @@ -6442,6 +6468,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, break; case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: operand->imm.value = default_value; break; @@ -8177,14 +8204,17 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->barrier = aarch64_barrier_dsb_nxs_options + val; break; + case AARCH64_OPND_NOT_BALANCED_1: case AARCH64_OPND_NOT_BALANCED: - val = parse_barrier (&str); - if (val != PARSE_FAIL) + val = parse_not_balanced (&str); + if (val == PARSE_FAIL2) + goto failure; + else if (val != PARSE_FAIL) info->imm.value = val; else { set_syntax_error (_("the specified operand is not accepted in" - " TCHANGE instruction")); + " TCHANGE/TENTER/TEXIT instructions")); /* Turn off backtrack as this optional operand is present. */ backtrack_pos = 0; goto failure; @@ -10847,6 +10877,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"predres", AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES}, {"predres2", AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)}, {"poe2", AARCH64_FEATURE (S1POE2), AARCH64_NO_FEATURES}, + {"tev", AARCH64_FEATURE (TEV), AARCH64_NO_FEATURES}, {"aes", AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)}, {"sm4", AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)}, {"sha3", AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)}, diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 2064d22706b..b466c7f4f13 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -367,6 +367,8 @@ automatically cause those extensions to be disabled. @tab Enable the Translation Hardening Extension. @item @code{tme} @tab @tab Enable the Transactional Memory Extension. +@item @code{tev} @tab + @tab TIndex Exception-like Vector Extension. @item @code{wfxt} @tab @tab Enable @code{wfet} and @code{wfit} instructions. @item @code{xs} @tab diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.l b/gas/testsuite/gas/aarch64/poe2-invalid-1.l index df536613fde..4998b76ed0e 100644 --- a/gas/testsuite/gas/aarch64/poe2-invalid-1.l +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.l @@ -2,17 +2,17 @@ .*: Error: constant expression required at operand 2 -- `tchangef x0,x31' .*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,x3' .*: Error: comma expected between operands at operand 2 -- `tchangef x7' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x15,x30,' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x30,x0,x10' +.*: Error: unexpected comma before the omitted optional operand at operand 3 -- `tchangef x15,x30,' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x30,x0,x10' .*: Error: comma expected between operands at operand 2 -- `tchangef x10 x0' .*: Error: expected an integer or zero register at operand 1 -- `tchangef #1,#100' .*: Error: expected an integer or zero register at operand 1 -- `tchangef #10,x0' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x0,x1,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x0,x1,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangef x1,x3 nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x3,x7,n' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x3,x7,n' .*: Error: unexpected characters following instruction at operand 3 -- `tchangef x7,x15,nb,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x15,x30,Nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x30,x0,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x15,x30,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x30,x0,nB' .*: Error: constant expression required at operand 2 -- `tchangef x10,NB,NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,NB' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10' @@ -22,10 +22,10 @@ .*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#15' .*: Error: constant expression required at operand 2 -- `tchangef x10,nb,#127' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x0,#1,nB' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x1,#3,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x0,#1,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x1,#3,Nb' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x3,#777,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x7,#15,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x7,#15,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangef x15,#31 NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#63,nb' .*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,#127' @@ -33,17 +33,17 @@ .*: Error: constant expression required at operand 2 -- `tchangeb x0,x31' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,x3' .*: Error: comma expected between operands at operand 2 -- `tchangeb x7' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x15,x30,' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x30,x0,x10' +.*: Error: unexpected comma before the omitted optional operand at operand 3 -- `tchangeb x15,x30,' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x30,x0,x10' .*: Error: comma expected between operands at operand 2 -- `tchangeb x10 x0' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb #1,#100' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb #10,x0' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x0,x1,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x0,x1,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangeb x1,x3 nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x3,x7,n' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x3,x7,n' .*: Error: unexpected characters following instruction at operand 3 -- `tchangeb x7,x15,nb,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x15,x30,Nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x30,x0,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x15,x30,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x30,x0,nB' .*: Error: constant expression required at operand 2 -- `tchangeb x10,NB,NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,NB' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10' @@ -53,10 +53,10 @@ .*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#15' .*: Error: constant expression required at operand 2 -- `tchangeb x10,nb,#127' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x0,#1,nB' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x1,#3,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x0,#1,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x1,#3,Nb' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x3,#777,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x7,#15,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x7,#15,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangeb x15,#31 NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#63,nb' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,#127' diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.d b/gas/testsuite/gas/aarch64/tev-invalid-1.d new file mode 100644 index 00000000000..f6a659e5888 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-1.d @@ -0,0 +1,4 @@ +#name: Invalid tev instructions. +#source: tev-invalid-1.s +#as: -march=armv8-a+tev +#error_output: tev-invalid-1.l diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.l b/gas/testsuite/gas/aarch64/tev-invalid-1.l new file mode 100644 index 00000000000..66d1b3b3492 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-1.l @@ -0,0 +1,21 @@ +.*: Assembler messages: +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #-10' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #128' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #3111' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #777' +.*: Error: constant expression required at operand 1 -- `tenter nb,#127' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #-10,nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 2 -- `tenter #1,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 2 -- `tenter #3,Nb' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #777,nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 2 -- `tenter #15,nbb' +.*: Error: comma expected between operands at operand 2 -- `tenter #31 NB' +.*: Error: immediate operand required at operand 1 -- `tenter x10,#127' +.*: Error: constant expression required at operand 1 -- `tenter NB,#128' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit x0' +.*: Error: operand 1 must be a 1-bit not_balanced optional operand -- `texit #10' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit n' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit nN' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit x0,nb' diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.s b/gas/testsuite/gas/aarch64/tev-invalid-1.s new file mode 100644 index 00000000000..44925fd19ba --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-1.s @@ -0,0 +1,25 @@ +#TENTER instructions + tenter #-10 + tenter #128 + tenter #3111 + tenter #777 + tenter nb, #127 + +#TENTER instructions with not_balanced + tenter #-10, nb + tenter #1, nB + tenter #3, Nb + tenter #777, nb + tenter #15, nbb + tenter #31 NB + tenter x10, #127 + tenter NB, #128 + +#TEXIT instructions + texit x0 + texit #10 + texit n + texit nN + texit nB + texit Nb + texit x0, nb diff --git a/gas/testsuite/gas/aarch64/tev-invalid-2.d b/gas/testsuite/gas/aarch64/tev-invalid-2.d new file mode 100644 index 00000000000..6d5c9c1b9aa --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-2.d @@ -0,0 +1,4 @@ +#name: TENTER and TEXIT instructions without +tev flag. +#source: tev.s +#as: -march=armv8-a +#error_output: tev-invalid-2.l diff --git a/gas/testsuite/gas/aarch64/tev-invalid-2.l b/gas/testsuite/gas/aarch64/tev-invalid-2.l new file mode 100644 index 00000000000..9f438e742ed --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-2.l @@ -0,0 +1,20 @@ +.*: Assembler messages: +.*: Error: selected processor does not support `tenter #0' +.*: Error: selected processor does not support `tenter #1' +.*: Error: selected processor does not support `tenter #3' +.*: Error: selected processor does not support `tenter #7' +.*: Error: selected processor does not support `tenter #15' +.*: Error: selected processor does not support `tenter #31' +.*: Error: selected processor does not support `tenter #63' +.*: Error: selected processor does not support `tenter #127' +.*: Error: selected processor does not support `tenter #0,nb' +.*: Error: selected processor does not support `tenter #1,nb' +.*: Error: selected processor does not support `tenter #3,nb' +.*: Error: selected processor does not support `tenter #7,nb' +.*: Error: selected processor does not support `tenter #15,nb' +.*: Error: selected processor does not support `tenter #31,NB' +.*: Error: selected processor does not support `tenter #63,nb' +.*: Error: selected processor does not support `tenter #127,NB' +.*: Error: selected processor does not support `texit' +.*: Error: selected processor does not support `texit nb' +.*: Error: selected processor does not support `texit NB' diff --git a/gas/testsuite/gas/aarch64/tev.d b/gas/testsuite/gas/aarch64/tev.d new file mode 100644 index 00000000000..a8d9f447617 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev.d @@ -0,0 +1,28 @@ +#objdump: -dr +#as: -march=armv8-a+tev + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d4e00000 tenter #0x0 +.*: d4e00020 tenter #0x1 +.*: d4e00060 tenter #0x3 +.*: d4e000e0 tenter #0x7 +.*: d4e001e0 tenter #0xf +.*: d4e003e0 tenter #0x1f +.*: d4e007e0 tenter #0x3f +.*: d4e00fe0 tenter #0x7f +.*: d4e20000 tenter #0x0, nb +.*: d4e20020 tenter #0x1, nb +.*: d4e20060 tenter #0x3, nb +.*: d4e200e0 tenter #0x7, nb +.*: d4e201e0 tenter #0xf, nb +.*: d4e203e0 tenter #0x1f, nb +.*: d4e207e0 tenter #0x3f, nb +.*: d4e20fe0 tenter #0x7f, nb +.*: d6ff03e0 texit +.*: d6ff07e0 texit nb +.*: d6ff07e0 texit nb diff --git a/gas/testsuite/gas/aarch64/tev.s b/gas/testsuite/gas/aarch64/tev.s new file mode 100644 index 00000000000..d6b1bfdb741 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev.s @@ -0,0 +1,26 @@ +#TENTER instruction + tenter #0 + tenter #1 + tenter #3 + tenter #7 + tenter #15 + tenter #31 + tenter #63 + tenter #127 + +#TENTER instruction with not_balanced + tenter #0, nb + tenter #1, nb + tenter #3, nb + tenter #7, nb + tenter #15, nb + tenter #31, NB + tenter #63, nb + tenter #127, NB + +#TEXIT instruction + texit + +#TEXIT instruction with not_balanced + texit nb + texit NB diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index e7c6ed601b1..ef5d0bae986 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -265,6 +265,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_MOP4, /* POE2 instructions. */ AARCH64_FEATURE_S1POE2, + /* TEV instructions. */ + AARCH64_FEATURE_TEV, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -675,7 +677,8 @@ enum aarch64_opnd AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ - AARCH64_OPND_NOT_BALANCED, /* a 1-bit not_balanced optional operand. */ + AARCH64_OPND_NOT_BALANCED, /* a 1-bit not_balanced optional operand. */ + AARCH64_OPND_NOT_BALANCED_1, /* a 1-bit not_balanced optional operand. */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for each condition flag. */ @@ -1136,6 +1139,7 @@ enum aarch64_insn_class movewide, pcreladdr, s1poe2, + tev, ic_system, sme_fp_sd, sme_int_sd, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index c93447742f8..919b6669722 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -931,6 +931,7 @@ aarch64_insert_operand (const aarch64_operand *self, case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_PCREL9: case AARCH64_OPND_ADDR_PCREL14: diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 657e1ec4f37..855d00d3c4f 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -26335,10 +26335,20 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 11010100x11xxxxxxxxxxxxxxxx0xx00. */ - return A64_OPID_d4600000_tcancel_TME_UIMM16; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11010100011xxxxxxxxxxxxxxxx0xx00. */ + return A64_OPID_d4600000_tcancel_TME_UIMM16; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11010100111xxxxxxxxxxxxxxxx0xx00. */ + return A64_OPID_d4e00000_tenter_UIMM7_NOT_BALANCED; + } } } } @@ -26430,19 +26440,29 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10101100x1xxxxxxxxxxxxxxxx0xxxx. */ - return A64_OPID_d63f0000_blr_Rn; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010110001xxxxxxxxxxxxxxxx0xxxx. */ + return A64_OPID_d63f0000_blr_Rn; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010110101xxxxxxxxxxxxxxxx0xxxx. */ + return A64_OPID_d6bf03e0_drps; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10101101x1xxxxxxxxxxxxxxxx0xxxx. */ - return A64_OPID_d6bf03e0_drps; + x1010110x11xxxxxxxxxxxxxxxx0xxxx. */ + return A64_OPID_d6ff03e0_texit_NOT_BALANCED_1; } } } @@ -37398,6 +37418,7 @@ aarch64_extract_operand (const aarch64_operand *self, case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_ADRP: case AARCH64_OPND_ADDR_PCREL9: diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index fc88fe82ed3..de468488c08 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -105,6 +105,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_17}, "a 1-bit not_balanced optional operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10}, "a 1-bit not_balanced optional operand"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 623fd7a4272..920a5dffc5a 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -5160,6 +5160,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, break; case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: if (opnd->imm.value) snprintf (buf, size, "%s", style_sub_mnem (styler, "nb")); break; diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h index 16b3448c828..fda9d456f3c 100644 --- a/opcodes/aarch64-tbl-2.h +++ b/opcodes/aarch64-tbl-2.h @@ -3999,5 +3999,7 @@ enum aarch64_opcode_idx A64_OPID_d5900000_tchangef_Rd_UIMM7_NOT_BALANCED, A64_OPID_d5840000_tchangeb_Rd_Rn_NOT_BALANCED, A64_OPID_d5940000_tchangeb_Rd_UIMM7_NOT_BALANCED, + A64_OPID_d4e00000_tenter_UIMM7_NOT_BALANCED, + A64_OPID_d6ff03e0_texit_NOT_BALANCED_1, A64_OPID_MAX, }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 572385621db..f7b7d610563 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3066,6 +3066,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 = AARCH64_FEATURES (2, SME_MOP4, SME_I16I64); static const aarch64_feature_set aarch64_feature_s1poe2 = AARCH64_FEATURE (S1POE2); +static const aarch64_feature_set aarch64_feature_tev = + AARCH64_FEATURE (TEV); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -3191,6 +3193,7 @@ static const aarch64_feature_set aarch64_feature_s1poe2 = #define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32 #define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64 #define S1POE2 &aarch64_feature_s1poe2 +#define TEV &aarch64_feature_tev #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } @@ -3522,6 +3525,8 @@ static const aarch64_feature_set aarch64_feature_s1poe2 = FLAGS | F_STRICT, 0, TIED, NULL } #define S1POE2_INSN(NAME,OPCODE,MASK,OPS,QUALS, FLAGS) \ { NAME, OPCODE, MASK, s1poe2, 0, S1POE2, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } +#define TEV_INSN(NAME,OPCODE,MASK,OPS,QUALS, FLAGS) \ + { NAME, OPCODE, MASK, tev, 0, TEV, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -7756,6 +7761,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = S1POE2_INSN("tchangeb", 0xd5840000, 0xfffdfc00, OP3 (Rd, Rn, NOT_BALANCED), QL_DST_X2, F_OPD2_OPT | F_DEFAULT (0x0)), S1POE2_INSN("tchangeb", 0xd5940000, 0xfffdf000, OP3 (Rd, UIMM7, NOT_BALANCED), QL_DST_X1, F_OPD2_OPT | F_DEFAULT (0x0)), + /* TEV instructions. */ + TEV_INSN("tenter", 0xd4e00000, 0xfffdf01f, OP2 (UIMM7, NOT_BALANCED), QL_PRFM_PCREL, F_OPD1_OPT | F_DEFAULT (0x0)), + TEV_INSN("texit", 0xd6ff03e0, 0xfffffbff, OP1 (NOT_BALANCED_1), {}, F_OPD0_OPT | F_DEFAULT (0x0)), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -7910,6 +7919,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 5-bit signed immediate") \ Y(IMMEDIATE, imm, "NOT_BALANCED", 0, F(FLD_imm1_17), \ "a 1-bit not_balanced optional operand") \ + Y(IMMEDIATE, imm, "NOT_BALANCED_1", 0, F(FLD_imm1_10), \ + "a 1-bit not_balanced optional operand") \ Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ "a flag bit specifier giving an alternative value for each flag") \ Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \