From patchwork Fri Dec 3 19:42:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 48477 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B469385841B for ; Fri, 3 Dec 2021 19:43:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 90C273858D28 for ; Fri, 3 Dec 2021 19:42:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 90C273858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:To:From:Sender:Reply-To:Cc:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=eC1R3zS/J8lO0tc+ZKWPhgdEeIC4BmwcsjgzvNAs28A=; b=KXjFmE3f5cHoHcOQjLmiAKPCKt Xv5LkXZE8wLShtRCIzphi0sNIqghicVjs3hmEht0WoKzWC1yogAmCQAP6t30jEAQS4Bz7Ill9Ryaz KYSXOFzsJ/VzjzSM/+ONvTot077hAz3u0dASukChEuc22HYch8AC36NMAwr2hIN515kZC8xEb+Vmy xpXn85dtOU4akedbKv57GkwMT1XfqIVjxw1+x7gmjbT4ehOwnCVbaFe2XuM2Ho3aJNXwNyg4fyLc4 W1lkyFcQSoNotWo/FLH35Jke3ul6c+AhkCH5G+Or4RvwfIfqHKflKbYT4xXSW82d90NbMuSJYGCGt BsId4Ubw==; Received: from [185.62.158.67] (port=50832 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mtESM-0002dg-HE for gcc-patches@gcc.gnu.org; Fri, 03 Dec 2021 14:42:54 -0500 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH take #2] PR target/43892: Some carry flag (CA) optimizations on PowerPC. Date: Fri, 3 Dec 2021 19:42:52 -0000 Message-ID: <03ae01d7e87d$f67f1a80$e37d4f80$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdfofYDKMcGpqekGRL+MIMwsp2vfAA== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Doh! This time with the patch attached... This patch resolves PR target/43892 (suboptimal add with carry) by adding four new define_insn_and_split to the rs6000 backend, that all recognize pairs of instructions where the first instruction sets the carry flag and the second one consumes it. It also adds a commutative variant of add3_carry_in_0 (aka "addze") to catch cases, not caught by recog's insn canonicalization, where CA_REG appears first. For the add32carry function in the original PR: unsigned int add32carry(unsigned int sum, unsigned int x) { unsigned int z = sum + x; if (sum + x < x) z++; return z; } previously "-O2 -m32" would generate: add32carry: add 3,3,4 subfc 4,4,3 subfe 9,9,9 subf 3,9,3 blr with this patch we now generate: add32carry: addc 3,3,4 addze 3,3 blr And for the related examples in the new test case, unsigned long add_leu(unsigned long a, unsigned long b, unsigned long c) { return a + (b <= c); } unsigned long add_geu(unsigned long a, unsigned long b, unsigned long c) { return a + (b >= c); } On powerpc64 with -O2 we'd previously generate: add_leu: subfc 4,4,5 subfe 9,9,9 addi 9,9,1 add 3,9,3 blr add_geu: subfc 5,5,4 subfe 9,9,9 addi 9,9,1 add 3,9,3 blr but with this patch we now generate: add_leu: subfc 4,4,5 addze 3,3 blr add_geu: subfc 5,5,4 addze 3,3 blr This patch has been tested on powerpc64-unknown-linux-gnu (many thanks to gcc203.fsffrance.org on the GCC compile farm) with a make bootstrap and make -k check with now new failures. Ok for mainline? 2021-12-03 Roger Sayle gcc/ChangeLog PR target/43892 * config/rs6000/rs6000.md (*add3_carry_in_0_2): New define_insn to recognize commutative form of add3_carry_in_0. (*add3_geu, *add3_leu, *subf3_carry_in_xx_subf, *add3_carry_in_addc): New define_insn_and_split patterns. gcc/testsuite/ChangeLog PR target/43892 * gcc.target/powerpc/addcmp.c: New test case. * gcc.target/powerpc/pr43892.c: New test case. Many thanks in advance. Roger diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 6bec2bddbde..90c23556ccb 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2067,6 +2067,16 @@ "addze %0,%1" [(set_attr "type" "add")]) +;; Non-canonical form of add3_carry_in_0 +(define_insn "*add3_carry_in_0_2" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (reg:GPR CA_REGNO) + (match_operand:GPR 1 "gpc_reg_operand" "r"))) + (clobber (reg:GPR CA_REGNO))] + "" + "addze %0,%1" + [(set_attr "type" "add")]) + (define_insn "add3_carry_in_m1" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") @@ -2078,6 +2088,95 @@ [(set_attr "type" "add")]) +;; PR target/43892 -> subf3_carry ; add3_carry_in_0 +(define_insn_and_split "*add3_geu" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "gpc_reg_operand" "r")) + (match_operand:P 3 "gpc_reg_operand" "r"))) + (clobber (match_scratch:P 4 "=r")) + (clobber (reg:P CA_REGNO))] + "" + "#" + "&& 1" + [(const_int 0)] +{ + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (mode); + emit_insn (gen_subf3_carry (operands[4], operands[1], operands[2])); + emit_insn (gen_add3_carry_in_0 (operands[0], operands[3])); + DONE; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + +;; PR target/43892 -> subf3_carry ; add3_carry_in_0 +(define_insn_and_split "*add3_leu" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "gpc_reg_operand" "r")) + (match_operand:P 3 "gpc_reg_operand" "r"))) + (clobber (match_scratch:P 4 "=r")) + (clobber (reg:P CA_REGNO))] + "" + "#" + "&& 1" + [(const_int 0)] +{ + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (mode); + emit_insn (gen_subf3_carry (operands[4], operands[2], operands[1])); + emit_insn (gen_add3_carry_in_0 (operands[0], operands[3])); + DONE; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + +;; PR target/43892 -> subf3_carry_in_xx ; subf3 +(define_insn_and_split "*subf3_carry_in_xx_subf" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (minus:P (match_operand:P 1 "gpc_reg_operand" "r") + (reg:P CA_REGNO)) + (const_int 1))) + (clobber (match_scratch:P 2 "=r")) + (clobber (reg:P CA_REGNO))] + "" + "#" + "&& 1" + [(const_int 0)] +{ + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (mode); + emit_insn (gen_subf3_carry_in_xx (operands[2])); + emit_insn (gen_sub3 (operands[0], operands[1], operands[2])); + DONE; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + +;; PR target/43892 -> add3_carry ; add3_carry_in_0 +(define_insn_and_split "*add3_carry_in_addc" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (plus:P + (ltu:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "gpc_reg_operand" "r")) + (match_dup 1)) + (match_dup 2)) + (match_dup 1))) + (clobber (reg:P CA_REGNO))] + "" + "#" + "&& 1" + [(const_int 0)] +{ + emit_insn (gen_add3_carry (operands[0], operands[1], operands[2])); + emit_insn (gen_add3_carry_in_0 (operands[0], operands[0])); + DONE; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + + (define_expand "one_cmpl2" [(set (match_operand:SDI 0 "gpc_reg_operand") (not:SDI (match_operand:SDI 1 "gpc_reg_operand")))] diff --git a/gcc/testsuite/gcc.target/powerpc/addcmp.c b/gcc/testsuite/gcc.target/powerpc/addcmp.c new file mode 100644 index 00000000000..6ca971bfc66 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/addcmp.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long add_leu(unsigned long a, unsigned long b, unsigned long c) { + return a + (b <= c); +} + +unsigned long add_geu(unsigned long a, unsigned long b, unsigned long c) { + return a + (b >= c); +} + +/* { dg-final { scan-assembler-times "addze " 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr43892.c b/gcc/testsuite/gcc.target/powerpc/pr43892.c new file mode 100644 index 00000000000..f5d6b852c5f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr43892.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +unsigned long foo(unsigned long sum, unsigned long x) +{ + unsigned long z = sum + x; + if (sum + x < x) + z++; + return z; +} + +/* { dg-final { scan-assembler "addze " } } */