From patchwork Fri Dec 3 06:18:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 48455 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C72F385741B for ; Fri, 3 Dec 2021 06:19:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C72F385741B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1638512369; bh=e4j9Ho4pO+JkKkckkGndh/jKYpQl4tcsmCMccfWMImo=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=a7tvFG1X1cgXVUyj6WrU/NBJefmwMgrtcVb8yogYU8B9WNbWTwr63aEautt8U7Naw Ej2Csqa8hZazki4hfCtJCRhs8mKDA6MoIShKWkYsEPIJ2z36b68aDJnAkr2yGJRV8Y uQNmsa8KxEDI1AJyKmq9tSv1UIA0X0+efZv9D0W0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 844883858428 for ; Fri, 3 Dec 2021 06:18:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 844883858428 X-IronPort-AV: E=McAfee;i="6200,9189,10186"; a="223793800" X-IronPort-AV: E=Sophos;i="5.87,283,1631602800"; d="scan'208";a="223793800" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2021 22:18:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,283,1631602800"; d="scan'208";a="501070555" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga007.jf.intel.com with ESMTP; 02 Dec 2021 22:18:57 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1B36ItH3003706; Thu, 2 Dec 2021 22:18:56 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class. Date: Fri, 3 Dec 2021 14:18:55 +0800 Message-Id: <20211203061855.32518-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: References: X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi: > Please also consider TARGET_INTER_UNIT_MOVES_TO_VEC and > TARGET_INTER_UNIT_MOVES_FROM_VEC. Here's updated patch. Also honor TARGET_INTER_UNIT_MOVES_TO/FROM_VEC and in preferred_{,out_}reload_class. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32\ -march=k8,\ -march=k8}. Ok? gcc/ChangeLog: PR target/95740 * config/i386/i386.c (ix86_preferred_output_reload_class): don't reload integer register to/from sse register when tune "inter_unit_moves_to/from_vec" is off. (ix86_preferred_reload_class): Ditto, also prefer INT_SSE_REGS for SSE_FLOAT_MODE_P. * config/i386/i386.h (INT_SSE_CLASS_P): New. gcc/testsuite/ChangeLog: * gcc.target/i386/pr95740.c: New test. --- gcc/config/i386/i386.c | 32 +++++++++++++++++++++++-- gcc/config/i386/i386.h | 2 ++ gcc/testsuite/gcc.target/i386/pr95740.c | 26 ++++++++++++++++++++ 3 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 80fee627358..5b90c09a0ba 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19194,9 +19194,24 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass) return NO_REGS; } - /* Prefer SSE regs only, if we can use them for math. */ + /* Unless hard register REGNO is known, it is hard to to tell whether a movd + instruction will be generated based on MODE and REGCLASS, because for + pseudo-registers, even SFmode could be assigned to INTGER_CLASS_P. */ + if (GENERAL_REG_P (x) + && !TARGET_INTER_UNIT_MOVES_TO_VEC + && MAYBE_SSE_CLASS_P (regclass)) + return NO_REGS; + + if (SSE_REG_P (x) + && !TARGET_INTER_UNIT_MOVES_FROM_VEC + && MAYBE_INTEGER_CLASS_P (regclass)) + return NO_REGS; + + /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS, + MAYBE_SSE_CLASS_P is too broad, for sse math, FLOAT_SSE_REGS, + FLOAT_INT_SSE_REGS should be disliked. */ if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - return SSE_CLASS_P (regclass) ? regclass : NO_REGS; + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS; /* Generally when we see PLUS here, it's the function invariant (plus soft-fp const_int). Which can only be computed into general @@ -19226,6 +19241,19 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass) static reg_class_t ix86_preferred_output_reload_class (rtx x, reg_class_t regclass) { + + /* Handle movement between integer and sse register like + ix86_preferred_reload_class. */ + if (GENERAL_REG_P (x) + && !TARGET_INTER_UNIT_MOVES_TO_VEC + && MAYBE_SSE_CLASS_P (regclass)) + return NO_REGS; + + if (SSE_REG_P (x) + && !TARGET_INTER_UNIT_MOVES_FROM_VEC + && MAYBE_INTEGER_CLASS_P (regclass)) + return NO_REGS; + /* Restrict the output reload class to the register bank that we are doing math on. If we would like not to return a subset of CLASS, reject this alternative: if reload cannot do this, it will still use its choice. */ diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 2fda1e0686e..ec90e47904b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1283,6 +1283,8 @@ enum reg_class reg_class_subset_p ((CLASS), FLOAT_REGS) #define SSE_CLASS_P(CLASS) \ reg_class_subset_p ((CLASS), ALL_SSE_REGS) +#define INT_SSE_CLASS_P(CLASS) \ + reg_class_subset_p ((CLASS), INT_SSE_REGS) #define MMX_CLASS_P(CLASS) \ ((CLASS) == MMX_REGS) #define MASK_CLASS_P(CLASS) \ diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c new file mode 100644 index 00000000000..9bc7b862787 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr95740.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */ +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */ + +int +foo (float a) +{ + union{ + int b; + float a;}u; + u.a = a; + return u.b + 1; +} + +long long +foo1 (double a) +{ + union{ + long long b; + double a;}u; + u.a = a; + return u.b + 1; +}