From patchwork Thu Dec 2 08:27:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 48387 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 76DAA385C40A for ; Thu, 2 Dec 2021 08:28:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 76DAA385C40A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1638433707; bh=fnt34elzDXiXnDsq8cQWE6tCNEbP5+Qw9zKwcsf9Q20=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=iSoHaFngou6JaOao6bZZkmdzcsubcjMQeN0OaFIOucOkZx+FuROvl3bZpgCvd2OLW BE9hh9pQ2bfUW1YGFL9uot5Yb0dsZP8nH0hxHcaiX3kDCrazKT96eTgsHmm9Rw1yke XzsSWUHCl8SuGlgYAkAkG51o8hRKi6h0iRpp9pno= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 3C2C03857C59 for ; Thu, 2 Dec 2021 08:27:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3C2C03857C59 X-IronPort-AV: E=McAfee;i="6200,9189,10185"; a="236597411" X-IronPort-AV: E=Sophos;i="5.87,281,1631602800"; d="scan'208";a="236597411" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2021 00:27:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,281,1631602800"; d="scan'208";a="541142448" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga001.jf.intel.com with ESMTP; 02 Dec 2021 00:27:54 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1B28Rr2Z023318; Thu, 2 Dec 2021 00:27:53 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class. Date: Thu, 2 Dec 2021 16:27:52 +0800 Message-Id: <20211202082752.62388-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The patch helps reload to choose GENENRAL_REGS alternatives for SSE_FLOAT_MODE and enabled optimization like - vmovd %xmm0, -4(%rsp) - movl $1, %eax - addl -4(%rsp), %eax + movd %xmm0, %eax + addl $1, %eax Bootstrapped anf regtested on x86_64-pc-linux-gnu{-m32,} and x86_64-pc-linux-gnu{-m32\ march=cascadelake,\ -march=cadcadelake}. No big performace impact is abserved for SPEC2017 on ICX/CLX with both Ofast -march=native -flto -funroll-loops and -O2 -mtune=generic options. Ok for trunk? gcc/ChangeLog: PR target/95740 * config/i386/i386.c (ix86_preferred_reload_class): Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P. * config/i386/i386.h (INT_SSE_CLASS_P): New. gcc/testsuite/ChangeLog: * gcc.target/i386/pr95740.c: New test. --- gcc/config/i386/i386.c | 5 +++-- gcc/config/i386/i386.h | 2 ++ gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 80fee627358..977af1c31a7 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19194,9 +19194,10 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass) return NO_REGS; } - /* Prefer SSE regs only, if we can use them for math. */ + /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS, + refer to PR95740. */ if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - return SSE_CLASS_P (regclass) ? regclass : NO_REGS; + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS; /* Generally when we see PLUS here, it's the function invariant (plus soft-fp const_int). Which can only be computed into general diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 2fda1e0686e..ec90e47904b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1283,6 +1283,8 @@ enum reg_class reg_class_subset_p ((CLASS), FLOAT_REGS) #define SSE_CLASS_P(CLASS) \ reg_class_subset_p ((CLASS), ALL_SSE_REGS) +#define INT_SSE_CLASS_P(CLASS) \ + reg_class_subset_p ((CLASS), INT_SSE_REGS) #define MMX_CLASS_P(CLASS) \ ((CLASS) == MMX_REGS) #define MASK_CLASS_P(CLASS) \ diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c new file mode 100644 index 00000000000..9bc7b862787 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr95740.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */ +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */ + +int +foo (float a) +{ + union{ + int b; + float a;}u; + u.a = a; + return u.b + 1; +} + +long long +foo1 (double a) +{ + union{ + long long b; + double a;}u; + u.a = a; + return u.b + 1; +}