From patchwork Tue Nov 30 09:43:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 48275 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 71F853858402 for ; Tue, 30 Nov 2021 09:44:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 71F853858402 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1638265497; bh=YtNjUbgNcfQOkrm1RzajYdgR+dGnumSAJ7hXnozAWSE=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=W69gw/R26uCl6e5I8cUulorsitDWBVplYSh9XS6e5tylyzPqPJQ5hQJgTliJpFXs3 q52y69W8HgSYWWRd9qSzSW4bton3mKjYLPh7JJxj1ab40OgxgTUHPxt2QGswY1LWwi sKh4W0obfQOre/BwlMJFHMCFd8gBcDOkrAJ4gZo0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id CC9EA3858C2C for ; Tue, 30 Nov 2021 09:43:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CC9EA3858C2C X-IronPort-AV: E=McAfee;i="6200,9189,10183"; a="260137235" X-IronPort-AV: E=Sophos;i="5.87,275,1631602800"; d="scan'208";a="260137235" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2021 01:43:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,275,1631602800"; d="scan'208";a="540353627" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga001.jf.intel.com with ESMTP; 30 Nov 2021 01:43:30 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1AU9hT6p009674; Tue, 30 Nov 2021 01:43:30 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Fix ICE in ix86_attr_length_immediate_default. Date: Tue, 30 Nov 2021 17:43:29 +0800 Message-Id: <20211130094329.22379-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: "Liu, Hongtao" Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" ix86_attr_length_immediate_default assume TYPE ishift only have 1 constant operand, but *x86_64_shld_1/*x86_shld_1/*x86_64_shrd_1/*x86_shrd_1 has 2, with condition: INTVAL (operands[3]) == 32 - INTVAL (operands[2]) or INTVAL (operands[3]) == 64 - INTVAL (operands[2]), and hit gcc_assert. Explicitly set_attr length_immediate for these patterns. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/103463 PR target/103484 * config/i386/i386.md (*x86_64_shld_1): Set_attr length_immediate to 1. (*x86_shld_1): Ditto. (*x86_64_shrd_1): Ditto. (*x86_shrd_1): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr103463.c: New test. * gcc.target/i386/pr103463-2.c: New test. --- gcc/config/i386/i386.md | 4 ++++ gcc/testsuite/gcc.target/i386/pr103463-2.c | 14 ++++++++++++++ gcc/testsuite/gcc.target/i386/pr103463.c | 13 +++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr103463-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103463.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c88374c9d2b..4e9fae80479 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11512,6 +11512,7 @@ (define_insn "*x86_64_shld_1" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") (set_attr "mode" "DI") + (set_attr "length_immediate" "1") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "vector") (set_attr "bdver1_decode" "vector")]) @@ -11573,6 +11574,7 @@ (define_insn "*x86_shld_1" "shld{l}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") + (set_attr "length_immediate" "1") (set_attr "mode" "SI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") @@ -12384,6 +12386,7 @@ (define_insn "*x86_64_shrd_1" "shrd{q}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") + (set_attr "length_immediate" "1") (set_attr "mode" "DI") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "vector") @@ -12446,6 +12449,7 @@ (define_insn "*x86_shrd_1" "shrd{l}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") + (set_attr "length_immediate" "1") (set_attr "mode" "SI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") diff --git a/gcc/testsuite/gcc.target/i386/pr103463-2.c b/gcc/testsuite/gcc.target/i386/pr103463-2.c new file mode 100644 index 00000000000..9c29b70bbd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103463-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-tree-bit-ccp" } */ + +int foo_u64_1; +unsigned __int128 foo_u128_1; + +void +foo (void) +{ + foo_u128_1 <<= 127; + foo_u64_1 += __builtin_sub_overflow_p (0, (long) foo_u128_1, 0); + foo_u128_1 = + foo_u128_1 >> (foo_u128_1 & 127) | foo_u128_1 << (-foo_u128_1 & 127); +} diff --git a/gcc/testsuite/gcc.target/i386/pr103463.c b/gcc/testsuite/gcc.target/i386/pr103463.c new file mode 100644 index 00000000000..faae9a858e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103463.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Os -fno-tree-dominator-opts -fno-tree-vrp" } */ + +int bar0_u8_0, bar0_u16_0, bar0_u32_0, bar0_u16_1, bar0_u32_1; +unsigned __int128 bar0_u128_0; + +int +bar0() { + bar0_u16_1 *= + __builtin_add_overflow_p(bar0_u16_0, bar0_u32_1, (long)bar0_u8_0); + bar0_u128_0 = bar0_u128_0 >> bar0_u16_1 | bar0_u128_0 << (-bar0_u16_1 & 127); + bar0_u128_0 += __builtin_mul_overflow_p(bar0_u32_0, 20, 0); +}