From patchwork Wed Sep 17 08:54:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 120419 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 16E5A3858425 for ; Wed, 17 Sep 2025 08:55:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 16E5A3858425 Authentication-Results: sourceware.org; dkim=fail reason="signature verification failed" (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=lB7Faawd X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by sourceware.org (Postfix) with ESMTPS id 154CA3858C41 for ; Wed, 17 Sep 2025 08:54:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 154CA3858C41 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 154CA3858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1758099287; cv=none; b=POT9wm+YbWXoOusy8INPvUHmFnyUD+EL74XiYIMgE/ll00i98L8fbQrXSxIAslS4K0ibGe9H7nRE8ttBDHTnnLkU1+nPibLeQvATfRlO79bCAC2dONTO8CrbCHOMHD1SkaZfZqj4VuPv/J1n7EAr8nw4XUoYNtjE3OHiv1pz2Pc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1758099287; c=relaxed/simple; bh=epmhi2KMCzi9WMLLR0DaPRAq4uqSBy8KFbnjq62tNEw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=rpN0z2bZK03cIQnveKwyJXwB9kAdycA5A0LbJ0qG/gjBcB+cS8InPQ15uplGoEsb9PARArREp01NT09VFiR4H0Z3YUioO4dDQcEXveXiM1iNNS9qdTS4GsAzoo+kk+7GpC1UHA6YbMYgU9L7Ot2WGjYAgdxZQo+Rp+44eaBepAw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 154CA3858C41 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1758099288; x=1789635288; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=epmhi2KMCzi9WMLLR0DaPRAq4uqSBy8KFbnjq62tNEw=; b=lB7FaawdQDlrcTXV5T2DMfiXlPlGn6BCf5ISIeADSvshmecixr3Y91k7 VGT+CPzbS6i9stwOkvHQuF1D4Z7ogNQIDsblTyKHc/Uc0OddZ7qypMDzb qJOMbvL0EPt15bCyYhuDZmcGiVRJJjyKIuWYZ86ShoE5sy0O185ZjgmYv R9jRlRy45M65jnABY30i1+O6jMBzuI/8284VzK3Aur9EdbjAXV71fOlrX 1Ex20neLXcl0LIK0P/KTuQ3GtzOBzkDJXd36ooknGHZr1/JUQRTOOacwz w0XDyWwEX1McOVEbfn4r3jytOhsTG5eWrqL9Q69VEEe6rUr//k6SPLqU9 g==; X-CSE-ConnectionGUID: OzFDLzhARYW4i9+jjm7F1A== X-CSE-MsgGUID: 3UdmIZRpSdS7LRG+4hZX0A== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="60316711" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="60316711" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2025 01:54:46 -0700 X-CSE-ConnectionGUID: PDWIKnEgSDS4TJKPDtZzhg== X-CSE-MsgGUID: MTiBSHHgTJiPmDaHD0P6Hw== X-ExtLoop1: 1 Received: from scymds04.sc.intel.com ([10.82.73.238]) by fmviesa003.fm.intel.com with ESMTP; 17 Sep 2025 01:54:45 -0700 Received: from jfel-spr-6155.jf.intel.com (jfel-spr-6155.jf.intel.com [10.165.119.109]) by scymds04.sc.intel.com (Postfix) with ESMTP id 308A020030E5; Wed, 17 Sep 2025 01:54:45 -0700 (PDT) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, "hongtao.liu" Subject: [PATCH v3] Remove SPR/GNR/DMR from avx512_{move, store}_by pieces tune. Date: Wed, 17 Sep 2025 01:54:45 -0700 Message-Id: <20250917085445.2320567-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: "hongtao.liu" Update in V3: #define MOVE_MAX \ ((TARGET_AVX512F \ && (ix86_move_max =3D=3D PVW_AVX512 \ || ix86_store_max =3D=3D PVW_AVX512)) \ ? 64 \ Since MOVE_MAX in x86 is also related to ix86_store_max, I'll still remove SPR/GNR/DMR from avx512_store_by_pieces. And why do we have ix86_store_max in MOVE_MAX? I guess, it's because: In the middle-end, the real size used for memset is decided by MIN (MOVE_MAX_PIECES(alignment request), STORE_MAX_PIECES) Maybe we should remove the option mstore-max= and the tune {avx512,avx256}_store_by_pieces. Since they eventually have the same impact as just setting ix86_move_max. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} Ready push to trunk. Align move_max with prefer_vector_width for SPR/GNR/DMR similar as below commit. commit 6ea25c041964bf63014fcf7bb68fb1f5a0a4e123 Author: liuhongt Date: Thu Aug 15 12:54:07 2024 +0800 Align ix86_{move_max,store_max} with vectorizer. When none of mprefer-vector-width, avx256_optimal/avx128_optimal, avx256_store_by_pieces/avx512_store_by_pieces is specified, GCC will set ix86_{move_max,store_max} as max available vector length except for AVX part. if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) && TARGET_EVEX512_P (opts->x_ix86_isa_flags2)) opts->x_ix86_move_max = PVW_AVX512; else opts->x_ix86_move_max = PVW_AVX128; So for -mavx2, vectorizer will choose 256-bit for vectorization, but 128-bit is used for struct copy, there could be a potential STLF issue due to this "misalign". gcc/ChangeLog: * config/i386/x86-tune.def (X86_TUNE_AVX512_MOVE_BY_PIECES): Remove SPR/GNR/DMR. (X86_TUNE_AVX512_STORE_BY_PIECES): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pieces-memcpy-18.c: Use -mtune=znver5 instead of -mtune=sapphirerapids. * gcc.target/i386/pieces-memcpy-21.c: Ditto. * gcc.target/i386/pieces-memset-46.c: Ditto. * gcc.target/i386/pieces-memset-49.c: Ditto. --- gcc/config/i386/x86-tune.def | 8 ++++---- gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c | 2 +- gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c | 2 +- gcc/testsuite/gcc.target/i386/pieces-memset-46.c | 2 +- gcc/testsuite/gcc.target/i386/pieces-memset-49.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index a86cbad281c..255ea4a16cc 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -612,6 +612,8 @@ DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM, /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops. */ DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4) +/* It's better to align MOVE_MAX with prefer_vector_width to reduce + risk of STLF stalls(small store followed by big load.) */ /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit AVX instructions. */ DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces", @@ -625,14 +627,12 @@ DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces", /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit AVX instructions. */ DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces", - m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D - | m_DIAMONDRAPIDS | m_ZNVER4 | m_ZNVER5) + m_ZNVER4 | m_ZNVER5) /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit AVX instructions. */ DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces", - m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D - | m_DIAMONDRAPIDS | m_ZNVER4 | m_ZNVER5) + m_ZNVER4 | m_ZNVER5) /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit vectorized loops. */ diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c index b15a0db9ff0..b4995ac0598 100644 --- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=sapphirerapids" } */ +/* { dg-options "-O2 -march=znver5" } */ extern char *dst, *src; diff --git a/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c b/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c index ef439f20f74..804a2989d64 100644 --- a/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c +++ b/gcc/testsuite/gcc.target/i386/pieces-memcpy-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */ +/* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */ extern char *dst, *src; diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-46.c b/gcc/testsuite/gcc.target/i386/pieces-memset-46.c index be1b054eed2..43d636ee3ff 100644 --- a/gcc/testsuite/gcc.target/i386/pieces-memset-46.c +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-46.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=sapphirerapids" } */ +/* { dg-options "-O2 -march=znver5" } */ extern char *dst; diff --git a/gcc/testsuite/gcc.target/i386/pieces-memset-49.c b/gcc/testsuite/gcc.target/i386/pieces-memset-49.c index ad43f89a9bd..ca4933ac1d8 100644 --- a/gcc/testsuite/gcc.target/i386/pieces-memset-49.c +++ b/gcc/testsuite/gcc.target/i386/pieces-memset-49.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mtune=sapphirerapids -march=x86-64 -mavx2" } */ +/* { dg-options "-O2 -mtune=znver5 -march=x86-64 -mavx2" } */ extern char *dst;