From patchwork Wed Sep 17 01:40:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 120396 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B09803858C42 for ; Wed, 17 Sep 2025 01:42:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B09803858C42 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=xry111.site header.i=@xry111.site header.a=rsa-sha256 header.s=default header.b=HzS8z4hf X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id A77543858D33 for ; Wed, 17 Sep 2025 01:40:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A77543858D33 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A77543858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1758073259; cv=none; b=AaHgSgW4BYZ1r2RVFl9SIQ64AfLli0g8yMeJTStzsdZPVUF7b21QOqnpfINmuRt2BH+oevl/Tqklf8ftvnKvr79p/+W+njXm/cp01QoXshVToLhQdukxzEg9YCz10J2ZlXEFaxV1iUXpsUz0twg0U5VqtPy/6PD8TPBq/ZNeM/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1758073259; c=relaxed/simple; bh=T1B8NzLBgl9DvRs9OWIITXncpPWo1uBaPE6WDlSo/ng=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=cAxfPKc5tNGMGDKNbfH9iQxiEpTZPaDGUnf/QM6AQIfAhYxzxMMJ18pnmkehROG473MiJVZ/Snv4oPgoj8BYFQfnXBZ+k5TxdCNWi6ZudOQwt/tiRrvfGBhUL7xGa31f8pq9teh5m9mk4wP2ddFav9rs5N+htVZj90u0c7ZxZb0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A77543858D33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xry111.site; s=default; t=1758073257; bh=qrgt6oBk84hvW1fBY4lqqJgnL5Qhw9R+u/wf0FHvMyE=; h=From:To:Cc:Subject:Date:From; b=HzS8z4hf8oUWpsdFFbP1HOhWZsj1c2o0InA4Inf3JydvBYZA/qcZeZWlCMi2NdyAh R+HW+afB7RuBTpfrttNHS5kKFEHcgmKDdjoHq6Rc1ydIfazAGGdeDH5c/0d97xfrIl 55BJbK7ZnaysDiBH96c9B2SFKeLs581PWi4Feb9w= Received: from stargazer (unknown [IPv6:2409:8a4c:e24:3370::b3c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 05CEF665BB; Tue, 16 Sep 2025 21:40:55 -0400 (EDT) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org, Lulu Cheng Cc: Mingcong Bai , WANG Xuerui , Xi Ruoyao Subject: [PATCH] LoongArch: Add isnan expander [PR 66462] Date: Wed, 17 Sep 2025 09:40:25 +0800 Message-ID: <20250917014041.10457-1-xry111@xry111.site> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Add an expander for isnan using fclass. Since isnan is just a compare, enable it only with -fsignaling-nans to avoid generating spurious exceptions. This fixes part of PR66462. int isnan1 (float x) { return __builtin_isnan (x); } With -fno-signaling-nans: fcmp.cun.s $fcc0,$f0,$f0 movcf2fr $f0,$fcc0 movfr2gr.s $r4,$f0 jr $r1 With -fsignaling-nans: fclass.s $f0,$f0 movfr2gr.s $r4,$f0 andi $r4,$r4,3 sltu $r4,$r0,$r4 jr $r1 PR middle-end/66462 gcc/ * config/loongarch/loongarch.md (FCLASS_MASK): Add 3. (fclass_optab): Assign isnan for 3. (2): If FCLASS_MASK is 3, only enable when -fsignaling-nans. gcc/testsuite: * gcc.target/loongarch/fclass-compile.c: Update test. * gcc.target/loongarch/fclass-run.c: Likewise. --- Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? gcc/config/loongarch/loongarch.md | 7 ++++--- gcc/testsuite/gcc.target/loongarch/fclass-compile.c | 9 ++++++--- gcc/testsuite/gcc.target/loongarch/fclass-run.c | 8 ++++---- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index f42dc102d10..a275a2d0158 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -4193,17 +4193,18 @@ (define_insn "fclass_" [(set_attr "type" "unknown") (set_attr "mode" "")]) -(define_int_iterator FCLASS_MASK [68 136 952]) +(define_int_iterator FCLASS_MASK [68 136 952 3]) (define_int_attr fclass_optab [(68 "isinf") (136 "isnormal") - (952 "isfinite")]) + (952 "isfinite") + (3 "isnan")]) (define_expand "2" [(match_operand:SI 0 "register_operand" "=r") (match_operand:ANYF 1 "register_operand" " f") (const_int FCLASS_MASK)] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && ( != 3 || flag_signaling_nans)" { rtx ft0 = gen_reg_rtx (SImode); rtx t0 = gen_reg_rtx (word_mode); diff --git a/gcc/testsuite/gcc.target/loongarch/fclass-compile.c b/gcc/testsuite/gcc.target/loongarch/fclass-compile.c index 9c24d6e263c..3db83e7b31d 100644 --- a/gcc/testsuite/gcc.target/loongarch/fclass-compile.c +++ b/gcc/testsuite/gcc.target/loongarch/fclass-compile.c @@ -1,14 +1,16 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=loongarch64 -mfpu=64 -mabi=lp64d" } */ +/* { dg-options "-O2 -fsignaling-nans -march=loongarch64 -mfpu=64 -mabi=lp64d" } */ /* { dg-final { scan-assembler-times "fclass\\.s" 1 } } */ /* { dg-final { scan-assembler-times "fclass\\.d" 1 } } */ +/* { dg-final { scan-assembler-not "fcmp" } } */ __attribute__ ((noipa)) int test_fclass_f (float f) { return __builtin_isinf (f) | __builtin_isnormal (f) << 1 - | __builtin_isfinite (f) << 2; + | __builtin_isfinite (f) << 2 + | __builtin_isnan (f) << 3; } __attribute__ ((noipa)) int @@ -16,5 +18,6 @@ test_fclass_d (double d) { return __builtin_isinf (d) | __builtin_isnormal (d) << 1 - | __builtin_isfinite (d) << 2; + | __builtin_isfinite (d) << 2 + | __builtin_isnan (d) << 3; } diff --git a/gcc/testsuite/gcc.target/loongarch/fclass-run.c b/gcc/testsuite/gcc.target/loongarch/fclass-run.c index e5585f9d557..3852d2015b3 100644 --- a/gcc/testsuite/gcc.target/loongarch/fclass-run.c +++ b/gcc/testsuite/gcc.target/loongarch/fclass-run.c @@ -37,8 +37,8 @@ main (void) ASSERT_EQ (test_fclass_f (-f_normal), 0b110); ASSERT_EQ (test_fclass_f (f_subnormal), 0b100); ASSERT_EQ (test_fclass_f (-f_subnormal), 0b100); - ASSERT_EQ (test_fclass_f (f_qnan), 0); - ASSERT_EQ (test_fclass_f (f_snan), 0); + ASSERT_EQ (test_fclass_f (f_qnan), 0b1000); + ASSERT_EQ (test_fclass_f (f_snan), 0b1000); ASSERT_EQ (test_fclass_d (d_inf), 0b001); ASSERT_EQ (test_fclass_d (-d_inf), 0b001); @@ -48,6 +48,6 @@ main (void) ASSERT_EQ (test_fclass_d (-d_normal), 0b110); ASSERT_EQ (test_fclass_d (d_subnormal), 0b100); ASSERT_EQ (test_fclass_d (-d_subnormal), 0b100); - ASSERT_EQ (test_fclass_d (d_qnan), 0); - ASSERT_EQ (test_fclass_d (d_snan), 0); + ASSERT_EQ (test_fclass_d (d_qnan), 0b1000); + ASSERT_EQ (test_fclass_d (d_snan), 0b1000); }