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d="scan'208";a="179186478" Received: from panli.sh.intel.com ([10.239.159.63]) by fmviesa005.fm.intel.com with ESMTP; 15 Sep 2025 20:22:44 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, richard.guenther@gmail.com, Pan Li Subject: [PATCH v2 1/2] Match: Add form 5 of unsigned SAT_MUL for widen-mul Date: Tue, 16 Sep 2025 11:19:46 +0800 Message-ID: <20250916032320.950614-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916032320.950614-1-pan2.li@intel.com> References: <20250916032320.950614-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li This patch would like to try to match the the unsigned SAT_MUL form 4, aka below: #define DEF_SAT_U_MUL_FMT_5(NT, WT) \ NT __attribute__((noinline)) \ sat_u_mul_##NT##_from_##WT##_fmt_5 (NT a, NT b) \ { \ WT x = (WT)a * (WT)b; \ NT hi = x >> (sizeof(NT) * 8); \ NT lo = (NT)x; \ return lo | -!!hi; \ } while WT is uint128_t, T is uint8_t, uint16_t, uint32_t or uint64_t. gcc/ChangeLog: * match.pd: Add pattern for SAT_MUL form 5. * tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children): Try match pattern for IOR. Signed-off-by: Pan Li --- gcc/match.pd | 25 +++++++++++++++++++++++++ gcc/tree-ssa-math-opts.cc | 1 + 2 files changed, 26 insertions(+) diff --git a/gcc/match.pd b/gcc/match.pd index 53320d7614c..2e629fd31ce 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3695,6 +3695,31 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) bool c2_is_type_precision_p = c2 == prec; } (if (widen_prec > prec && c2_is_type_precision_p && c4_is_max_p))))) + (match (unsigned_integer_sat_mul @0 @1) + /* SAT_U_MUL (X, Y) = { + WT x = (WT)a * (WT)b; + NT hi = x >> (sizeof(NT) * 8); + NT lo = (NT)x; + return lo | -!!hi; + } while WT is uint128_t, T is uint8_t, uint16_t, uint32_t or uint64_t. */ + (convert1? + (bit_ior (convert? (negate (convert (ne (convert (rshift @3 INTEGER_CST@2)) + integer_zerop)))) + (convert (widen_mult:c@3 (convert@4 @0) + (convert@5 @1))))) + (if (types_match (type, @0, @1)) + (with + { + unsigned widen_prec = TYPE_PRECISION (TREE_TYPE (@3)); + unsigned cvt4_prec = TYPE_PRECISION (TREE_TYPE (@4)); + unsigned cvt5_prec = TYPE_PRECISION (TREE_TYPE (@5)); + bool widen_mult_p = cvt4_prec == cvt5_prec && widen_prec == cvt5_prec * 2; + + unsigned c2 = tree_to_uhwi (@2); + unsigned prec = TYPE_PRECISION (type); + bool c2_is_type_precision_p = c2 == prec; + } + (if (widen_mult_p && c2_is_type_precision_p))))) ) /* The boundary condition for case 10: IMM = 1: diff --git a/gcc/tree-ssa-math-opts.cc b/gcc/tree-ssa-math-opts.cc index 6fafa1b4096..344ffddd385 100644 --- a/gcc/tree-ssa-math-opts.cc +++ b/gcc/tree-ssa-math-opts.cc @@ -6529,6 +6529,7 @@ math_opts_dom_walker::after_dom_children (basic_block bb) break; case BIT_IOR_EXPR: + match_unsigned_saturation_mul (&gsi, as_a (stmt)); match_saturation_add_with_assign (&gsi, as_a (stmt)); match_unsigned_saturation_trunc (&gsi, as_a (stmt)); /* fall-through */ From patchwork Tue Sep 16 03:19:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 120331 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7801A385743A for ; Tue, 16 Sep 2025 03:30:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7801A385743A Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kntgNKvs X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by sourceware.org (Postfix) with ESMTPS id 546883857348 for ; Tue, 16 Sep 2025 03:22:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 546883857348 Authentication-Results: sourceware.org; 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d="scan'208";a="179186483" Received: from panli.sh.intel.com ([10.239.159.63]) by fmviesa005.fm.intel.com with ESMTP; 15 Sep 2025 20:22:46 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, richard.guenther@gmail.com, Pan Li Subject: [PATCH v2 2/2] RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for widen-mul Date: Tue, 16 Sep 2025 11:19:47 +0800 Message-ID: <20250916032320.950614-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916032320.950614-1-pan2.li@intel.com> References: <20250916032320.950614-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li The form 5 of unsigned scalar SAT_MUL is covered in middle-expand alreay, add test case here to cover form 5. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat/sat_u_mul-6-u16-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-6-u32-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-6-u64-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-6-u8-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-6-u64-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u128.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat/sat_arith.h | 15 +++++++++++++++ .../riscv/sat/sat_u_mul-6-u16-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-6-u32-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-6-u64-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-6-u8-from-u128.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-run-6-u16-from-u128.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-6-u32-from-u128.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-6-u64-from-u128.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-6-u8-from-u128.c | 16 ++++++++++++++++ 9 files changed, 123 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u128.c diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index 035545c9e0f..7cd16a29648 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -741,4 +741,19 @@ sat_u_mul_##NT##_from_##WT##_fmt_4 (NT a, NT b) \ sat_u_mul_##NT##_from_##WT##_fmt_4 (a, b) #define RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_4(NT, WT, a, b) +#define DEF_SAT_U_MUL_FMT_5(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_mul_##NT##_from_##WT##_fmt_5 (NT a, NT b) \ +{ \ + WT x = (WT)a * (WT)b; \ + NT hi = x >> (sizeof(NT) * 8); \ + NT lo = (NT)x; \ + return lo | -!!hi; \ +} + +#define DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_5(NT, WT) +#define RUN_SAT_U_MUL_FMT_5(NT, WT, a, b) \ + sat_u_mul_##NT##_from_##WT##_fmt_5 (a, b) +#define RUN_SAT_U_MUL_FMT_5_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_5(NT, WT, a, b) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u128.c new file mode 100644 index 00000000000..d5896650036 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u128.c new file mode 100644 index 00000000000..6a074228492 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u64-from-u128.c new file mode 100644 index 00000000000..438b420f95a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u64-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint64_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u128.c new file mode 100644 index 00000000000..9dbb434d56a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u128.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u128.c new file mode 100644 index 00000000000..88fe3a74e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_5_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u128.c new file mode 100644 index 00000000000..c8d802efdf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_5_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u64-from-u128.c new file mode 100644 index 00000000000..acc999fc748 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u64-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_5_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u128.c new file mode 100644 index 00000000000..88fe3a74e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_5_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_5_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h"