From patchwork Sun Sep 14 00:50:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gross X-Patchwork-Id: 120209 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 64C143858C40 for ; Sun, 14 Sep 2025 00:53:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 64C143858C40 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=umich.edu header.i=@umich.edu header.a=rsa-sha256 header.s=relay-2 header.b=DsZ7lEGk X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from diligent-afallach.relay-egress.a.mail.umich.edu (relay-egress-host.us-east-2.a.mail.umich.edu [18.219.209.13]) by sourceware.org (Postfix) with ESMTPS id 07B72385C6FC for ; Sun, 14 Sep 2025 00:51:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 07B72385C6FC Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=umich.edu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=umich.edu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 07B72385C6FC Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=18.219.209.13 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1757811093; cv=none; b=utejdpJK4DjuhAIUlJv5cAVkqg8ovJZen41LdRwPxiEyh+v9ylX6+g1zYE6BEKiyeHyVyZa0KTjsV4nPdlefQE5g3ao+hjuS0lrZy3veMRgqMu4jdCaW5xq0NX+Nlie5T83MEsuPqccekTN2vIs0w0GIzKqtegh9fmQg1b9SKIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1757811093; c=relaxed/simple; bh=B4QU3gVXZnQtI0Kv6c+YfKQqo5oyGUZBFVVtJY3YvqE=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=U1yhmGTyEUiP9+shV/czCVNjyl4JpCuq8Cydl8gtKh/v8i4OMekXNANAxiGS6QT181lvr/2HQ3halE2nNNWJ3jumGcH+K+ViipISPS+Kq4YIlXw0DaFAX/kL+qDLnuzW7l61IBAy0zF/7QgBjrhSjJp/nEmzA0FBfcqt1Yo+6oc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 07B72385C6FC Received: from jointed-coblynau.authn-relay.a.mail.umich.edu (ip-10-0-73-227.us-east-2.compute.internal [10.0.73.227]) by diligent-afallach.relay-egress.a.mail.umich.edu with ESMTPS id 68C61189.14FA0F37.1176D1A9.1542076; Sat, 13 Sep 2025 20:51:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=umich.edu; s=relay-2; t=1757811081; bh=KIGxoxGalSz7RV92I9Rqy0AVmPmQEiuqr+8aCTWAfuc=; h=From:To:Cc:Subject:Date; b=DsZ7lEGkJ8TaW4AfDMGRPE/pISVVV9JJJPMcDV7lpEFtqX4drj6Kx2K2p8YHqTdo8 AJazJBxMMj3eHSW2agVvv2RwrHBfZWEAyvYciOZanDZ9EyfM/WAT3EklmNv1zFyP+a jxPSw2Yit4cv/TBK5iqsCRxtvYnL5yT84oEBCB8avesedLT9QFFTvOA4/sjer/N2HX +xvUZhrOei7bvyonU/Yxhb3doUY0+fMVdGdPJd/B3K9eETAGspCMOXW8Os2eiXBkaA nLQkuXCeLlKclI9RCs2H4JxVB2v1HGeUGHN6GHsoKx1ahAAlscy007NATPIJ+PLGSe uY/rxFF6yrdAg== Authentication-Results: jointed-coblynau.authn-relay.a.mail.umich.edu; iprev=fail policy.iprev=73.110.187.65 (Mismatch); auth=pass smtp.auth=tmgross Received: from localhost.localdomain (Mismatch [73.110.187.65]) by jointed-coblynau.authn-relay.a.mail.umich.edu with ESMTPSA id 68C61188.2C936B17.1A5CA974.2789437; Sat, 13 Sep 2025 20:51:20 -0400 From: Trevor Gross To: gcc-patches@gcc.gnu.org, Jonathan Yong <10walls@gmail.com>, LIU Hao Cc: Christoph Reiter , Reid Kleckner , Trevor Gross , Bernhard Reutner-Fischer Subject: [PATCH v3] x86-64: mingw: Pass and return _Float16 in vector registers [PR115054] Date: Sat, 13 Sep 2025 19:50:21 -0500 Message-Id: <20250914005020.29063-1-tmgross@umich.edu> X-Mailer: git-send-email 2.39.5 (Apple Git-154) MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org For MinGW on x86-64, GCC currently passes and returns `_Float16` in GPRs. Microsoft does not specify an ABI for the type so this is purely an extension; however, there are a few reasons the current ABI is not ideal: 1. `float` and `double` are both passed and returned in xmm registers under the MSVC ABI, there isn't any reason for `_Float16` to deviate. 2. `_Float16` is returned in xmm0 on Windows x86-32 by both GCC and Clang. 2. There is a platform-natural ABI with AVX512-FP16, which requires half-precision operands to be in vector registers. 3. System V uses vector registers for `_Float16`. Thus, update the `HFmode` ABI to both pass and return in vector registers, meaning its ABI is now identical to `float` and `double`. This is already Clang's behavior on both its x64 MSVC and MinGW targets, so the change here also resolves an ABI incompatibility (originally reported in linked issue). The results can be verified by evaluating the change in assembly output with this source: void pass_f16(_Float16 x, _Float16 *dst) { *dst = x; } void callee_f16(_Float16); void call_f16() { callee_f16(1.0); } _Float16 ret_f16(_Float16 *x) { return *x; } /* Check libcall ABI */ void extend_f16(_Float16 *x, _Float32 *dst) { *dst = (_Float32)*x; } void trunc_f16(_Float32 *x, _Float16 *dst) { *dst = (_Float16)*x; } /* Float varargs should be in vregs with a zeroed shadow GPR */ void va(_Float16, ...); void va_f16() { va(1.0f16, 2.0f16, 3.0f16, 4.0f16, 5.0f16); } While modifying the `function_value_ms_64` `switch` statement, a redundant condition and trailing whitespace in the 16-byte case is cleaned up. 2025-09-13 Trevor Gross gcc/: PR target/115054 * gcc/config/i386/i386.cc (function_arg_ms_64, function_value_ms_64): Pass and return _Float16 in vector registers on Windows. Signed-off-by: Trevor Gross --- * Changes v1->v2: no code changes, only updated a commit message * Changes v2->v3: fix a typo in a comment missed from [1] v1: https://inbox.sourceware.org/gcc-patches/20250831215847.64430-1-tmgross@umich.edu/ v2: https://inbox.sourceware.org/gcc-patches/20250913175452.16582-1-tmgross@umich.edu/ I have sample output with and without this patch at [2] for reference. [1]: https://inbox.sourceware.org/gcc-patches/8fc02832-aac1-4341-987b-849f17281839@gmail.com/ [2]: https://github.com/tgross35/gcc-build-output gcc/config/i386/i386.cc | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 5ef7c315091..d56094e1daa 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -3493,8 +3493,10 @@ function_arg_ms_64 (const CUMULATIVE_ARGS *cum, machine_mode mode, regno = x86_64_ms_abi_int_parameter_registers[cum->regno]; - /* Only floating point modes are passed in anything but integer regs. */ - if (TARGET_SSE && (mode == SFmode || mode == DFmode)) + /* Only floating point modes less than 64 bits are passed in anything but + integer regs. Larger floating point types are excluded as the Windows + ABI requires vreg args can be shadowed in GPRs (for red zone / varargs). */ + if (TARGET_SSE && (mode == HFmode || mode == SFmode || mode == DFmode)) { if (named) { @@ -4314,9 +4316,8 @@ function_value_ms_64 (machine_mode orig_mode, machine_mode mode, { switch (GET_MODE_SIZE (mode)) { - case 16: + case 16: if (valtype != NULL_TREE - && !VECTOR_INTEGER_TYPE_P (valtype) && !VECTOR_INTEGER_TYPE_P (valtype) && !INTEGRAL_TYPE_P (valtype) && !VECTOR_FLOAT_TYPE_P (valtype)) @@ -4327,9 +4328,10 @@ function_value_ms_64 (machine_mode orig_mode, machine_mode mode, break; case 8: case 4: + case 2: if (valtype != NULL_TREE && AGGREGATE_TYPE_P (valtype)) break; - if (mode == SFmode || mode == DFmode) + if (mode == HFmode || mode == SFmode || mode == DFmode) regno = FIRST_SSE_REG; break; default: