From patchwork Fri Sep 12 14:14:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 120174 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D89493857737 for ; Fri, 12 Sep 2025 23:35:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 286413858039 for ; Fri, 12 Sep 2025 23:34:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 286413858039 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 286413858039 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1757720076; cv=none; b=qYp09qRTBP1mO5ItsUYrxwWttXUYhvbrA4fW/rMTNFgiQi1mDEdssNQkdVWbCdL1wUFKA9HCY6yBu2Srl50+rXolq7/T1fNt1dyM0424PbwpF4XxiF08s5m144NKkyVmRHmiD5bzWf5oA7/rNecTIVkXatr4BqaGN4sGH/IOMP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1757720076; c=relaxed/simple; bh=RgiAPVpqNvZBRxrylw60zRcyNijejtb2i9N02YJI8lg=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=ZtoFri65AxmKb5Ln/WVTJIqbQJdKRdhUaaM5nEpw1blaor3yOb/0mXXX2zjpvAQ1CRzF90P7GD4JLwe9eKxd7/OTccyE/kNgJoUrp6rxbVAHUCJimdZwaF7K1ekuanQLWNGd/aivqe2/BNhBt68JdqHT+ypeG5rv6SEHCWtMOrs= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 286413858039 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=duAwJZDl DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757720076; x=1789256076; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RgiAPVpqNvZBRxrylw60zRcyNijejtb2i9N02YJI8lg=; b=duAwJZDl3IovQlATBBZF8ik0n+l9YH9RuxW81Ycl7KSWYv1u1sxpuTF4 hYF3RoGDLbm0d/+j9XLOZiB1nLKiUiIHoyVu/cbMgMtaPYS3Bl0i6HxxR f78EXAr25OkwxlC2c/1czGQ2TfyY3pRJSuA09wpXJ2ZBw9kcYMJEepQo2 G62uRDJbAlWGHWMubmb6UVygXINCfAh1S5VR4gbxp6bPYBiHna7zpK/OT p5lXSICe+9v57YS9TWqHsDoHlpx52I2naB9jF2Pb0PJMWqh3uEyLicyxy 3nXA4uYVnFikUXVmQuvAjuFNHXxkNoYHouNZDxbLrwRGiig/dfHYNFqax A==; X-CSE-ConnectionGUID: xEmHY5V3RRWFznUAe1PjGQ== X-CSE-MsgGUID: Om31hCHyQuqUeW6IIqPu2A== X-IronPort-AV: E=McAfee;i="6800,10657,11551"; a="85500925" X-IronPort-AV: E=Sophos;i="6.18,260,1751266800"; d="scan'208";a="85500925" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2025 16:34:35 -0700 X-CSE-ConnectionGUID: UGdsWuaLS4OC2H4drC76pQ== X-CSE-MsgGUID: s6DQAWArS3G8NU16XSDBjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,260,1751266800"; d="scan'208";a="173285388" Received: from panli.sh.intel.com ([10.239.159.63]) by orviesa006.jf.intel.com with ESMTP; 12 Sep 2025 16:34:33 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 1/4] RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on GR2VR cost Date: Fri, 12 Sep 2025 22:14:30 +0800 Message-ID: <20250912233514.3586587-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250912233514.3586587-1-pan2.li@intel.com> References: <20250912233514.3586587-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li This patch would like to combine the vec_duplicate + vwaddu.vv to the vwaddu.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the GR2VR cost is greater than zero. Assume we have example code like below, GR2VR cost is 0. Before this patch: 11 beq a3,zero,.L8 12 vsetvli a5,zero,e32,m1,ta,ma 13 vmv.v.x v2,a2 ... 16 .L3: 17 vsetvli a5,a3,e32,m1,ta,ma ... 22 vwaddu.vv v1,v2,v3 ... 25 bne a3,zero,.L3 After this patch: 11 beq a3,zero,.L8 ... 14 .L3: 15 vsetvli a5,a3,e32,m1,ta,ma ... 20 vwaddu.vx v1,a2,v3 ... 23 bne a3,zero,.L3 The pattern of this patch only works on DImode, aka below pattern. v1:RVVM1DImode = (zero_extend:RVVM1DImode v2:RVVM1SImode) + (vec_dup:RVVM1DImode (zero_extend:DImode x2:SImode)); Unfortunately, for uint16_t to uint32_t or uint8_t to uint16_t, we loss this extend op after expand. For uint16_t => uint32_t we have: (set (reg:SI 149) (subreg/s/v:SI (reg/v:DI 146 [ rs1 ]) 0)) For uint32_t => uint64_t we have: (set (reg:DI 148 [ _6 ]) (zero_extend:DI (subreg/s/u:SI (reg/v:DI 146 [ rs1 ]) 0))) We can see there is no zero_extend for uint16_t to uint32_t, and we cannot hit the pattern above. So the combine will try below pattern for uint16_t to uint32_t. v1:RVVM1SImode = (zero_extend:RVVM1SImode v2:RVVM1HImode) + (vec_dup:RVVM1SImode (subreg:SIMode (:DImode x2:SImode))) But it cannot match the vwaddu sematics, thus we need another handing for the vwaddu.vv for uint16_t to uint32_t, as well as the uint8_t to uint16_t. gcc/ChangeLog: * config/riscv/autovec-opt.md (*widen_frist__vx_): Add helper bridge pattern for vwaddu.vx combine. (*widen___vx_): Add new pattern to match vwaddu.vx combine. * config/riscv/iterators.md: Add code attr to get extend CODE. * config/riscv/vector-iterators.md: Add Dmode iterator for widen. Signed-off-by: Pan Li --- gcc/config/riscv/autovec-opt.md | 44 ++++++++++++++++++++++++++++ gcc/config/riscv/iterators.md | 3 ++ gcc/config/riscv/vector-iterators.md | 16 ++++++++++ 3 files changed, 63 insertions(+) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 02f19bc6a42..fefd2dc63c3 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1868,6 +1868,50 @@ (define_insn_and_split "*mul_minus_vx_" } [(set_attr "type" "vimuladd")]) +(define_insn_and_split "*widen_frist__vx_" + [(set (match_operand:VWEXTI_D 0 "register_operand") + (vec_duplicate:VWEXTI_D + (any_extend: + (match_operand: 1 "register_operand"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + machine_mode d_trunc_mode = mode; + rtx vec_dup = gen_reg_rtx (d_trunc_mode); + insn_code icode = code_for_pred_broadcast (d_trunc_mode); + rtx vec_dup_ops[] = {vec_dup, operands[1]}; + riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, vec_dup_ops); + + icode = code_for_pred_vf2 (, mode); + rtx extend_ops[] = {operands[0], vec_dup}; + riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, extend_ops); + + DONE; + }) + +(define_insn_and_split "*widen___vx_" + [(set (match_operand:VWEXTI_D 0 "register_operand") + (any_widen_binop:VWEXTI_D + (any_extend:VWEXTI_D + (match_operand: 1 "register_operand")) + (vec_duplicate:VWEXTI_D + (any_extend: + (match_operand: 2 "register_operand")))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_dual_widen_scalar (, + , + mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); + + DONE; + } + [(set_attr "type" "viwalu")]) ;; ============================================================================= ;; Combine vec_duplicate + op.vv to op.vf diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index d3002241509..41e56c721c5 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -207,6 +207,9 @@ (define_mode_attr slot12_offset [(SI "-52") (DI "-104")]) ;; This code iterator allows signed and unsigned widening multiplications ;; to use the same template. (define_code_iterator any_extend [sign_extend zero_extend]) +(define_code_attr extend_code [ + (sign_extend "SIGN_EXTEND") (zero_extend "ZERO_EXTEND") +]) ;; These code iterators allow unsigned and signed extraction to be generated ;; from the same template. diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index ed7e9c3a951..45af65642cd 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -943,6 +943,22 @@ (define_mode_iterator V_FRACT [ (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_VECTOR_ELEN_64") ]) +(define_mode_iterator VWEXTI_D [ + (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") + (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") + + (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64") + (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64") + (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64") + (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64") + (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") + (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256") + (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512") + (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") + (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") + (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") +]) + (define_mode_iterator VWEXTI [ RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_VECTOR_ELEN_64") From patchwork Fri Sep 12 14:14:31 2025 Content-Type: text/plain; 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d="scan'208";a="173285395" Received: from panli.sh.intel.com ([10.239.159.63]) by orviesa006.jf.intel.com with ESMTP; 12 Sep 2025 16:34:35 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 2/4] RISC-V: Add test for vec_duplicate + vwaddu.vv signed combine with GR2VR cost 0, 1 and 15 Date: Fri, 12 Sep 2025 22:14:31 +0800 Message-ID: <20250912233514.3586587-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250912233514.3586587-1-pan2.li@intel.com> References: <20250912233514.3586587-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add asm dump check and run test for vec_duplicate + vwaddu.vv combine to vwaddu.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vwaddu.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 4 + .../rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c | 18 +++++ .../riscv/rvv/autovec/vx_vf/vx_widen.h | 34 ++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 79 +++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h | 27 +++++++ 13 files changed, 194 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index d191097e2bb..bb29ef5638c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint16_t +#define NT uint8_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index e0b4b732c79..1d738571b49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint32_t +#define NT uint16_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index 65528400b5b..dc6d1c6b183 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint64_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -29,3 +32,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 23479d97b65..c6da9c7e19d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint16_t +#define NT uint8_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 8c41bd85686..6f1adef686c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint32_t +#define NT uint16_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index abe16cd7b50..5ea7cc96ae6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint64_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index f232d6a97bd..f18409e7643 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint16_t +#define NT uint8_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 24e187ce2b0..b33d8269136 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint32_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index 977aa463232..40f4142a88a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint64_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c new file mode 100644 index 00000000000..e7a75d56f77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_widen.h" +#include "vx_widen_data.h" + +#define WT uint64_t +#define NT uint32_t +#define NAME add +#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) +#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) + +DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, NAME) + +#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \ + RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N) + +#include "vx_widen_vx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h new file mode 100644 index 00000000000..646edab4310 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h @@ -0,0 +1,34 @@ +#ifndef HAVE_DEFINED_VX_VF_BINARY_WIDEN_H +#define HAVE_DEFINED_VX_VF_BINARY_WIDEN_H + +#include + +#undef HAS_INT128 + +#if __riscv_xlen == 64 +#define HAS_INT128 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_VX_WIDEN_BINARY_CASE_0(WT, NT, OP, NAME) \ +void \ +test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \ + NT * restrict vs2, \ + NT rs1, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + vd[i] = (WT)vs2[i] OP (WT)rs1; \ +} + +#define DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, OP, NAME) \ + DEF_VX_WIDEN_BINARY_CASE_0(WT, NT, OP, NAME) +#define RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) \ + test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0(vd, vs2, rs1, n) +#define RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \ + RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) + +#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \ + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h new file mode 100644 index 00000000000..48dc4d4c849 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h @@ -0,0 +1,79 @@ +#ifndef HAVE_DEFINED_VX_WIDEN_DATA_H +#define HAVE_DEFINED_VX_WIDEN_DATA_H + +#define N 16 + +#define DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME) \ + binary_widen_##WT##_##NT##_##NAME##_s +#define DEF_BINARY_WIDEN_STRUCT_0_NAME_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0_TYPE(WT, NT, NAME) \ + struct DEF_BINARY_WIDEN_STRUCT_0_NAME_WRAP(WT, NT, NAME) +#define DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_TYPE(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME) \ + binary_widen_##WT##_##NT##_##NAME##_data +#define DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0_DECL(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) +#define DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_DECL(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \ + { \ + NT vs2[N]; \ + NT rs1; \ + WT expect[N]; \ + WT vd[N]; \ + }; +#define DEF_BINARY_WIDEN_STRUCT_0_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME) + +DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add) + +DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + /* rs1 */ + 2147483647, + /* expect */ + { + 2147483648, 2147483648, 2147483648, 2147483648, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + }, + /* rs1 */ + 4294967295, + /* expect */ + { + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull, + 8589934589ull, 8589934589ull, 8589934589ull, 8589934589ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h new file mode 100644 index 00000000000..87fe0b13215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h @@ -0,0 +1,27 @@ +#ifndef HAVE_DEFINED_VX_WIDEN_RUN_H +#define HAVE_DEFINED_VX_WIDEN_RUN_H + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + DATA_TYPE *data = &TEST_DATA[i]; + NT *vs2 = data->vs2; + NT rs1 = data->rs1; + WT *expect = data->expect; + WT *vd = data->vd; + + TEST_RUN (WT, NT, NAME, vd, vs2, rs1, N); + + for (k = 0; k < N; k++) + if (vd[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif From patchwork Fri Sep 12 14:14:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" 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080tw1ClQCKS1CM+1nnDKg== X-CSE-MsgGUID: RjEMB5qsRoGpb8Y3eavoIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,260,1751266800"; d="scan'208";a="173285401" Received: from panli.sh.intel.com ([10.239.159.63]) by orviesa006.jf.intel.com with ESMTP; 12 Sep 2025 16:34:38 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 3/4] RISC-V: Add test for vec_duplicate + vwsubu.vv signed combine with GR2VR cost 0, 1 and 15 Date: Fri, 12 Sep 2025 22:14:32 +0800 Message-ID: <20250912233514.3586587-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250912233514.3586587-1-pan2.li@intel.com> References: <20250912233514.3586587-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add asm dump check and run test for vec_duplicate + vwsubu.vv combine to vwsubu.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vwsubu.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c | 18 +++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen.h | 5 ++- .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 40 +++++++++++++++++++ 12 files changed, 70 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index bb29ef5638c..25bb93c8ce5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index 1d738571b49..475b74b10f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index dc6d1c6b183..c7f3f2b25d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index c6da9c7e19d..1c0024c273e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 6f1adef686c..3e88fc0623f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 5ea7cc96ae6..541b6e678b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index f18409e7643..6d25e26d83b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index b33d8269136..f0c6624a536 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index 40f4142a88a..8de1d6fd807 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vwsubu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c new file mode 100644 index 00000000000..f94281002ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_widen.h" +#include "vx_widen_data.h" + +#define WT uint64_t +#define NT uint32_t +#define NAME sub +#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) +#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) + +DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, NAME) + +#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \ + RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N) + +#include "vx_widen_vx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h index 646edab4310..290d8a4b5d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h @@ -28,7 +28,8 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \ #define RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \ RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) -#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \ - DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) +#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \ + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \ + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h index 48dc4d4c849..7359f0bc85d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h @@ -36,6 +36,7 @@ DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME) DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add) +DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub) DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { { @@ -76,4 +77,43 @@ DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { }, }; +DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, sub)[] = { + { + /* vs2 */ + { + 2147483648, 2147483648, 2147483648, 2147483648, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + /* rs1 */ + 2147483647, + /* expect */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, + { + /* vs2 */ + { + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + /* rs1 */ + 4294967295, + /* expect */ + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744069414584322ull, 18446744069414584322ull, 18446744069414584322ull, 18446744069414584322ull, + 18446744069414584321ull, 18446744069414584321ull, 18446744069414584321ull, 18446744069414584321ull, + }, + }, +}; + #endif From patchwork Fri Sep 12 14:14:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 120177 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F2D363857B84 for ; Fri, 12 Sep 2025 23:40:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F2D363857B84 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gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 4/4] RISC-V: Add test for vec_duplicate + vwmulu.vv signed combine with GR2VR cost 0, 1 and 15 Date: Fri, 12 Sep 2025 22:14:33 +0800 Message-ID: <20250912233514.3586587-5-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250912233514.3586587-1-pan2.li@intel.com> References: <20250912233514.3586587-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add asm dump check and run test for vec_duplicate + vwmulu.vv combine to vwmulu.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vwmulu.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test data for vwmulu.vx run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c | 18 +++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen.h | 3 +- .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 40 +++++++++++++++++++ 12 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index 25bb93c8ce5..c86461beadf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index 475b74b10f0..90de1974ab1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index c7f3f2b25d4..522ddd19ccd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -34,3 +34,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 1c0024c273e..6ea17bb83d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 3e88fc0623f..8b8fba54b72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 541b6e678b9..6f66de906a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 6d25e26d83b..cd129f1f50e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index f0c6624a536..48aeed71eb9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index 8de1d6fd807..b88c350acf3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c new file mode 100644 index 00000000000..11c11eded43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_widen.h" +#include "vx_widen_data.h" + +#define WT uint64_t +#define NT uint32_t +#define NAME mul +#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) +#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) + +DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, NAME) + +#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \ + RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N) + +#include "vx_widen_vx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h index 290d8a4b5d4..998c05961ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h @@ -30,6 +30,7 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \ #define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \ - DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \ + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, mul) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h index 7359f0bc85d..5b49083abe7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h @@ -37,6 +37,7 @@ DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add) DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub) +DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul) DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { { @@ -116,4 +117,43 @@ DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, sub)[] = { }, }; +DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, mul)[] = { + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 9, 9, 9, 9, + }, + /* rs1 */ + 2147483647, + /* expect */ + { + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 4294967294, 4294967294, 4294967294, 4294967294, + 19327352823ull, 19327352823ull, 19327352823ull, 19327352823ull, + }, + }, + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull, + }, + /* rs1 */ + 4294967295, + /* expect */ + { + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 0, 0, 0, 0, + 18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull, + 18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull, + }, + }, +}; + #endif