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Fri, 12 Sep 2025 07:22:53 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 4911gmsk3m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Sep 2025 07:22:53 +0000 Received: from smtpav01.fra02v.mail.ibm.com (smtpav01.fra02v.mail.ibm.com [10.20.54.100]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 58C7MnQO56361224 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 12 Sep 2025 07:22:49 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9B1D020040; Fri, 12 Sep 2025 07:22:49 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 65D062004D; Fri, 12 Sep 2025 07:22:48 +0000 (GMT) Received: from li-4c4c4544-0036-3810-8050-b5c04f423534.in.ibm.com (unknown [9.109.217.10]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 12 Sep 2025 07:22:48 +0000 (GMT) From: Avinash Jayakar To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, jskumari@linux.ibm.com Subject: [PATCH v4] rs6000: Use vector addition when left shifting by 1[PR119702] Date: Fri, 12 Sep 2025 12:52:47 +0530 Message-ID: <20250912072247.19751-1-avinashd@linux.ibm.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: P1EbyTxgGn-e9cKvf64s7ALsCF1BsDvr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDIzNSBTYWx0ZWRfX6+sfjwZCxnNE Hg2NciO3B4Udj8uBvEjw7Y3mTcnkN/hiuEP1RSl2Y/ohXOCdwqj0L+17I3G1WjmdPU/h3XmC530 XR4SyzO91AT74O2xSlWvON1JgDBey41fwh7wrdPdjqI30xRdQAAFxL7/at6Feqwn0yP34MxoaKm 2dZwSfOfuJ6G9ult5X57+K3eKvjBG9dyqBCRBHPWa/aMIWm5ipSeRzhGj/vxdV6hwr7y7J58lRY xQEsFziMk+gQS4LnFi/xI27QQVyOt4dIijbbqEmhjczMD7KQJZdkY+sZkJCp9qx+AG/3sBwTWaC W/TAujAe0P1vHa5evXosW8xLF+8GI5Q+zFrBOuQqNH5MXW2jbqQUI2g6pVGAEcOShgpvfFIY703 g3VEHbnR X-Proofpoint-GUID: P1EbyTxgGn-e9cKvf64s7ALsCF1BsDvr X-Authority-Analysis: v=2.4 cv=F59XdrhN c=1 sm=1 tr=0 ts=68c3ca4e cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=_yZUpEu_CqeDjeUINowA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-12_02,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060235 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Hi, Following is version 4 of the patch proposed for master to fix PR119702. This patch has been bootstrapped and regtested on powerpc64le-linux. Kindly review the patch. Thanks and regards, Avinash Jayakar Changes from v3: 1. Add author information before changelog. 2. Right placement of PR target/119702. 3. Added new test to check multiply by 2 generates vadd insn. Changes from v2: 1. Indentation fixes in the commit message 2. define_insn has the name *altivec_vsl_const_1 3. Iterate starting from 0 for checking vector constant = 1 and fixed source code formatting for the for loop. 4. Removed unused macro in pr119702-1.c test file Changes from v1: 1. Use define_insn instead of define_expand to recognize left shift by constant 1 and generate add instruction. 2. Updated test cases to cover integer types from byte, half- word, word and double word. rs6000: Use vector addition when left shifting by 1[PR119702] Whenever a vector of integers is left shifted by a constant value 1, gcc generates the following code for powerpc64le target: vspltisw 0,1 vsld 2,2,0 Instead the following code can be generated which is more efficient: vaddudm 2,2,2 This patch adds a pattern in altivec.md to recognize a vector left shift by a constant value, and generates an add instruction if constant is 1. Added the pattern in altivec.md to recognize a vector left shift by a constant value, and generate add instructions if constant is 1. Added a predicate in predicates.md to recognize if the rtl node is a uniform constant vector with value 1. Two test files have been added 1. Check if left shift by 1 is converted to vadd instructions for byte, half-word, word, and double-word. 2. Check the same but for multiply by 2. 2025-09-12 Avinash Jayakar gcc/ChangeLog: PR target/119702 * config/rs6000/altivec.md (*altivec_vsl_const_1): recognize << 1 and replace with vadd insn. * config/rs6000/predicates.md (vector_constant_1): predicate to check vector constant of all 1. gcc/testsuite/ChangeLog: PR target/119702 * gcc.target/powerpc/pr119702-1.c: New test * gcc.target/powerpc/pr119702-2.c: New test --- gcc/config/rs6000/altivec.md | 8 +++ gcc/config/rs6000/predicates.md | 11 ++++ gcc/testsuite/gcc.target/powerpc/pr119702-1.c | 53 +++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr119702-2.c | 53 +++++++++++++++++++ 4 files changed, 125 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr119702-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr119702-2.c diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 7edc288a656..7621f5c4f0a 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2107,6 +2107,14 @@ "vsrv %0,%1,%2" [(set_attr "type" "vecsimple")]) +(define_insn "*altivec_vsl_const_1" + [(set (match_operand:VI2 0 "register_operand" "=v") + (ashift:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "vector_constant_1" "")))] + "" + "vaddum %0,%1,%1" +) + (define_insn "*altivec_vsl" [(set (match_operand:VI2 0 "register_operand" "=v") (ashift:VI2 (match_operand:VI2 1 "register_operand" "v") diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 647e89afb6a..7a9c7df84ad 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -924,6 +924,17 @@ } }) +(define_predicate "vector_constant_1" + (match_code "const_vector") +{ + unsigned nunits = GET_MODE_NUNITS (mode), i; + for (i = 0; i < nunits; i++) + if (INTVAL (CONST_VECTOR_ELT(op, i)) != 1) + return 0; + + return 1; +}) + ;; Return 1 if operand is 0.0. (define_predicate "zero_fp_constant" (and (match_code "const_double") diff --git a/gcc/testsuite/gcc.target/powerpc/pr119702-1.c b/gcc/testsuite/gcc.target/powerpc/pr119702-1.c new file mode 100644 index 00000000000..3f292cde9a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr119702-1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +#include + +void lshift1_64(uint64_t *a) { + a[0] <<= 1; + a[1] <<= 1; +} + +void lshift1_32(unsigned int *a) { + a[0] <<= 1; + a[1] <<= 1; + a[2] <<= 1; + a[3] <<= 1; +} + +void lshift1_16(uint16_t *a) { + a[0] <<= 1; + a[1] <<= 1; + a[2] <<= 1; + a[3] <<= 1; + a[4] <<= 1; + a[5] <<= 1; + a[6] <<= 1; + a[7] <<= 1; +} + +void lshift1_8(uint8_t *a) { + a[0] <<= 1; + a[1] <<= 1; + a[2] <<= 1; + a[3] <<= 1; + a[4] <<= 1; + a[5] <<= 1; + a[6] <<= 1; + a[7] <<= 1; + a[8] <<= 1; + a[9] <<= 1; + a[10] <<= 1; + a[11] <<= 1; + a[12] <<= 1; + a[13] <<= 1; + a[14] <<= 1; + a[15] <<= 1; +} + + +/* { dg-final { scan-assembler-times {\mvaddudm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvadduwm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvadduhm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvaddubm\M} 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/pr119702-2.c b/gcc/testsuite/gcc.target/powerpc/pr119702-2.c new file mode 100644 index 00000000000..f1c1b8b86e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr119702-2.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +#include + +void lshift1_64(uint64_t *a) { + a[0] *= 2; + a[1] *= 2; +} + +void lshift1_32(unsigned int *a) { + a[0] *= 2; + a[1] *= 2; + a[2] *= 2; + a[3] *= 2; +} + +void lshift1_16(uint16_t *a) { + a[0] *= 2; + a[1] *= 2; + a[2] *= 2; + a[3] *= 2; + a[4] *= 2; + a[5] *= 2; + a[6] *= 2; + a[7] *= 2; +} + +void lshift1_8(uint8_t *a) { + a[0] *= 2; + a[1] *= 2; + a[2] *= 2; + a[3] *= 2; + a[4] *= 2; + a[5] *= 2; + a[6] *= 2; + a[7] *= 2; + a[8] *= 2; + a[9] *= 2; + a[10] *= 2; + a[11] *= 2; + a[12] *= 2; + a[13] *= 2; + a[14] *= 2; + a[15] *= 2; +} + + +/* { dg-final { scan-assembler-times {\mvaddudm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvadduwm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvadduhm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvaddubm\M} 1 } } */ +