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Lu" X-Patchwork-Id: 39668 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0FE55389365C; Thu, 18 Jun 2020 13:20:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0FE55389365C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1592486418; bh=XVj3ySdOZ0rmlObsVhZMj6i/KIg8mrbElthAPytGBX8=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=mabhy1FNG8CoELBpCQlw8yyReKeT+8qCiEE+s7FA6elYcA7g4LBOyv+xnAa2vH2SV i4/mp744ZQcjQfve93Qt1uxsJVQE9JGvdGUzmpdl2D7+X7vTQ++aw9pv+R/9jsJzUj rviD5g1/05jFXphU7DxP9Zg2TweyynSOcDZczcw8= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id 98BA4388E836 for ; Thu, 18 Jun 2020 13:20:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 98BA4388E836 Received: by mail-pl1-x644.google.com with SMTP id g12so2420992pll.10 for ; Thu, 18 Jun 2020 06:20:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=XVj3ySdOZ0rmlObsVhZMj6i/KIg8mrbElthAPytGBX8=; b=IoHc/vCPqnOjOSUJrW+cyf/86Pf0kci5qCmhuK+vJ2oFGSSAM4vSE+lvEctoL7A+YJ duucY9whjiCM8HA+URewF+T1QXgSPjJ9Qa418f5Jn9zB1gflvY6m6OCNIpasiEWw796L P5ozoTQQQrqZnGe1ZeCbuwObL9sTlLVThBdzK6H5fTQdT/YZCl2uCotcS4onP1OMVT/J jn6rAo56stL5+lDRjlOByFRQSH7E+GeT9oyLAUwJEyZr5ecrr1aqtht2Ox9e4Qg2PUfd UYjYR6MRVN/Gvh3aOXzO/acbYS1b8FxImmeLBIJSU/IxU3i14wTQXUuvKG/+VQ+Ntmws oufw== X-Gm-Message-State: AOAM5300ScafOtekkWz6z/8X6v5Loo2GKjaCPuS0u9ApHZu/UX1zS2/x emzgygK3EaHZVoEBIX/A0juOOp20 X-Google-Smtp-Source: ABdhPJxlCN3CxHNKJtNmZqfoHenSN9SUcdZVATtZ8rLZ2simkpsWsH6tKl0NNnm9qBVh+wQYPUDf3g== X-Received: by 2002:a17:90a:5d85:: with SMTP id t5mr4424319pji.154.1592486414418; Thu, 18 Jun 2020 06:20:14 -0700 (PDT) Received: from gnu-gram-1.localdomain (c-69-181-90-243.hsd1.ca.comcast.net. [69.181.90.243]) by smtp.gmail.com with ESMTPSA id p12sm2727400pgk.40.2020.06.18.06.20.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 06:20:13 -0700 (PDT) Received: from gnu-gram-1.localdomain (localhost [IPv6:::1]) by gnu-gram-1.localdomain (Postfix) with ESMTP id E1A7EE003F for ; Thu, 18 Jun 2020 06:20:12 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH] x86: Update F16C detection [BZ #26133] Date: Thu, 18 Jun 2020 06:20:12 -0700 Message-Id: <20200618132012.936532-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Libc-alpha" From: "H.J. Lu" Reply-To: "H.J. Lu" Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" Since F16C requires AVX, set F16C usable only when AVX is usable. --- sysdeps/x86/cpu-features.c | 4 ++++ sysdeps/x86/cpu-features.h | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 489c370348..f873b55e8d 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -153,6 +153,10 @@ get_common_indices (struct cpu_features *cpu_features, if (CPU_FEATURES_CPU_P (cpu_features, XOP)) cpu_features->feature[index_arch_XOP_Usable] |= bit_arch_XOP_Usable; + /* Determine if F16C is usable. */ + if (CPU_FEATURES_CPU_P (cpu_features, F16C)) + cpu_features->feature[index_arch_F16C_Usable] + |= bit_arch_F16C_Usable; } /* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index de20044417..969c61773f 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -145,6 +145,7 @@ extern const struct cpu_features *__get_cpu_features (void) #define bit_arch_XSAVEC_Usable (1u << 22) #define bit_arch_AVX512_VP2INTERSECT_Usable (1u << 23) #define bit_arch_AVX512_BF16_Usable (1u << 24) +#define bit_arch_F16C_Usable (1u << 25) #define index_arch_AVX_Usable FEATURE_INDEX_1 #define index_arch_AVX2_Usable FEATURE_INDEX_1 @@ -171,6 +172,7 @@ extern const struct cpu_features *__get_cpu_features (void) #define index_arch_XSAVEC_Usable FEATURE_INDEX_1 #define index_arch_AVX512_VP2INTERSECT_Usable FEATURE_INDEX_1 #define index_arch_AVX512_BF16_Usable FEATURE_INDEX_1 +#define index_arch_F16C_Usable FEATURE_INDEX_1 /* Unused. Compiler will optimize them out. */ #define bit_arch_SSE3_Usable (1u << 0) @@ -184,7 +186,6 @@ extern const struct cpu_features *__get_cpu_features (void) #define bit_arch_AES_Usable (1u << 0) #define bit_arch_XSAVE_Usable (1u << 0) #define bit_arch_OSXSAVE_Usable (1u << 0) -#define bit_arch_F16C_Usable (1u << 0) #define bit_arch_RDRAND_Usable (1u << 0) #define bit_arch_FPU_Usable (1u << 0) #define bit_arch_TSC_Usable (1u << 0) @@ -241,7 +242,6 @@ extern const struct cpu_features *__get_cpu_features (void) #define index_arch_AES_Usable FEATURE_INDEX_1 #define index_arch_XSAVE_Usable FEATURE_INDEX_1 #define index_arch_OSXSAVE_Usable FEATURE_INDEX_1 -#define index_arch_F16C_Usable FEATURE_INDEX_1 #define index_arch_RDRAND_Usable FEATURE_INDEX_1 #define index_arch_FPU_Usable FEATURE_INDEX_1 #define index_arch_TSC_Usable FEATURE_INDEX_1 @@ -301,7 +301,7 @@ extern const struct cpu_features *__get_cpu_features (void) #define need_arch_feature_XSAVE 0 #define need_arch_feature_OSXSAVE 0 #define need_arch_feature_AVX 1 -#define need_arch_feature_F16C 0 +#define need_arch_feature_F16C 1 #define need_arch_feature_RDRAND 0 /* EDX. */