From patchwork Tue Nov 16 17:06:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 47778 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 87250385AC1A for ; Tue, 16 Nov 2021 17:07:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 87250385AC1A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1637082453; bh=TlDr0MmXSRKIalBoEOS0/nmP1ykxAEUcij7BIEEiRXg=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=xAeu91qT2bwbSMZpWIOGVUmRidE0t+FCm/ZoolwAiQOfOIHLSM2wGcxbE8mSkysxN 5cl64yMNP6mohjNiIXSAaNh5xJe6Y4AHXhq5W37UkALjT6lt18U1w0bBN08KvltQeW Dz4aJPf1/LAkrl4bfS1OjxgYoMbon7aRFFgEjmK0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 9C7BA385B833 for ; Tue, 16 Nov 2021 17:06:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9C7BA385B833 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1AGFntNY009658 for ; Tue, 16 Nov 2021 17:06:58 GMT Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com with ESMTP id 3ccfmqhxr6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 16 Nov 2021 17:06:58 +0000 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 1AGH4RJn028265 for ; Tue, 16 Nov 2021 17:06:57 GMT Received: from b03cxnp07027.gho.boulder.ibm.com (b03cxnp07027.gho.boulder.ibm.com [9.17.130.14]) by ppma03dal.us.ibm.com with ESMTP id 3ca50beunk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 16 Nov 2021 17:06:57 +0000 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp07027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1AGH6u8m50397566 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 16 Nov 2021 17:06:56 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 54DFA78069 for ; Tue, 16 Nov 2021 17:06:56 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 406BE78066 for ; Tue, 16 Nov 2021 17:06:56 +0000 (GMT) Received: from [9.211.84.243] (unknown [9.211.84.243]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP for ; Tue, 16 Nov 2021 17:06:56 +0000 (GMT) Message-ID: Date: Tue, 16 Nov 2021 11:06:55 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 To: GCC Patches Subject: [PATCH] rs6000: Add [power6-64] stanza to new builtin support X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 283Mqw6YJ4ulb06XJ-dX2Og0LZyV8Hwu X-Proofpoint-GUID: 283Mqw6YJ4ulb06XJ-dX2Og0LZyV8Hwu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-16_03,2021-11-16_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 spamscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111160084 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Bill Schmidt via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: wschmidt@linux.ibm.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi! While reviewing the recent 32-bit changes for the new builtin infrastructure, I realized that I needed another stanza to represent builtins requiring both -mcpu=power6 and -mpowerpc64. (There's only one of these, but nonetheless...) So this patch adds that support in the same fashion as [power7-64] and [power9-64]. Bootstrapped and tested on powerpc64le-linux-gnu, and on powerpc64-linux-gnu with -m32/-m64. Is this okay for trunk? Thanks! Bill 2021-11-16 Bill Schmidt gcc/ * config/rs6000/rs6000-builtin-new.def: Add power6-64 stanza. Move CMPB to power6-64 stanza. * config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin): Handle ENB_P6_64 case. (rs6000_new_builtin_is_supported): Likewise. (rs6000_expand_new_builtin): Likewise. (rs6000_init_builtins): Likewise. * config/rs6000/rs6000-gen-builtins.c (bif_stanza): Add BSTZ_P6_64. (stanza_map): Add entry mapping power6-64 to BSTZ_P6_64. (enable_string): Add "ENB_P6_64". (write_decls): Add ENB_P6_64 to bif_enable enum. --- gcc/config/rs6000/rs6000-builtin-new.def | 9 ++++++--- gcc/config/rs6000/rs6000-call.c | 10 ++++++++++ gcc/config/rs6000/rs6000-gen-builtins.c | 4 ++++ 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def index 1dd8f6b40b2..58dfce1ca37 100644 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ b/gcc/config/rs6000/rs6000-builtin-new.def @@ -266,13 +266,16 @@ ; Power6 builtins (ISA 2.05). [power6] - const signed long __builtin_p6_cmpb (signed long, signed long); - CMPB cmpbdi3 {} - const signed int __builtin_p6_cmpb_32 (signed int, signed int); CMPB_32 cmpbsi3 {} +; Power6 builtins requiring 64-bit GPRs (even with 32-bit addressing). +[power6-64] + const signed long __builtin_p6_cmpb (signed long, signed long); + CMPB cmpbdi3 {} + + ; AltiVec builtins. [altivec] const vsc __builtin_altivec_abs_v16qi (vsc); diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 83e1abb6118..822a9736591 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -11919,6 +11919,10 @@ rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode) case ENB_P6: error ("%qs requires the %qs option", name, "-mcpu=power6"); break; + case ENB_P6_64: + error ("%qs requires the %qs option and either the %qs or %qs option", + name, "-mcpu=power6", "-m64", "-mpowerpc64"); + break; case ENB_ALTIVEC: error ("%qs requires the %qs option", name, "-maltivec"); break; @@ -13346,6 +13350,8 @@ rs6000_new_builtin_is_supported (enum rs6000_gen_builtins fncode) return TARGET_POPCNTB; case ENB_P6: return TARGET_CMPB; + case ENB_P6_64: + return TARGET_CMPB && TARGET_POWERPC64; case ENB_P7: return TARGET_POPCNTD; case ENB_P7_64: @@ -15697,6 +15703,8 @@ rs6000_expand_new_builtin (tree exp, rtx target, if (!(e == ENB_ALWAYS || (e == ENB_P5 && TARGET_POPCNTB) || (e == ENB_P6 && TARGET_CMPB) + || (e == ENB_P6_64 && TARGET_CMPB + && TARGET_POWERPC64) || (e == ENB_ALTIVEC && TARGET_ALTIVEC) || (e == ENB_CELL && TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL) @@ -16419,6 +16427,8 @@ rs6000_init_builtins (void) continue; if (e == ENB_P6 && !TARGET_CMPB) continue; + if (e == ENB_P6_64 && !(TARGET_CMPB && TARGET_POWERPC64)) + continue; if (e == ENB_ALTIVEC && !TARGET_ALTIVEC) continue; if (e == ENB_VSX && !TARGET_VSX) diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c index 1655a2fd765..4ce83bd2290 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.c +++ b/gcc/config/rs6000/rs6000-gen-builtins.c @@ -212,6 +212,7 @@ enum bif_stanza BSTZ_ALWAYS, BSTZ_P5, BSTZ_P6, + BSTZ_P6_64, BSTZ_ALTIVEC, BSTZ_CELL, BSTZ_VSX, @@ -245,6 +246,7 @@ static stanza_entry stanza_map[NUMBIFSTANZAS] = { "always", BSTZ_ALWAYS }, { "power5", BSTZ_P5 }, { "power6", BSTZ_P6 }, + { "power6-64", BSTZ_P6_64 }, { "altivec", BSTZ_ALTIVEC }, { "cell", BSTZ_CELL }, { "vsx", BSTZ_VSX }, @@ -269,6 +271,7 @@ static const char *enable_string[NUMBIFSTANZAS] = "ENB_ALWAYS", "ENB_P5", "ENB_P6", + "ENB_P6_64", "ENB_ALTIVEC", "ENB_CELL", "ENB_VSX", @@ -2227,6 +2230,7 @@ write_decls (void) fprintf (header_file, " ENB_ALWAYS,\n"); fprintf (header_file, " ENB_P5,\n"); fprintf (header_file, " ENB_P6,\n"); + fprintf (header_file, " ENB_P6_64,\n"); fprintf (header_file, " ENB_ALTIVEC,\n"); fprintf (header_file, " ENB_CELL,\n"); fprintf (header_file, " ENB_VSX,\n");