From patchwork Thu Nov 11 14:10:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47466 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 160BF385AC2E for ; Thu, 11 Nov 2021 14:13:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by sourceware.org (Postfix) with ESMTPS id 37C853857823 for ; Thu, 11 Nov 2021 14:10:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 37C853857823 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x22d.google.com with SMTP id h11so12237098ljk.1 for ; Thu, 11 Nov 2021 06:10:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Z4aYaIgpj6TniDsVoyYPXaMCCvyBY06ipmVaZ2BHeY=; b=pdcjl3Ij/hU6t6l6Gfqh9YiDqWcvGWKhIp1NnPENHzurqkJ3TvR8ysZKI+LGQADTd8 DW7rQ3r4lRvmrgYNu92Fw1IB53F/JyUKaDe3Vj8Ihy05bOFrxKsYbbY+C3Xcf+GACOOw Kqfqy2uCl1WMDXtNlPumU5HKGtEb2Kby+dKURrpfFODtjzDoIvwTw8HCyyyA4KGfbuqJ 22eXgybO9lj9ssicQWnpC+t0KwyQR0b5x16bWGUIhFKPouwZaNDVUtUROQus3hESZ+2z S2VeSHrvfYUDHr7RMjUE3t7v+coDMQMJ1+tomDUa61NMVzyeJr1bR61eG5l/7sHCG6ur bNyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2Z4aYaIgpj6TniDsVoyYPXaMCCvyBY06ipmVaZ2BHeY=; b=AB/cG/8GvC9ligwc3N2D+z46eQnaEc5LqktY+XCLIyGud+ce3L6R254Fn8jMWb+fjI 8r+v91a70xLMklzc4KgeBGesR5KG42MDhaou3NHVJWSRYKRoG/vOLdSfNWc2nzOCo7/B sE6EgfxW3sC9N8gXi+1uARM2gJBFCOOPN/uqJHXDseOL+4izwk2Smn8ITyNyxTG+bez3 g4tYphugPKN4TX9jY6IVZ5izoUE81Su7VWO32tMPDq4bg2JhU++Mg62JPn//R+aV5EXQ XP7OnSq98SFBxA4M8gCzr8FUFO8nktJ41Qwj4jFkm/iARNkkXxW3SIHGjVsRreSruPZz 3cMA== X-Gm-Message-State: AOAM5311doDrG9L3JfW9kg6bw+FZAEYegGdBR4lXiL0bwzTOcY3bnlmk kMyoQ9fb0ZrdhbTX7N8mC1Tb/mDPXCXi+bwG X-Google-Smtp-Source: ABdhPJxZTYQPHCKzwCrov1CTPjZgj6SvtyUct9Zcec42dOt/xzjtFKZWixE+ivMQTyxLM/epBIw0rA== X-Received: by 2002:a2e:9b41:: with SMTP id o1mr7223770ljj.499.1636639824804; Thu, 11 Nov 2021 06:10:24 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:24 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 1/8] bswap: synthesize HImode bswap from SImode or DImode Date: Thu, 11 Nov 2021 15:10:13 +0100 Message-Id: <20211111141020.2738001-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The RISC-V Zbb extension adds an XLEN (i.e. SImode for rv32, DImode for rv64) bswap instruction (rev8). While, with the current master, SImode is synthesized correctly from DImode, HImode is not. This change adds an appropriate expansion for a HImode bswap, if a wider bswap is available. Without this change, the following rv64gc_zbb code is generated for __builtin_bswap16(): slliw a5,a0,8 zext.h a0,a0 srliw a0,a0,8 or a0,a5,a0 sext.h a0,a0 // this is a 16bit sign-extension following // the byteswap (e.g. on a 'short' function // return). After this change, a bswap (rev8) is used and any extensions are combined into the shift-right: rev8 a0,a0 srai a0,a0,48 // the sign-extension is combined into the // shift; a srli is emitted otherwise... gcc/ChangeLog: * optabs.c (expand_unop): support expanding a HImode bswap using SImode or DImode, followed by a shift. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-bswap.c: New test. Signed-off-by: Philipp Tomsich --- gcc/optabs.c | 6 ++++++ gcc/testsuite/gcc.target/riscv/zbb-bswap.c | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-bswap.c diff --git a/gcc/optabs.c b/gcc/optabs.c index 019bbb62882..7a3ffbe4525 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -3307,6 +3307,12 @@ expand_unop (machine_mode mode, optab unoptab, rtx op0, rtx target, return temp; } + /* If we are missing a HImode BSWAP, but have one for SImode or + DImode, use a BSWAP followed by a SHIFT. */ + temp = widen_bswap (as_a (mode), op0, target); + if (temp) + return temp; + last = get_last_insn (); temp1 = expand_binop (mode, ashl_optab, op0, diff --git a/gcc/testsuite/gcc.target/riscv/zbb-bswap.c b/gcc/testsuite/gcc.target/riscv/zbb-bswap.c new file mode 100644 index 00000000000..6ee27d9f47a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-bswap.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */ + +unsigned long +func64 (unsigned long i) +{ + return __builtin_bswap64(i); +} + +unsigned int +func32 (unsigned int i) +{ + return __builtin_bswap32(i); +} + +unsigned short +func16 (unsigned short i) +{ + return __builtin_bswap16(i); +} + +/* { dg-final { scan-assembler-times "rev8" 3 } } */ From patchwork Thu Nov 11 14:10:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47468 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B7785385AC1D for ; Thu, 11 Nov 2021 14:14:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by sourceware.org (Postfix) with ESMTPS id E7C1A3857C64 for ; Thu, 11 Nov 2021 14:10:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E7C1A3857C64 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x132.google.com with SMTP id b1so8611121lfs.13 for ; Thu, 11 Nov 2021 06:10:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BFD6ISME8C+orS+3J2LXk3cTm00Lpf2p4Bi/zPt2h4c=; b=NRB2u1i4DKBD6h5U5ddpT4+LRU5T6zNTfrZUDkr5oOnkmKsMu9N58Li5DAQdybif1s F9oAVyhVrcdvS2QdtqkkOU1BbMl316g8FsYU/ImqSwBZL61dJI7RYleQ54ry1NNQGr3M HEubQh2L6zo7Uj1mDbCHi3B+S98WuzN/m71Rsaar9GKJ4yfXkN3uhc/panCmS9r5Mlfy L9julM089WE2VmXnktFFixtK/RKFGgHHd1dFvcanXSlAKBaX/iRhVatISLDT29TY4d+E WuCSEQWDNdCxWzXAXTBBT3MNL4LEOeH7BVnk5pCjwPVnBFM1Fhpd+EzV8FrXOY9NvPIm piKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BFD6ISME8C+orS+3J2LXk3cTm00Lpf2p4Bi/zPt2h4c=; b=ct/Fo7CEuWAI9JBNTTUTFsChVBpS1fw3enksZIYI2fgUV8zn4/yw58A/MUZ5nXt9hQ 2uV5gPcmRntkfgSSOrW7S8lZMMjhHsaDSdPS1CMvUQ6T1x1gNl91ZKtiV+g9z7lw4Zro YZpyN68ndmlSvpDyiVKwhsyykCSpCvnCzGjXBD5o/JcwZj5VApEpWitTQqU+Ojbu26rN XNNI5JBkrlsysfdwf0jsz2riAhQZWQjganCyO7C+spUKJuclQLZRie3VuI/CHOIDif7S KZ7IE8cbv7U7mnnVVkh3/ejqwt7RqU2HzTfhxhSdXwAvCDSO4Iwnu0n486icnggVF4Mg YEnA== X-Gm-Message-State: AOAM532e4LeZgpyqX9Cll6jvLQ2n+LsePU9sayKGf7XmhXp00N0yp33r 7bcSaA0mFGB4WUo0GYCKdacEXLFRjcAYru9u X-Google-Smtp-Source: ABdhPJyCXpBMQ2ZBhaTn7y+vX79CWjIxyM9SgWldT/YWvAJvlaBBUJ1xB8OOYzzky+tuFLQDpaM1jA== X-Received: by 2002:a05:6512:2611:: with SMTP id bt17mr6648779lfb.189.1636639825655; Thu, 11 Nov 2021 06:10:25 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:25 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 2/8] RISC-V: costs: handle BSWAP Date: Thu, 11 Nov 2021 15:10:14 +0100 Message-Id: <20211111141020.2738001-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The BSWAP operation is not handled in rtx_costs. Add it. gcc/ChangeLog: * config/riscv/riscv.c (rtx_costs): Add BSWAP. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index c77b0322869..8480cf09294 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -2131,6 +2131,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND); return false; + case BSWAP: + if (TARGET_ZBB) + { + *total = COSTS_N_INSNS (1); + return true; + } + return false; + case FLOAT: case UNSIGNED_FLOAT: case FIX: From patchwork Thu Nov 11 14:10:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47469 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 30C2B385B805 for ; Thu, 11 Nov 2021 14:14:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by sourceware.org (Postfix) with ESMTPS id C422B3857C43 for ; Thu, 11 Nov 2021 14:10:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C422B3857C43 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x22a.google.com with SMTP id e9so12171213ljl.5 for ; Thu, 11 Nov 2021 06:10:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ffzBkEz8pHEWlkeWXQL89ffmXABHe5GflU+Fi4bXXv4=; b=VLFHiVqE/sYi/w5LOHqW//QrWXTwOZ8W6Mszyd23YzwePkGty1esDwmXdjee9ePgiJ o0imRRr4SQ8fwHWsej7+uGPxY2tR5mwKGz22xqYU5EA6Nx4FH5CDZ3mRpUwSjmp/kys3 Cm587bkX/TznHuV0Cb+AZlcPA3KYje8vMeaR7DofgF2utxBGDWV7rk9MLQ1WvheTbWQg XURj1dVvyiE2GAIfV9LUV4ow47cBsamsGcNHs3e1aLDpUctkVGlspH6Q0sWuK4kYp0+m w4QYC9vYX5+vWc9/ORN0sgrhB5TVWzJh7fU1q4sizZ95da77lNkkUFPG75IO3WvQ5TQ4 kT8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ffzBkEz8pHEWlkeWXQL89ffmXABHe5GflU+Fi4bXXv4=; b=FP7MRbVzI0bDryCferMeQSL0XlYIH/nMHgaUEtqRqtRZE9xSxDARI+5EATixrXnLWo X29zcftlV7kGTWTT5yihXAg1rqjNbTGB3fnJ5nsH9p9AVzVL81dnfqinZOzptg0V+49G lzHS0F5VEor8eFUdNzVNxOG+DHVA6FPTw8etSMalbD9Xa0TZJsxmQzKhDeENnhjRahgy 3DViETa1KWN+OL0m6eiXD3QiU0jcIYGMVqEz3N6P/shSRrxMatMz0wh8XDW4QylqGks5 C7H0btxS8xly1RR/Z7TcIwFvpxO8h+H7Bzp84jESMEnx6cSX8zBVUGTWX54yHCXvyVSr it8g== X-Gm-Message-State: AOAM531gyRjK018Os8RizoLML0pnnKlGuxn5Kr+1zZpyhu3vX/WP10qU qBCs6YcfzNjAQtRsORTQq7DZb2wxQgs6IHjC X-Google-Smtp-Source: ABdhPJzHRKDSo8eHbjA5OxvJ1coSvpYWBDYmbicZ2mFbdsS/wu8xagc4grxqKSYWqkPqQfVMT5JEHg== X-Received: by 2002:a05:651c:211c:: with SMTP id a28mr7545319ljq.323.1636639826342; Thu, 11 Nov 2021 06:10:26 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:26 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 3/8] RISC-V: costs: support shift-and-add in strength-reduction Date: Thu, 11 Nov 2021 15:10:15 +0100 Message-Id: <20211111141020.2738001-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The strength-reduction implementation in expmed.c will assess the profitability of using shift-and-add using a RTL expression that wraps a MULT (with a power-of-2) in a PLUS. Unless the RISC-V rtx_costs function recognizes this as expressing a sh[123]add instruction, we will return an inflated cost, thus defeating the optimization. This change adds the necessary idiom recognition to provide an accurate cost for this for of expressing sh[123]add. Instead on expanding to li a5,200 mulw a0,a5,a0 with this change, the expression 'a * 200' is sythesized as: sh2add a0,a0,a0 // *5 = a + 4 * a sh2add a0,a0,a0 // *5 = a + 4 * a slli a0,a0,3 // *8 gcc/ChangeLog: * config/riscv/riscv.c (riscv_rtx_costs): Recognize shNadd, if expressed as a plus and multiplication with a power-of-2. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 8480cf09294..dff4e370471 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -2020,6 +2020,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (1); return true; } + /* Before strength-reduction, the shNadd can be expressed as the addition + of a multiplication with a power-of-two. If this case is not handled, + the strength-reduction in expmed.c will calculate an inflated cost. */ + if (TARGET_ZBA + && ((!TARGET_64BIT && (mode == SImode)) || + (TARGET_64BIT && (mode == DImode))) + && (GET_CODE (XEXP (x, 0)) == MULT) + && REG_P (XEXP (XEXP (x, 0), 0)) + && CONST_INT_P (XEXP (XEXP (x, 0), 1)) + && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3)) + { + *total = COSTS_N_INSNS (1); + return true; + } /* shNadd.uw pattern for zba. [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI From patchwork Thu Nov 11 14:10:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47470 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D810385AC32 for ; Thu, 11 Nov 2021 14:15:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by sourceware.org (Postfix) with ESMTPS id 69B303858017 for ; Thu, 11 Nov 2021 14:10:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 69B303858017 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x229.google.com with SMTP id 1so12218724ljv.2 for ; Thu, 11 Nov 2021 06:10:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=843mDBOJUKw0cLlTreo12MimvayYA+T/u2HDj5BuOhE=; b=KxkrCXW3LHifG9bD9gm7SJ91IvS+6B0peKefi9e+G0+Eeslu/swS9/gNfcZI9Jz7Ma 6B2QpbWZGvITQgOPJfomCQmTaDHSuEPIrxLEgnjdrqwYEBmQACRTCyLQkeyXDHC6+e/7 /Wz0/gDOCTE7euKwQbnhhtGbE9AYsYpaaQ4Sbcn4iZytc5MFEVwipcChjcdV7z3a39g7 IR4zCMBG0Z5jLoztIF6+U2AGM5O1DOeTPi/WZLvTvqkyKskas3+xc3UZBpXeGp/j1waC D5Htusluwkm8vIEnsgiohi7DWuonlt8noOw8+XZeSf0whDkr3psJI+LBti6c59Xyr74U KWeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=843mDBOJUKw0cLlTreo12MimvayYA+T/u2HDj5BuOhE=; b=uDdQKoOFoZWnu09VfuKrct9jjnwse2hONzcOS4rDHUJ1WKf2lY2yEuyzk8UieMYLCd AM+lC2oM1T0JakZva9oCemWQyTse8GPvxfn91PooG/KbKEfeJvUNYvOzJPC0BouHbSqz Fw7JjXaQ8gyF4K8NfksEx5lA5y0uDwhdW3foa3a404Do6swNznSuLTmOPRwVaDjj88fP basNsD9dSt+1+dyjBtH8tYziRlALk1RnVoRsTaYeytQKCpoWC2E9Iqf8TE84ABr1QA0t HLkemRW+W41fqP3IKEeWuJfSmYW8F9mEq8Z+Ewuvh6yyey26J2yAQAIjc0FQibsn7qbu Kykw== X-Gm-Message-State: AOAM531qjviqHGSMKFmFUAoQ8kFwn6LlNpueJ/vVweXzEeKHKJqf+IdG lcOO28gJu+KAekqGgQoIk5e5ZjlshSCQI2hb X-Google-Smtp-Source: ABdhPJw3n9ri6K1okmn/ysZM8rIiLMsv7wGRp07+6CabiXaMxgggUNBqhwmJ2hRqtvRI7/ypy1ucwg== X-Received: by 2002:a2e:814b:: with SMTP id t11mr7574213ljg.171.1636639827071; Thu, 11 Nov 2021 06:10:27 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:26 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 4/8] RISC-V: bitmanip: fix constant-loading for (1ULL << 31) in DImode Date: Thu, 11 Nov 2021 15:10:16 +0100 Message-Id: <20211111141020.2738001-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The SINGLE_BIT_MASK_OPERAND() is overly restrictive, triggering for bits above 31 only (to side-step any issues with the negative SImode value 0x80000000). This moves the special handling of this SImode value (i.e. the check for -2147483648) to riscv.c and relaxes the SINGLE_BIT_MASK_OPERAND() test. This changes the code-generation for loading (1ULL << 31) from: li a0,1 slli a0,a0,31 to: bseti a0,zero,31 gcc/ChangeLog: * config/riscv/riscv.c (riscv_build_integer_1): Rewrite value as -2147483648 for the single-bit case, when operating on 0x80000000 in SImode. * gcc/config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for any single-bit value, moving the special case for 0x80000000 to riscv_build_integer_1 (in riscv.c). Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.c | 9 +++++++++ gcc/config/riscv/riscv.h | 11 ++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index dff4e370471..4c30d4e521d 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -415,6 +415,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], /* Simply BSETI. */ codes[0].code = UNKNOWN; codes[0].value = value; + + /* RISC-V sign-extends all 32bit values that life in a 32bit + register. To avoid paradoxes, we thus need to use the + sign-extended (negative) representation for the value, if we + want to build 0x80000000 in SImode. This will then expand + to an ADDI/LI instruction. */ + if (mode == SImode && value == 0x80000000) + codes[0].value = -2147483648; + return 1; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 64287124735..abb121ddbea 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -526,13 +526,10 @@ enum reg_class (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) -/* If this is a single bit mask, then we can load it with bseti. But this - is not useful for any of the low 31 bits because we can use addi or lui - to load them. It is wrong for loading SImode 0x80000000 on rv64 because it - needs to be sign-extended. So we restrict this to the upper 32-bits - only. */ -#define SINGLE_BIT_MASK_OPERAND(VALUE) \ - (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32)) +/* If this is a single bit mask, then we can load it with bseti. Special + handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ +#define SINGLE_BIT_MASK_OPERAND(VALUE) \ + (pow2p_hwi (VALUE)) /* Stack layout; function entry, exit and calling. */ From patchwork Thu Nov 11 14:10:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47471 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 43D83385AC1D for ; Thu, 11 Nov 2021 14:15:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by sourceware.org (Postfix) with ESMTPS id 4FD1F3857C50 for ; Thu, 11 Nov 2021 14:10:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4FD1F3857C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12d.google.com with SMTP id l22so14470014lfg.7 for ; Thu, 11 Nov 2021 06:10:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Doc0iDwS3kurq11/jjg2jkQusuoaJvYFrHvFpr3aneA=; b=OH+ihJ0alSd7Vequr+9rcO1rx9q4ZtJ2Rw+orlig6B/ewZ5iWHILaLlytuyUM1Z0ij rN0SgXZC0X2wWo0FD+pM3qo+L9UG62lpaGgRa3FykDvqU0H99OYPumYozKq47026pJt0 zdZ6bdamC1UP11n9QKaclU6wrXvc4fOHyi+hblAWRtHxrBH4yJl8KCUejYUMGv3KK5Vu WBNwCM9TnIUVOqsoVrfIldSFzhOKG7mGp/jSE5zHV3acpKmkXlhXBYyC4X/WVgMnSbLx YYDMMmz08VbdhfFiBDsd7QyyAItEadknlQeqgrK1k059fw3KagfW40zoML8NLywiUT5m USvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Doc0iDwS3kurq11/jjg2jkQusuoaJvYFrHvFpr3aneA=; b=3kgAe0ZHrWct6JzDMQnkmgcWTfVTTGoPe+Or7vZTJVEnSPm5jt9FRVDu55KjTXF6Jz T6sdm7VOZxU1g+LHz7GkA1KlGnYv8B0j02fxQzAOTRIh5AqFy6ynAEubpLOoXz2z0HAL 2ldc//dxcw+4mPPH9cAC7UDOc6qGZFedHsDdRddosF16sMM5ilEseb1lR00+R0KST6Wb 3jhneVCRPTLdE5hFkxaEofaKAqQxMNnPaxzY019teUZyRIp31E7yKOflY2kAN+lc7+7z Ya/89xYvuRpLFBJL5+zVxRcgvTjWIe65a4BJ6HfEeaEvDVZsaSSuogy198M6hrm0oZW7 ZSLQ== X-Gm-Message-State: AOAM5314uziHmNt5gzmMzjN6+6Rph1ipC3i7Y2Zudjh+IgIqDuLLjbjf JArERzgq/4Tl2WTIhRIeTxjgL7zNtcLadyK4 X-Google-Smtp-Source: ABdhPJyDOROkiEnBNC1q0Y0XNDQxA71ay4PcmAy0RW0l5dL7VnH8hEm6i228tYJx4T9xlpommJmmAQ== X-Received: by 2002:a05:6512:3053:: with SMTP id b19mr6837884lfb.276.1636639827756; Thu, 11 Nov 2021 06:10:27 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:27 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 5/8] RISC-V: bitmanip: improvements to rotate instructions Date: Thu, 11 Nov 2021 15:10:17 +0100 Message-Id: <20211111141020.2738001-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This change improves rotate instructions (motivated by a review of the code generated for OpenSSL): rotate-left by a constant are synthesized using a rotate-right-immediate to avoid putting the shift-amount into a temporary; to do so, we allow either a register or an immediate for the expansion of rotl3 and then check if the shift-amount is a constant. Without these changes, the function unsigned int f(unsigned int a) { return (a << 2) | (a >> 30); } turns into li a5,2 rolw a0,a0,a5 while these changes give us: roriw a0,a0,30 gcc/ChangeLog: * config/riscv/bitmanip.md (rotlsi3, rotldi3, rotlsi3_sext): Synthesize rotate-left-by-immediate from a rotate-right insn. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/bitmanip.md | 39 ++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 59779b48f27..178d1ca0e4b 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -204,25 +204,52 @@ (define_insn "rotrsi3_sext" (define_insn "rotlsi3" [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r")))] + (match_operand:QI 2 "arith_operand" "rI")))] "TARGET_ZBB" - { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; } + { + /* If the rotate-amount is constant, let's synthesize using a + rotate-right-immediate instead of using a temporary. */ + + if (CONST_INT_P(operands[2])) { + operands[2] = GEN_INT(32 - INTVAL(operands[2])); + return TARGET_64BIT ? "roriw\t%0,%1,%2" : "rori\t%0,%1,%2"; + } + + return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; + } [(set_attr "type" "bitmanip")]) (define_insn "rotldi3" [(set (match_operand:DI 0 "register_operand" "=r") (rotate:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r")))] + (match_operand:QI 2 "arith_operand" "rI")))] "TARGET_64BIT && TARGET_ZBB" - "rol\t%0,%1,%2" + { + if (CONST_INT_P(operands[2])) { + operands[2] = GEN_INT(64 - INTVAL(operands[2])); + return "rori\t%0,%1,%2"; + } + + return "rol\t%0,%1,%2"; + } [(set_attr "type" "bitmanip")]) +;; Until we have improved REE to understand that sign-extending the result of +;; an implicitly sign-extending operation is redundant, we need an additional +;; pattern to gobble up the redundant sign-extension. (define_insn "rotlsi3_sext" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r"))))] + (match_operand:QI 2 "arith_operand" "rI"))))] "TARGET_64BIT && TARGET_ZBB" - "rolw\t%0,%1,%2" + { + if (CONST_INT_P(operands[2])) { + operands[2] = GEN_INT(32 - INTVAL(operands[2])); + return "roriw\t%0,%1,%2"; + } + + return "rolw\t%0,%1,%2"; + } [(set_attr "type" "bitmanip")]) (define_insn "bswap2" From patchwork Thu Nov 11 14:10:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47472 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9B600385AC1E for ; Thu, 11 Nov 2021 14:16:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by sourceware.org (Postfix) with ESMTPS id 44C653857C47 for ; Thu, 11 Nov 2021 14:10:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 44C653857C47 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x131.google.com with SMTP id l22so14470135lfg.7 for ; Thu, 11 Nov 2021 06:10:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+2URXdDrLiNkTCN+zizlI9W83wt65buglYHNyqTIYhk=; b=nus9c5YioWG33AXgTLVtHRP+UOuxadfxWLg+7aeEHULWmxitE9x4XktY/hb0m5QG53 PKwROUoEs1ivHwntZpx+JEs0+Lh7CVYKfMHmVn9kqgQurPhaK51GaL4+hZYvY0DeudR/ jvSzJAlGsttmaftykNHYDObS8foM8OYIeSLwd87/bp8EanIVmBF+0yb3jrdbLzX/LFD4 zLrFK8oEiqOhL4Z9B6Wkb6XbPMRm1mM4UiDTy74NUoFBUeM4dbKOCtmzYi3NFrUfHqi6 8GcBp9wtwPpdID202rNbFLSHCtfzBYq6UiTFnBchb2s52S7QImFZlXyEgIsAXFuZs0wH l75A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+2URXdDrLiNkTCN+zizlI9W83wt65buglYHNyqTIYhk=; b=LVmtfegKE7g6dEO1v4dHGGKObM2B0Jt5S+ugdWa2hkBbsHg318tYw1TPjc1+ubx6fb gd+PBLN1aA5uUGrPq/abq70ucef+s+t4uOd0Jgeqq+DgbnWRYaxs8UOTcFs+eVn8nnSC wDmuXhZji+82PJygB3OWxwIj75qARIEd9ZyNmyEcWm4Ewq/fpskVhQ4Fq7DmTTY5uwVs KEDtN1JKBOYTaOHBhEvxDPQtm52Qpx9GfFFpIB7gdY/nZh2pIjy0O7isS0B/XjGifCLt /RL2kGfl/JrkmBSGC6J0/gxojU4YWrFG+E49MkCI6qboo//405y6qsAd5ng4xcsiBBzW xJsw== X-Gm-Message-State: AOAM532ge94zWFJUwk+j5KRWBMT4pHdAurwzzmBYgEaHKkj2dvapoE4h 4jnhQECv85QejDMAA52TQ8wBw2IJsV4Os2EH X-Google-Smtp-Source: ABdhPJwLEnZMDlu0A4TuZJ5HHNCo711nk1BulAPBZ+J7fCBLs12SCYBWgis1xPb11nvDdV2Dvitr7w== X-Received: by 2002:a19:f242:: with SMTP id d2mr6883041lfk.516.1636639828764; Thu, 11 Nov 2021 06:10:28 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:28 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 6/8] RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" Date: Thu, 11 Nov 2021 15:10:18 +0100 Message-Id: <20211111141020.2738001-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Consider creating a polarity-reversed mask from a set-bit (i.e., if the bit is set, produce all-ones; otherwise: all-zeros). Using Zbb, this can be expressed as bexti, followed by an addi of minus-one. To enable the combiner to discover this opportunity, we need to split the canonical expression for "(a & (1 << BIT_NO)) ? 0 : -1" into a form combinable into bexti. Consider the function: long f(long a) { return (a & (1 << BIT_NO)) ? 0 : -1; } This produces the following sequence prior to this change: andi a0,a0,16 seqz a0,a0 neg a0,a0 ret Following this change, it results in: bexti a0,a0,4 addi a0,a0,-1 ret gcc/ChangeLog: * config/riscv/bitmanip.md: Add a splitter to generate polarity-reversed masks from a set bit using bexti + addi. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bexti.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/bitmanip.md | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 14 ++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bexti.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 178d1ca0e4b..9e10280e306 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -367,3 +367,16 @@ (define_insn "*bexti" "TARGET_ZBS" "bexti\t%0,%1,%2" [(set_attr "type" "bitmanip")]) + +;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 }) +;; using a bext(i) followed by an addi instruction. +;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1". +(define_split + [(set (match_operand:GPR 0 "register_operand") + (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand") + (const_int 1) + (match_operand 2)) + (const_int 0))))] + "TARGET_ZBB" + [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))]) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c new file mode 100644 index 00000000000..d02c3f7a98d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ + +/* bexti */ +#define BIT_NO 27 + +long +foo0 (long a) +{ + return (a & (1 << BIT_NO)) ? 0 : -1; +} + +/* { dg-final { scan-assembler "bexti" } } */ +/* { dg-final { scan-assembler "addi" } } */ From patchwork Thu Nov 11 14:10:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47473 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0815B3857C64 for ; Thu, 11 Nov 2021 14:16:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by sourceware.org (Postfix) with ESMTPS id 226413857823 for ; Thu, 11 Nov 2021 14:10:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 226413857823 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x231.google.com with SMTP id d11so12161092ljg.8 for ; Thu, 11 Nov 2021 06:10:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZLeGmZ4rVwk0KRCBm//8Vou29MREGqxU8Eaun5UCiZ0=; b=548hCUl3nA/9vZNhy9aZPRXCEsMZB7V/C4b76UEoLlk+Qkw+BMUkAHbrUiG1fY+CbW yF7M/SryEPc81PbrcQe5yEKaOg2oLhIQk+miMcD/h9SslvbFfUruhCAWnhMQroRR+au/ mKlmuJptejeUsG8TVA84pPDWxWXah+GurLmVZAm8FoKbHqTczeOFm+OZv54eaKxP3DHb Nr8JBDlYwEfWmUf7ZZqf9TG6rjYdT1gCHHgxdjty+wuaWRdOFZACRvqw2brZqfnWZq2M 2YezkYhaMIkhcmAhrXhLZn5XHFS5JBcaJn1EPcAchuK3Om3si2oO2n49MlwdCApYaASq hY7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZLeGmZ4rVwk0KRCBm//8Vou29MREGqxU8Eaun5UCiZ0=; b=5ChLfojCd1R83QlG4irOrt6c0QJ8iVTG8JrCL5oBMv/EafrhaFxhKwuxCj+oQqIBog JPuCHSWRHRH9ZA9EhCNRfdXz6lvZB4+LGqmQnT7OeA5NPZu1YtfyvCmeiYWgtKfyeFXW 76ngA44d43UGh7Vo3vSVTAngrMkPnhk7dGIvuH3qVdGi/b+RjJty6/uwEME0SgpOMSjh 8Oe5dogf7dyfHhb5C+xRoT0IJTDcxdc1baZaivmd9Lc95Fmc7r1VwHbLtIrXUnbZr9uE rKKRlVmZ4R2SmZ47hKzkbahFLQTjH3r8WgvNJ1Wg8pvbHX0kB++NgIP7yV3Lk1VTXQQo Birg== X-Gm-Message-State: AOAM532lqvo33dJmUYiF/WVZRm5s0/lletff4Da8rLDhRRx84CY6zqRo W2Jn5iMeV2pQh4wnug2LA3xJPGuKy7YANjDJ X-Google-Smtp-Source: ABdhPJwB7GefcYvtTrXWjf0B4Jz+sOu63leA6TiLgz5ZNmJN5+ukeCTXT1pxOX3+xfLPBf/qZlZ+PA== X-Received: by 2002:a2e:a376:: with SMTP id i22mr7397134ljn.201.1636639829854; Thu, 11 Nov 2021 06:10:29 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:29 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 7/8] RISC-V: bitmanip: add orc.b as an unspec Date: Thu, 11 Nov 2021 15:10:19 +0100 Message-Id: <20211111141020.2738001-8-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" As a basis for optimized string functions (e.g., the by-pieces implementations), we need orc.b available. This adds orc.b as an unspec, so we can expand to it. gcc/ChangeLog: * config/riscv/bitmanip.md (orcb2): Add orc.b as an unspec. * config/riscv/riscv.md: Add UNSPEC_ORC_B. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/bitmanip.md | 8 ++++++++ gcc/config/riscv/riscv.md | 3 +++ 2 files changed, 11 insertions(+) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 9e10280e306..000deb48b16 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -267,6 +267,14 @@ (define_insn "3" "\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +;; orc.b (or-combine) is added as an unspec for the benefit of the support +;; for optimized string functions (such as strcmp). +(define_insn "orcb2" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand")] UNSPEC_ORC_B))] + "TARGET_ZBB" + "orc.b\t%0,%1") + ;; ZBS extension. (define_insn "*bset" diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 225e5b259c1..7a2501ec7a9 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -45,6 +45,9 @@ (define_c_enum "unspec" [ ;; Stack tie UNSPEC_TIE + + ;; Zbb OR-combine instruction + UNSPEC_ORC_B ]) (define_c_enum "unspecv" [ From patchwork Thu Nov 11 14:10:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 47474 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5C413385C017 for ; Thu, 11 Nov 2021 14:17:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by sourceware.org (Postfix) with ESMTPS id D2566385803B for ; Thu, 11 Nov 2021 14:10:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D2566385803B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x234.google.com with SMTP id h11so12237683ljk.1 for ; Thu, 11 Nov 2021 06:10:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qqDixyoHYpxeAjez9OS4WxHR+tBwB1Agd+13DTASX6U=; b=2keC10x3aSF607LmYJjUob+Cc/C985UnL2Ll2kJTWNsoSm1RmHtYWgFwmSM1hcN+uR Qrd7pq63ic0yagcS6xjZ5UHW9vA+26MCoVHr26TeXx+d+Y0M/h/20aW9AKfg+GIzspLr /S1pbDJ3ho/Vphsgl31qMLp3CsA+eNxyho4KkZ0VhxypvgyMVuB20rqGswhNyPBG6/0y u28ETknVESiZyOkxLe15PIidcCr+haIXa2Xpvg8xtSK0gG8FIPUyFAiZudFh79loOyEA UsVIqv4PG8jkWanCjuhnUVWgTcSK5i4iNLRcvQfnVvGJa3CEXmzCzSbgBskq6JMYh3Kt I4tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qqDixyoHYpxeAjez9OS4WxHR+tBwB1Agd+13DTASX6U=; b=Vf7PlmijNSytHt6l8UwJp4HNORUZv7dNRxc988qVztoJS0YTCp3ltvppXp4Cy7a0rM lseWQYZy//Zp8nQLSNGI3ZJ0SK1OlnjgB2+ZJvd00yf+0HrRNFQeNci61hrJYtg6H4o+ 4f1e4Ci1qqSghiCAlyXE36X1vwoO4Bn0ChA/v7d1HrNCLR/E0+oFpcPC3tbSlx36FBdU 4GG/YrYLxrocER/gyHV/pXbxl1pig8v4m7mCkPiOp6lkV9Va5GxW/JsJIKh+XXlTB6DN sEDVYfcgX8VPBzuF2qbePzeDCfroDaE4RullHSEhBWge0EYkBGeIpopnyux6FSWfRCNM zD3A== X-Gm-Message-State: AOAM531t+pu+1l3FCWUubLXx1i1s9l+RI8ixheY5rgAV5IWro/Os/J3h aesTvgC1cvlEOWU8J/W5f9j4CG9G0fahAJHx X-Google-Smtp-Source: ABdhPJyvLVuYvaWOl3AhNi1As/yOKbMDHBONT+T+wmg3SvA0PueXfR6Ya9DKKX3Ro35wL+UdPRUSpw== X-Received: by 2002:a2e:9601:: with SMTP id v1mr7676857ljh.478.1636639830526; Thu, 11 Nov 2021 06:10:30 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:30 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 8/8] RISC-V: bitmanip: relax minmax to operate on GPR Date: Thu, 11 Nov 2021 15:10:20 +0100 Message-Id: <20211111141020.2738001-9-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" While min/minu/max/maxu instructions are provided for XLEN only, these can safely operate on GPRs (i.e. SImode or DImode for RV64): SImode is always sign-extended, which ensures that the XLEN-wide instructions can be used for signed and unsigned comparisons on SImode yielding a correct ordering of value. This commit - relaxes the minmax pattern to express for GPR (instead of X only), providing both a si3 and di3 expansion on RV64 - adds a sign-extending form for thee si3 pattern for RV64 to all REE to eliminate redundant extensions - adds test-cases for both gcc/ChangeLog: * config/riscv/bitmanip.md: Relax minmax to GPR (i.e SImode or DImode) on RV64. * config/riscv/bitmanip.md (si3_sext): Add pattern for REE. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-min-max.c: Add testcases for SImode operands checking that no redundant sign- or zero-extensions are emitted. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/bitmanip.md | 14 +++++++++++--- gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 20 +++++++++++++++++--- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 000deb48b16..2a28f78f5f6 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -260,13 +260,21 @@ (define_insn "bswap2" [(set_attr "type" "bitmanip")]) (define_insn "3" - [(set (match_operand:X 0 "register_operand" "=r") - (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r") - (match_operand:X 2 "register_operand" "r")))] + [(set (match_operand:GPR 0 "register_operand" "=r") + (bitmanip_minmax:GPR (match_operand:GPR 1 "register_operand" "r") + (match_operand:GPR 2 "register_operand" "r")))] "TARGET_ZBB" "\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +(define_insn "si3_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (bitmanip_minmax:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_64BIT && TARGET_ZBB" + "\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + ;; orc.b (or-combine) is added as an unspec for the benefit of the support ;; for optimized string functions (such as strcmp). (define_insn "orcb2" diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c index f44c398ea08..7169e873551 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */ +/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64 -O2" } */ long foo1 (long i, long j) @@ -25,7 +25,21 @@ foo4 (unsigned long i, unsigned long j) return i > j ? i : j; } +unsigned int +foo5(unsigned int a, unsigned int b) +{ + return a > b ? a : b; +} + +int +foo6(int a, int b) +{ + return a > b ? a : b; +} + /* { dg-final { scan-assembler-times "min" 3 } } */ -/* { dg-final { scan-assembler-times "max" 3 } } */ +/* { dg-final { scan-assembler-times "max" 4 } } */ /* { dg-final { scan-assembler-times "minu" 1 } } */ -/* { dg-final { scan-assembler-times "maxu" 1 } } */ +/* { dg-final { scan-assembler-times "maxu" 3 } } */ +/* { dg-final { scan-assembler-not "zext.w" } } */ +/* { dg-final { scan-assembler-not "sext.w" } } */