From patchwork Sat Nov 6 15:43:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Edelsohn X-Patchwork-Id: 47164 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 61B9D385780A for ; Sat, 6 Nov 2021 15:43:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 61B9D385780A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1636213432; bh=6PWp8AXPxjZUEtPLlQbLeuo7IMfIX2jnYZw5OpoALRQ=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=MIOc/s87V70gMSlB/vgeIsgF1aLOK6F9DZTnLBWfo94bgexbb9xNsIf2c7cNhT6Do 59grGECNx1tZugcqUZwIL92/E7cbaDKOPJs2nIXhPPm1sosCD8dOhBE84kEkY9mLK9 nJpjUfCNUjZcqHeoH6DjVZzHmpoDblJ5uJGCrj2o= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-vk1-xa31.google.com (mail-vk1-xa31.google.com [IPv6:2607:f8b0:4864:20::a31]) by sourceware.org (Postfix) with ESMTPS id 5CA183858401 for ; Sat, 6 Nov 2021 15:43:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5CA183858401 Received: by mail-vk1-xa31.google.com with SMTP id f78so3951217vka.5 for ; Sat, 06 Nov 2021 08:43:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=6PWp8AXPxjZUEtPLlQbLeuo7IMfIX2jnYZw5OpoALRQ=; b=pI3CWYdy/E3oTkq9RIKw8qSRmzypWD85ZQH45ybbQcKaWn0UROZLmQsndx4NQ9evuF SX8LL0ULGA9Dn7su1umhR0JWwKTmVVmQsaGAWY1z4M0CBJ5bBvQ28WWYH3/ursaTA9V6 lbQoTL5Nloksuhvc9rUprQggFYlhZAy3B3ieJFudRrUr+OEdquANJOLi5k6PHj1ex0bt FZ6O8j5ZloFwhzRa0l4vG9OXIKLGS1e7VPiuOXjOGYl7aW0JuY97Ft9Hoz/etbJqbtcq bQb5LGJPOrK3V7bIBF95x0rC/ISQF8IVciksljQdppJUt1hWvz30eT2q2EXru9/ySqlY 0MVg== X-Gm-Message-State: AOAM5316JTmd/81B/hK9evyOk9qtz2AE4u7ezqATAnxTurLIw08q6t0M pLE/uLiO0YPsxuN8yGwRuEjhTnWTb4gVJsziKpUd8RsHLv0= X-Google-Smtp-Source: ABdhPJwUgZZs48SToNT7aDzYXmig1GfEsmvOACAMNQh3I4JtxReIOr4riOoD08GOnBCZkhWiNp6zWdmfqB5VgN3pvsA= X-Received: by 2002:a05:6122:221f:: with SMTP id bb31mr35962898vkb.23.1636213402698; Sat, 06 Nov 2021 08:43:22 -0700 (PDT) MIME-Version: 1.0 Date: Sat, 6 Nov 2021 11:43:11 -0400 Message-ID: Subject: [PATCH] Fix vsx_splat_v4si in 32 bit mode To: GCC Patches X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: David Edelsohn via Gcc-patches From: David Edelsohn Reply-To: David Edelsohn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" powerpc: Fix vsx_splat_v4si in 32 bit mode Tamar's recent patch to teach CSE to perform vector extract exercises VSX splat more frequently, which exposed a constraint error for the vsx_splat patterns. The pattern could be created for Power9, but the "we constraint only provided alternatives in 64 bit mode. The instructions are valid in 32 bit mode and SImode is allowed in VSX registers. This patch updates the constraints from "we" to "wa" to allow the pattern and fix the failing testcases. Bootstrapped on powerpc-ibm-aix7.2.3.0. gcc/ChangeLog: * config/rs6000/vsx.md (vsx_splat_v4si): Change constraints to "wa". (vsx_splat_v4si_di): Change constraint to "wa" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 0bf04feb6c4..a97f7f2a680 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4565,7 +4565,7 @@ (define_insn "vsx_splat__mem" ;; V4SI splat support (define_insn "vsx_splat_v4si" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=we,we") + [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa") (vec_duplicate:V4SI (match_operand:SI 1 "splat_input_operand" "r,Z")))] "TARGET_P9_VECTOR" @@ -4578,7 +4578,7 @@ (define_insn "vsx_splat_v4si" ;; allows us to use direct move to get the value in a vector register ;; so that we can use XXSPLTW (define_insn "vsx_splat_v4si_di" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we") + [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa") (vec_duplicate:V4SI (truncate:SI (match_operand:DI 1 "gpc_reg_operand" "wa,r"))))]