From patchwork Sat Nov 6 08:40:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenghua Xu X-Patchwork-Id: 47154 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BC76E3857828 for ; Sat, 6 Nov 2021 08:42:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 191393857C7A for ; Sat, 6 Nov 2021 08:41:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 191393857C7A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxT9OcP4ZhnHsAAA--.1091S4; Sat, 06 Nov 2021 16:41:26 +0800 (CST) From: Chenghua Xu To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 2/7] LoongArch Port: Regenerate gcc/configure. Date: Sat, 6 Nov 2021 16:40:51 +0800 Message-Id: <20211106084056.2506166-3-xuchenghua@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211106084056.2506166-1-xuchenghua@loongson.cn> References: <20211106084056.2506166-1-xuchenghua@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxT9OcP4ZhnHsAAA--.1091S4 X-Coremail-Antispam: 1UD129KBjvJXoWxCF45CFWUXw4ftryxWw1fCrg_yoWrGFWUpF y7uF43Kr48Jr1fGwsxta1rur4rtwn7ur9Iva9xWr1kCa1Fy3Wvqr4rK3y29F40ka1rZr1Y vw1F93W7WFWkZFUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBa14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVCm-wCF04k20x vY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I 3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIx AIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAI cVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2js IEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUgiSdUUUUU= X-CM-SenderInfo: x0xfxv5qjk3to6or00hjvr0hdfq/ X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenglulu@loongson.cn, xuchenghua@loongson.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: chenglulu --- gcc/configure | 63 ++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/gcc/configure b/gcc/configure index 920868bcd33..5044fc27e42 100755 --- a/gcc/configure +++ b/gcc/configure @@ -7759,6 +7759,9 @@ else mips*-*-*) enable_fixed_point=yes ;; + loongarch*-*-*) + enable_fixed_point=yes + ;; *) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: fixed-point is not supported for this target, ignored" >&5 $as_echo "$as_me: WARNING: fixed-point is not supported for this target, ignored" >&2;} @@ -19455,7 +19458,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 19458 "configure" +#line 19461 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -19561,7 +19564,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 19564 "configure" +#line 19567 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -25326,6 +25329,17 @@ foo: data8 25 movl r24 = @tprel(foo#)' tls_as_opt=--fatal-warnings ;; + loongarch*-*-*) + conftest_s=' + .section .tdata,"awT",@progbits +x: .word 2 + .text + la.tls.gd $a0,x + bl __tls_get_addr' + tls_first_major=0 + tls_first_minor=0 + tls_as_opt='--fatal-warnings' + ;; microblaze*-*-*) conftest_s=' .section .tdata,"awT",@progbits @@ -28548,6 +28562,43 @@ $as_echo "#define HAVE_AS_MARCH_ZIFENCEI 1" >>confdefs.h fi ;; + loongarch*-*-*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .dtprelword support" >&5 +$as_echo_n "checking assembler for .dtprelword support... " >&6; } +if ${gcc_cv_as_loongarch_dtprelword+:} false; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_loongarch_dtprelword=no + if test x$gcc_cv_as != x; then + $as_echo '' > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags 2,18,0 -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + .section .tdata,"awT",@progbits +x: + .word 2 + .text + .dtprelword x+0x8000 + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_loongarch_dtprelword" >&5 +$as_echo "$gcc_cv_as_loongarch_dtprelword" >&6; } + +if test $gcc_cv_as_loongarch_dtprelword != yes; then + +$as_echo "#define HAVE_AS_DTPRELWORD 1" >>confdefs.h + +fi + ;; s390*-*-*) { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .gnu_attribute support" >&5 $as_echo_n "checking assembler for .gnu_attribute support... " >&6; } @@ -28711,11 +28762,11 @@ fi ;; esac -# Mips and HP-UX need the GNU assembler. +# Mips, LoongArch and HP-UX need the GNU assembler. # Linux on IA64 might be able to use the Intel assembler. case "$target" in - mips*-*-* | *-*-hpux* ) + mips*-*-* | loongarch*-*-* | *-*-hpux* ) if test x$gas_flag = xyes \ || test x"$host" != x"$build" \ || test ! -x "$gcc_cv_as" \ @@ -29152,8 +29203,8 @@ esac # ??? Once 2.11 is released, probably need to add first known working # version to the per-target configury. case "$cpu_type" in - aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | m32c | m68k \ - | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \ + aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | m32c \ + | m68k | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \ | tilegx | tilepro | visium | xstormy16 | xtensa) insn="nop" ;; From patchwork Sat Nov 6 08:40:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenghua Xu X-Patchwork-Id: 47155 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 66CF4385783A for ; Sat, 6 Nov 2021 08:42:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id CD06D3857825 for ; Sat, 6 Nov 2021 08:41:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CD06D3857825 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxT9OcP4ZhnHsAAA--.1091S5; Sat, 06 Nov 2021 16:41:27 +0800 (CST) From: Chenghua Xu To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 3/7] LoongArch Port: libgcc Date: Sat, 6 Nov 2021 16:40:52 +0800 Message-Id: <20211106084056.2506166-4-xuchenghua@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211106084056.2506166-1-xuchenghua@loongson.cn> References: <20211106084056.2506166-1-xuchenghua@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxT9OcP4ZhnHsAAA--.1091S5 X-Coremail-Antispam: 1UD129KBjvAXoW3uFyfAw4rCr17tw1UJFykGrg_yoW8Cw18Ko W3tFZIvw48Gr1xZ39YkrnxWryDur1Y9r47A343Z3yxCF4DZr1UGFy2gw4Fva43tr9FgFyr Aayjqr97Ja12kFn5n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYu7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWx Jr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2 80aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUj5rcDUUUUU== X-CM-SenderInfo: x0xfxv5qjk3to6or00hjvr0hdfq/ X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenglulu@loongson.cn, xuchenghua@loongson.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: chenglulu libgcc/ * config/loongarch/crtfastmath.c: New file. * config/loongarch/crti.S: Like wise. * config/loongarch/crtn.S: Like wise. * config/loongarch/lib2funcs.c: Like wise. * config/loongarch/linux-unwind.h: Like wise. * config/loongarch/sfp-machine.h: Like wise. * config/loongarch/t-crtstuff: Like wise. * config/loongarch/t-elf: Like wise. * config/loongarch/t-loongarch: Like wise. * config/loongarch/t-loongarch64: Like wise. * config/loongarch/t-softfp-tf: Like wise. * config.host: Add LoongArch tuples. * configure.ac: Add LoongArch support. --- libgcc/config.host | 26 +++++ libgcc/config/loongarch/crtfastmath.c | 52 +++++++++ libgcc/config/loongarch/crti.S | 43 +++++++ libgcc/config/loongarch/crtn.S | 39 +++++++ libgcc/config/loongarch/lib2funcs.c | 0 libgcc/config/loongarch/linux-unwind.h | 80 +++++++++++++ libgcc/config/loongarch/sfp-machine.h | 152 +++++++++++++++++++++++++ libgcc/config/loongarch/t-crtstuff | 2 + libgcc/config/loongarch/t-elf | 3 + libgcc/config/loongarch/t-loongarch | 9 ++ libgcc/config/loongarch/t-loongarch64 | 1 + libgcc/config/loongarch/t-softfp-tf | 3 + libgcc/configure.ac | 2 +- 13 files changed, 411 insertions(+), 1 deletion(-) create mode 100644 libgcc/config/loongarch/crtfastmath.c create mode 100644 libgcc/config/loongarch/crti.S create mode 100644 libgcc/config/loongarch/crtn.S create mode 100644 libgcc/config/loongarch/lib2funcs.c create mode 100644 libgcc/config/loongarch/linux-unwind.h create mode 100644 libgcc/config/loongarch/sfp-machine.h create mode 100644 libgcc/config/loongarch/t-crtstuff create mode 100644 libgcc/config/loongarch/t-elf create mode 100644 libgcc/config/loongarch/t-loongarch create mode 100644 libgcc/config/loongarch/t-loongarch64 create mode 100644 libgcc/config/loongarch/t-softfp-tf diff --git a/libgcc/config.host b/libgcc/config.host index 168535b1780..11b0af6f409 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -138,6 +138,22 @@ hppa*-*-*) lm32*-*-*) cpu_type=lm32 ;; +loongarch*-*-*) + cpu_type=loongarch + tmake_file="loongarch/t-loongarch" + if test "${libgcc_cv_loongarch_hard_float}" = yes; then + tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp" + else + tmake_file="${tmake_file} t-softfp-sfdf" + fi + if test "${ac_cv_sizeof_long_double}" = 16; then + tmake_file="${tmake_file} loongarch/t-softfp-tf" + fi + if test "${host_address}" = 64; then + tmake_file="${tmake_file} loongarch/t-loongarch64" + fi + tmake_file="${tmake_file} t-softfp" + ;; m32r*-*-*) cpu_type=m32r ;; @@ -922,6 +938,16 @@ lm32-*-uclinux*) extra_parts="$extra_parts crtbegin.o crtendS.o crtbeginT.o" tmake_file="lm32/t-lm32 lm32/t-uclinux t-libgcc-pic t-softfp-sfdf t-softfp" ;; +loongarch*-*-linux*) + extra_parts="$extra_parts crtfastmath.o" + tmake_file="${tmake_file} t-crtfm" + case ${host} in + *) + tmake_file="${tmake_file} t-slibgcc-libgcc" + ;; + esac + md_unwind_header=loongarch/linux-unwind.h + ;; m32r-*-elf*) tmake_file="$tmake_file m32r/t-m32r t-fdpbit" extra_parts="$extra_parts crtinit.o crtfini.o" diff --git a/libgcc/config/loongarch/crtfastmath.c b/libgcc/config/loongarch/crtfastmath.c new file mode 100644 index 00000000000..8f3ec599cbc --- /dev/null +++ b/libgcc/config/loongarch/crtfastmath.c @@ -0,0 +1,52 @@ +/* Copyright (C) 2021 Free Software Foundation, Inc. + Contributed by Loongson Ltd. + Based on MIPS target for GNU compiler. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License +and a copy of the GCC Runtime Library Exception along with this +program; see the files COPYING3 and COPYING.RUNTIME respectively. +If not, see . */ + +#ifdef __loongarch_hard_float + +/* Rounding control. */ +#define _FPU_RC_NEAREST 0x000 /* RECOMMENDED. */ +#define _FPU_RC_ZERO 0x100 +#define _FPU_RC_UP 0x200 +#define _FPU_RC_DOWN 0x300 + +/* Enable interrupts for IEEE exceptions. */ +#define _FPU_IEEE 0x0000001F + +/* Macros for accessing the hardware control word. */ +#define _FPU_GETCW(cw) __asm__ ("movgr2fcsr %0,$r1" : "=r" (cw)) +#define _FPU_SETCW(cw) __asm__ ("movfcsr2gr %0,$r1" : : "r" (cw)) + +static void __attribute__((constructor)) +set_fast_math (void) +{ + unsigned int fcr; + + /* Flush to zero, round to nearest, IEEE exceptions disabled. */ + fcr = _FPU_RC_NEAREST; + + _FPU_SETCW (fcr); +} + +#endif /* __loongarch_hard_float */ diff --git a/libgcc/config/loongarch/crti.S b/libgcc/config/loongarch/crti.S new file mode 100644 index 00000000000..bac029874b5 --- /dev/null +++ b/libgcc/config/loongarch/crti.S @@ -0,0 +1,43 @@ +/* Copyright (C) 2021 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +. */ + +/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. + Return spill offset of 8. Aligned to 16 bytes for lp64. */ + + .section .init,"ax",@progbits + .globl _init + .type _init,@function +_init: + addi.d $r3,$r3,-16 + st.d $r1,$r3,8 + addi.d $r3,$r3,16 + jirl $r0,$r1,0 + + .section .fini,"ax",@progbits + .globl _fini + .type _fini,@function +_fini: + addi.d $r3,$r3,-16 + st.d $r1,$r3,8 + addi.d $r3,$r3,16 + jirl $r0,$r1,0 diff --git a/libgcc/config/loongarch/crtn.S b/libgcc/config/loongarch/crtn.S new file mode 100644 index 00000000000..7af6728690f --- /dev/null +++ b/libgcc/config/loongarch/crtn.S @@ -0,0 +1,39 @@ +/* Copyright (C) 2021 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +. */ + +/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. + Return spill offset of 8. Aligned to 16 bytes for lp64. */ + + + .section .init,"ax",@progbits +init: + ld.d $r1,$r3,8 + addi.d $r3,$r3,16 + jirl $r0,$r1,0 + + .section .fini,"ax",@progbits +fini: + ld.d $r1,$r3,8 + addi.d $r3,$r3,16 + jirl $r0,$r1,0 + diff --git a/libgcc/config/loongarch/lib2funcs.c b/libgcc/config/loongarch/lib2funcs.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/libgcc/config/loongarch/linux-unwind.h b/libgcc/config/loongarch/linux-unwind.h new file mode 100644 index 00000000000..8c9dfa56a6d --- /dev/null +++ b/libgcc/config/loongarch/linux-unwind.h @@ -0,0 +1,80 @@ +/* DWARF2 EH unwinding support for LoongArch Linux. + Copyright (C) 2021 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +. */ + +#ifndef inhibit_libc +/* Do code reading to identify a signal frame, and set the frame + state data appropriately. See unwind-dw2.c for the structs. */ + +#include +#include +#include + +#define MD_FALLBACK_FRAME_STATE_FOR loongarch_fallback_frame_state + +static _Unwind_Reason_Code +loongarch_fallback_frame_state (struct _Unwind_Context *context, + _Unwind_FrameState *fs) +{ + u_int32_t *pc = (u_int32_t *) context->ra; + struct sigcontext *sc; + _Unwind_Ptr new_cfa; + int i; + + /* 03822c0b dli a7, 0x8b (sigreturn) */ + /* 002b0000 syscall 0 */ + if (pc[1] != 0x002b0000) + return _URC_END_OF_STACK; + if (pc[0] == 0x03822c0b) + { + struct rt_sigframe + { + siginfo_t info; + ucontext_t uc; + } *rt_ = context->cfa; + sc = &rt_->uc.uc_mcontext; + } + else + return _URC_END_OF_STACK; + + new_cfa = (_Unwind_Ptr) sc; + fs->regs.cfa_how = CFA_REG_OFFSET; + fs->regs.cfa_reg = __LIBGCC_STACK_POINTER_REGNUM__; + fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa; + + for (i = 0; i < 32; i++) + { + fs->regs.reg[i].how = REG_SAVED_OFFSET; + fs->regs.reg[i].loc.offset = (_Unwind_Ptr) & (sc->sc_regs[i]) - new_cfa; + } + + fs->signal_frame = 1; + fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].how + = REG_SAVED_VAL_OFFSET; + fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].loc.offset + = (_Unwind_Ptr) (sc->sc_pc) - new_cfa; + fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__; + + return _URC_NO_REASON; +} +#endif diff --git a/libgcc/config/loongarch/sfp-machine.h b/libgcc/config/loongarch/sfp-machine.h new file mode 100644 index 00000000000..cb5b04feede --- /dev/null +++ b/libgcc/config/loongarch/sfp-machine.h @@ -0,0 +1,152 @@ +/* softfp machine description for LoongArch. + Copyright (C) 2021 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +. */ + +#ifdef __loongarch64 +#define _FP_W_TYPE_SIZE 64 +#define _FP_W_TYPE unsigned long long +#define _FP_WS_TYPE signed long long +#define _FP_I_TYPE long long + +typedef int TItype __attribute__ ((mode (TI))); +typedef unsigned int UTItype __attribute__ ((mode (TI))); +#define TI_BITS (__CHAR_BIT__ * (int) sizeof (TItype)) + +#define _FP_MUL_MEAT_S(R, X, Y) \ + _FP_MUL_MEAT_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm) +#define _FP_MUL_MEAT_D(R, X, Y) \ + _FP_MUL_MEAT_1_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) +#define _FP_MUL_MEAT_Q(R, X, Y) \ + _FP_MUL_MEAT_2_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) + +#define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_udiv_norm (S, R, X, Y) +#define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_1_udiv_norm (D, R, X, Y) +#define _FP_DIV_MEAT_Q(R, X, Y) _FP_DIV_MEAT_2_udiv (Q, R, X, Y) + +#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) +#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 +#else +#define _FP_W_TYPE_SIZE 32 +#define _FP_W_TYPE unsigned int +#define _FP_WS_TYPE signed int +#define _FP_I_TYPE int + +#define _FP_MUL_MEAT_S(R, X, Y) \ + _FP_MUL_MEAT_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm) +#define _FP_MUL_MEAT_D(R, X, Y) \ + _FP_MUL_MEAT_2_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) +#define _FP_MUL_MEAT_Q(R, X, Y) \ + _FP_MUL_MEAT_4_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) + +#define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_udiv_norm (S, R, X, Y) +#define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_2_udiv (D, R, X, Y) +#define _FP_DIV_MEAT_Q(R, X, Y) _FP_DIV_MEAT_4_udiv (Q, R, X, Y) + +#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 +#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 +#endif + +/* The type of the result of a floating point comparison. This must + match __libgcc_cmp_return__ in GCC for the target. */ +typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); +#define CMPtype __gcc_CMPtype + +#define _FP_NANSIGN_S 0 +#define _FP_NANSIGN_D 0 +#define _FP_NANSIGN_Q 0 + +#define _FP_KEEPNANFRACP 1 +#define _FP_QNANNEGATEDP 0 + +/* NaN payloads should be preserved for NAN2008. */ +#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ + do \ + { \ + R##_s = X##_s; \ + _FP_FRAC_COPY_##wc (R, X); \ + R##_c = FP_CLS_NAN; \ + } \ + while (0) + +#ifdef __loongarch_hard_float +#define FP_EX_INVALID 0x100000 +#define FP_EX_DIVZERO 0x080000 +#define FP_EX_OVERFLOW 0x040000 +#define FP_EX_UNDERFLOW 0x020000 +#define FP_EX_INEXACT 0x010000 +#define FP_EX_ALL \ + (FP_EX_INVALID | FP_EX_DIVZERO | FP_EX_OVERFLOW | FP_EX_UNDERFLOW \ + | FP_EX_INEXACT) + +#define FP_EX_ENABLE_SHIFT 16 +#define FP_EX_CAUSE_SHIFT 8 + +#define FP_RND_NEAREST 0x000 +#define FP_RND_ZERO 0x100 +#define FP_RND_PINF 0x200 +#define FP_RND_MINF 0x300 +#define FP_RND_MASK 0x300 + +#define _FP_DECL_EX \ + unsigned long int _fcsr __attribute__ ((unused)) = FP_RND_NEAREST + +#define FP_INIT_ROUNDMODE \ + do \ + { \ + _fcsr = __builtin_loongarch_movfcsr2gr (0); \ + } \ + while (0) + +#define FP_ROUNDMODE (_fcsr & FP_RND_MASK) + +#define FP_TRAPPING_EXCEPTIONS ((_fcsr << FP_EX_ENABLE_SHIFT) & FP_EX_ALL) + +#define FP_HANDLE_EXCEPTIONS \ + do \ + { \ + _fcsr &= ~(FP_EX_ALL << FP_EX_CAUSE_SHIFT); \ + _fcsr |= _fex | (_fex << FP_EX_CAUSE_SHIFT); \ + __builtin_loongarch_movgr2fcsr (0, _fcsr); \ + } \ + while (0) + +#else +#define FP_EX_INVALID (1 << 4) +#define FP_EX_DIVZERO (1 << 3) +#define FP_EX_OVERFLOW (1 << 2) +#define FP_EX_UNDERFLOW (1 << 1) +#define FP_EX_INEXACT (1 << 0) +#endif + +#define _FP_TININESS_AFTER_ROUNDING 1 + +#define __LITTLE_ENDIAN 1234 + +#define __BYTE_ORDER __LITTLE_ENDIAN + +/* Define ALIASNAME as a strong alias for NAME. */ +#define strong_alias(name, aliasname) _strong_alias (name, aliasname) +#define _strong_alias(name, aliasname) \ + extern __typeof (name) aliasname __attribute__ ((alias (#name))); diff --git a/libgcc/config/loongarch/t-crtstuff b/libgcc/config/loongarch/t-crtstuff new file mode 100644 index 00000000000..d8ab43be2ae --- /dev/null +++ b/libgcc/config/loongarch/t-crtstuff @@ -0,0 +1,2 @@ +# Don't let CTOR_LIST end up in sdata section. +CRTSTUFF_T_CFLAGS = -G 0 diff --git a/libgcc/config/loongarch/t-elf b/libgcc/config/loongarch/t-elf new file mode 100644 index 00000000000..651f10a5303 --- /dev/null +++ b/libgcc/config/loongarch/t-elf @@ -0,0 +1,3 @@ +# We must build libgcc2.a with -G 0, in case the user wants to link +# without the $gp register. +HOST_LIBGCC2_CFLAGS += -G 0 diff --git a/libgcc/config/loongarch/t-loongarch b/libgcc/config/loongarch/t-loongarch new file mode 100644 index 00000000000..9508cb2fcae --- /dev/null +++ b/libgcc/config/loongarch/t-loongarch @@ -0,0 +1,9 @@ +LIB2_SIDITI_CONV_FUNCS = yes + +softfp_float_modes := +softfp_int_modes := si di +softfp_extensions := +softfp_truncations := +softfp_exclude_libgcc2 := n + +LIB2ADD_ST += $(srcdir)/config/loongarch/lib2funcs.c diff --git a/libgcc/config/loongarch/t-loongarch64 b/libgcc/config/loongarch/t-loongarch64 new file mode 100644 index 00000000000..a1e3513e288 --- /dev/null +++ b/libgcc/config/loongarch/t-loongarch64 @@ -0,0 +1 @@ +softfp_int_modes += ti diff --git a/libgcc/config/loongarch/t-softfp-tf b/libgcc/config/loongarch/t-softfp-tf new file mode 100644 index 00000000000..306677b1255 --- /dev/null +++ b/libgcc/config/loongarch/t-softfp-tf @@ -0,0 +1,3 @@ +softfp_float_modes += tf +softfp_extensions += sftf dftf +softfp_truncations += tfsf tfdf diff --git a/libgcc/configure.ac b/libgcc/configure.ac index 13a80b2551b..b17d788dbd0 100644 --- a/libgcc/configure.ac +++ b/libgcc/configure.ac @@ -317,7 +317,7 @@ AC_CACHE_CHECK([whether assembler supports CFI directives], [libgcc_cv_cfi], # word size rather than the address size. cat > conftest.c < X-Patchwork-Id: 47156 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C52283857009 for ; Sat, 6 Nov 2021 08:43:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 60A1F3857818 for ; Sat, 6 Nov 2021 08:41:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 60A1F3857818 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxT9OcP4ZhnHsAAA--.1091S6; Sat, 06 Nov 2021 16:41:31 +0800 (CST) From: Chenghua Xu To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 4/7] LoongArch Port: Regenerate libgcc/configure. Date: Sat, 6 Nov 2021 16:40:53 +0800 Message-Id: <20211106084056.2506166-5-xuchenghua@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211106084056.2506166-1-xuchenghua@loongson.cn> References: <20211106084056.2506166-1-xuchenghua@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxT9OcP4ZhnHsAAA--.1091S6 X-Coremail-Antispam: 1UD129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73 VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjp_UUUYN7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E 6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14 v26r126s0DM28IrcIa0xkI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CE w4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6x kF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv 6xkF7I0E14v26r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4 CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvj eVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I 1lc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E 5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAV WUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY 1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI 0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7V UjeHq7UUUUU== X-CM-SenderInfo: x0xfxv5qjk3to6or00hjvr0hdfq/ X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenglulu@loongson.cn, xuchenghua@loongson.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: chenglulu --- libgcc/configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libgcc/configure b/libgcc/configure index 4919a56f518..150ea04cb3d 100755 --- a/libgcc/configure +++ b/libgcc/configure @@ -5066,7 +5066,7 @@ $as_echo "$libgcc_cv_cfi" >&6; } # word size rather than the address size. cat > conftest.c < X-Patchwork-Id: 47157 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C6BF4385781F for ; Sat, 6 Nov 2021 08:43:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 81E96385AC08 for ; Sat, 6 Nov 2021 08:41:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 81E96385AC08 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxT9OcP4ZhnHsAAA--.1091S7; Sat, 06 Nov 2021 16:41:33 +0800 (CST) From: Chenghua Xu To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 5/7] LoongArch Port: libgomp Date: Sat, 6 Nov 2021 16:40:54 +0800 Message-Id: <20211106084056.2506166-6-xuchenghua@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211106084056.2506166-1-xuchenghua@loongson.cn> References: <20211106084056.2506166-1-xuchenghua@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxT9OcP4ZhnHsAAA--.1091S7 X-Coremail-Antispam: 1UD129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73 VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjp_UUUYN7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E 6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14 v26r126s0DM28IrcIa0xkI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CE w4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6x kF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv 6xkF7I0E14v26r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4 CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvj eVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I 1lc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E 5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAV WUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY 1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI 0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7V UjeHq7UUUUU== X-CM-SenderInfo: x0xfxv5qjk3to6or00hjvr0hdfq/ X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenglulu@loongson.cn, xuchenghua@loongson.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: chenglulu libgomp/ * configure.tgt: Add LoongArch tuple. --- libgomp/configure.tgt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt index d4f1e741b5a..2cd7272fcd8 100644 --- a/libgomp/configure.tgt +++ b/libgomp/configure.tgt @@ -56,6 +56,10 @@ if test x$enable_linux_futex = xyes; then config_path="linux/ia64 linux posix" ;; + loongarch*-*-linux*) + config_path="linux posix" + ;; + mips*-*-linux*) config_path="linux/mips linux posix" ;; From patchwork Sat Nov 6 08:40:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenghua Xu X-Patchwork-Id: 47158 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 424013857831 for ; Sat, 6 Nov 2021 08:44:21 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 17EA03857027 for ; Sat, 6 Nov 2021 08:41:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 17EA03857027 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxT9OcP4ZhnHsAAA--.1091S8; Sat, 06 Nov 2021 16:41:34 +0800 (CST) From: Chenghua Xu To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 6/7] LoongArch Port: gcc/testsuite Date: Sat, 6 Nov 2021 16:40:55 +0800 Message-Id: <20211106084056.2506166-7-xuchenghua@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211106084056.2506166-1-xuchenghua@loongson.cn> References: <20211106084056.2506166-1-xuchenghua@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxT9OcP4ZhnHsAAA--.1091S8 X-Coremail-Antispam: 1UD129KBjvJXoW3ur1fKr4UZry5KryDKF17ZFb_yoWkAFWUpw nrCryFkF48GFZ7G3srKFyrXF15Xws3Gry5uFyxKa1Ikw13tryIqF1xtF43JF15Ja15Wrya qa18uw15uayFgw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j 6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUOBTYUUUUU X-CM-SenderInfo: x0xfxv5qjk3to6or00hjvr0hdfq/ X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenglulu@loongson.cn, xuchenghua@loongson.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: chenglulu gcc/testsuite/ * g++.dg/cpp0x/constexpr-rom.C: Add build options for LoongArch. * g++.old-deja/g++.abi/ptrmem.C: Add LoongArch support. * g++.old-deja/g++.pt/ptrmem6.C: xfail for LoongArch. * gcc.dg/20020312-2.c: Add LoongArch support. * gcc.dg/loop-8.c: Skip on LoongArch. * gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise. * gcc.dg/tree-ssa/ssa-fre-3.c: Likewise. * go.test/go-test.exp: Define the LoongArch target. * lib/target-supports.exp: Like wise. * gcc.target/loongarch/loongarch.exp: New file. * gcc.target/loongarch/tst-asm-const.c: Like wise. --- gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C | 2 +- gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C | 2 +- gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C | 2 +- gcc/testsuite/gcc.dg/20020312-2.c | 2 + gcc/testsuite/gcc.dg/loop-8.c | 2 +- .../torture/stackalign/builtin-apply-2.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c | 2 +- .../gcc.target/loongarch/loongarch.exp | 40 +++++++++++++++++++ .../gcc.target/loongarch/tst-asm-const.c | 16 ++++++++ gcc/testsuite/go.test/go-test.exp | 3 ++ gcc/testsuite/lib/target-supports.exp | 14 +++++++ 11 files changed, 81 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/loongarch.exp create mode 100644 gcc/testsuite/gcc.target/loongarch/tst-asm-const.c diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C index 2e0ef685f36..424979a604b 100644 --- a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C @@ -1,6 +1,6 @@ // PR c++/49673: check that test_data goes into .rodata // { dg-do compile { target c++11 } } -// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } } +// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* loongarch*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } } // { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } } // { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* *-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } } diff --git a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C index bda7960d8a2..f69000e9081 100644 --- a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C +++ b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C @@ -7,7 +7,7 @@ function. However, some platforms use all bits to encode a function pointer. Such platforms use the lowest bit of the delta, that is shifted left by one bit. */ -#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__ +#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__ || defined __loongarch__ #define ADJUST_PTRFN(func, virt) ((void (*)())(func)) #define ADJUST_DELTA(delta, virt) (((delta) << 1) + !!(virt)) #else diff --git a/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C b/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C index 9f4bbe43f89..8f8f7017ab7 100644 --- a/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C +++ b/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C @@ -25,7 +25,7 @@ int main() { h<&B::j>(); // { dg-error "" } g<(void (A::*)()) &A::f>(); // { dg-error "" "" { xfail c++11 } } h<(int A::*) &A::i>(); // { dg-error "" "" { xfail c++11 } } - g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { aarch64*-*-* arm*-*-* mips*-*-* } } } } + g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { aarch64*-*-* arm*-*-* mips*-*-* loongarch*-*-* } } } } h<(int A::*) &B::j>(); // { dg-error "" } g<(void (A::*)()) 0>(); // { dg-error "" "" { target { ! c++11 } } } h<(int A::*) 0>(); // { dg-error "" "" { target { ! c++11 } } } diff --git a/gcc/testsuite/gcc.dg/20020312-2.c b/gcc/testsuite/gcc.dg/20020312-2.c index 52c33d09b90..2e35d443a1d 100644 --- a/gcc/testsuite/gcc.dg/20020312-2.c +++ b/gcc/testsuite/gcc.dg/20020312-2.c @@ -49,6 +49,8 @@ extern void abort (void); # define PIC_REG "r20" #elif defined(__mips__) /* PIC register is $28, but is used even without -fpic. */ +#elif defined(__loongarch__) +/* PIC register is $r2, but is used even without -fpic. */ #elif defined(__MMIX__) /* No pic register. */ #elif defined(__mn10300__) diff --git a/gcc/testsuite/gcc.dg/loop-8.c b/gcc/testsuite/gcc.dg/loop-8.c index a685fc25056..8e5f2087831 100644 --- a/gcc/testsuite/gcc.dg/loop-8.c +++ b/gcc/testsuite/gcc.dg/loop-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */ -/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-* mmix-*-* vax-*-*" } } */ +/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-* mmix-*-* vax-*-* loongarch*-*-*" } } */ /* Load immediate on condition is available from z13 on and prevents moving the load out of the loop, so always run this test with -march=zEC12 that does not have load immediate on condition. */ diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c index 5ec05587dba..552ca1433f4 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c @@ -9,7 +9,7 @@ /* arm_hf_eabi: Variadic funcs use Base AAPCS. Normal funcs use VFP variant. avr: Variadic funcs don't pass arguments in registers, while normal funcs do. */ -/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { csky*-*-* avr-*-* riscv*-*-* or1k*-*-* msp430-*-* amdgcn-*-* pru-*-* } } } */ +/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { csky*-*-* avr-*-* riscv*-*-* or1k*-*-* msp430-*-* amdgcn-*-* pru-*-* loongarch*-*-* } } } */ /* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } { v850*-*-* } } */ /* { dg-require-effective-target untyped_assembly } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c index 6b6255b9713..224dd4f72ef 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c @@ -5,7 +5,7 @@ When the condition is true, we distribute "(int) (a + b)" as "(int) a + (int) b", otherwise we keep the original. */ -/* { dg-do compile { target { ! mips64 } } } */ +/* { dg-do compile { target { ! mips64 } && { ! loongarch64 } } } */ /* { dg-options "-O -fno-tree-forwprop -fno-tree-ccp -fwrapv -fdump-tree-fre1-details" } */ /* From PR14844. */ diff --git a/gcc/testsuite/gcc.target/loongarch/loongarch.exp b/gcc/testsuite/gcc.target/loongarch/loongarch.exp new file mode 100644 index 00000000000..9f374a9bc73 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/loongarch.exp @@ -0,0 +1,40 @@ +# Copyright (C) 2021 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a LoongArch target. +if ![istarget loongarch*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " " +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c b/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c new file mode 100644 index 00000000000..2e04b99e301 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c @@ -0,0 +1,16 @@ +/* Test asm const. */ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-times "foo:.*\\.long 1061109567.*\\.long 52" 1 } } */ +int foo () +{ + __asm__ volatile ( + "foo:" + "\n\t" + ".long %a0\n\t" + ".long %a1\n\t" + : + :"i"(0x3f3f3f3f), "i"(52) + : + ); +} + diff --git a/gcc/testsuite/go.test/go-test.exp b/gcc/testsuite/go.test/go-test.exp index f16754513e4..63755aed106 100644 --- a/gcc/testsuite/go.test/go-test.exp +++ b/gcc/testsuite/go.test/go-test.exp @@ -232,6 +232,9 @@ proc go-set-goarch { } { "riscv64-*-*" { set goarch "riscv64" } + "loongarch64-*-*" { + set goarch "loongarch64" + } "s390*-*-*" { if [check_effective_target_ilp32] { set goarch "s390" diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index e07d563f6f4..9dc2050b366 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -284,6 +284,10 @@ proc check_configured_with { pattern } { proc check_weak_available { } { global target_cpu + if { [ string first "loongarch" $target_cpu ] >= 0 } { + return 1 + } + # All mips targets should support it if { [ string first "mips" $target_cpu ] >= 0 } { @@ -1295,6 +1299,14 @@ proc check_effective_target_mpaired_single { } { # Return true if the target has access to FPU instructions. proc check_effective_target_hard_float { } { + if { [istarget loongarch*-*-*] } { + return [check_no_compiler_messages hard_float assembly { + #if (defined __loongarch_soft_float) + #error __loongarch_soft_float + #endif + }] + } + if { [istarget mips*-*-*] } { return [check_no_compiler_messages hard_float assembly { #if (defined __mips_soft_float || defined __mips16) @@ -8570,6 +8582,7 @@ proc check_effective_target_sync_char_short { } { || [istarget cris-*-*] || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9]) || ([istarget arc*-*-*] && [check_effective_target_arc_atomic]) + || [istarget loongarch*-*-*] || [check_effective_target_mips_llsc] }}] } @@ -10658,6 +10671,7 @@ proc check_effective_target_branch_cost {} { || [istarget epiphany*-*-*] || [istarget frv*-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] + || [istarget loongarch*-*-*] || [istarget mips*-*-*] || [istarget s390*-*-*] || [istarget riscv*-*-*] From patchwork Sat Nov 6 08:40:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenghua Xu X-Patchwork-Id: 47159 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E28583857C70 for ; Sat, 6 Nov 2021 08:44:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id ED064385783B for ; Sat, 6 Nov 2021 08:41:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org ED064385783B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxT9OcP4ZhnHsAAA--.1091S9; Sat, 06 Nov 2021 16:41:37 +0800 (CST) From: Chenghua Xu To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 7/7] LoongArch Port: Regenerate configure Date: Sat, 6 Nov 2021 16:40:56 +0800 Message-Id: <20211106084056.2506166-8-xuchenghua@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211106084056.2506166-1-xuchenghua@loongson.cn> References: <20211106084056.2506166-1-xuchenghua@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9DxT9OcP4ZhnHsAAA--.1091S9 X-Coremail-Antispam: 1UD129KBjvJXoWxAryUAF4rJw1rCw48ZF17GFg_yoW5WFyfpF 47Ca45GF45tFW3XF42v3yrWr4UAFn7Cw48uF42qFy8J3ZFk34DZr4vkwnxWF1j939rZF1F qFyrCF1q9FZ8KrUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j 6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUOBTYUUUUU X-CM-SenderInfo: x0xfxv5qjk3to6or00hjvr0hdfq/ X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chenglulu@loongson.cn, xuchenghua@loongson.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: chenglulu * config/picflag.m4: Default add build option '-fpic' for LoongArch. * configure: Add LoongArch tuples. * configure.ac: Like wise. --- config/picflag.m4 | 3 +++ configure | 12 +++++++++++- configure.ac | 10 +++++++++- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/config/picflag.m4 b/config/picflag.m4 index 8b106f9af88..0aefcf619bf 100644 --- a/config/picflag.m4 +++ b/config/picflag.m4 @@ -44,6 +44,9 @@ case "${$2}" in # sets the default TLS model and affects inlining. $1=-fPIC ;; + loongarch*-*-*) + $1=-fpic + ;; mips-sgi-irix6*) # PIC is the default. ;; diff --git a/configure b/configure index 58979d6e3b1..fcdb8b3d1b9 100755 --- a/configure +++ b/configure @@ -3052,7 +3052,7 @@ case "${ENABLE_GOLD}" in # Check for target supported by gold. case "${target}" in i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* \ - | aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-*) + | aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-* | loongarch*-*-*) configdirs="$configdirs gold" if test x${ENABLE_GOLD} = xdefault; then default_ld=gold @@ -3638,6 +3638,9 @@ case "${target}" in i[3456789]86-*-*) libgloss_dir=i386 ;; + loongarch*-*-*) + libgloss_dir=loongarch + ;; m68hc11-*-*|m6811-*-*|m68hc12-*-*|m6812-*-*) libgloss_dir=m68hc11 ;; @@ -4022,6 +4025,11 @@ case "${target}" in wasm32-*-*) noconfigdirs="$noconfigdirs ld" ;; + loongarch*-*-linux*) + ;; + loongarch*-*-*) + noconfigdirs="$noconfigdirs gprof" + ;; esac # If we aren't building newlib, then don't build libgloss, since libgloss @@ -10083,6 +10091,8 @@ done + + # Generate default definitions for YACC, M4, LEX and other programs that run # on the build machine. These are used if the Makefile can't locate these # programs in objdir. diff --git a/configure.ac b/configure.ac index 550e6993b59..8d1cf5eaf27 100644 --- a/configure.ac +++ b/configure.ac @@ -353,7 +353,7 @@ case "${ENABLE_GOLD}" in # Check for target supported by gold. case "${target}" in i?86-*-* | x86_64-*-* | sparc*-*-* | powerpc*-*-* | arm*-*-* \ - | aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-*) + | aarch64*-*-* | tilegx*-*-* | mips*-*-* | s390*-*-* | loongarch*-*-*) configdirs="$configdirs gold" if test x${ENABLE_GOLD} = xdefault; then default_ld=gold @@ -899,6 +899,9 @@ case "${target}" in i[[3456789]]86-*-*) libgloss_dir=i386 ;; + loongarch*-*-*) + libgloss_dir=loongarch + ;; m68hc11-*-*|m6811-*-*|m68hc12-*-*|m6812-*-*) libgloss_dir=m68hc11 ;; @@ -1283,6 +1286,11 @@ case "${target}" in wasm32-*-*) noconfigdirs="$noconfigdirs ld" ;; + loongarch*-*-linux*) + ;; + loongarch*-*-*) + noconfigdirs="$noconfigdirs gprof" + ;; esac # If we aren't building newlib, then don't build libgloss, since libgloss