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To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stack. During function epilogue R12 will be popped and AUT R12, LR, SP will be used to verify that the content of LR is still valid before return. Here an example of PAC instrumented function prologue and epilogue: pac r12, lr, sp push {r3, r7, lr} push {r12} sub sp, sp, #4 [...] function body add sp, sp, #4 pop {r12} pop {r3, r7, lr} aut r12, lr, sp bx lr The patch also takes care of generating a PACBTI instruction in place of the sequence BTI+PAC when Branch Target Identification is enabled contextually. These two patches apply on top of Tejas series posted here [2]. Regressioned and arm-linux-gnu aarch64-linux-gnu bootstraped. Best Regards Andrea [1] [2] From 605970bdef506d749bbe9650ee469f41b1d7377f Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Fri, 24 Sep 2021 14:50:29 +0200 Subject: [PATCH 1/2] [PATCH] [1/2] arm: Implement cortex-M return signing address codegen gcc/Changelog 2021-11-03 Andrea Corallo * config/arm/arm.c: (arm_compute_frame_layout) (arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue) (arm_conditional_register_usage): Update for pac codegen. (arm_pac_enabled_for_curr_function_p): New function. * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp): Add new patterns. * config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP) (UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs. gcc/testsuite/Changelog 2021-11-03 Andrea Corallo * gcc.target/arm/pac-1.c : New test case. * gcc.target/arm/pac-2.c : Likewise. * gcc.target/arm/pac-3.c : Likewise. * gcc.target/arm/pac-4.c : Likewise. * gcc.target/arm/pac-5.c : Likewise. --- gcc/config/arm/arm.c | 85 ++++++++++++++++++++++++---- gcc/config/arm/arm.md | 20 +++++++ gcc/config/arm/unspecs.md | 3 + gcc/testsuite/gcc.target/arm/pac-1.c | 25 ++++++++ gcc/testsuite/gcc.target/arm/pac-2.c | 25 ++++++++ gcc/testsuite/gcc.target/arm/pac-3.c | 25 ++++++++ gcc/testsuite/gcc.target/arm/pac-4.c | 25 ++++++++ gcc/testsuite/gcc.target/arm/pac-5.c | 26 +++++++++ 8 files changed, 224 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/pac-1.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-2.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-3.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-4.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-5.c diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a87bcb298f9..2889a471fa5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -302,6 +302,7 @@ static bool arm_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, const vec_perm_indices &); static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*); +static bool arm_pac_enabled_for_curr_function_p (void); static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, tree vectype, @@ -22696,6 +22697,10 @@ arm_compute_frame_layout (void) nonecure entry functions with VSTR/VLDR. */ if (TARGET_HAVE_FPCXT_CMSE && IS_CMSE_ENTRY (func_type)) saved += 4; + + /* Allocate space for saving R12 */ + if (arm_pac_enabled_for_curr_function_p ()) + saved += 4; } else /* TARGET_THUMB1 */ { @@ -23288,11 +23293,12 @@ arm_expand_prologue (void) /* The static chain register is the same as the IP register. If it is clobbered when creating the frame, we need to save and restore it. */ clobber_ip = IS_NESTED (func_type) - && ((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) - || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK - || flag_stack_clash_protection) - && !df_regs_ever_live_p (LR_REGNUM) - && arm_r3_live_at_start_p ())); + && (((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) + || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK + || flag_stack_clash_protection) + && !df_regs_ever_live_p (LR_REGNUM) + && arm_r3_live_at_start_p ())) + || (arm_pac_enabled_for_curr_function_p ())); /* Find somewhere to store IP whilst the frame is being created. We try the following places in order: @@ -23368,6 +23374,14 @@ arm_expand_prologue (void) } } + if (arm_pac_enabled_for_curr_function_p ()) + { + if (aarch_bti_enabled ()) + emit_insn (gen_pacbti_ip_lr_sp ()); + else + emit_insn (gen_pac_ip_lr_sp ()); + } + if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) { if (IS_INTERRUPT (func_type)) @@ -23490,6 +23504,9 @@ arm_expand_prologue (void) if (! IS_VOLATILE (func_type)) saved_regs += arm_save_coproc_regs (); + if (arm_pac_enabled_for_curr_function_p ()) + emit_multi_reg_push (1 << IP_REGNUM, 1 << IP_REGNUM); + if (frame_pointer_needed && TARGET_ARM) { /* Create the new frame pointer. */ @@ -27150,7 +27167,8 @@ thumb2_expand_return (bool simple_return) to assert it for now to ensure that future code changes do not silently change this behavior. */ gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ())); - if (num_regs == 1) + if (num_regs == 1 + && !(arm_pac_enabled_for_curr_function_p ())) { rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); rtx reg = gen_rtx_REG (SImode, PC_REGNUM); @@ -27165,13 +27183,34 @@ thumb2_expand_return (bool simple_return) } else { - saved_regs_mask &= ~ (1 << LR_REGNUM); - saved_regs_mask |= (1 << PC_REGNUM); - arm_emit_multi_reg_pop (saved_regs_mask); + if (arm_pac_enabled_for_curr_function_p ()) + { + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (4))); + arm_emit_multi_reg_pop (1 << IP_REGNUM); + saved_regs_mask &= ~ (1 << PC_REGNUM); + arm_emit_multi_reg_pop (saved_regs_mask); + emit_insn (gen_aut_ip_lr_sp ()); + emit_jump_insn (simple_return_rtx); + } + else + { + saved_regs_mask &= ~ (1 << LR_REGNUM); + saved_regs_mask |= (1 << PC_REGNUM); + arm_emit_multi_reg_pop (saved_regs_mask); + } } } else { + if (arm_pac_enabled_for_curr_function_p ()) + { + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (4))); + arm_emit_multi_reg_pop (1 << IP_REGNUM); + emit_insn (gen_aut_ip_lr_sp ()); + } + if (IS_CMSE_ENTRY (arm_current_func_type ())) cmse_nonsecure_entry_clear_before_return (); emit_jump_insn (simple_return_rtx); @@ -27469,6 +27508,9 @@ arm_expand_epilogue (bool really_return) /* In Thumb-2 mode, the frame pointer points to the last saved register. */ amount = offsets->locals_base - offsets->saved_regs; + if (arm_pac_enabled_for_curr_function_p ()) + amount += 4; + if (amount) { insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, @@ -27497,6 +27539,10 @@ arm_expand_epilogue (bool really_return) /* Pop off outgoing args and local frame to adjust stack pointer to last saved register. */ amount = offsets->outgoing_args - offsets->saved_regs; + + if (arm_pac_enabled_for_curr_function_p ()) + amount += 4; + if (amount) { rtx_insn *tmp; @@ -27562,6 +27608,9 @@ arm_expand_epilogue (bool really_return) stack_pointer_rtx, stack_pointer_rtx); } + if (arm_pac_enabled_for_curr_function_p ()) + arm_emit_multi_reg_pop (1 << IP_REGNUM); + if (saved_regs_mask) { rtx insn; @@ -27574,7 +27623,8 @@ arm_expand_epilogue (bool really_return) && really_return && crtl->args.pretend_args_size == 0 && saved_regs_mask & (1 << LR_REGNUM) - && !crtl->calls_eh_return) + && !crtl->calls_eh_return + && !arm_pac_enabled_for_curr_function_p ()) { saved_regs_mask &= ~(1 << LR_REGNUM); saved_regs_mask |= (1 << PC_REGNUM); @@ -27688,6 +27738,9 @@ arm_expand_epilogue (bool really_return) } } + if (arm_pac_enabled_for_curr_function_p ()) + emit_insn (gen_aut_ip_lr_sp ()); + if (!really_return) return; @@ -30393,6 +30446,9 @@ arm_conditional_register_usage (void) global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; } + if (TARGET_HAVE_PACBTI) + call_used_regs[IP_REGNUM] = 1; + /* The Q and GE bits are only accessed via special ACLE patterns. */ CLEAR_HARD_REG_BIT (operand_reg_set, APSRQ_REGNUM); CLEAR_HARD_REG_BIT (operand_reg_set, APSRGE_REGNUM); @@ -32822,6 +32878,15 @@ arm_fusion_enabled_p (tune_params::fuse_ops op) return current_tune->fusible_ops & op; } +/* Return TRUE if return address signing mechanism is enabled. */ +static bool +arm_pac_enabled_for_curr_function_p (void) +{ + return aarch_ra_sign_scope == AARCH_FUNCTION_ALL + || (aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF + && !crtl->is_leaf); +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4adc976b8b6..132135d244d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12823,6 +12823,26 @@ (set_attr "length" "8")] ) +(define_insn "pac_ip_lr_sp" + [(set (reg:DI IP_REGNUM) + (unspec:DI [(reg:DI SP_REGNUM) (reg:DI LR_REGNUM)] + UNSPEC_PAC_IP_LR_SP))] + "" + "pac\tr12, lr, sp") + +(define_insn "pacbti_ip_lr_sp" + [(set (reg:DI IP_REGNUM) + (unspec:DI [(reg:DI SP_REGNUM) (reg:DI LR_REGNUM)] + UNSPEC_PACBTI_IP_LR_SP))] + "" + "pacbti\tr12, lr, sp") + +(define_insn "aut_ip_lr_sp" + [(unspec:DI [(reg:DI IP_REGNUM) (reg:DI SP_REGNUM) (reg:DI LR_REGNUM)] + UNSPEC_AUT_IP_LR_SP)] + "" + "aut\tr12, lr, sp") + ;; Vector bits common to IWMMXT, Neon and MVE (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index ad1c6edd005..d60d0ceb87c 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -159,6 +159,9 @@ UNSPEC_VCDE ; Custom Datapath Extension instruction. UNSPEC_VCDEA ; Custom Datapath Extension instruction. UNSPEC_DLS ; Used for DLS (Do Loop Start), Armv8.1-M Mainline instruction + UNSPEC_PAC_IP_LR_SP ; Represents PAC signing LR + UNSPEC_PACBTI_IP_LR_SP ; Represents PAC signing LR + valid landing pad + UNSPEC_AUT_IP_LR_SP ; Represents PAC verifying LR ]) diff --git a/gcc/testsuite/gcc.target/arm/pac-1.c b/gcc/testsuite/gcc.target/arm/pac-1.c new file mode 100644 index 00000000000..8979a554e63 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-1.c @@ -0,0 +1,25 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + return a + b; +} + +int +main (void) +{ + if (foo1 (1, 2) != 3) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tr12, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tr12, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-2.c b/gcc/testsuite/gcc.target/arm/pac-2.c new file mode 100644 index 00000000000..678294af67d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-2.c @@ -0,0 +1,25 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret -mthumb --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + return a + b; +} + +int +main (void) +{ + if (foo1 (1, 2) != 3) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler "pac\tr12, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tr12, lr, sp" } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-3.c b/gcc/testsuite/gcc.target/arm/pac-3.c new file mode 100644 index 00000000000..e67ee910683 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-3.c @@ -0,0 +1,25 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=bti+pac-ret+leaf -mthumb --save-temps -O2" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + return a + b; +} + +int +main (void) +{ + if (foo1 (1, 2) != 3) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pacbti\tr12, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tr12, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-4.c b/gcc/testsuite/gcc.target/arm/pac-4.c new file mode 100644 index 00000000000..404457313a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-4.c @@ -0,0 +1,25 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main+pacbti -mthumb --save-temps -O2" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + return a + b; +} + +int +main (void) +{ + if (foo1 (1, 2) != 3) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-not "\tbti\t" } } */ +/* { dg-final { scan-assembler-not "\tpac\t" } } */ +/* { dg-final { scan-assembler-not "\tpacbti\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-5.c b/gcc/testsuite/gcc.target/arm/pac-5.c new file mode 100644 index 00000000000..d2d996b921a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-5.c @@ -0,0 +1,26 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + int square (int z) { return z * z; } + return square (a) + square (b); +} + +int +main (void) +{ + if (foo1 (1, 2) != 5) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tr12, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "aut\tr12, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ From patchwork Fri Nov 5 08:55:53 2021 Content-Type: text/plain; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(235185007)(2616005)(508600001)(8936002)(6916009)(36756003)(316002)(36860700001)(54906003)(2906002)(5660300002)(47076005)(82310400003)(81166007)(6666004)(33964004)(426003)(336012)(70586007)(186003)(44832011)(8676002)(26005)(70206006)(86362001)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2021 08:56:04.0219 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5301bf6-b74e-4e5b-3523-08d9a03a1933 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT039.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7084 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: nd , Richard Earnshaw Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, this patch enables Branch Target Identification Armv8.1-M Mechanism [1]. This is achieved by moving and generalizing the Aarch64 "bti" pass so it can be used also by the Arm backend. The pass iterates through the instructions and adds the necessary BTI instructions at the beginning of every function and at every landing pads targeted by indirect jumps. Regressioned and arm-linux-gnu aarch64-linux-gnu bootstraped. Best Regards Andrea [1] From 3fc8c64d20efd618b72e4527b7486d779fdaf13b Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 28 Jul 2021 15:49:16 +0200 Subject: [PATCH 2/2] [PATCH] [2/2] arm: add arm bti pass gcc/ChangeLog 2021-11-03 Andrea Corallo * config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into 'aarch-bti-insert.o'. (arm*-*-*): Add 'aarch-bti-insert.o'. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Update. * config/aarch64/aarch64-protos.h (aarch64_bti_enabled): Remove proto. * config/aarch64/aarch64.c (aarch_bti_enabled): Rename from 'aarch64_bti_enabled'. (aarch_bti_j_insn_p, aarch_pac_insn_p, aarch_gen_bti_c) (aarch_gen_bti_j): New functions. (aarch64_output_mi_thunk) (aarch64_print_patchable_function_entry) (aarch64_file_end_indicate_exec_stack): Update. * config/aarch64/t-aarch64 (aarch-bti-insert.o): Rename from 'aarch64-bti-insert.o' and account for new folder. * config/arm/aarch-bti-insert.c: New file, rename from 'gcc/config/aarch64/aarch64-bti-insert.c' and generalize. * config/arm/aarch-common-protos.h (aarch_bti_enabled) (aarch_bti_j_insn_p, aarch_pac_insn_p, aarch_gen_bti_c) (aarch_gen_bti_j): New protos. * config/arm/arm-passes.def: New file. * config/arm/arm-protos.h (make_pass_insert_bti): New proto. * config/arm/arm.c (aarch_bti_enabled, aarch_bti_j_insn_p) (aarch_pac_insn_p, aarch_gen_bti_c, aarch_pac_insn_p): New functions. * config/arm/arm.md (bti): Add pattern. * config/arm/t-arm (aarch-bti-insert.o): Add rule. * config/arm/unspecs.md (UNSPECV_BTI): New unspec. gcc/testsuite/ChangeLog 2021-09-15 Andrea Corallo * gcc.target/arm/bti-1.c: New testcase. * gcc.target/arm/bti-2.c: Likewise. --- gcc/config.gcc | 4 +- gcc/config/aarch64/aarch64-c.c | 2 +- gcc/config/aarch64/aarch64-protos.h | 1 - gcc/config/aarch64/aarch64.c | 58 ++++++++++++++-- gcc/config/aarch64/t-aarch64 | 4 +- .../aarch-bti-insert.c} | 66 ++++--------------- gcc/config/arm/aarch-common-protos.h | 5 ++ gcc/config/arm/arm-passes.def | 21 ++++++ gcc/config/arm/arm-protos.h | 2 + gcc/config/arm/arm.c | 50 ++++++++++++++ gcc/config/arm/arm.md | 6 ++ gcc/config/arm/t-arm | 10 +++ gcc/config/arm/unspecs.md | 1 + gcc/testsuite/gcc.target/arm/bti-1.c | 12 ++++ gcc/testsuite/gcc.target/arm/bti-2.c | 58 ++++++++++++++++ 15 files changed, 237 insertions(+), 63 deletions(-) rename gcc/config/{aarch64/aarch64-bti-insert.c => arm/aarch-bti-insert.c} (80%) create mode 100644 gcc/config/arm/arm-passes.def create mode 100644 gcc/testsuite/gcc.target/arm/bti-1.c create mode 100644 gcc/testsuite/gcc.target/arm/bti-2.c diff --git a/gcc/config.gcc b/gcc/config.gcc index fb1f06f3da8..5e3114c7f0c 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -328,7 +328,7 @@ aarch64*-*-*) c_target_objs="aarch64-c.o" cxx_target_objs="aarch64-c.o" d_target_objs="aarch64-d.o" - extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch64-bti-insert.o aarch64-cc-fusion.o" + extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch-bti-insert.o aarch64-cc-fusion.o" target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.c \$(srcdir)/config/aarch64/aarch64-sve-builtins.h \$(srcdir)/config/aarch64/aarch64-sve-builtins.cc" target_has_targetm_common=yes ;; @@ -352,7 +352,7 @@ arc*-*-*) ;; arm*-*-*) cpu_type=arm - extra_objs="arm-builtins.o aarch-common.o" + extra_objs="arm-builtins.o aarch-common.o aarch-bti-insert.o" extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve_types.h arm_mve.h arm_cde.h" target_type_format_char='%' c_target_objs="arm-c.o" diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index 3518e9ab6ca..a3d43c60f39 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -179,7 +179,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile); aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile); - aarch64_def_or_undef (aarch64_bti_enabled (), + aarch64_def_or_undef (aarch_bti_enabled (), "__ARM_FEATURE_BTI_DEFAULT", pfile); cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT"); diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index b1dc87bcbdc..9e77f4b6115 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -876,7 +876,6 @@ void aarch64_register_pragmas (void); void aarch64_relayout_simd_types (void); void aarch64_reset_previous_fndecl (void); bool aarch64_return_address_signing_enabled (void); -bool aarch64_bti_enabled (void); void aarch64_save_restore_target_globals (tree); void aarch64_addti_scratch_regs (rtx, rtx, rtx *, rtx *, rtx *, diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d2e1324520f..59d08a8d39f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7705,11 +7705,61 @@ aarch64_return_address_signing_enabled (void) /* Return TRUE if Branch Target Identification Mechanism is enabled. */ bool -aarch64_bti_enabled (void) +aarch_bti_enabled (void) { return (aarch_enable_bti == 1); } +/* Check if INSN is a BTI J insn. */ +bool +aarch_bti_j_insn_p (rtx_insn *insn) +{ + if (!insn || !INSN_P (insn)) + return false; + + rtx pat = PATTERN (insn); + return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J; +} + +/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */ +bool +aarch_pac_insn_p (rtx x) +{ + if (!INSN_P (x)) + return false; + + subrtx_var_iterator::array_type array; + FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL) + { + rtx sub = *iter; + if (sub && GET_CODE (sub) == UNSPEC) + { + int unspec_val = XINT (sub, 1); + switch (unspec_val) + { + case UNSPEC_PACIASP: + case UNSPEC_PACIBSP: + return true; + + default: + return false; + } + iter.skip_subrtxes (); + } + } + return false; +} + +rtx aarch_gen_bti_c (void) +{ + return gen_bti_c (); +} + +rtx aarch_gen_bti_j (void) +{ + return gen_bti_j (); +} + /* The caller is going to use ST1D or LD1D to save or restore an SVE register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by: @@ -9072,7 +9122,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, rtx_insn *insn; const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); - if (aarch64_bti_enabled ()) + if (aarch_bti_enabled ()) emit_insn (gen_bti_c()); reload_completed = 1; @@ -21227,7 +21277,7 @@ aarch64_print_patchable_function_entry (FILE *file, bool record_p) { if (cfun->machine->label_is_assembled - && aarch64_bti_enabled () + && aarch_bti_enabled () && !cgraph_node::get (cfun->decl)->only_called_directly_p ()) { /* Remove the BTI that follows the patch area and insert a new BTI @@ -25371,7 +25421,7 @@ aarch64_file_end_indicate_exec_stack () file_end_indicate_exec_stack (); unsigned feature_1_and = 0; - if (aarch64_bti_enabled ()) + if (aarch_bti_enabled ()) feature_1_and |= GNU_PROPERTY_AARCH64_FEATURE_1_BTI; if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE) diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64 index 7e1606c47ac..f6ace450e17 100644 --- a/gcc/config/aarch64/t-aarch64 +++ b/gcc/config/aarch64/t-aarch64 @@ -149,14 +149,14 @@ falkor-tag-collision-avoidance.o: \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/aarch64/falkor-tag-collision-avoidance.c -aarch64-bti-insert.o: $(srcdir)/config/aarch64/aarch64-bti-insert.c \ +aarch-bti-insert.o: $(srcdir)/config/arm/aarch-bti-insert.c \ $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \ dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \ output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \ $(CONTEXT_H) $(TREE_PASS_H) regrename.h \ $(srcdir)/config/aarch64/aarch64-protos.h $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ - $(srcdir)/config/aarch64/aarch64-bti-insert.c + $(srcdir)/config/arm/aarch-bti-insert.c aarch64-cc-fusion.o: $(srcdir)/config/aarch64/aarch64-cc-fusion.cc \ $(CONFIG_H) $(SYSTEM_H) $(CORETYPES_H) $(BACKEND_H) $(RTL_H) $(DF_H) \ diff --git a/gcc/config/aarch64/aarch64-bti-insert.c b/gcc/config/arm/aarch-bti-insert.c similarity index 80% rename from gcc/config/aarch64/aarch64-bti-insert.c rename to gcc/config/arm/aarch-bti-insert.c index 5d6bc169d6b..6b03238470b 100644 --- a/gcc/config/aarch64/aarch64-bti-insert.c +++ b/gcc/config/arm/aarch-bti-insert.c @@ -1,4 +1,4 @@ -/* Branch Target Identification for AArch64 architecture. +/* Branch Target Identification for Arm/AArch64 architecture. Copyright (C) 2019-2021 Free Software Foundation, Inc. Contributed by Arm Ltd. @@ -42,10 +42,11 @@ #include "tree-pass.h" #include "cgraph.h" -/* This pass enables the support for Branch Target Identification Mechanism - for AArch64. This is a new security feature introduced in ARMv8.5-A - archtitecture. A BTI instruction is used to guard against the execution - of instructions which are not the intended target of an indirect branch. +/* This pass enables the support for Branch Target Identification Mechanism for + Arm/AArch64. This is a security feature introduced in ARMv8.5-A + architecture and ARMv8.1-M. A BTI instruction is used to guard against the + execution of instructions which are not the intended target of an indirect + branch. Outside of a guarded memory region, a BTI instruction executes as a NOP. Within a guarded memory region any target of an indirect branch must be @@ -90,47 +91,6 @@ const pass_data pass_data_insert_bti = 0, /* todo_flags_finish. */ }; -/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */ -static bool -aarch64_pac_insn_p (rtx x) -{ - if (!INSN_P (x)) - return false; - - subrtx_var_iterator::array_type array; - FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL) - { - rtx sub = *iter; - if (sub && GET_CODE (sub) == UNSPEC) - { - int unspec_val = XINT (sub, 1); - switch (unspec_val) - { - case UNSPEC_PACIASP: - /* fall-through. */ - case UNSPEC_PACIBSP: - return true; - - default: - return false; - } - iter.skip_subrtxes (); - } - } - return false; -} - -/* Check if INSN is a BTI J insn. */ -static bool -aarch64_bti_j_insn_p (rtx_insn *insn) -{ - if (!insn || !INSN_P (insn)) - return false; - - rtx pat = PATTERN (insn); - return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J; -} - /* Insert the BTI instruction. */ /* This is implemented as a late RTL pass that runs before branch shortening and does the following. */ @@ -155,7 +115,7 @@ rest_of_insert_bti (void) && (LABEL_PRESERVE_P (insn) || bb->flags & BB_NON_LOCAL_GOTO_TARGET)) { - bti_insn = gen_bti_j (); + bti_insn = aarch_gen_bti_j (); emit_insn_after (bti_insn, insn); continue; } @@ -177,10 +137,10 @@ rest_of_insert_bti (void) { label = as_a (XEXP (RTVEC_ELT (vec, j), 0)); rtx_insn *next = next_nonnote_nondebug_insn (label); - if (aarch64_bti_j_insn_p (next)) + if (aarch_bti_j_insn_p (next)) continue; - bti_insn = gen_bti_j (); + bti_insn = aarch_gen_bti_j (); emit_insn_after (bti_insn, label); } } @@ -191,7 +151,7 @@ rest_of_insert_bti (void) will return. */ if (CALL_P (insn) && (find_reg_note (insn, REG_SETJMP, NULL))) { - bti_insn = gen_bti_j (); + bti_insn = aarch_gen_bti_j (); emit_insn_after (bti_insn, insn); continue; } @@ -207,9 +167,9 @@ rest_of_insert_bti (void) { bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb; insn = BB_HEAD (bb); - if (!aarch64_pac_insn_p (get_first_nonnote_insn ())) + if (!aarch_pac_insn_p (get_first_nonnote_insn ())) { - bti_insn = gen_bti_c (); + bti_insn = aarch_gen_bti_c (); emit_insn_before (bti_insn, insn); } } @@ -229,7 +189,7 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { - return aarch64_bti_enabled (); + return aarch_bti_enabled (); } virtual unsigned int execute (function *) diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index bea0f306ecf..16e6ae92a60 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -42,6 +42,11 @@ extern int arm_no_early_alu_shift_value_dep (rtx, rtx); extern int arm_no_early_mul_dep (rtx, rtx); extern int arm_no_early_store_addr_dep (rtx, rtx); extern bool arm_rtx_shift_left_p (rtx); +extern bool aarch_bti_enabled (void); +extern bool aarch_bti_j_insn_p (rtx_insn *); +extern bool aarch_pac_insn_p (rtx); +extern rtx aarch_gen_bti_c (void); +extern rtx aarch_gen_bti_j (void); /* RTX cost table definitions. These are used when tuning for speed rather than for size and should reflect the _additional_ cost over the cost diff --git a/gcc/config/arm/arm-passes.def b/gcc/config/arm/arm-passes.def new file mode 100644 index 00000000000..beecd2b5455 --- /dev/null +++ b/gcc/config/arm/arm-passes.def @@ -0,0 +1,21 @@ +/* Arm-specific passes declarations. + Copyright (C) 2021 Free Software Foundation, Inc. + Contributed by Arm Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_bti); diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 463ecdc4f36..01413c4f6a3 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -24,6 +24,8 @@ #include "sbitmap.h" +rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt); + extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); extern int use_return_insn (int, rtx); extern bool use_simple_return_p (void); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 2889a471fa5..a3e34747ba5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -32887,6 +32887,56 @@ arm_pac_enabled_for_curr_function_p (void) && !crtl->is_leaf); } +/* Return TRUE if Branch Target Identification Mechanism is enabled. */ +bool +aarch_bti_enabled (void) +{ + return aarch_enable_bti == 1; +} + +/* Check if INSN is a BTI J insn. */ +bool +aarch_bti_j_insn_p (rtx_insn *insn) +{ + if (!insn || !INSN_P (insn)) + return false; + + rtx pat = PATTERN (insn); + return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI; +} + +/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */ +bool +aarch_pac_insn_p (rtx x) +{ + if (!x || !INSN_P (x)) + return false; + + rtx pat = PATTERN (x); + + if (GET_CODE (pat) == SET) + { + rtx tmp = XEXP (pat, 1); + if (tmp + && GET_CODE (tmp) == UNSPEC + && (XINT (tmp, 1) == UNSPEC_PAC_IP_LR_SP + || XINT (tmp, 1) == UNSPEC_PACBTI_IP_LR_SP)) + return true; + } + + return false; +} + +rtx aarch_gen_bti_c (void) +{ + return gen_bti (); +} + +rtx aarch_gen_bti_j (void) +{ + return gen_bti (); +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 132135d244d..564170dc450 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12843,6 +12843,12 @@ "" "aut\tr12, lr, sp") +(define_insn "bti" + [(unspec_volatile [(const_int 0)] UNSPECV_BTI)] + "" + "bti" + [(set_attr "type" "mov_reg")]) + ;; Vector bits common to IWMMXT, Neon and MVE (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 5f69ee6451e..358f7e5a707 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -165,3 +165,13 @@ arm-d.o: $(srcdir)/config/arm/arm-d.c arm-common.o: arm-cpu-cdata.h driver-arm.o: arm-native.h + +PASSES_EXTRA += $(srcdir)/config/arm/arm-passes.def + +aarch-bti-insert.o: $(srcdir)/config/arm/aarch-bti-insert.c \ + $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \ + dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \ + output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \ + $(CONTEXT_H) $(TREE_PASS_H) regrename.h + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/arm/aarch-bti-insert.c diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index d60d0ceb87c..c9dadefd17d 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -162,6 +162,7 @@ UNSPEC_PAC_IP_LR_SP ; Represents PAC signing LR UNSPEC_PACBTI_IP_LR_SP ; Represents PAC signing LR + valid landing pad UNSPEC_AUT_IP_LR_SP ; Represents PAC verifying LR + UNSPECV_BTI ; Represent BTI ]) diff --git a/gcc/testsuite/gcc.target/arm/bti-1.c b/gcc/testsuite/gcc.target/arm/bti-1.c new file mode 100644 index 00000000000..230ebb5a1da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bti-1.c @@ -0,0 +1,12 @@ +/* Check that GCC does bti instruction. */ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ +/* { dg-options "-march=armv8.1-m.main -mthumb -mbranch-protection=bti --save-temps" } */ + +int +main (void) +{ + return 0; +} + +/* { dg-final { scan-assembler "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/bti-2.c b/gcc/testsuite/gcc.target/arm/bti-2.c new file mode 100644 index 00000000000..35aef6992e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bti-2.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* -Os to create jump table. */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ +/* { dg-options "-march=armv8.1-m.main -mthumb -mbranch-protection=bti --save-temps" } */ + +extern int f1 (void); +extern int f2 (void); +extern int f3 (void); +extern int f4 (void); +extern int f5 (void); +extern int f6 (void); +extern int f7 (void); +extern int f8 (void); +extern int f9 (void); +extern int f10 (void); + +int (*ptr) (void); + +int +f_jump_table (int y, int n) +{ + int i; + for (i = 0; i < n ;i ++) + { + switch (y) + { + case 0 : ptr = f1; break; + case 1 : ptr = f2; break; + case 2 : ptr = f3; break; + case 3 : ptr = f4; break; + case 4 : ptr = f5; break; + case 5 : ptr = f6; break; + case 6 : ptr = f7; break; + case 7 : ptr = f8; break; + case 8 : ptr = f9; break; + case 9 : ptr = f10; break; + default: break; + } + y += ptr (); + } + return (y == 0)? y+1:4; +} + +int +f_label_address () +{ + static void * addr = &&lab1; + goto *addr; +lab1: + addr = &&lab2; + return 1; +lab2: + addr = &&lab1; + return 2; +} + +/* { dg-final { scan-assembler-times "bti" 15 } } */