From patchwork Fri Feb 21 09:57:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: daichengrong X-Patchwork-Id: 106951 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2B4BA3858C2F for ; Fri, 21 Feb 2025 09:59:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2B4BA3858C2F X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 63D9A3858C2A for ; Fri, 21 Feb 2025 09:57:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 63D9A3858C2A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 63D9A3858C2A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1740131872; cv=none; b=kMPyDf9vJQU1RNHklSpwwexyNW+yoI34gwdSJj7LP2rW5t5tMfgbrAGHn6yvkq7YT+MXLsssBUsoBLyUy2s+KAGG7e/4h5Xqb6D2uV7hDmzWw7QT1QDKXH9Gxag6HJeRX7GqUhFKcfKh9iDtmpDhgMrVe01lQ1SxB9OGwY3TA8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1740131872; c=relaxed/simple; bh=wYPZ0OcVxnrrQVBQT+r0/ngaPavEggWllum3z7NACEU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=NvWSTAQGxwblRgR7tebngkASjTLHSr0qrwLZ/o+vpPgiqf9qoG8xx2EKnnOggjduhIde1BAU8I5SLYnPZXGpTb4wEcsmjoVffNbgxPuzPJIcaA+Eypnn6JHj+R95H4teX0f0On12tbOV6XRyyo2H0NBg5Tb78fyQs1HmE9Yz4pk= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 63D9A3858C2A Received: from chengrong-ubuntu-02.home.arpa (unknown [124.16.138.129]) by APP-03 (Coremail) with SMTP id rQCowAAX_jAVTrhnrXEdDw--.13464S3; Fri, 21 Feb 2025 17:57:43 +0800 (CST) From: daichengrong@iscas.ac.cn To: libc-alpha@sourceware.org Cc: aswaterman@gmail.com, palmer@rivosinc.com, adhemerval.zanella@linaro.org, darius@bluespec.com, jiageng08@iscas.ac.cn, enh@google.com Subject: [PATCH v7 1/2] RISC-V: check rvv support in asm at sysdeps/riscv Date: Fri, 21 Feb 2025 17:57:39 +0800 Message-Id: <20250221095740.582183-2-daichengrong@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221095740.582183-1-daichengrong@iscas.ac.cn> References: <20250221095740.582183-1-daichengrong@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: rQCowAAX_jAVTrhnrXEdDw--.13464S3 X-Coremail-Antispam: 1UD129KBjvJXoWxWF4rWFykXr18ur15WrWrAFb_yoW5Aw1DpF ySkr1rGasxJrn3CanIyry0gr4rJF4rGr1rJw1fAw4UJaykAayDZ39ruw1ayws5uF95XF98 Cr18K3W7C398ArDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm2b7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r4j6ryUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_JFI_Gr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280 aVCY1x0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzV Aqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAFwI0_Gr1j6F4UJwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lw4CEc2x0rVAKj4xxMxkF7I0En4 kS14v26r126r1DMxkIecxEwVAFwVW8uwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVF xhVjvjDU0xZFpf9x07bzrchUUUUU= X-Originating-IP: [124.16.138.129] X-CM-SenderInfo: pgdluxxhqj201qj6x2xfdvhtffof0/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org From: daichengrong Changes in v7: update asm rvv support check with option,+v Changes in v5: update riscv vector support check in assembler update vector support macro to HAVE_RISCV_ASM_VECTOR_SUPPORT --- config.h.in | 3 +++ sysdeps/riscv/configure | 35 +++++++++++++++++++++++++++++++++++ sysdeps/riscv/configure.ac | 25 +++++++++++++++++++++++++ 3 files changed, 63 insertions(+) mode change 100644 => 100755 sysdeps/riscv/configure diff --git a/config.h.in b/config.h.in index cdbd555366..7802e8f9c4 100644 --- a/config.h.in +++ b/config.h.in @@ -139,6 +139,9 @@ /* RISC-V floating-point ABI for ld.so. */ #undef RISCV_ABI_FLEN +/* Define if assembler supports vector instructions on RISC-V. */ +#undef HAVE_RISCV_ASM_VECTOR_SUPPORT + /* LOONGARCH integer ABI for ld.so. */ #undef LOONGARCH_ABI_GRLEN diff --git a/sysdeps/riscv/configure b/sysdeps/riscv/configure old mode 100644 new mode 100755 index 3ae4ae3bdb..bbda6a0d4a --- a/sysdeps/riscv/configure +++ b/sysdeps/riscv/configure @@ -83,3 +83,38 @@ if test "$libc_cv_static_pie_on_riscv" = yes; then fi +# Check if assembler supports attribute riscv vector macro. +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for gcc attribute riscv vector support" >&5 +printf %s "checking for gcc attribute riscv vector support... " >&6; } +if test ${libc_cv_gcc_rvv+y} +then : + printf %s "(cached) " >&6 +else case e in #( + e) cat > conftest.S <&5 \ + 2>&5 ; then + libc_cv_gcc_rvv=yes +fi +rm -f conftest* ;; +esac +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_gcc_rvv" >&5 +printf "%s\n" "$libc_cv_gcc_rvv" >&6; } + +if test x"$libc_cv_gcc_rvv" = xyes; then + printf "%s\n" "#define HAVE_RISCV_ASM_VECTOR_SUPPORT 1" >>confdefs.h + +fi + +config_vars="$config_vars +have-gcc-riscv-rvv = $libc_cv_gcc_rvv" + + diff --git a/sysdeps/riscv/configure.ac b/sysdeps/riscv/configure.ac index ee3d1ed014..27e0e51b1c 100644 --- a/sysdeps/riscv/configure.ac +++ b/sysdeps/riscv/configure.ac @@ -43,3 +43,28 @@ EOF if test "$libc_cv_static_pie_on_riscv" = yes; then AC_DEFINE(SUPPORT_STATIC_PIE) fi + +# Check if assembler supports attribute riscv vector macro. +AC_CACHE_CHECK([for gcc attribute riscv vector support], + libc_cv_gcc_rvv, [dnl +cat > conftest.S <&AS_MESSAGE_LOG_FD \ + 2>&AS_MESSAGE_LOG_FD ; then + libc_cv_gcc_rvv=yes +fi +rm -f conftest*]) + +if test x"$libc_cv_gcc_rvv" = xyes; then + AC_DEFINE(HAVE_RISCV_ASM_VECTOR_SUPPORT) +fi + +LIBC_CONFIG_VAR([have-gcc-riscv-rvv], [$libc_cv_gcc_rvv]) + From patchwork Fri Feb 21 09:57:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: daichengrong X-Patchwork-Id: 106950 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F05CF385840E for ; Fri, 21 Feb 2025 09:58:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F05CF385840E X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 444FA3858C66 for ; Fri, 21 Feb 2025 09:57:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 444FA3858C66 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; 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Fri, 21 Feb 2025 17:57:44 +0800 (CST) From: daichengrong@iscas.ac.cn To: libc-alpha@sourceware.org Cc: aswaterman@gmail.com, palmer@rivosinc.com, adhemerval.zanella@linaro.org, darius@bluespec.com, jiageng08@iscas.ac.cn, enh@google.com Subject: [PATCH v7 2/2] RISC-V: add riscv vector support for memcpy Date: Fri, 21 Feb 2025 17:57:40 +0800 Message-Id: <20250221095740.582183-3-daichengrong@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250221095740.582183-1-daichengrong@iscas.ac.cn> References: <20250221095740.582183-1-daichengrong@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: rQCowAAX_jAVTrhnrXEdDw--.13464S4 X-Coremail-Antispam: 1UD129KBjvJXoW3WrW3Cr1rAw45ZrWfWr1kAFb_yoW7CryrpF Z5C3W5KFZ5Jr1xGrWSkw1jg3W5Zry8JF1Yk34Y93yUA3yjqr4xJa92ywn8KFyDJrWSkFWf ZF1kWF1qkay5ZaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm2b7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUXwA2048vs2IY020Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280 aVCY1x0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzV Aqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAFwI0_Gr1j6F4UJwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lw4CEc2x0rVAKj4xxMxkF7I0En4 kS14v26r126r1DMxkIecxEwVAFwVW8uwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVF xhVjvjDU0xZFpf9x07b4NVkUUUUU= X-Originating-IP: [124.16.138.129] X-CM-SenderInfo: pgdluxxhqj201qj6x2xfdvhtffof0/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org From: daichengrong Change in v7: update dl_hwcap support using kernel header update rvv memcpy compile with option,+v delete optimization for small lengths Change in v6: Optimize the RVV memcpy for small lengths less than VLEN/8 bytes Changes in v5: check ifunc-impl-list memcpy vector support with by dl_hwcap Changes in v4: update rvv memcpy support by compiler check whether rvv enabled by dl_hwcap Changes in v2: delete size-0 branch Tested-by: Anton Blanchard Tested-by: daichengrogn --- sysdeps/riscv/multiarch/memcpy_vector.S | 37 +++++++++++++++++++ .../unix/sysv/linux/riscv/multiarch/Makefile | 6 +++ .../linux/riscv/multiarch/ifunc-impl-list.c | 14 +++++++ .../unix/sysv/linux/riscv/multiarch/memcpy.c | 8 ++++ 4 files changed, 65 insertions(+) create mode 100644 sysdeps/riscv/multiarch/memcpy_vector.S diff --git a/sysdeps/riscv/multiarch/memcpy_vector.S b/sysdeps/riscv/multiarch/memcpy_vector.S new file mode 100644 index 0000000000..eaf28aaf6d --- /dev/null +++ b/sysdeps/riscv/multiarch/memcpy_vector.S @@ -0,0 +1,37 @@ +/* memcpy for RISC-V Vector. + Copyright (C) 2024-2025 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + + +#include +#include + +ENTRY (__memcpy_vector) +.option push +.option arch, +v + mv a6, a0 +L(loop): + vsetvli a3,a2,e8,m8,ta,ma + vle8.v v8,(a1) + vse8.v v8,(a6) + add a1,a1,a3 + sub a2,a2,a3 + add a6,a6,a3 + bnez a2,L(loop) + ret +.option pop +END (__memcpy_vector) diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile index fcef5659d4..478338006b 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile @@ -5,5 +5,11 @@ sysdep_routines += \ memcpy_noalignment \ # sysdep_routines +ifeq ($(have-gcc-riscv-rvv),yes) +sysdep_routines += \ + memcpy_vector \ + # rvv sysdep_routines +endif + CFLAGS-memcpy_noalignment.c += -mno-strict-align endif diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c index 1c1deca8f6..26f3376d23 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include size_t __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, @@ -27,6 +29,9 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, size_t i = max; bool fast_unaligned = false; +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) + bool rvv_ext = false; +#endif struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_CPUPERF_0 }; if (__riscv_hwprobe (&pair, 1, 0, NULL, 0) == 0 @@ -34,7 +39,16 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, == RISCV_HWPROBE_MISALIGNED_FAST) fast_unaligned = true; +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) + if (GLRO(dl_hwcap) & COMPAT_HWCAP_ISA_V) + rvv_ext = true; +#endif + IFUNC_IMPL (i, name, memcpy, +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) + IFUNC_IMPL_ADD (array, i, memcpy, rvv_ext, + __memcpy_vector) +#endif IFUNC_IMPL_ADD (array, i, memcpy, fast_unaligned, __memcpy_noalignment) IFUNC_IMPL_ADD (array, i, memcpy, 1, __memcpy_generic)) diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/memcpy.c b/sysdeps/unix/sysv/linux/riscv/multiarch/memcpy.c index 8544f5402a..4bedd21866 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/memcpy.c +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/memcpy.c @@ -27,16 +27,24 @@ # include # include # include +# include extern __typeof (__redirect_memcpy) __libc_memcpy; extern __typeof (__redirect_memcpy) __memcpy_generic attribute_hidden; extern __typeof (__redirect_memcpy) __memcpy_noalignment attribute_hidden; +extern __typeof (__redirect_memcpy) __memcpy_vector attribute_hidden; static inline __typeof (__redirect_memcpy) * select_memcpy_ifunc (uint64_t dl_hwcap, __riscv_hwprobe_t hwprobe_func) { unsigned long long int v; + +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) + if (dl_hwcap & COMPAT_HWCAP_ISA_V) + return __memcpy_vector; +#endif + if (__riscv_hwprobe_one (hwprobe_func, RISCV_HWPROBE_KEY_CPUPERF_0, &v) == 0 && (v & RISCV_HWPROBE_MISALIGNED_MASK) == RISCV_HWPROBE_MISALIGNED_FAST) return __memcpy_noalignment;