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Tue, 11 Feb 2025 17:17:37 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 43F4C20043; Tue, 11 Feb 2025 17:17:37 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 28F1E20040; Tue, 11 Feb 2025 17:17:37 +0000 (GMT) Received: from a8345010.lnxne.boe (unknown [9.152.108.100]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTPS; Tue, 11 Feb 2025 17:17:37 +0000 (GMT) From: Stefan Schulze Frielinghaus To: gcc-patches@gcc.gnu.org Cc: krebbel@linux.ibm.com, Stefan Schulze Frielinghaus Subject: [PATCH] s390: Fix s390_valid_shift_count() for TI mode [PR118835] Date: Tue, 11 Feb 2025 18:17:19 +0100 Message-ID: <20250211171719.3433768-1-stefansf@gcc.gnu.org> X-Mailer: git-send-email 2.47.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: i4eODLAwdtrdhLb9NMYi_lmnlF3L6y8w X-Proofpoint-ORIG-GUID: i4eODLAwdtrdhLb9NMYi_lmnlF3L6y8w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-11_07,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 phishscore=0 lowpriorityscore=0 clxscore=1034 malwarescore=0 spamscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502110111 X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, KAM_SHORT, LOCAL_AUTHENTICATION_FAIL_SPF, PROLO_LEO1, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NEUTRAL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org During combine we may end up with (set (reg:DI 66 [ _6 ]) (ashift:DI (reg:DI 72 [ x ]) (subreg:QI (and:TI (reg:TI 67 [ _1 ]) (const_wide_int 0x0aaaaaaaaaaaaaabf)) 15))) where the shift count operand does not trivially fit the scheme of address operands. Reject those operands, especially since strip_address_mutations() expects expressions of the form (and ... (const_int ...)) and fails for (and ... (const_wide_int ...)). While on it, fix indentation of the if block. gcc/ChangeLog: PR target/118835 * config/s390/s390.cc (s390_valid_shift_count): Reject shift count operands which do not trivially fit the scheme of address operands. gcc/testsuite/ChangeLog: * gcc.target/s390/pr118835.c: New test. --- Bootstrap and regtest are still running. Assuming they finish without regressions and there are no further comments, I will push this. gcc/config/s390/s390.cc | 37 ++++++++++++++---------- gcc/testsuite/gcc.target/s390/pr118835.c | 21 ++++++++++++++ 2 files changed, 43 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/s390/pr118835.c diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index 1d96df49fea..c2636c54613 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -3510,26 +3510,33 @@ s390_valid_shift_count (rtx op, HOST_WIDE_INT implicit_mask) /* Check for an and with proper constant. */ if (GET_CODE (op) == AND) - { - rtx op1 = XEXP (op, 0); - rtx imm = XEXP (op, 1); + { + rtx op1 = XEXP (op, 0); + rtx imm = XEXP (op, 1); - if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1)) - op1 = XEXP (op1, 0); + if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1)) + op1 = XEXP (op1, 0); - if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS)) - return false; + if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS)) + return false; - if (!immediate_operand (imm, GET_MODE (imm))) - return false; + if (!immediate_operand (imm, GET_MODE (imm))) + return false; - HOST_WIDE_INT val = INTVAL (imm); - if (implicit_mask > 0 - && (val & implicit_mask) != implicit_mask) - return false; + /* Reject shift count operands which do not trivially fit the scheme of + address operands. Especially since strip_address_mutations() expects + expressions of the form (and ... (const_int ...)) and fails for + (and ... (const_wide_int ...)). */ + if (CONST_WIDE_INT_P (imm)) + return false; - op = op1; - } + HOST_WIDE_INT val = INTVAL (imm); + if (implicit_mask > 0 + && (val & implicit_mask) != implicit_mask) + return false; + + op = op1; + } /* Check the rest. */ return s390_decompose_addrstyle_without_index (op, NULL, NULL); diff --git a/gcc/testsuite/gcc.target/s390/pr118835.c b/gcc/testsuite/gcc.target/s390/pr118835.c new file mode 100644 index 00000000000..1ca6cd95543 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr118835.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2" } */ + +/* During combine we may end up with patterns of the form + + (set (reg:DI 66 [ _6 ]) + (ashift:DI (reg:DI 72 [ x ]) + (subreg:QI (and:TI (reg:TI 67 [ _1 ]) + (const_wide_int 0x0aaaaaaaaaaaaaabf)) + 15))) + + which should be rejected since the shift count does not trivially fit the + scheme of address operands. */ + +long +test (long x, int y) +{ + __int128 z = 0xAAAAAAAAAAAAAABF; + z &= y; + return x << z; +}