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Fri, 31 Jan 2025 17:13:01 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Robert Suchanek , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 01/61] Multilib changes Thread-Topic: [PATCH 01/61] Multilib changes Thread-Index: AQHbdANilGK0ARPPVUifehTyLEnnBQ== Date: Fri, 31 Jan 2025 17:13:01 +0000 Message-ID: <20250131171232.1018281-3-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|PR3PR09MB5442:EE_ x-ms-office365-filtering-correlation-id: 90f1b26e-fb6e-4ba5-a81a-08dd421a84af x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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The single-float/short-double combination is not immediately supportable from GCC 6 as the -fshort-double option has been removed and we do not have backend logic to implement a direct replacement. If/when we do this then it needs appropriate ABI markers to describe the additional variant. Remove final remnant of single/short config. Add the mips32r2 mips16 little endian soft-float multilib. Add big-endian, MIPS64R6, soft-float, N32/N64 Linux libs. Add MIPS32R1 HF LE Linux libraries. Add big endian microMIPSr2 hard/soft float support. Disable microMIPSr6 multilib configs. Cherry-picked 2b2481cc71284ad9db3dff60bd6cab2be678e87e, 0e3416279af1417b85d1a09b1e74327c31899a5d, e50ab07265fd8188bd4275c14b744ed2dc39116d, 32f7098d7d5bee9754c7728639a0e1cdb24d63f7, 24e261b2c9a9bea1c205cfab761c218ad50f938e, and 796ddebed418e953ba7cd5de1da42311fb1fe096 from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek Signed-off-by: Matthew Fortune Signed-off-by: Chao-ying Fu Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- config-ml.in | 25 ++- configure | 25 +++ configure.ac | 25 +++ gcc/Makefile.in | 20 ++ gcc/config.gcc | 12 +- gcc/config/mips/ml-img-elf | 12 + gcc/config/mips/ml-img-linux | 10 + gcc/config/mips/ml-mti-elf | 31 +++ gcc/config/mips/ml-mti-linux | 27 +++ gcc/config/mips/mti-elf.h | 2 + gcc/config/mips/mti-linux.h | 2 + gcc/config/mips/t-img-elf | 33 --- gcc/config/mips/t-img-linux | 38 ---- gcc/config/mips/t-mips-multi | 409 +++++++++++++++++++++++++++++++++++ gcc/config/mips/t-mti-elf | 48 ---- gcc/config/mips/t-mti-linux | 158 -------------- gcc/configure | 8 +- gcc/configure.ac | 3 + gcc/genmultilib | 3 - 19 files changed, 604 insertions(+), 287 deletions(-) create mode 100644 gcc/config/mips/ml-img-elf create mode 100644 gcc/config/mips/ml-img-linux create mode 100644 gcc/config/mips/ml-mti-elf create mode 100644 gcc/config/mips/ml-mti-linux delete mode 100644 gcc/config/mips/t-img-elf delete mode 100644 gcc/config/mips/t-img-linux create mode 100644 gcc/config/mips/t-mips-multi delete mode 100644 gcc/config/mips/t-mti-elf delete mode 100644 gcc/config/mips/t-mti-linux diff --git a/config-ml.in b/config-ml.in index 645cac822fd..44bfd616f62 100644 --- a/config-ml.in +++ b/config-ml.in @@ -382,6 +382,23 @@ mips*-*-*) esac done fi + if [ x$with_multi_buildlist != x ] + then + old_multidirs="${multidirs}" + if [ ! -f $with_multi_buildlist ] + then + echo "config-ml.in: Failed to find $with_multi_buildlist" + exit 1 + fi + multidirs="" + for x in ${old_multidirs}; do + found=`grep "^${x}$" $with_multi_buildlist` + if [ -n "$found" ] + then + multidirs="${multidirs} ${x}" + fi + done + fi ;; msp430-*-*) if [ x$enable_no_exceptions = xno ] @@ -597,7 +614,8 @@ else fi if [ -z "${with_multisubdir}" ]; then - ml_subdir= + ml_top_subdir=`${CC-gcc} --print-multi-directory 2>/dev/null` + ml_subdir=/$ml_top_subdir ml_builddotdot= : # ml_srcdotdot= # already set else @@ -676,6 +694,11 @@ if [ -n "${multidirs}" ] && [ -z "${ml_norecursion}" ]; then for ml_dir in ${multidirs}; do + if [ "${ml_dir}" == "${ml_top_subdir}" ]; then + echo "Skipping configure in multilib subdir ${ml_dir}" + continue + fi + if [ "${ml_verbose}" = --verbose ]; then echo "Running configure in multilib subdir ${ml_dir}" echo "pwd: `${PWDCMD-pwd}`" diff --git a/configure b/configure index a2e86731b08..c84ce115bea 100755 --- a/configure +++ b/configure @@ -11338,6 +11338,31 @@ if test x${enable_multilib} = x ; then target_configargs="--enable-multilib ${target_configargs}" fi +# Select default multilib build variants +if test x${with_multi_buildlist} = x ; then + case "$target" in + mips*-img-linux*) multi_buildlist=${srcdir}/gcc/config/mips/ml-img-linux ;; + mips*-mti-linux*) multi_buildlist=${srcdir}/gcc/config/mips/ml-mti-linux ;; + mips*-img-elf*) multi_buildlist=${srcdir}/gcc/config/mips/ml-img-elf ;; + mips*-mti-elf*) multi_buildlist=${srcdir}/gcc/config/mips/ml-mti-elf ;; + esac + # Verify the file exists before using it in case the gcc component is not + # present in the tree. + if test -f "${multi_buildlist}" ; then + with_multi_buildlist=$multi_buildlist + fi +fi + +# Pass through with_multi_buildlist to host and target. 'gcc' needs it for the +# fixed includes which are multilib'd and target libraries need it as they use +# config-ml.in. +if test x${with_multi_buildlist} != x ; then + target_configargs="--with-multi-buildlist=${with_multi_buildlist} \ + ${target_configargs}" + host_configargs="--with-multi-buildlist=${with_multi_buildlist} \ + ${host_configargs}" +fi + # Pass --with-newlib if appropriate. Note that target_configdirs has # changed from the earlier setting of with_newlib. if test x${with_newlib} != xno && echo " ${target_configdirs} " | grep " newlib " > /dev/null 2>&1 && test -d ${srcdir}/newlib ; then diff --git a/configure.ac b/configure.ac index 25419a1d2ab..091707ab6bf 100644 --- a/configure.ac +++ b/configure.ac @@ -3577,6 +3577,31 @@ if test x${enable_multilib} = x ; then target_configargs="--enable-multilib ${target_configargs}" fi +# Select default multilib build variants +if test x${with_multi_buildlist} = x ; then + case "$target" in + mips*-img-linux*) multi_buildlist=${srcdir}/gcc/config/mips/ml-img-linux ;; + mips*-mti-linux*) multi_buildlist=${srcdir}/gcc/config/mips/ml-mti-linux ;; + mips*-img-elf*) multi_buildlist=${srcdir}/gcc/config/mips/ml-img-elf ;; + mips*-mti-elf*) multi_buildlist=${srcdir}/gcc/config/mips/ml-mti-elf ;; + esac + # Verify the file exists before using it in case the gcc component is not + # present in the tree. + if test -f "${multi_buildlist}" ; then + with_multi_buildlist=$multi_buildlist + fi +fi + +# Pass through with_multi_buildlist to host and target. 'gcc' needs it for the +# fixed includes which are multilib'd and target libraries need it as they use +# config-ml.in. +if test x${with_multi_buildlist} != x ; then + target_configargs="--with-multi-buildlist=${with_multi_buildlist} \ + ${target_configargs}" + host_configargs="--with-multi-buildlist=${with_multi_buildlist} \ + ${host_configargs}" +fi + # Pass --with-newlib if appropriate. Note that target_configdirs has # changed from the earlier setting of with_newlib. if test x${with_newlib} != xno && echo " ${target_configdirs} " | grep " newlib " > /dev/null 2>&1 && test -d ${srcdir}/newlib ; then diff --git a/gcc/Makefile.in b/gcc/Makefile.in index e8b2a38c8b3..e1a515504ab 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -642,6 +642,9 @@ else endif endif +# Multilib control +with_multi_buildlist = @with_multi_buildlist@ + # ------------------------ # Installation directories # ------------------------ @@ -3383,10 +3386,27 @@ fixinc_list: s-fixinc_list; @true s-fixinc_list : $(GCC_PASSES) # Build up a list of multilib directories and corresponding sysroot # suffixes, in form sysroot;multilib. +# Use a filtered multilib list if requested. if $(GCC_FOR_TARGET) -print-sysroot-headers-suffix > /dev/null 2>&1; then \ set -e; for ml in `$(GCC_FOR_TARGET) -print-multi-lib`; do \ multi_dir=`echo $${ml} | sed -e 's/;.*$$//'`; \ flags=`echo $${ml} | sed -e 's/^[^;]*;//' -e 's/@/ -/g'`; \ + case "$(target)" in \ + mips*-*-*) \ + if [ x$(with_multi_buildlist) != x ]; then \ + if [ ! -f $(with_multi_buildlist) ]; then \ + echo "fixinc_list: Failed to find $(with_multi_buildlist)"; \ + exit 1; \ + fi; \ + set +e; \ + found=`grep "^$${multi_dir}$$" $(with_multi_buildlist)`; \ + set -e; \ + if [ -z "$$found" ]; then \ + continue; \ + fi; \ + fi; \ + ;; \ + esac; \ sfx=`$(GCC_FOR_TARGET) $${flags} -print-sysroot-headers-suffix`; \ if [ "$${multi_dir}" = "." ]; \ then multi_dir=""; \ diff --git a/gcc/config.gcc b/gcc/config.gcc index 9b616bd6e1f..9ec3001527a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2625,22 +2625,24 @@ mips*-*-netbsd*) # NetBSD/mips, either endian. mips*-img-linux*) tm_file="elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h mips/mti-linux.h" extra_options="${extra_options} linux-android.opt" - tmake_file="${tmake_file} mips/t-img-linux" + tmake_file="${tmake_file} mips/t-mips-multi" tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r6" with_arch_64="mips64r6" gnu_ld=yes gas=yes + TM_MULTILIB_EXCEPTIONS_CONFIG="*mclib=*" ;; mips*-mti-linux*) tm_file="elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h mips/mti-linux.h" extra_options="${extra_options} linux-android.opt" - tmake_file="${tmake_file} mips/t-mti-linux" + tmake_file="${tmake_file} mips/t-mips-multi" tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r2" with_arch_64="mips64r2" gnu_ld=yes gas=yes + TM_MULTILIB_EXCEPTIONS_CONFIG="*mclib=*" ;; mips*-*-linux*) # Linux MIPS, either endian. tm_file="elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h" @@ -2705,17 +2707,19 @@ mips*-*-linux*) # Linux MIPS, either endian. ;; mips*-mti-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h mips/sde.h mips/mti-elf.h" - tmake_file="mips/t-mti-elf" + tmake_file="mips/t-mips-multi" tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r2" with_arch_64="mips64r2" + TM_MULTILIB_EXCEPTIONS_CONFIG="*mglibc* *muclibc*" ;; mips*-img-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h mips/sde.h mips/mti-elf.h" - tmake_file="mips/t-img-elf" + tmake_file="mips/t-mips-multi" tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r6" with_arch_64="mips64r6" + TM_MULTILIB_EXCEPTIONS_CONFIG="*mglibc* *muclibc* *mandroid*" ;; mips*-sde-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h mips/sde.h" diff --git a/gcc/config/mips/ml-img-elf b/gcc/config/mips/ml-img-elf new file mode 100644 index 00000000000..91204f825ed --- /dev/null +++ b/gcc/config/mips/ml-img-elf @@ -0,0 +1,12 @@ +mips-r6-hard-newlib/lib +mips-r6-hard-newlib/lib32 +mips-r6-hard-newlib/lib64 +mips-r6-soft-newlib/lib +mips-r6-soft-newlib/lib32 +mips-r6-soft-newlib/lib64 +mipsel-r6-hard-newlib/lib +mipsel-r6-hard-newlib/lib32 +mipsel-r6-hard-newlib/lib64 +mipsel-r6-soft-newlib/lib +mipsel-r6-soft-newlib/lib32 +mipsel-r6-soft-newlib/lib64 diff --git a/gcc/config/mips/ml-img-linux b/gcc/config/mips/ml-img-linux new file mode 100644 index 00000000000..c9a58272f55 --- /dev/null +++ b/gcc/config/mips/ml-img-linux @@ -0,0 +1,10 @@ +mips-r6-hard/lib +mips-r6-soft/lib +mips-r6-hard/lib32 +mips-r6-soft/lib32 +mips-r6-hard/lib64 +mips-r6-soft/lib64 +mipsel-r6-hard/lib +mipsel-r6-soft/lib +mipsel-r6-hard/lib32 +mipsel-r6-hard/lib64 diff --git a/gcc/config/mips/ml-mti-elf b/gcc/config/mips/ml-mti-elf new file mode 100644 index 00000000000..ba61eb3efa6 --- /dev/null +++ b/gcc/config/mips/ml-mti-elf @@ -0,0 +1,31 @@ +mips-r2-hard-newlib/lib +mips-r2-hard-newlib/lib32 +mips-r2-hard-newlib/lib64 +mips-r2-hard-nan2008-newlib/lib +mips-r2-soft-newlib/lib +mips-r2-soft-newlib/lib32 +mips-r2-soft-newlib/lib64 +mipsel-r2-hard-newlib/lib +mipsel-r2-hard-newlib/lib32 +mipsel-r2-hard-newlib/lib64 +mipsel-r2-soft-newlib/lib +mipsel-r2-soft-newlib/lib32 +mipsel-r2-soft-newlib/lib64 +mipsel-r2-mips16-soft-newlib/lib +mipsel-r2-hard-nan2008-newlib/lib +micromips-r2-hard-nan2008-newlib/lib +micromips-r2-soft-newlib/lib +micromipsel-r2-hard-nan2008-newlib/lib +micromipsel-r2-soft-newlib/lib +mips-r6-hard-newlib/lib +mips-r6-hard-newlib/lib32 +mips-r6-hard-newlib/lib64 +mips-r6-soft-newlib/lib +mips-r6-soft-newlib/lib32 +mips-r6-soft-newlib/lib64 +mipsel-r6-hard-newlib/lib +mipsel-r6-hard-newlib/lib32 +mipsel-r6-hard-newlib/lib64 +mipsel-r6-soft-newlib/lib +mipsel-r6-soft-newlib/lib32 +mipsel-r6-soft-newlib/lib64 diff --git a/gcc/config/mips/ml-mti-linux b/gcc/config/mips/ml-mti-linux new file mode 100644 index 00000000000..aabd81bceb9 --- /dev/null +++ b/gcc/config/mips/ml-mti-linux @@ -0,0 +1,27 @@ +mips-r2-hard/lib +mips-r2-soft/lib +mips-r2-hard/lib32 +mips-r2-hard/lib64 +mips-r2-hard-nan2008/lib +mipsel-r1-hard/lib +mipsel-r2-hard/lib +mipsel-r2-soft/lib +mipsel-r2-hard/lib32 +mipsel-r2-hard/lib64 +mipsel-r2-hard-nan2008/lib +micromipsel-r2-hard-nan2008/lib +micromipsel-r2-soft/lib +mips-r2-hard-uclibc/lib +mips-r2-hard-nan2008-uclibc/lib +mipsel-r2-hard-uclibc/lib +mipsel-r2-hard-nan2008-uclibc/lib +mips-r6-hard/lib +mips-r6-soft/lib +mips-r6-hard/lib32 +mips-r6-soft/lib32 +mips-r6-hard/lib64 +mips-r6-soft/lib64 +mipsel-r6-hard/lib +mipsel-r6-soft/lib +mipsel-r6-hard/lib32 +mipsel-r6-hard/lib64 diff --git a/gcc/config/mips/mti-elf.h b/gcc/config/mips/mti-elf.h index 5dd7e2f4f5a..5cd1d30f245 100644 --- a/gcc/config/mips/mti-elf.h +++ b/gcc/config/mips/mti-elf.h @@ -17,6 +17,8 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ +#undef MULTILIB_DEFAULTS + #undef DRIVER_SELF_SPECS #define DRIVER_SELF_SPECS \ /* Set the ISA for the default multilib. */ \ diff --git a/gcc/config/mips/mti-linux.h b/gcc/config/mips/mti-linux.h index a6698d3ad97..eac4228b1c0 100644 --- a/gcc/config/mips/mti-linux.h +++ b/gcc/config/mips/mti-linux.h @@ -23,6 +23,8 @@ along with GCC; see the file COPYING3. If not see mips64r3, and mips64r5 will all default to 'r2'. See MULTILIB_MATCHES definition in t-mti-linux. */ +#undef MULTILIB_DEFAULTS + #define MIPS_SYSVERSION_SPEC \ "%{mips32|mips64:r1;mips32r6|mips64r6:r6;:r2}%{mips16:-mips16}" diff --git a/gcc/config/mips/t-img-elf b/gcc/config/mips/t-img-elf deleted file mode 100644 index 25d33eda9fb..00000000000 --- a/gcc/config/mips/t-img-elf +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (C) 2014-2024 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# . - -# The default build is mips32r6, hard-float big-endian. -# A multilib for mips32r6+LE -# A multilib for mips64r6 -# A multilib for mips64r6+LE - -MULTILIB_OPTIONS = mips64r6 mabi=64 EL msoft-float/msingle-float -MULTILIB_DIRNAMES = mips64r6 64 el sof sgl -MULTILIB_MATCHES = EL=mel EB=meb - -# Don't build 64r6 with single-float -MULTILIB_EXCEPTIONS += mips64r6/*msingle-float* - -MULTILIB_EXCEPTIONS += mabi=64* -MULTILIB_EXCEPTIONS += msingle-float* -MULTILIB_EXCEPTIONS += *msingle-float diff --git a/gcc/config/mips/t-img-linux b/gcc/config/mips/t-img-linux deleted file mode 100644 index b899080cd37..00000000000 --- a/gcc/config/mips/t-img-linux +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (C) 2014-2024 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# . - -# The default build is mips32r6, hard-float big-endian. Add mips64r6, -# 64-bit ABI and little-endian variations. - -MULTILIB_OPTIONS = mips64r6 mabi=64 EL -MULTILIB_DIRNAMES = mips64r6 64 el -MULTILIB_MATCHES = EL=mel EB=meb - -MULTILIB_REQUIRED = -MULTILIB_OSDIRNAMES = .=mips-r6-hard/lib -MULTILIB_REQUIRED += mips64r6 -MULTILIB_OSDIRNAMES += mips64r6=!mips-r6-hard/lib32 -MULTILIB_REQUIRED += mips64r6/mabi=64 -MULTILIB_OSDIRNAMES += mips64r6/mabi.64=!mips-r6-hard/lib64 - -MULTILIB_REQUIRED += EL -MULTILIB_OSDIRNAMES += EL=!mipsel-r6-hard/lib -MULTILIB_REQUIRED += mips64r6/EL -MULTILIB_OSDIRNAMES += mips64r6/EL=!mipsel-r6-hard/lib32 -MULTILIB_REQUIRED += mips64r6/mabi=64/EL -MULTILIB_OSDIRNAMES += mips64r6/mabi.64/EL=!mipsel-r6-hard/lib64 diff --git a/gcc/config/mips/t-mips-multi b/gcc/config/mips/t-mips-multi new file mode 100644 index 00000000000..b6797a98811 --- /dev/null +++ b/gcc/config/mips/t-mips-multi @@ -0,0 +1,409 @@ +# Copyright (C) 2024 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# There is no default build in this multilib setup. This +# unfortunately does not prevent config-ml.in from building a default +# but this can be removed via post install scripts. +# +# All possible MIPS multilibs are shown in this file. They are +# limited via a file that lists required multilibs for each vendor/OS +# combination which can be overridden at build time as well. +# +# The benefit to describing all multilibs is that the compiler driver +# can use any multilib if it is present and therefore additional +# library variants can be added to an installation after initial +# build. This could be achieved by building all libraries and +# removing the ones we don't want to ship but this would massively +# increase build times in situations where only a few are required +# immediately. + +MULTILIB_OPTIONS = mclib=small/mclib=tiny/muclibc \ + mips32/mips32r2/mips32r6/mips64/mips64r2/mips64r6 \ + mips16/mmicromips \ + mabi=32/mabi=n32/mabi=64 \ + EB/EL \ + msoft-float \ + mnan=2008 +MULTILIB_DIRNAMES = small tiny uclibc mips32 mips32r2 mips32r6 mips64 \ + mips64r2 mips64r6 mips16 micromips 32 n32 64 \ + eb el sof nan2008 +MULTILIB_MATCHES = EL=mel EB=meb \ + mips32r2=mips32r3 mips32r2=mips32r5 \ + mips64r2=mips64r3 mips64r2=mips64r5 + +# Allow the exceptions list to be controlled by configure time options +MULTILIB_EXCEPTIONS = $(TM_MULTILIB_EXCEPTIONS_CONFIG) + +# Determine if this is a bare metal target with a newlib default library +is_newlib = $(if $(filter elf, $(lastword $(subst -, ,$(target)))),-newlib) + +MULTILIB_EXCLUSIONS := !mclib=small/!mclib=tiny/!muclibc/!mips32/!mips32r2 +MULTILIB_EXCLUSIONS := $(MULTILIB_EXCLUSIONS)/!mips32r6/!mips64/!mips64r2 +MULTILIB_EXCLUSIONS := $(MULTILIB_EXCLUSIONS)/!mips64r6/!mips16/!mmicromips +MULTILIB_EXCLUSIONS := $(MULTILIB_EXCLUSIONS)/!mabi=32/!mabi=n32/!mabi=64/!EB +MULTILIB_EXCLUSIONS := $(MULTILIB_EXCLUSIONS)/!EL/!msoft-float/!mnan=2008 + +# MIPS32R6/MIPS64R6 +MULTILIB_REQUIRED = mips32r6/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES = mips32r6/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-hard$(is_newlib)/lib +MULTILIB_REUSE = mips32r6/mabi.32/EB/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EB/mnan.2008 +MULTILIB_REQUIRED += mips64r6/mabi=n32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.n32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-hard$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r6/mabi=64/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.64/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-hard$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r6/mabi=32/EB/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r6/mabi.32/EB/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-soft$(is_newlib)/lib +MULTILIB_REUSE += mips32r6/mabi.32/EB/msoft-float/mnan.2008=mips64r6 +MULTILIB_REUSE := $(MULTILIB_REUSE)/mabi.32/EB/msoft-float/mnan.2008 +MULTILIB_REQUIRED += mips64r6/mabi=n32/EB/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.n32/EB/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-soft$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r6/mabi=64/EB/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.64/EB/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-soft$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r6/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r6/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-hard$(is_newlib)/lib +MULTILIB_REUSE += mips32r6/mabi.32/EL/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EL/mnan.2008 +MULTILIB_REQUIRED += mips64r6/mabi=n32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.n32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-hard$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r6/mabi=64/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.64/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-hard$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r6/mabi=32/EL/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r6/mabi.32/EL/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES :=$(MULTILIB_OSDIRNAMES)!mipsel-r6-soft$(is_newlib)/lib +MULTILIB_REUSE += mips32r6/mabi.32/EL/msoft-float/mnan.2008=mips64r6 +MULTILIB_REUSE := $(MULTILIB_REUSE)/mabi.32/EL/msoft-float/mnan.2008 +MULTILIB_REQUIRED += mips64r6/mabi=n32/EL/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.n32/EL/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-soft$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r6/mabi=64/EL/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r6/mabi.64/EL/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-soft$(is_newlib)/lib64 + +# MIPS32R2/MIPS64R2 +MULTILIB_REQUIRED += mips32r2/mabi=32/EB +MULTILIB_OSDIRNAMES += mips32r2/mabi.32/EB=!mips-r2-hard$(is_newlib)/lib +MULTILIB_REUSE += mips32r2/mabi.32/EB=mips64r2/mabi.32/EB +MULTILIB_REQUIRED += mips64r2/mabi=n32/EB +MULTILIB_OSDIRNAMES += mips64r2/mabi.n32/EB=!mips-r2-hard$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r2/mabi=64/EB +MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EB=!mips-r2-hard$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r2/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r2/mabi.32/EB/mnan.2008=!mips-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REUSE += mips32r2/mabi.32/EB/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EB/mnan.2008 +MULTILIB_REQUIRED += mips64r2/mabi=n32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r2/mabi.n32/EB/mnan.2008=!mips-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r2/mabi=64/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EB/mnan.2008=!mips-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r2/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mips32r2/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-soft$(is_newlib)/lib +MULTILIB_REUSE += mips32r2/mabi.32/EB/msoft-float= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EB/msoft-float +MULTILIB_REQUIRED += mips64r2/mabi=n32/EB/msoft-float +MULTILIB_OSDIRNAMES += mips64r2/mabi.n32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-soft$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r2/mabi=64/EB/msoft-float +MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-soft$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r2/mabi=32/EL +MULTILIB_OSDIRNAMES += mips32r2/mabi.32/EL=!mipsel-r2-hard$(is_newlib)/lib +MULTILIB_REUSE += mips32r2/mabi.32/EL=mips64r2/mabi.32/EL +MULTILIB_REQUIRED += mips64r2/mabi=n32/EL +MULTILIB_OSDIRNAMES += mips64r2/mabi.n32/EL=!mipsel-r2-hard$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r2/mabi=64/EL +MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EL=!mipsel-r2-hard$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r2/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r2/mabi.32/EL/mnan.2008=!mipsel-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REUSE += mips32r2/mabi.32/EL/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EL/mnan.2008 +MULTILIB_REQUIRED += mips64r2/mabi=n32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r2/mabi.n32/EL/mnan.2008=!mipsel-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r2/mabi=64/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EL/mnan.2008=!mipsel-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32r2/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mips32r2/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-soft$(is_newlib)/lib +MULTILIB_REUSE += mips32r2/mabi.32/EL/msoft-float= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EL/msoft-float +MULTILIB_REQUIRED += mips64r2/mabi=n32/EL/msoft-float +MULTILIB_OSDIRNAMES += mips64r2/mabi.n32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-soft$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64r2/mabi=64/EL/msoft-float +MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-soft$(is_newlib)/lib64 + +# MIPS16 - We will not include any 64 bit mips16 combinations. +MULTILIB_REQUIRED += mips32r2/mips16/mabi=32/EB +MULTILIB_OSDIRNAMES += mips32r2/mips16/mabi.32/EB=!mips-r2-mips16-hard +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32r2/mips16/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r2/mips16/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-mips16-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32r2/mips16/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mips32r2/mips16/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-mips16-soft +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib + +MULTILIB_REQUIRED += mips32r2/mips16/mabi=32/EL +MULTILIB_OSDIRNAMES += mips32r2/mips16/mabi.32/EL= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-mips16-hard +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32r2/mips16/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r2/mips16/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-mips16-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32r2/mips16/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mips32r2/mips16/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-mips16-soft +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib + +# microMIPS32R3 - We will not include any 64 bit microMIPS combinations +MULTILIB_REQUIRED += mips32r2/mmicromips/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r2/mmicromips/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32r2/mmicromips/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mips32r2/mmicromips/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-soft$(is_newlib)/lib + +MULTILIB_REQUIRED += mips32r2/mmicromips/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r2/mmicromips/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r2-hard-nan2008 +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32r2/mmicromips/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mips32r2/mmicromips/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r2-soft +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib + +# Version 1 multilibs + +MULTILIB_REQUIRED += mips32/mabi=32/EB +MULTILIB_OSDIRNAMES += mips32/mabi.32/EB=!mips-r1-hard$(is_newlib)/lib +MULTILIB_REUSE += mips32/mabi.32/EB=mips64/mabi.32/EB +MULTILIB_REQUIRED += mips64/mabi=n32/EB +MULTILIB_OSDIRNAMES += mips64/mabi.n32/EB=!mips-r1-hard$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64/mabi=64/EB +MULTILIB_OSDIRNAMES += mips64/mabi.64/EB=!mips-r1-hard$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mips32/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r1-soft$(is_newlib)/lib +MULTILIB_REUSE += mips32/mabi.32/EB/msoft-float= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64/mabi.32/EB/msoft-float +MULTILIB_REQUIRED += mips64/mabi=n32/EB/msoft-float +MULTILIB_OSDIRNAMES += mips64/mabi.n32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r1-soft$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64/mabi=64/EB/msoft-float +MULTILIB_OSDIRNAMES += mips64/mabi.64/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r1-soft$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32/mabi=32/EL +MULTILIB_OSDIRNAMES += mips32/mabi.32/EL=!mipsel-r1-hard$(is_newlib)/lib +MULTILIB_REUSE += mips32/mabi.32/EL=mips64/mabi.32/EL +MULTILIB_REQUIRED += mips64/mabi=n32/EL +MULTILIB_OSDIRNAMES += mips64/mabi.n32/EL=!mipsel-r1-hard$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64/mabi=64/EL +MULTILIB_OSDIRNAMES += mips64/mabi.64/EL=!mipsel-r1-hard$(is_newlib)/lib64 + +MULTILIB_REQUIRED += mips32/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mips32/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r1-soft$(is_newlib)/lib +MULTILIB_REUSE += mips32/mabi.32/EL/msoft-float= +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64/mabi.32/EL/msoft-float +MULTILIB_REQUIRED += mips64/mabi=n32/EL/msoft-float +MULTILIB_OSDIRNAMES += mips64/mabi.n32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r1-soft$(is_newlib)/lib32 +MULTILIB_REQUIRED += mips64/mabi=64/EL/msoft-float +MULTILIB_OSDIRNAMES += mips64/mabi.64/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r1-soft$(is_newlib)/lib64 + +# We will not include any 64 bit mips16 combinations. +MULTILIB_REQUIRED += mips32/mips16/mabi=32/EB +MULTILIB_OSDIRNAMES += mips32/mips16/mabi.32/EB=!mips-r1-mips16-hard +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32/mips16/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mips32/mips16/mabi.32/EB/msoft-float=!mips-r1-mips16-soft +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib + +MULTILIB_REQUIRED += mips32/mips16/mabi=32/EL +MULTILIB_OSDIRNAMES += mips32/mips16/mabi.32/EL=!mipsel-r1-mips16-hard +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib +MULTILIB_REQUIRED += mips32/mips16/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mips32/mips16/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r1-mips16-soft +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)$(is_newlib)/lib + +# Uclibc variants +MULTILIB_REQUIRED += muclibc/mips32r2/mabi=32/EB +MULTILIB_OSDIRNAMES += muclibc/mips32r2/mabi.32/EB=!mips-r2-hard-uclibc/lib +MULTILIB_REUSE += muclibc/mips32r2/mabi.32/EB=muclibc/mips64r2/mabi.32/EB +MULTILIB_REQUIRED += muclibc/mips32r2/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += muclibc/mips32r2/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-hard-nan2008-uclibc/lib +MULTILIB_REUSE += muclibc/mips32r2/mabi.32/EB/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)muclibc/mips64r2/mabi.32/EB/mnan.2008 + +MULTILIB_REQUIRED += muclibc/mips32r2/mabi=32/EL +MULTILIB_OSDIRNAMES += muclibc/mips32r2/mabi.32/EL=!mipsel-r2-hard-uclibc/lib +MULTILIB_REUSE += muclibc/mips32r2/mabi.32/EL=muclibc/mips64r2/mabi.32/EL +MULTILIB_REQUIRED += muclibc/mips32r2/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += muclibc/mips32r2/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-hard-nan2008-uclibc/lib +MULTILIB_REUSE += muclibc/mips32r2/mabi.32/EL/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)muclibc/mips64r2/mabi.32/EL/mnan.2008 + +# MIPS Small/Tiny C library variants +MULTILIB_REQUIRED += mclib=small/mips32r6/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-hard-small/lib +MULTILIB_REUSE += mclib.small/mips32r6/mabi.32/EB/mnan.2008=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EB/mnan.2008 +MULTILIB_REQUIRED += mclib=small/mips32r6/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-hard-small/lib +MULTILIB_REUSE += mclib.small/mips32r6/mabi.32/EL/mnan.2008=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EL/mnan.2008 +MULTILIB_REQUIRED += mclib=small/mips32r6/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-soft-small/lib +MULTILIB_REUSE += mclib.small/mips32r6/mabi.32/EB/msoft-float=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EB/msoft-float +MULTILIB_REQUIRED += mclib=small/mips32r6/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-soft-small/lib +MULTILIB_REUSE += mclib.small/mips32r6/mabi.32/EL/msoft-float=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EL/msoft-float + +MULTILIB_REQUIRED += mclib=small/mips32r2/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-hard-nan2008-small/lib +MULTILIB_REUSE += mclib.small/mips32r2/mabi.32/EB/mnan.2008=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EB/mnan.2008 +MULTILIB_REQUIRED += mclib=small/mips32r2/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-hard-nan2008-small/lib +MULTILIB_REUSE += mclib.small/mips32r2/mabi.32/EL/mnan.2008=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EL/mnan.2008 +MULTILIB_REQUIRED += mclib=small/mips32r2/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-soft-small/lib +MULTILIB_REUSE += mclib.small/mips32r2/mabi.32/EB/msoft-float=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EB/msoft-float +MULTILIB_REQUIRED += mclib=small/mips32r2/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-soft-small/lib +MULTILIB_REUSE += mclib.small/mips32r2/mabi.32/EL/msoft-float=mclib.small/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EL/msoft-float + +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-hard-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r6/mabi.32/EB/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mclib.tiny/mips64r6/mabi.32/EB/mnan.2008 +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-hard-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r6/mabi.32/EL/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mclib.tiny/mips64r6/mabi.32/EL/mnan.2008 +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r6-soft-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r6/mabi.32/EB/msoft-float=mclib.tiny/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EB/msoft-float +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-soft-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r6/mabi.32/EL/msoft-float=mclib.tiny/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r6/mabi.32/EL/msoft-float + +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-hard-nan2008-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r2/mabi.32/EB/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mclib.tiny/mips64r2/mabi.32/EB/mnan.2008 +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-hard-nan2008-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r2/mabi.32/EL/mnan.2008= +MULTILIB_REUSE := $(MULTILIB_REUSE)mclib.tiny/mips64r2/mabi.32/EL/mnan.2008 +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mips-r2-soft-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r2/mabi.32/EB/msoft-float=mclib.tiny/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EB/msoft-float +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r2-soft-tiny/lib +MULTILIB_REUSE += mclib.tiny/mips32r2/mabi.32/EL/msoft-float=mclib.tiny/ +MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EL/msoft-float + +# microMIPS Small/Tiny C library variants +MULTILIB_REQUIRED += mclib=small/mips32r2/mmicromips/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mmicromips/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-hard-nan2008-small +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)/lib +MULTILIB_REQUIRED += mclib=small/mips32r2/mmicromips/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mmicromips/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r2-hard-nan2008-small +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)/lib +MULTILIB_REQUIRED += mclib=small/mips32r2/mmicromips/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mmicromips/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-soft-small/lib +MULTILIB_REQUIRED += mclib=small/mips32r2/mmicromips/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mmicromips/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r2-soft-small/lib + +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mmicromips/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mmicromips/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-hard-nan2008-tiny/lib +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mmicromips/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mmicromips/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r2-hard-nan2008-tiny +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)/lib +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mmicromips/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mmicromips/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-soft-tiny/lib +MULTILIB_REQUIRED += mclib=tiny/mips32r2/mmicromips/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mmicromips/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r2-soft-tiny/lib diff --git a/gcc/config/mips/t-mti-elf b/gcc/config/mips/t-mti-elf deleted file mode 100644 index 9655397e4de..00000000000 --- a/gcc/config/mips/t-mti-elf +++ /dev/null @@ -1,48 +0,0 @@ -# Copyright (C) 2012-2024 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# . - -# The default build is mips32r2, hard-float big-endian. Add mips32, -# soft-float, and little-endian variations. - -MULTILIB_OPTIONS = mips32/mips64/mips64r2 mips16/mmicromips mabi=64 EL msoft-float mnan=2008 -MULTILIB_DIRNAMES = mips32 mips64 mips64r2 mips16 micromips 64 el sof nan2008 -MULTILIB_MATCHES = EL=mel EB=meb mips32r2=mips32r3 mips32r2=mips32r5 mips64r2=mips64r3 mips64r2=mips64r5 - -# The 64 bit ABI is not supported on the mips32 architecture. -MULTILIB_EXCEPTIONS += *mips32*/*mabi=64* - -# The 64 bit ABI is not supported on the mips32r2 architecture. -# Because mips32r2 is the default we can't use that flag to trigger -# the exception so we check for mabi=64 with no specific mips -# architecture flag instead. -MULTILIB_EXCEPTIONS += mabi=64* - -# We do not want to build mips16 versions of mips64* architectures. -MULTILIB_EXCEPTIONS += *mips64*/*mips16* -MULTILIB_EXCEPTIONS += *mips16/mabi=64* - -# We only want micromips for mips32r2 architecture. -MULTILIB_EXCEPTIONS += *mips32/mmicromips* -MULTILIB_EXCEPTIONS += *mips64*/mmicromips* -MULTILIB_EXCEPTIONS += *mmicromips/mabi=64* - -# We do not want nan2008 libraries for soft-float, -# mips32[r1], or mips64[r1]. -MULTILIB_EXCEPTIONS += *msoft-float*/*mnan=2008* -MULTILIB_EXCEPTIONS += *mips32/*mnan=2008* -MULTILIB_EXCEPTIONS += *mips64/*mnan=2008* diff --git a/gcc/config/mips/t-mti-linux b/gcc/config/mips/t-mti-linux deleted file mode 100644 index 4919fd9bc45..00000000000 --- a/gcc/config/mips/t-mti-linux +++ /dev/null @@ -1,158 +0,0 @@ -# Copyright (C) 2012-2024 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# . - -# The default build is mips32r2, hard-float big-endian. Add mips32, -# soft-float, and little-endian variations. - -MULTILIB_OPTIONS = mips32/mips64/mips64r2 mips16/mmicromips mabi=64 EL msoft-float mnan=2008 -MULTILIB_DIRNAMES = mips32 mips64 mips64r2 mips16 micromips 64 el sof nan2008 -MULTILIB_MATCHES = EL=mel EB=meb mips32r2=mips32r3 mips32r2=mips32r5 mips64r2=mips64r3 mips64r2=mips64r5 - -MULTILIB_REQUIRED = -MULTILIB_OSDIRNAMES = .=mips-r2-hard/lib -MULTILIB_REQUIRED += mips64r2 -MULTILIB_OSDIRNAMES += mips64r2=!mips-r2-hard/lib32 -MULTILIB_REQUIRED += mips64r2/mabi=64 -MULTILIB_OSDIRNAMES += mips64r2/mabi.64=!mips-r2-hard/lib64 - -MULTILIB_REQUIRED += mnan=2008 -MULTILIB_OSDIRNAMES += mnan.2008=!mips-r2-hard-nan2008/lib -MULTILIB_REQUIRED += mips64r2/mnan=2008 -MULTILIB_OSDIRNAMES += mips64r2/mnan.2008=!mips-r2-hard-nan2008/lib32 -MULTILIB_REQUIRED += mips64r2/mabi=64/mnan=2008 -MULTILIB_OSDIRNAMES += mips64r2/mabi.64/mnan.2008=!mips-r2-hard-nan2008/lib64 - -MULTILIB_REQUIRED += msoft-float -MULTILIB_OSDIRNAMES += msoft-float=!mips-r2-soft/lib -MULTILIB_REQUIRED += mips64r2/msoft-float -MULTILIB_OSDIRNAMES += mips64r2/msoft-float=!mips-r2-soft/lib32 -MULTILIB_REQUIRED += mips64r2/mabi=64/msoft-float -MULTILIB_OSDIRNAMES += mips64r2/mabi.64/msoft-float=!mips-r2-soft/lib64 - -#MULTILIB_REQUIRED += msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += msoft-float/mnan.2008=!mips-r2-soft-nan2008/lib -#MULTILIB_REQUIRED += mips64r2/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mips64r2/msoft-float/mnan.2008=!mips-r2-soft-nan2008/lib32 -#MULTILIB_REQUIRED += mips64r2/mabi=64/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mips64r2/mabi.64/msoft-float/mnan.2008=!mips-r2-soft-nan2008/lib64 - -MULTILIB_REQUIRED += EL -MULTILIB_OSDIRNAMES += EL=!mipsel-r2-hard/lib -MULTILIB_REQUIRED += mips64r2/EL -MULTILIB_OSDIRNAMES += mips64r2/EL=!mipsel-r2-hard/lib32 -MULTILIB_REQUIRED += mips64r2/mabi=64/EL -MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EL=!mipsel-r2-hard/lib64 - -MULTILIB_REQUIRED += EL/mnan=2008 -MULTILIB_OSDIRNAMES += EL/mnan.2008=!mipsel-r2-hard-nan2008/lib -MULTILIB_REQUIRED += mips64r2/EL/mnan=2008 -MULTILIB_OSDIRNAMES += mips64r2/EL/mnan.2008=!mipsel-r2-hard-nan2008/lib32 -MULTILIB_REQUIRED += mips64r2/mabi=64/EL/mnan=2008 -MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EL/mnan.2008=!mipsel-r2-hard-nan2008/lib64 - -MULTILIB_REQUIRED += EL/msoft-float -MULTILIB_OSDIRNAMES += EL/msoft-float=!mipsel-r2-soft/lib -MULTILIB_REQUIRED += mips64r2/EL/msoft-float -MULTILIB_OSDIRNAMES += mips64r2/EL/msoft-float=!mipsel-r2-soft/lib32 -MULTILIB_REQUIRED += mips64r2/mabi=64/EL/msoft-float -MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EL/msoft-float=!mipsel-r2-soft/lib64 - -#MULTILIB_REQUIRED += EL/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += EL/msoft-float/mnan.2008=!mipsel-r2-soft-nan2008/lib -#MULTILIB_REQUIRED += mips64r2/EL/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mips64r2/EL/msoft-float/mnan.2008=!mipsel-r2-soft-nan2008/lib32 -#MULTILIB_REQUIRED += mips64r2/mabi=64/EL/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mips64r2/mabi.64/EL/msoft-float/mnan.2008=!mipsel-r2-soft-nan2008/lib64 - -# We will not include any 64 bit mips16 combinations. -MULTILIB_REQUIRED += mips16 -MULTILIB_OSDIRNAMES += mips16=!mips-r2-mips16-hard/lib -MULTILIB_REQUIRED += mips16/mnan=2008 -MULTILIB_OSDIRNAMES += mips16/mnan.2008=!mips-r2-mips16-hard-nan2008/lib -MULTILIB_REQUIRED += mips16/msoft-float -MULTILIB_OSDIRNAMES += mips16/msoft-float=!mips-r2-mips16-soft/lib -#MULTILIB_REQUIRED += mips16/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mips16/msoft-float/mnan.2008=!mips-r2-mips16-soft-nan2008/lib - -MULTILIB_REQUIRED += mips16/EL -MULTILIB_OSDIRNAMES += mips16/EL=!mipsel-r2-mips16-hard/lib -MULTILIB_REQUIRED += mips16/EL/mnan=2008 -MULTILIB_OSDIRNAMES += mips16/EL/mnan.2008=!mipsel-r2-mips16-hard-nan2008/lib -MULTILIB_REQUIRED += mips16/EL/msoft-float -MULTILIB_OSDIRNAMES += mips16/EL/msoft-float=!mipsel-r2-mips16-soft/lib -#MULTILIB_REQUIRED += mips16/EL/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mips16/EL/msoft-float/mnan.2008=!mipsel-r2-mips16-soft-nan2008/lib - -MULTILIB_REQUIRED += mmicromips -MULTILIB_OSDIRNAMES += mmicromips=!micromips-r2-hard/lib -MULTILIB_REQUIRED += mmicromips/mnan=2008 -MULTILIB_OSDIRNAMES += mmicromips/mnan.2008=!micromips-r2-hard-nan2008/lib -MULTILIB_REQUIRED += mmicromips/msoft-float -MULTILIB_OSDIRNAMES += mmicromips/msoft-float=!micromips-r2-soft/lib -#MULTILIB_REQUIRED += mmicromips/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mmicromips/msoft-float/mnan.2008=!micromips-r2-soft-nan2008/lib - -MULTILIB_REQUIRED += mmicromips/EL -MULTILIB_OSDIRNAMES += mmicromips/EL=!micromipsel-r2-hard/lib -MULTILIB_REQUIRED += mmicromips/EL/mnan=2008 -MULTILIB_OSDIRNAMES += mmicromips/EL/mnan.2008=!micromipsel-r2-hard-nan2008/lib -MULTILIB_REQUIRED += mmicromips/EL/msoft-float -MULTILIB_OSDIRNAMES += mmicromips/EL/msoft-float=!micromipsel-r2-soft/lib -#MULTILIB_REQUIRED += mmicromips/EL/msoft-float/mnan=2008 -#MULTILIB_OSDIRNAMES += mmicromips/EL/msoft-float/mnan.2008=!micromipsel-r2-soft-nan2008/lib - -# Version 1 multilibs - -MULTILIB_REQUIRED += mips32 -MULTILIB_OSDIRNAMES += mips32=!mips-r1-hard/lib -MULTILIB_REQUIRED += mips64 -MULTILIB_OSDIRNAMES += mips64=!mips-r1-hard/lib32 -MULTILIB_REQUIRED += mips64/mabi=64 -MULTILIB_OSDIRNAMES += mips64/mabi.64=!mips-r1-hard/lib64 - -MULTILIB_REQUIRED += mips32/msoft-float -MULTILIB_OSDIRNAMES += mips32/msoft-float=!mips-r1-soft/lib -MULTILIB_REQUIRED += mips64/msoft-float -MULTILIB_OSDIRNAMES += mips64/msoft-float=!mips-r1-soft/lib32 -MULTILIB_REQUIRED += mips64/mabi=64/msoft-float -MULTILIB_OSDIRNAMES += mips64/mabi.64/msoft-float=!mips-r1-soft/lib64 - -MULTILIB_REQUIRED += mips32/EL -MULTILIB_OSDIRNAMES += mips32/EL=!mipsel-r1-hard/lib -MULTILIB_REQUIRED += mips64/EL -MULTILIB_OSDIRNAMES += mips64/EL=!mipsel-r1-hard/lib32 -MULTILIB_REQUIRED += mips64/mabi=64/EL -MULTILIB_OSDIRNAMES += mips64/mabi.64/EL=!mipsel-r1-hard/lib64 - -MULTILIB_REQUIRED += mips32/EL/msoft-float -MULTILIB_OSDIRNAMES += mips32/EL/msoft-float=!mipsel-r1-soft/lib -MULTILIB_REQUIRED += mips64/EL/msoft-float -MULTILIB_OSDIRNAMES += mips64/EL/msoft-float=!mipsel-r1-soft/lib32 -MULTILIB_REQUIRED += mips64/mabi=64/EL/msoft-float -MULTILIB_OSDIRNAMES += mips64/mabi.64/EL/msoft-float=!mipsel-r1-soft/lib64 - -# We will not include any 64 bit mips16 combinations. -MULTILIB_REQUIRED += mips32/mips16 -MULTILIB_OSDIRNAMES += mips32/mips16=!mips-r1-mips16-hard/lib -MULTILIB_REQUIRED += mips32/mips16/msoft-float -MULTILIB_OSDIRNAMES += mips32/mips16/msoft-float=!mips-r1-mips16-soft/lib - -MULTILIB_REQUIRED += mips32/mips16/EL -MULTILIB_OSDIRNAMES += mips32/mips16/EL=!mipsel-r1-mips16-hard/lib -MULTILIB_REQUIRED += mips32/mips16/EL/msoft-float -MULTILIB_OSDIRNAMES += mips32/mips16/EL/msoft-float=!mipsel-r1-mips16-soft/lib diff --git a/gcc/configure b/gcc/configure index 150ab616414..1341e1cbd3f 100755 --- a/gcc/configure +++ b/gcc/configure @@ -853,6 +853,7 @@ enable_fixed_point enable_decimal_float DEFAULT_INSNEMIT_PARTITIONS DEFAULT_MATCHPD_PARTITIONS +with_multi_buildlist with_float with_cpu enable_multiarch @@ -7870,6 +7871,9 @@ $as_echo "$enable_multiarch$ma_msg_suffix" >&6; } +# needed for restricting the fixedincludes multilibs that we install + + # default stack clash protection guard size as power of twos in bytes. # Please keep these in sync with params.def. stk_clash_min=12 @@ -21454,7 +21458,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 21457 "configure" +#line 21461 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -21560,7 +21564,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 21563 "configure" +#line 21567 "configure" #include "confdefs.h" #if HAVE_DLFCN_H diff --git a/gcc/configure.ac b/gcc/configure.ac index bdb22d53e2c..ee98191411e 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -877,6 +877,9 @@ AC_MSG_RESULT($enable_multiarch$ma_msg_suffix) AC_SUBST(with_cpu) AC_SUBST(with_float) +# needed for restricting the fixedincludes multilibs that we install +AC_SUBST(with_multi_buildlist) + # default stack clash protection guard size as power of twos in bytes. # Please keep these in sync with params.def. stk_clash_min=12 diff --git a/gcc/genmultilib b/gcc/genmultilib index 85b241cd72a..5df8148e031 100644 --- a/gcc/genmultilib +++ b/gcc/genmultilib @@ -500,9 +500,6 @@ for rrule in ${multilib_reuse}; do echo "The rule ${rrule} contains an option absent from MULTILIB_OPTIONS." >&2 exit 1 fi - else - echo "The rule ${rrule} is trying to reuse nonexistent multilib." >&2 - exit 1 fi done From patchwork Fri Jan 31 17:13:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105756 Return-Path: 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9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NfH8BxbCWxEUTtkoRAEDGTK9oGYUCdRTk/rienRSVkHeNV9E0IpOFQnGYy4dl61c4zfVPMoiEtQ3jmA5WwubIGXijBNF0raoecAu4HkIjAo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR09MB5442 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Faraz Shahbazker libsanitizer: * asan/asan_mapping.h (ASAN_SHADOW_OFFSET_CONST): Set correct offset for n32 ABI. Cherry-picked 12ec4fc5c3a19e6304b58775db1820892942efbc from https://github.com/MIPS/gcc Signed-off-by: Faraz Shahbazker Signed-off-by: Chao-ying Fu Signed-off-by: Aleksandar Rakic --- libsanitizer/asan/asan_mapping.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/libsanitizer/asan/asan_mapping.h b/libsanitizer/asan/asan_mapping.h index 54890ca1789..7a6d94623b4 100644 --- a/libsanitizer/asan/asan_mapping.h +++ b/libsanitizer/asan/asan_mapping.h @@ -65,6 +65,13 @@ // || `[0x0aaa0000, 0x0bff3fff]` || LowShadow || // || `[0x00000000, 0x0aa9ffff]` || LowMem || // +// Default Linux/MIPS64 n32 ABI mapping: +// || `[0x40000000, 0xffffffff]` || HighMem || +// || `[0x28000000, 0x3fffffff]` || HighShadow || +// || `[0x24000000, 0x27ffffff]` || ShadowGap || +// || `[0x20000000, 0x23ffffff]` || LowShadow || +// || `[0x00000000, 0x1fffffff]` || LowMem || +// // Default Linux/MIPS64 mapping: // || `[0x4000000000, 0xffffffffff]` || HighMem || // || `[0x2800000000, 0x3fffffffff]` || HighShadow || @@ -169,7 +176,11 @@ # if SANITIZER_ANDROID # define ASAN_SHADOW_OFFSET_DYNAMIC # elif defined(__mips__) -# define ASAN_SHADOW_OFFSET_CONST 0x0aaa0000 +# if _MIPS_SIM == _ABIN32 +# define ASAN_SHADOW_OFFSET_CONST 0x20000000 +# else +# define ASAN_SHADOW_OFFSET_CONST 0x0aaa0000 +# endif # elif SANITIZER_FREEBSD # define ASAN_SHADOW_OFFSET_CONST 0x40000000 # elif SANITIZER_NETBSD From patchwork Fri Jan 31 17:13:02 2025 Content-Type: text/plain; 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However this directory is not in RPATH, so attempting to build a dynamically linked application with -fsanitize=xx gives a linkage error. In the opinion of libsanitizer maintainer, this is a problem with the tree structure of the installation. See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69839 Specifying an explicit -rpath-link is not a problem for the end-user, but this problem also causes target checks for libasan regression tests to fail. In order to be able to run regression tests on a cross toolchain, this patch hacks the gcc driver and adds the requisite -rpath-link option automatically for -fsanitize=address/undefined relative to toolchain sysroot. gcc/ * gcc.cc (LIBSAN_RPATH): New macro. (LIBASAN_SPEC): Add LIBSAN_RPATH. (LIBUBSAN_SPEC): Likewise. (LIBTSAN_SPEC): Likewise. (LIBLSAN_SPEC): Likewise. libsanitizer/ * configure.ac (link_libsan_rpath): New config variable. * libsanitizer.spec.in (link_libsan_rpath): New spec. * configure: Regenerate with autoconf 2.69 * Makefile.in: Regenerate with automake 1.15.1. * asan/Makefile.in: Likewise. * interception/Makefile.in: Likewise. * libbacktrace/Makefile.in: Likewise. * lsan/Makefile.in: Likewise. * sanitizer_common/Makefile.in: Likewise. * tsan/Makefile.in: Likewise. * ubsan/Makefile.in: Likewise. * hwasan/Makefile.in: Likewise. Cherry-picked e45e8831afb40eddfa82bedf7fc5536619d7382f, 25c48b961e16748cfa468830040a865ece7dd235 and 96b7557473a09bb181be86c741c6e79a4a3c41b1 from https://github.com/MIPS/gcc Signed-off-by: Faraz Shahbazker Signed-off-by: Chao-ying Fu Signed-off-by: Aleksandar Rakic --- gcc/gcc.cc | 20 ++++++++++++-------- libsanitizer/Makefile.in | 1 + libsanitizer/asan/Makefile.in | 1 + libsanitizer/configure | 14 ++++++++++++-- libsanitizer/configure.ac | 9 +++++++++ libsanitizer/hwasan/Makefile.in | 1 + libsanitizer/interception/Makefile.in | 1 + libsanitizer/libbacktrace/Makefile.in | 1 + libsanitizer/libsanitizer.spec.in | 2 ++ libsanitizer/lsan/Makefile.in | 1 + libsanitizer/sanitizer_common/Makefile.in | 1 + libsanitizer/tsan/Makefile.in | 1 + libsanitizer/ubsan/Makefile.in | 1 + 13 files changed, 44 insertions(+), 10 deletions(-) diff --git a/gcc/gcc.cc b/gcc/gcc.cc index 5fe5fd86a98..20a165762e9 100644 --- a/gcc/gcc.cc +++ b/gcc/gcc.cc @@ -765,17 +765,21 @@ proper position among the other output files. */ #define STACK_SPLIT_SPEC " %{fsplit-stack: --wrap=pthread_create}" #endif +#ifndef LIBSAN_RPATH +#define LIBSAN_RPATH " %:include(libsanitizer.spec)%(link_libsan_rpath)" +#endif + #ifndef LIBASAN_SPEC #define STATIC_LIBASAN_LIBS \ " %{static-libasan|static:%:include(libsanitizer.spec)%(link_libasan)}" #ifdef LIBASAN_EARLY_SPEC -#define LIBASAN_SPEC STATIC_LIBASAN_LIBS +#define LIBASAN_SPEC STATIC_LIBASAN_LIBS LIBSAN_RPATH #elif defined(HAVE_LD_STATIC_DYNAMIC) #define LIBASAN_SPEC "%{static-libasan:" LD_STATIC_OPTION \ "} -lasan %{static-libasan:" LD_DYNAMIC_OPTION "}" \ STATIC_LIBASAN_LIBS #else -#define LIBASAN_SPEC "-lasan" STATIC_LIBASAN_LIBS +#define LIBASAN_SPEC "-lasan" STATIC_LIBASAN_LIBS LIBSAN_RPATH #endif #endif @@ -805,13 +809,13 @@ proper position among the other output files. */ #define STATIC_LIBTSAN_LIBS \ " %{static-libtsan|static:%:include(libsanitizer.spec)%(link_libtsan)}" #ifdef LIBTSAN_EARLY_SPEC -#define LIBTSAN_SPEC STATIC_LIBTSAN_LIBS +#define LIBTSAN_SPEC STATIC_LIBTSAN_LIBS LIBSAN_RPATH #elif defined(HAVE_LD_STATIC_DYNAMIC) #define LIBTSAN_SPEC "%{static-libtsan:" LD_STATIC_OPTION \ "} -ltsan %{static-libtsan:" LD_DYNAMIC_OPTION "}" \ STATIC_LIBTSAN_LIBS #else -#define LIBTSAN_SPEC "-ltsan" STATIC_LIBTSAN_LIBS +#define LIBTSAN_SPEC "-ltsan" STATIC_LIBTSAN_LIBS LIBSAN_RPATH #endif #endif @@ -823,13 +827,13 @@ proper position among the other output files. */ #define STATIC_LIBLSAN_LIBS \ " %{static-liblsan|static:%:include(libsanitizer.spec)%(link_liblsan)}" #ifdef LIBLSAN_EARLY_SPEC -#define LIBLSAN_SPEC STATIC_LIBLSAN_LIBS +#define LIBLSAN_SPEC STATIC_LIBLSAN_LIBS LIBSAN_RPATH #elif defined(HAVE_LD_STATIC_DYNAMIC) #define LIBLSAN_SPEC "%{static-liblsan:" LD_STATIC_OPTION \ "} -llsan %{static-liblsan:" LD_DYNAMIC_OPTION "}" \ STATIC_LIBLSAN_LIBS #else -#define LIBLSAN_SPEC "-llsan" STATIC_LIBLSAN_LIBS +#define LIBLSAN_SPEC "-llsan" STATIC_LIBLSAN_LIBS LIBSAN_RPATH #endif #endif @@ -843,9 +847,9 @@ proper position among the other output files. */ #ifdef HAVE_LD_STATIC_DYNAMIC #define LIBUBSAN_SPEC "%{static-libubsan:" LD_STATIC_OPTION \ "} -lubsan %{static-libubsan:" LD_DYNAMIC_OPTION "}" \ - STATIC_LIBUBSAN_LIBS + STATIC_LIBUBSAN_LIBS LIBSAN_RPATH #else -#define LIBUBSAN_SPEC "-lubsan" STATIC_LIBUBSAN_LIBS +#define LIBUBSAN_SPEC "-lubsan" STATIC_LIBUBSAN_LIBS LIBSAN_RPATH #endif #endif diff --git a/libsanitizer/Makefile.in b/libsanitizer/Makefile.in index f11219cae84..16eda5dffc7 100644 --- a/libsanitizer/Makefile.in +++ b/libsanitizer/Makefile.in @@ -334,6 +334,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/asan/Makefile.in b/libsanitizer/asan/Makefile.in index ef4b65dda97..d737e6fc94c 100644 --- a/libsanitizer/asan/Makefile.in +++ b/libsanitizer/asan/Makefile.in @@ -387,6 +387,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/configure b/libsanitizer/configure index 6bfd28916d2..eed0e6d62fc 100755 --- a/libsanitizer/configure +++ b/libsanitizer/configure @@ -661,6 +661,7 @@ link_libubsan link_libtsan link_libhwasan link_libasan +link_libsan_rpath HWASAN_SUPPORTED_FALSE HWASAN_SUPPORTED_TRUE LSAN_SUPPORTED_FALSE @@ -12475,7 +12476,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 12478 "configure" +#line 12479 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -12581,7 +12582,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 12584 "configure" +#line 12585 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -16132,6 +16133,15 @@ if test "x$ac_cv_lib_dl_dlsym" = xyes; then : fi +lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS \ + -print-multi-os-directory 2>/dev/null` +if test -n "$with_cross_host" && + test x"$with_cross_host" != x"no"; then + link_libsan_rpath="-rpath-link=%R/../../${target_alias}/lib/" + link_libsan_rpath="${link_libsan_rpath}$lt_multi_os_dir" +fi + + # Set up the set of additional libraries that we need to link against for libasan. link_libasan=$link_sanitizer_common diff --git a/libsanitizer/configure.ac b/libsanitizer/configure.ac index 8037c941774..db515303a09 100644 --- a/libsanitizer/configure.ac +++ b/libsanitizer/configure.ac @@ -120,6 +120,15 @@ AC_CHECK_LIB(rt, shm_open, AC_CHECK_LIB(dl, dlsym, [link_sanitizer_common="-ldl $link_sanitizer_common"]) +lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS \ + -print-multi-os-directory 2>/dev/null` +if test -n "$with_cross_host" && + test x"$with_cross_host" != x"no"; then + link_libsan_rpath="-rpath-link=%R/../../${target_alias}/lib/" + link_libsan_rpath="${link_libsan_rpath}$lt_multi_os_dir" +fi +AC_SUBST(link_libsan_rpath) + # Set up the set of additional libraries that we need to link against for libasan. link_libasan=$link_sanitizer_common AC_SUBST(link_libasan) diff --git a/libsanitizer/hwasan/Makefile.in b/libsanitizer/hwasan/Makefile.in index 4420bd6a7a9..dd6db8773b4 100644 --- a/libsanitizer/hwasan/Makefile.in +++ b/libsanitizer/hwasan/Makefile.in @@ -380,6 +380,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/interception/Makefile.in b/libsanitizer/interception/Makefile.in index 2d807c98d3b..1f06c1c7e3d 100644 --- a/libsanitizer/interception/Makefile.in +++ b/libsanitizer/interception/Makefile.in @@ -306,6 +306,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/libbacktrace/Makefile.in b/libsanitizer/libbacktrace/Makefile.in index 33faa78bb43..d60f85f774f 100644 --- a/libsanitizer/libbacktrace/Makefile.in +++ b/libsanitizer/libbacktrace/Makefile.in @@ -356,6 +356,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/libsanitizer.spec.in b/libsanitizer/libsanitizer.spec.in index 70a33574d7b..1df604335d5 100644 --- a/libsanitizer/libsanitizer.spec.in +++ b/libsanitizer/libsanitizer.spec.in @@ -11,3 +11,5 @@ *link_liblsan: @link_liblsan@ +*link_libsan_rpath: @link_libsan_rpath@ + diff --git a/libsanitizer/lsan/Makefile.in b/libsanitizer/lsan/Makefile.in index 0870f9e7136..80b538ddfdf 100644 --- a/libsanitizer/lsan/Makefile.in +++ b/libsanitizer/lsan/Makefile.in @@ -351,6 +351,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/sanitizer_common/Makefile.in b/libsanitizer/sanitizer_common/Makefile.in index df7a2549129..f27221df485 100644 --- a/libsanitizer/sanitizer_common/Makefile.in +++ b/libsanitizer/sanitizer_common/Makefile.in @@ -344,6 +344,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/tsan/Makefile.in b/libsanitizer/tsan/Makefile.in index 5bbdf3915b8..0382d436e99 100644 --- a/libsanitizer/tsan/Makefile.in +++ b/libsanitizer/tsan/Makefile.in @@ -380,6 +380,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ diff --git a/libsanitizer/ubsan/Makefile.in b/libsanitizer/ubsan/Makefile.in index 717d1571556..967dc180f10 100644 --- a/libsanitizer/ubsan/Makefile.in +++ b/libsanitizer/ubsan/Makefile.in @@ -345,6 +345,7 @@ libexecdir = @libexecdir@ link_libasan = @link_libasan@ link_libhwasan = @link_libhwasan@ link_liblsan = @link_liblsan@ +link_libsan_rpath = @link_libsan_rpath@ link_libtsan = @link_libtsan@ link_libubsan = @link_libubsan@ localedir = @localedir@ From patchwork Fri Jan 31 17:13:03 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:13:04 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Chao-ying Fu , Prachi Godbole , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 05/61] Hazard barrier return support Thread-Topic: [PATCH 05/61] Hazard barrier return support Thread-Index: AQHbdANj42X2lGq3k0a9DXNdVwoQjw== Date: Fri, 31 Jan 2025 17:13:03 +0000 Message-ID: <20250131171232.1018281-7-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|PR3PR09MB5442:EE_ x-ms-office365-filtering-correlation-id: 4fee6bbe-6dcb-4909-d05c-08dd421a85ec x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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(mips_function_attr_inlinable_p): Likewise. (mips_compute_frame_info): Set use_hazard_barrier_return_p. Emit error for unsupported architecture choice. (mips_function_ok_for_sibcall, mips_can_use_return_insn): Return false for use_hazard_barrier_return. (mips_expand_epilogue): Emit hazard barrier return. gcc/testsuite/ * gcc.target/mips/hazard-barrier-return-attribute.c: Modified test. Cherry-picked 42eb0571165dbb5ae518808ba7123b0b9db09a11 from https://github.com/MIPS/gcc Signed-off-by: Prachi Godbole Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Chao-ying Fu Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 60 +++++++++++++++++-- .../mips/hazard-barrier-return-attribute.c | 2 +- 2 files changed, 57 insertions(+), 5 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 392755316eb..9db2a2a9396 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -1391,6 +1391,16 @@ mips_get_code_readable_attr (tree decl) } +/* Check if the attribute to use hazard barrier return is set for + the function declaration DECL. */ + +static bool +mips_use_hazard_barrier_return_p (const_tree decl) +{ + return lookup_attribute ("use_hazard_barrier_return", + DECL_ATTRIBUTES (decl)) != NULL; +} + /* Return the set of compression modes that are explicitly required by the attributes in ATTRIBUTES. */ @@ -1576,6 +1586,21 @@ mips_can_inline_p (tree caller, tree callee) return default_target_can_inline_p (caller, callee); } +/* Implement TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P. + + A function reqeuesting clearing of all instruction and execution hazards + before returning cannot be inlined - thereby not clearing any hazards. + All our other function attributes are related to how out-of-line copies + should be compiled or called. They don't in themselves prevent inlining. */ + +static bool +mips_function_attr_inlinable_p (const_tree decl) +{ + if (mips_use_hazard_barrier_return_p (decl)) + return false; + return hook_bool_const_tree_true (decl); +} + /* Handle an "interrupt" attribute with an optional argument. */ static tree @@ -8350,6 +8375,11 @@ mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) && !targetm.binds_local_p (decl)) return false; + /* Can't generate sibling calls if returning from current function using + hazard barrier return. */ + if (mips_use_hazard_barrier_return_p (current_function_decl)) + return false; + /* Otherwise OK. */ return true; } @@ -11450,6 +11480,18 @@ mips_compute_frame_info (void) } } + /* Determine whether to use hazard barrier return or not. */ + if (mips_use_hazard_barrier_return_p (current_function_decl)) + { + if (mips_isa_rev < 2) + error ("hazard barrier returns require a MIPS32r2 processor or" + " greater"); + else if (TARGET_MIPS16) + error ("hazard barrier returns are not supported for MIPS16 functions"); + else + cfun->machine->use_hazard_barrier_return_p = true; + } + frame = &cfun->machine->frame; memset (frame, 0, sizeof (*frame)); size = get_frame_size (); @@ -13139,7 +13181,8 @@ mips_expand_epilogue (bool sibcall_p) && !crtl->calls_eh_return && !sibcall_p && step2 > 0 - && mips_unsigned_immediate_p (step2, 5, 2)) + && mips_unsigned_immediate_p (step2, 5, 2) + && !cfun->machine->use_hazard_barrier_return_p) use_jraddiusp_p = true; else /* Deallocate the final bit of the frame. */ @@ -13180,6 +13223,11 @@ mips_expand_epilogue (bool sibcall_p) else emit_jump_insn (gen_mips_eret ()); } + else if (cfun->machine->use_hazard_barrier_return_p) + { + rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); + emit_jump_insn (gen_mips_hb_return_internal (reg)); + } else { rtx pat; @@ -13238,6 +13286,11 @@ mips_can_use_return_insn (void) if (cfun->machine->interrupt_handler_p) return false; + /* Even if the function has a null epilogue, generating hazard barrier return + in epilogue handler is a lot cleaner and more manageable. */ + if (cfun->machine->use_hazard_barrier_return_p) + return false; + if (!reload_completed) return false; @@ -23506,10 +23559,9 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE mips_attribute_table -/* All our function attributes are related to how out-of-line copies should - be compiled or called. They don't in themselves prevent inlining. */ + #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P -#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true +#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P mips_function_attr_inlinable_p #undef TARGET_EXTRA_LIVE_ON_ENTRY #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry diff --git a/gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c b/gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c index 3575af44dcd..c5b1973af36 100644 --- a/gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c +++ b/gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c @@ -17,4 +17,4 @@ foo1 () } /* { dg-final { scan-assembler "foo0:" } } */ -/* { dg-final { scan-assembler-times "\tjr.hb\t\\\$31\n\tnop\\n" 1 } } */ +/* { dg-final { scan-assembler "(\tjr.hb\t\\\$31\n\tnop\\n|\tjrc.hb\t)" } } */ From patchwork Fri Jan 31 17:13:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105746 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0AF3E3858401 for ; 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+ +/* Enumerates the setting of the -mclib= option. */ +enum mips_lib_setting { + MIPS_LIB_NEWLIB, + MIPS_LIB_SMALL, + MIPS_LIB_TINY +}; #endif diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index fb696ed9957..cf3a4e04880 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -609,6 +609,12 @@ struct mips_cpu_info { if (mips_nan == MIPS_IEEE_754_2008) \ builtin_define ("__mips_nan2008"); \ \ + if (mips_c_lib == MIPS_LIB_SMALL) \ + builtin_define ("__mips_clib_small"); \ + \ + if (mips_c_lib == MIPS_LIB_TINY) \ + builtin_define ("__mips_clib_tiny"); \ + \ if (TARGET_BIG_ENDIAN) \ { \ builtin_define_std ("MIPSEB"); \ @@ -879,8 +885,8 @@ struct mips_cpu_info { /* Infer a -mnan=2008 setting from a -mips argument. */ #define MIPS_ISA_NAN2008_SPEC \ - "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \ - %{!msoft-float:-mnan=2008}}" + "%{mnan*:;mips32r6|mips64r6:-mnan=2008; \ + march=m51*|mclib=small|mclib=tiny:%{!msoft-float:-mnan=2008}}" #if (MIPS_ABI_DEFAULT == ABI_O64 \ || MIPS_ABI_DEFAULT == ABI_N32 \ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 99fe9301900..c04a3d9dbfa 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -508,3 +508,20 @@ Use Loongson EXTension (EXT) instructions. mloongson-ext2 Target Var(TARGET_LOONGSON_EXT2) Use Loongson EXTension R2 (EXT2) instructions. + +mclib= +Target RejectNegative Joined Var(mips_c_lib) ToLower Enum(mips_lib_setting) Init(MIPS_LIB_NEWLIB) +Specify the C library to use with this application. + +Enum +Name(mips_lib_setting) Type(enum mips_lib_setting) +Known MIPS C libraries (for use with the -mclib= option): + +EnumValue +Enum(mips_lib_setting) String(newlib) Value(MIPS_LIB_NEWLIB) + +EnumValue +Enum(mips_lib_setting) String(small) Value(MIPS_LIB_SMALL) + +EnumValue +Enum(mips_lib_setting) String(tiny) Value(MIPS_LIB_TINY) From patchwork Fri Jan 31 17:13:22 2025 Content-Type: text/plain; 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} -/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tshort_call_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnear_func\n" } } */ -/* { dg-final { scan-assembler-not "\tjal\tnormal_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tnear_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-2.c b/gcc/testsuite/gcc.target/mips/near-far-2.c index 2e8dbb17f7e..ed9757c4812 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-2.c +++ b/gcc/testsuite/gcc.target/mips/near-far-2.c @@ -16,8 +16,8 @@ int test () + normal_func ()); } -/* { dg-final { scan-assembler-not "\tjal(|s)\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tjal(|s)\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tshort_call_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnear_func\n" } } */ -/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t(jals?|balc)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t(jals?|balc)\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-3.c b/gcc/testsuite/gcc.target/mips/near-far-3.c index 19e1b3a7334..d4ad3e753b9 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-3.c +++ b/gcc/testsuite/gcc.target/mips/near-far-3.c @@ -13,8 +13,8 @@ NOMIPS16 int test3 () { return near_func (); } NOMIPS16 int test4 () { return normal_func (); } NOMIPS16 int test5 () { return short_call_func (); } -/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnear_func\n" } } */ -/* { dg-final { scan-assembler-not "\tj\tnormal_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tnear_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tshort_call_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-4.c b/gcc/testsuite/gcc.target/mips/near-far-4.c index ac7d7273814..37baad9b4f6 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-4.c +++ b/gcc/testsuite/gcc.target/mips/near-far-4.c @@ -13,8 +13,8 @@ NOMIPS16 int test3 () { return near_func (); } NOMIPS16 int test4 () { return normal_func (); } NOMIPS16 int test5 () { return short_call_func (); } -/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ -/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnear_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnormal_func\n" } } */ -/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tshort_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tlong_call_func\n" } } */ +/* { dg-final { scan-assembler-not "\t((j(|al|als))|b(|al)c)\tfar_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler "\t((j(|al|als))|b(|al)c)\tshort_call_func\n" } } */ From patchwork Fri Jan 31 17:13:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105748 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 94AD43858C52 for ; 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Cherry-picked fc330482ef0a8f93d44b9ff4c458691d7785cc77 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- contrib/test_installed | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/contrib/test_installed b/contrib/test_installed index fe9533e44b7..8de9cdf9847 100755 --- a/contrib/test_installed +++ b/contrib/test_installed @@ -110,10 +110,14 @@ set tmpdir "${tmpdir-`${PWDCMD-pwd}`}" set srcdir "${testsuite-${srcdir}/gcc/testsuite}" set CFLAGS "" set CXXFLAGS "" -set GCC_UNDER_TEST "${GCC_UNDER_TEST-${prefix}${prefix+/bin/}gcc}" -set GXX_UNDER_TEST "${GXX_UNDER_TEST-${prefix}${prefix+/bin/}g++}" -set GFORTRAN_UNDER_TEST "${GFORTRAN_UNDER_TEST-${prefix}${prefix+/bin/}gfortran}" -set OBJC_UNDER_TEST "${OBJC_UNDER_TEST-${prefix}${prefix+/bin/}gcc}" +set GCC_UNDER_TEST "${GCC_UNDER_TEST-${prefix}${prefix+/bin/}\ +${target+$target-}gcc}" +set GXX_UNDER_TEST "${GXX_UNDER_TEST-${prefix}${prefix+/bin/}\ +${target+$target-}g++}" +set GFORTRAN_UNDER_TEST "${GFORTRAN_UNDER_TEST-${prefix}${prefix+/bin/}\ +${target+$target-}gfortran}" +set OBJC_UNDER_TEST "${OBJC_UNDER_TEST-${prefix}${prefix+/bin/}\ +${target+$target-}gcc}" set HOSTCC "${HOSTCC-cc}" set HOSTCXX "${HOSTCXX-c++}" set HOSTCFLAGS "" From patchwork Fri Jan 31 17:13:23 2025 Content-Type: text/plain; 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By growing the frame downwards we get spill slots created at the lowest address rather than highest address in a local frame. The benefit being that when the frame is large the spill slots can still be accessed using a 16bit instruction whereas it is less important for large local variables to be accessed using short instructions as they are (probably) accessed less frequently. This is default on for MIPS16. Cherry-picked 7c1bf276c0ebb45c87fe7bc30f057866d6153ec4 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.h | 10 ++++++++-- gcc/config/mips/mips.opt | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index cf3a4e04880..535172d3406 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2365,8 +2365,14 @@ enum reg_class #define STACK_GROWS_DOWNWARD 1 -#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ - || (flag_sanitize & SANITIZE_ADDRESS) != 0) +/* Growing the frame downwards allows us to put spills closest to + the stack pointer which is good as they are likely to be accessed + frequently. We can also arrange for normal stack usage to place + scalars last so that they too are close to the stack pointer. */ +#define FRAME_GROWS_DOWNWARD ((TARGET_MIPS16 \ + && TARGET_FRAME_GROWS_DOWNWARDS) \ + || (flag_stack_protect != 0 \ + || (flag_sanitize & SANITIZE_ADDRESS) != 0)) /* Size of the area allocated in the frame to save the GP. */ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index c04a3d9dbfa..ca4d377291e 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -473,6 +473,10 @@ mframe-header-opt Target Var(flag_frame_header_optimization) Optimization Optimize frame header. +mgrow-frame-downwards +Target Var(TARGET_FRAME_GROWS_DOWNWARDS) Init(1) Undocumented +Change the behaviour to grow the frame downwards. + noasmopt Driver From patchwork Fri Jan 31 17:13:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105759 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CD4FD3857739 for ; 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This means that just doing a straight address comparision of a rtx against stack_pointer_rtx to see whether it is the stack pointer register will not be correct in all cases. This patch rewrites these comparisons to check that firstly the rtx is a register and its register number is STACK_POINTER_REGNUM. Cherry-picked 1a066c0af8e7ccf36e8c3f01529c90603a981c18 from https://github.com/MIPS/gcc Signed-off-by: Andrew Bennett Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 16 +++++++++------- gcc/config/mips/mips.md | 2 +- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 9db2a2a9396..69c5cdbe20d 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2804,7 +2804,7 @@ mips_stack_address_p (rtx x, machine_mode mode) return (mips_classify_address (&addr, x, mode, false) && addr.type == ADDRESS_REG - && addr.reg == stack_pointer_rtx); + && REGNO (addr.reg) == STACK_POINTER_REGNUM); } /* Return true if ADDR matches the pattern for the LWXS load scaled indexed @@ -2870,7 +2870,8 @@ mips16_unextended_reference_p (machine_mode mode, rtx base, if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0 && REGNO (base) != GLOBAL_POINTER_REGNUM) { - if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) + if (GET_MODE_SIZE (mode) == 4 && GET_CODE (base) == REG + && REGNO (base) == STACK_POINTER_REGNUM) return offset < 256U * GET_MODE_SIZE (mode); return offset < 32U * GET_MODE_SIZE (mode); } @@ -9879,7 +9880,7 @@ mips_debugger_offset (rtx addr, HOST_WIDE_INT offset) if (offset == 0) offset = INTVAL (offset2); - if (reg == stack_pointer_rtx + if ((GET_CODE (reg) == REG && REGNO (reg) == STACK_POINTER_REGNUM) || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx) { @@ -10622,7 +10623,7 @@ mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values, required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD; if (base == hard_frame_pointer_rtx) required_offset -= cfun->machine->frame.hard_frame_pointer_offset; - else if (base != stack_pointer_rtx) + else if (!(GET_CODE (base) == REG && REGNO (base) == STACK_POINTER_REGNUM)) return false; if (offset != required_offset) return false; @@ -10833,7 +10834,7 @@ mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust, /* Check that the address is the sum of the stack pointer and a possibly-zero constant offset. */ mips_split_plus (XEXP (mem, 0), &base, &offset); - if (base != stack_pointer_rtx) + if (!(GET_CODE (base) == REG && REGNO (base) == STACK_POINTER_REGNUM)) return false; /* Check that SET's other operand is a register. */ @@ -13001,7 +13002,8 @@ mips_restore_reg (rtx reg, rtx mem) static void mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size) { - if (base == stack_pointer_rtx && offset == const0_rtx) + if (GET_CODE (base) == REG && REGNO (base) == STACK_POINTER_REGNUM + && offset == const0_rtx) return; mips_frame_barrier (); @@ -18222,7 +18224,7 @@ r10k_simplify_address (rtx x, rtx_insn *insn) { /* Replace the incoming value of $sp with virtual_incoming_args_rtx. */ - if (x == stack_pointer_rtx + if (GET_CODE (x) == REG && REGNO (x) == STACK_POINTER_REGNUM && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun)) newx = virtual_incoming_args_rtx; } diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index f147667d63a..4b486a7ad29 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7714,7 +7714,7 @@ [(set (match_operand:SI 1 "register_operand") (plus:SI (match_dup 1) (match_operand:SI 2 "const_int_operand")))])] - "operands[1] == stack_pointer_rtx + "GET_CODE (operands[1]) == REG && REGNO (operands[1]) == STACK_POINTER_REGNUM && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)" { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); 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Some micromips insns have length of 2, but unfortuantely 2/4 returns 0, so the routine incorrectly thinks that the instruction is a barrier and does not reset the fs_delay state. This patch does need to check whether the hilo calculcation is still ok for micromips instructions. - Add undocumented command line option to enable forbidden slot filling. Option is -mforbidden-slots. - Fix micromips r6 issue with clear_hazard insn. - Prevent -mdsp and -mdspr2 with -mmicromips -mips32r6. - Update ZC/ZD constraints for microMIPS R6 9-bit offsets. - LWXS removed for microMIPS R6. - Add DSPr3 support. - Add m6201 architecture and scheduler. - Ensure micromips is always considered NAN2008 for hard-float. Cherry-picked 02af969d5f07fb73f23cedd95a82fe581ccfe820 from https://github.com/MIPS/gcc Signed-off-by: Andrew Bennett Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/constraints.md | 33 ++-- gcc/config/mips/m6200.md | 229 +++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 3 + gcc/config/mips/mips-dsp.md | 17 +- gcc/config/mips/mips-tables.opt | 49 +++--- gcc/config/mips/mips.cc | 54 ++++-- gcc/config/mips/mips.h | 40 +++-- gcc/config/mips/mips.md | 88 ++++++++-- gcc/config/mips/mips.opt | 7 + gcc/config/mips/ml-img-elf | 4 + gcc/config/mips/ml-img-linux | 4 + gcc/config/mips/t-mips-multi | 43 +++++ gcc/doc/invoke.texi | 2 +- gcc/doc/md.texi | 11 +- gcc/testsuite/gcc.target/mips/mips.exp | 1 - 15 files changed, 498 insertions(+), 87 deletions(-) create mode 100644 gcc/config/mips/m6200.md diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index a96028dd746..3b8fe9c3b70 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -368,25 +368,30 @@ (match_test "mips_const_vector_same_bytes_p (op, mode)"))) (define_memory_constraint "ZC" - "A memory operand whose address is formed by a base register and offset - that is suitable for use in instructions with the same addressing mode - as @code{ll} and @code{sc}." + "When compiling R6 code, this constraint matches a memory operand whose + address is formed from a base register and a 9-bit offset. + When compiling microMIPS code, this constraint matches a memory operand + whose address is formed from a base register and a 12-bit offset. + When not compiling for microMIPS nor R6, @code{ZC} is equivalent to + @code{R}. + These operands can be used for instructions such as @code{ll} and + @code{sc}." (and (match_code "mem") - (if_then_else - (match_test "TARGET_MICROMIPS") - (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)") - (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT") - (match_test "mips_9bit_offset_address_p (XEXP (op, 0), mode)") - (match_test "mips_address_insns (XEXP (op, 0), mode, false)"))))) + (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT") + (match_test "mips_9bit_offset_address_p (XEXP (op, 0), mode)") + (if_then_else + (match_test "TARGET_MICROMIPS") + (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)") + (match_test "mips_address_insns (XEXP (op, 0), mode, false)"))))) (define_address_constraint "ZD" "An address suitable for a @code{prefetch} instruction, or for any other instruction with the same addressing mode as @code{prefetch}." - (if_then_else (match_test "TARGET_MICROMIPS") - (match_test "umips_12bit_offset_address_p (op, mode)") - (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT") - (match_test "mips_9bit_offset_address_p (op, mode)") - (match_test "mips_address_insns (op, mode, false)")))) + (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT") + (match_test "mips_9bit_offset_address_p (op, mode)") + (if_then_else (match_test "TARGET_MICROMIPS") + (match_test "umips_12bit_offset_address_p (op, mode)") + (match_test "mips_address_insns (op, mode, false)")))) (define_memory_constraint "ZR" "@internal diff --git a/gcc/config/mips/m6200.md b/gcc/config/mips/m6200.md new file mode 100644 index 00000000000..10f07475be0 --- /dev/null +++ b/gcc/config/mips/m6200.md @@ -0,0 +1,229 @@ +;; DFA-based pipeline description for MIPS32 models M6200. +;; +;; Copyright (C) 2024 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "m62_alu_pipe, m62_mdu_pipe, m62_fpu_pipe") +(define_cpu_unit "m62_mul" "m62_mdu_pipe") +(define_cpu_unit "m62_alu" "m62_alu_pipe") +(define_cpu_unit "m62_fpu" "m62_fpu_pipe") + +;; -------------------------------------------------------------- +;; ALU Instructions +;; -------------------------------------------------------------- + +;; ALU: Logicals +(define_insn_reservation "m62_int_logical" 1 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "logical,move,signext,slt")) + "m62_alu") + +;; Arithmetics +(define_insn_reservation "m62_int" 1 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "arith,const,shift,clz")) + "m62_alu") + +(define_insn_reservation "m62_int_nop" 0 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "nop")) + "nothing") + +;; Conditional move +(define_insn_reservation "m62_int_cmove" 1 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "condmove") + (eq_attr "mode" "SI,DI"))) + "m62_alu") + +;; Call +(define_insn_reservation "m62_int_call" 1 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "call")) + "m62_alu") + +;; branch/jump +(define_insn_reservation "m62_int_jump" 1 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "branch,jump")) + "m62_alu") + +;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs +;; prefetch: prefetch, prefetchx +(define_insn_reservation "m62_int_load" 2 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "load,multimem,prefetch,prefetchx")) + "m62_alu") + +;; stores +(define_insn_reservation "m62_int_store" 1 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "store,multimem")) + "m62_alu") + +;; load->next use : 2 cycles (Default) +;; load->load base: 3 cycles +;; load->store base: 3 cycles +;; load->store: 1 cycles +(define_bypass 3 "m62_int_load" "m62_int_load") +(define_bypass 3 "m62_int_load" "m62_int_store" "!mips_store_data_bypass_p") +(define_bypass 1 "m62_int_load" "m62_int_store" "mips_store_data_bypass_p") + +;; ALU->load base: 2 cycles +;; ALU->store base: 2 cycles +(define_bypass 2 "m62_int" "m62_int_load") +(define_bypass 2 "m62_int_logical" "m62_int_load") +(define_bypass 2 "m62_int_cmove" "m62_int_load") +(define_bypass 2 "m62_int" "m62_int_store" "!mips_store_data_bypass_p") +(define_bypass 2 "m62_int_logical" "m62_int_store" "!mips_store_data_bypass_p") +(define_bypass 2 "m62_int_cmove" "m62_int_store" "!mips_store_data_bypass_p") + +;; -------------------------------------------------------------- +;; MDU Instructions +;; -------------------------------------------------------------- + +;; High performance fully pipelined multiplier +;; MUL to GPR +(define_insn_reservation "m62_int_mul3" 2 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "imul3,imul3nc")) + "(m62_alu*2)+(m62_mul*2)") + + +;; div +(define_insn_reservation "m62_int_div_si" 34 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "idiv,idiv3")) + "m62_alu+m62_mul*34") + +(define_bypass 2 "m62_int" "m62_int_mul3") +(define_bypass 3 "m62_int_load" "m62_int_mul3") + +(define_bypass 3 "m62_int_mul3" "m62_int_store" "!mips_store_data_bypass_p") +(define_bypass 3 "m62_int_mul3" "m62_int_load") + +(define_bypass 36 "m62_int_div_si" "m62_int_store" "!mips_store_data_bypass_p") +(define_bypass 36 "m62_int_div_si" "m62_int_load") + +;; -------------------------------------------------------------- +;; Floating Point Instructions +;; -------------------------------------------------------------- + +;; fadd, fabs, fneg +(define_insn_reservation "m62_fadd" 4 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "fadd,fabs,fneg")) + "m62_fpu") + +;; fmove +(define_insn_reservation "m62_fmove" 4 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "fmove")) + "m62_fpu") + +;; conditional move +(define_insn_reservation "m62_fp_cmove" 4 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "condmove") + (eq_attr "mode" "SF,DF"))) + "m62_fpu") + +;; fload +(define_insn_reservation "m62_fload" 3 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "fpload,fpidxload")) + "m62_fpu") + +;; fstore +(define_insn_reservation "m62_fstore" 1 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "fpstore,fpidxstore")) + "m62_fpu") + +;; fmul, fmadd +(define_insn_reservation "m62_fmul_sf" 4 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "SF"))) + "m62_fpu") + +(define_insn_reservation "m62_fmul_df" 5 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "DF"))) + "m62_fpu*2") + +;; fdiv, fsqrt +(define_insn_reservation "m62_fdiv_sf" 17 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "SF"))) + "m62_fpu*14") + +(define_insn_reservation "m62_fdiv_df" 32 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "DF"))) + "m62_fpu*29") + +;; frsqrt +(define_insn_reservation "m62_frsqrt_sf" 17 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "frsqrt") + (eq_attr "mode" "SF"))) + "m62_fpu*14") + +(define_insn_reservation "m62_frsqrt_df" 35 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "frsqrt") + (eq_attr "mode" "DF"))) + "m62_fpu*31") + +;; fcmp +(define_insn_reservation "m62_fcmp" 4 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "fcmp")) + "m62_fpu") + +;; fcvt +;; cvt.s.d +(define_insn_reservation "m62_fcvt_6" 6 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "D2S"))) + "m62_fpu") + +;; trunc +(define_insn_reservation "m62_fcvt_5" 5 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "D2I,S2I"))) + "m62_fpu") + +;; cvt +(define_insn_reservation "m62_fcvt_4" 4 + (and (eq_attr "cpu" "m6200") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "S2D,I2D,I2S"))) + "m62_fpu") + +;; mtc, mfc +(define_insn_reservation "m62_move_to_from_c1" 2 + (and (eq_attr "cpu" "m6200") + (eq_attr "type" "mtc, mfc")) + "m62_fpu") diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 17bbba42bd6..50843480b03 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -152,6 +152,9 @@ MIPS_CPU ("p5600", PROCESSOR_P5600, MIPS_ISA_MIPS32R5, (PTF_AVOID_BRANCHLIKELY_S MIPS_CPU ("m5100", PROCESSOR_M5100, MIPS_ISA_MIPS32R5, PTF_AVOID_BRANCHLIKELY_SPEED) MIPS_CPU ("m5101", PROCESSOR_M5100, MIPS_ISA_MIPS32R5, PTF_AVOID_BRANCHLIKELY_SPEED) +/* MIPS32 Release 6 processors. */ +MIPS_CPU ("m6201", PROCESSOR_M6200, MIPS_ISA_MIPS32R6, 0) + /* MIPS64 processors. */ MIPS_CPU ("5kc", PROCESSOR_5KC, MIPS_ISA_MIPS64, 0) MIPS_CPU ("5kf", PROCESSOR_5KF, MIPS_ISA_MIPS64, 0) diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md index ac3efb28cf3..f39636ff959 100644 --- a/gcc/config/mips/mips-dsp.md +++ b/gcc/config/mips/mips-dsp.md @@ -1152,8 +1152,21 @@ (label_ref (match_operand 0 "" "")) (pc)))] "ISA_HAS_DSP" - "%*bposge%1\t%0%/" - [(set_attr "type" "branch")]) +{ + if (TARGET_DSPR3 && TARGET_CB_MAYBE) + return "%*bposge%1%:\t%0"; + else + return "%*bposge%1\t%0%/"; +} + [(set_attr "type" "branch") + (set (attr "compact_form") (if_then_else (match_test "TARGET_DSPR3 + && TARGET_CB_MAYBE") + (const_string "maybe") + (const_string "never"))) + (set (attr "hazard") (if_then_else (match_test "TARGET_DSPR3 + && TARGET_CB_MAYBE") + (const_string "forbidden_slot") + (const_string "none")))]) (define_expand "mips_madd" [(set (match_operand:DI 0 "register_operand") diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 874157d22bd..c26009cfb5c 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -643,71 +643,74 @@ EnumValue Enum(mips_arch_opt_value) String(m5101) Value(88) Canonical EnumValue -Enum(mips_arch_opt_value) String(5kc) Value(89) Canonical +Enum(mips_arch_opt_value) String(m6201) Value(89) Canonical EnumValue -Enum(mips_arch_opt_value) String(r5kc) Value(89) +Enum(mips_arch_opt_value) String(5kc) Value(90) Canonical EnumValue -Enum(mips_arch_opt_value) String(5kf) Value(90) Canonical +Enum(mips_arch_opt_value) String(r5kc) Value(90) EnumValue -Enum(mips_arch_opt_value) String(r5kf) Value(90) +Enum(mips_arch_opt_value) String(5kf) Value(91) Canonical EnumValue -Enum(mips_arch_opt_value) String(20kc) Value(91) Canonical +Enum(mips_arch_opt_value) String(r5kf) Value(91) EnumValue -Enum(mips_arch_opt_value) String(r20kc) Value(91) +Enum(mips_arch_opt_value) String(20kc) Value(92) Canonical EnumValue -Enum(mips_arch_opt_value) String(sb1) Value(92) Canonical +Enum(mips_arch_opt_value) String(r20kc) Value(92) EnumValue -Enum(mips_arch_opt_value) String(sb1a) Value(93) Canonical +Enum(mips_arch_opt_value) String(sb1) Value(93) Canonical EnumValue -Enum(mips_arch_opt_value) String(sr71000) Value(94) Canonical +Enum(mips_arch_opt_value) String(sb1a) Value(94) Canonical EnumValue -Enum(mips_arch_opt_value) String(sr71k) Value(94) +Enum(mips_arch_opt_value) String(sr71000) Value(95) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlr) Value(95) Canonical +Enum(mips_arch_opt_value) String(sr71k) Value(95) EnumValue -Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical +Enum(mips_arch_opt_value) String(xlr) Value(96) Canonical EnumValue -Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical +Enum(mips_arch_opt_value) String(loongson3a) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical +Enum(mips_arch_opt_value) String(gs464) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical +Enum(mips_arch_opt_value) String(gs464e) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical +Enum(mips_arch_opt_value) String(gs264e) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(105) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(106) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(107) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(108) Canonical diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 69c5cdbe20d..069c7ef6a42 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -1164,7 +1164,20 @@ static const struct mips_rtx_cost_data COSTS_N_INSNS (8), /* int_div_di */ 2, /* branch_cost */ 4 /* memory_latency */ - } + }, + { /* M6200 */ + COSTS_N_INSNS (4), /* fp_add */ + COSTS_N_INSNS (4), /* fp_mult_sf */ + COSTS_N_INSNS (5), /* fp_mult_df */ + COSTS_N_INSNS (17), /* fp_div_sf */ + COSTS_N_INSNS (32), /* fp_div_df */ + COSTS_N_INSNS (5), /* int_mult_si */ + COSTS_N_INSNS (5), /* int_mult_di */ + COSTS_N_INSNS (34), /* int_div_si */ + COSTS_N_INSNS (68), /* int_div_di */ + 1, /* branch_cost */ + 4 /* memory_latency */ + } }; static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool); @@ -5400,7 +5413,12 @@ mips_output_move (rtx dest, rtx src) /* Moves to HI are handled by special .md insns. */ if (REGNO (dest) == LO_REGNUM) - return "mtlo\t%z1"; + { + if (ISA_HAS_MULT) + return "mtlo\t%z1"; + else + return "mtlo\t%z1,$ac0"; + } if (DSP_ACC_REG_P (REGNO (dest))) { @@ -5453,7 +5471,10 @@ mips_output_move (rtx dest, rtx src) -mfix-vr4130. */ if (ISA_HAS_MACCHI) return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; - return "mflo\t%0"; + if (ISA_HAS_MULT) + return "mflo\t%0"; + else + return "mflo\t%0,$ac0"; } if (DSP_ACC_REG_P (REGNO (src))) @@ -19008,7 +19029,7 @@ mips_mult_zero_zero_cost (struct mips_sim *state, bool setting) static void mips_set_fast_mult_zero_zero_p (struct mips_sim *state) { - if (TARGET_MIPS16 || !ISA_HAS_HILO) + if (TARGET_MIPS16 || (!ISA_HAS_HILO && !TARGET_DSP)) /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO registers then there is no reason to zero them, arbitrarily choose to say that "MULT $0,$0" would be faster. */ @@ -19404,7 +19425,7 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, /* Ignore zero-length instructions (barriers and the like). */ ninsns = get_attr_length (insn) / 4; - if (ninsns == 0) + if (get_attr_length (insn) == 0) return; /* Work out how many nops are needed. Note that we only care about @@ -19419,7 +19440,8 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, branch instruction was not in a sequence (as the sequence would imply it is not actually a compact branch anyway) and the current insn is not an inline asm, and can't go in a delay slot. */ - else if (*fs_delay && get_attr_can_delay (insn) == CAN_DELAY_NO + else if (TARGET_FORBIDDEN_SLOTS && *fs_delay + && get_attr_can_delay (insn) == CAN_DELAY_NO && GET_CODE (PATTERN (after)) != SEQUENCE && GET_CODE (pattern) != ASM_INPUT && asm_noperands (pattern) < 0) @@ -20446,6 +20468,7 @@ static void mips_option_override (void) { int i, regno, mode; + unsigned int is_micromips; if (OPTION_SET_P (mips_isa_option)) mips_isa_option_info = &mips_cpu_info_table[mips_isa_option]; @@ -20466,6 +20489,7 @@ mips_option_override (void) /* Save the base compression state and process flags as though we were generating uncompressed code. */ mips_base_compression_flags = TARGET_COMPRESSION; + is_micromips = TARGET_MICROMIPS; target_flags &= ~TARGET_COMPRESSION; mips_base_code_readable = mips_code_readable; @@ -20706,7 +20730,7 @@ mips_option_override (void) if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER) { error ("unsupported combination: %qs%s %s", - mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "", + mips_arch_info->name, is_micromips ? " -mmicromips" : "", "-mcompact-branches=never"); } @@ -20863,12 +20887,16 @@ mips_option_override (void) if (TARGET_DSPR2) TARGET_DSP = true; - if (TARGET_DSP && mips_isa_rev >= 6) + if (is_micromips && mips_isa_rev >= 6 + && (TARGET_DSP || TARGET_DSPR2) + && !TARGET_DSPR3) + error ("unsupported combination: -mmicromips -mips32r6 %s, use " + "-mdspr3 instead", TARGET_DSPR2 ? "-mdspr2" : "-mdsp"); + + if (TARGET_DSPR3) { - error ("the %qs architecture does not support DSP instructions", - mips_arch_info->name); - TARGET_DSP = false; - TARGET_DSPR2 = false; + TARGET_DSP = true; + TARGET_DSPR2 = true; } /* Make sure that when TARGET_LOONGSON_MMI is true, TARGET_HARD_FLOAT_ABI @@ -21064,7 +21092,7 @@ mips_conditional_register_usage (void) else accessible_reg_set &= ~reg_class_contents[DSP_ACC_REGS]; - if (!ISA_HAS_HILO) + if (!ISA_HAS_HILO && !ISA_HAS_DSP) accessible_reg_set &= ~reg_class_contents[MD_REGS]; if (!TARGET_HARD_FLOAT) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 535172d3406..70a7b2032dc 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -116,6 +116,9 @@ struct mips_cpu_info { /* Run-time compilation parameters selecting different hardware subsets. */ +/* True if we are targetting micromips R6 onwards. */ +#define TARGET_MICROMIPS_R6 (TARGET_MICROMIPS && mips_isa_rev >= 6) + /* True if we are generating position-independent VxWorks RTP code. */ #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic) @@ -509,6 +512,11 @@ struct mips_cpu_info { builtin_define ("__mips_dspr2"); \ builtin_define ("__mips_dsp_rev=2"); \ } \ + else if (TARGET_DSPR3) \ + { \ + builtin_define ("__mips_dspr3"); \ + builtin_define ("__mips_dsp_rev=3"); \ + } \ else \ builtin_define ("__mips_dsp_rev=1"); \ } \ @@ -838,7 +846,7 @@ struct mips_cpu_info { |march=interaptiv: -mips32r2} \ %{march=mips32r3: -mips32r3} \ %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \ - %{march=mips32r6: -mips32r6} \ + %{march=mips32r6|march=m6201: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ @@ -862,7 +870,8 @@ struct mips_cpu_info { "%{mhard-float|msoft-float|mno-float|march=mips*:; \ march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \ - |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \ + |march=m14k*|march=m5101|march=m6201|march=octeon \ + |march=xlr: -msoft-float; \ march=*: -mhard-float}" /* A spec condition that matches 32-bit options. It only works if @@ -886,7 +895,7 @@ struct mips_cpu_info { /* Infer a -mnan=2008 setting from a -mips argument. */ #define MIPS_ISA_NAN2008_SPEC \ "%{mnan*:;mips32r6|mips64r6:-mnan=2008; \ - march=m51*|mclib=small|mclib=tiny:%{!msoft-float:-mnan=2008}}" + mmicromips|march=m51*|mclib=small|mclib=tiny:%{!msoft-float:-mnan=2008}}" #if (MIPS_ABI_DEFAULT == ABI_O64 \ || MIPS_ABI_DEFAULT == ABI_N32 \ @@ -955,7 +964,9 @@ struct mips_cpu_info { "%{!mno-dsp: \ %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \ |march=interaptiv: -mdsp} \ - %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" + %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" \ + "%{!mforbidden-slots: \ + %{mips32r6|mips64r6:%{mmicromips:-mno-forbidden-slots}}}" #define MIPS_ASE_LOONGSON_MMI_SPEC \ "%{!mno-loongson-mmi: \ @@ -1011,7 +1022,8 @@ struct mips_cpu_info { #define ISA_HAS_JR (mips_isa_rev <= 5) -#define ISA_HAS_DELAY_SLOTS 1 +#define ISA_HAS_DELAY_SLOTS (mips_isa_rev <= 5 \ + || !TARGET_MICROMIPS) #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6) @@ -1295,7 +1307,8 @@ struct mips_cpu_info { && mips_isa_rev >= 2) /* ISA has lwxs instruction (load w/scaled index address. */ -#define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \ +#define ISA_HAS_LWXS ((TARGET_SMARTMIPS \ + || (TARGET_MICROMIPS && mips_isa_rev <= 5)) \ && !TARGET_MIPS16) /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */ @@ -1459,6 +1472,7 @@ struct mips_cpu_info { %{mdmx} %{mno-mdmx:-no-mdmx} \ %{mdsp} %{mno-dsp} \ %{mdspr2} %{mno-dspr2} \ +%{mdspr3} %{mno-dspr3} \ %{mmcu} %{mno-mcu} \ %{meva} %{mno-eva} \ %{mvirt} %{mno-virt} \ @@ -1483,6 +1497,7 @@ struct mips_cpu_info { %{modd-spreg} %{mno-odd-spreg} \ %{mshared} %{mno-shared} \ %{msym32} %{mno-sym32} \ +%{mforbidden-slots} \ %{mtune=*}" \ FP_ASM_SPEC "\ %{mmips16e2} \ @@ -3185,9 +3200,8 @@ while (0) asm (SECTION_OP "\n\ .set push\n\ .set nomips16\n\ - .set noreorder\n\ bal 1f\n\ - nop\n\ + .set noreorder\n\ 1: .cpload $31\n\ .set reorder\n\ la $25, " USER_LABEL_PREFIX #FUNC "\n\ @@ -3199,11 +3213,8 @@ while (0) asm (SECTION_OP "\n\ .set push\n\ .set nomips16\n\ - .set noreorder\n\ bal 1f\n\ - nop\n\ -1: .set reorder\n\ - .cpsetup $31, $2, 1b\n\ +1: .cpsetup $31, $2, 1b\n\ la $25, " USER_LABEL_PREFIX #FUNC "\n\ jalr $25\n\ .set pop\n\ @@ -3213,11 +3224,8 @@ while (0) asm (SECTION_OP "\n\ .set push\n\ .set nomips16\n\ - .set noreorder\n\ bal 1f\n\ - nop\n\ -1: .set reorder\n\ - .cpsetup $31, $2, 1b\n\ +1: .cpsetup $31, $2, 1b\n\ dla $25, " USER_LABEL_PREFIX #FUNC "\n\ jalr $25\n\ .set pop\n\ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4b486a7ad29..f67fa2e66be 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -72,6 +72,7 @@ m5100 i6400 p6600 + m6200 ]) (define_c_enum "unspec" [ @@ -1182,6 +1183,7 @@ (include "p5600.md") (include "m5100.md") (include "p6600.md") +(include "m6200.md") (include "4k.md") (include "5k.md") (include "20kc.md") @@ -2116,7 +2118,7 @@ [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP) && ISA_HAS_MULT" + "!TARGET_64BIT && ((!TARGET_FIX_R4000 && ISA_HAS_MULT) || ISA_HAS_DSP)" { if (ISA_HAS_DSP_MULT) return "mult\t%q0,%1,%2"; @@ -5467,7 +5469,8 @@ (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")] UNSPEC_MFHI))] "" - { return ISA_HAS_MACCHI ? "macchi\t%0,%.,%." : "mfhi\t%0"; } + { return ISA_HAS_MACCHI ? "macchi\t%0,%.,%." : + ISA_HAS_MULT ? "mfhi\t%0" : "mfhi\t%0,$ac0"; } [(set_attr "type" "mfhi") (set_attr "mode" "")]) @@ -5480,7 +5483,12 @@ (match_operand:GPR 2 "register_operand" "l")] UNSPEC_MTHI))] "" - "mthi\t%z1" + { + if (ISA_HAS_MULT) + return "mthi\t%z1"; + else + return "mthi\t%z1, $ac0"; + } [(set_attr "type" "mthi") (set_attr "mode" "SI")]) @@ -5730,7 +5738,12 @@ { mips_expand_synci_loop (operands[0], operands[1]); emit_insn (gen_sync ()); - emit_insn (PMODE_INSN (gen_clear_hazard, ())); + if (TARGET_MICROMIPS_R6) + emit_insn (PMODE_INSN (gen_clear_hazard_ur6, ())); + else if (ISA_HAS_R6MUL) + emit_insn (PMODE_INSN (gen_clear_hazard_r6, ())); + else + emit_insn (PMODE_INSN (gen_clear_hazard, ())); } else if (mips_cache_flush_func && mips_cache_flush_func[0]) { @@ -5767,11 +5780,36 @@ return "%(%addiu\t$31,$31,12\n" - "\tjr.hb\t$31\n" - "\tnop%>%)"; + "\tjr.hb\t$31\n" + "\tnop%>%)"; } [(set_attr "insn_count" "5")]) +(define_insn "clear_hazard_ur6_" + [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD) + (clobber (match_scratch:P 0 "=d"))] + "ISA_HAS_SYNCI && TARGET_MICROMIPS_R6" +{ + return "%(%addiu\t%0,%0,%%pcrel_lo(1f+4)\n" + "\tjrc.hb\t%0\n" + "1:%>%)"; +} + [(set_attr "insn_count" "3")]) + +(define_insn "clear_hazard_r6_" + [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD) + (clobber (match_scratch:P 0 "=d"))] + "ISA_HAS_SYNCI && ISA_HAS_R6MUL && !TARGET_MICROMIPS_R6" +{ + return "%(%addiu\t%0,%0,%%pcrel_lo(1f+4)\n" + "\tjr.hb\t%0\n" + "\tnop\n" + "1:%>%)"; +} + [(set_attr "insn_count" "4")]) + ;; Cache operations for R4000-style caches. (define_insn "mips_cache" [(set (mem:BLK (scratch)) @@ -6074,11 +6112,22 @@ (pc)))] "TARGET_HARD_FLOAT" { - return mips_output_conditional_branch (insn, operands, - MIPS_BRANCH ("b%F1", "%Z2%0"), - MIPS_BRANCH ("b%W1", "%Z2%0")); + if (TARGET_MICROMIPS_R6) + return mips_output_conditional_branch (insn, operands, + MIPS_BRANCH_C ("b%F1", "%Z2%0"), + MIPS_BRANCH_C ("b%W1", "%Z2%0")); + else + return mips_output_conditional_branch (insn, operands, + MIPS_BRANCH ("b%F1", "%Z2%0"), + MIPS_BRANCH ("b%W1", "%Z2%0")); } - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set (attr "compact_form") (if_then_else (match_test "TARGET_MICROMIPS_R6") + (const_string "always") + (const_string "never"))) + (set (attr "hazard") (if_then_else (match_test "TARGET_MICROMIPS_R6") + (const_string "forbidden_slot") + (const_string "none")))]) (define_insn "*branch_fp_inverted_" [(set (pc) @@ -6090,11 +6139,22 @@ (label_ref (match_operand 0 "" ""))))] "TARGET_HARD_FLOAT" { - return mips_output_conditional_branch (insn, operands, - MIPS_BRANCH ("b%W1", "%Z2%0"), - MIPS_BRANCH ("b%F1", "%Z2%0")); + if (TARGET_MICROMIPS_R6) + return mips_output_conditional_branch (insn, operands, + MIPS_BRANCH_C ("b%W1", "%Z2%0"), + MIPS_BRANCH_C ("b%F1", "%Z2%0")); + else + return mips_output_conditional_branch (insn, operands, + MIPS_BRANCH ("b%W1", "%Z2%0"), + MIPS_BRANCH ("b%F1", "%Z2%0")); } - [(set_attr "type" "branch")]) + [(set_attr "type" "branch") + (set (attr "compact_form") (if_then_else (match_test "TARGET_MICROMIPS_R6") + (const_string "always") + (const_string "never"))) + (set (attr "hazard") (if_then_else (match_test "TARGET_MICROMIPS_R6") + (const_string "forbidden_slot") + (const_string "none")))]) ;; Conditional branches on ordered comparisons with zero. diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index ca4d377291e..201a9650915 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -123,6 +123,10 @@ mdspr2 Target Var(TARGET_DSPR2) Use MIPS-DSP REV 2 instructions. +mdspr3 +Target Var(TARGET_DSPR3) +Use MIPS-DSP Rev 3 instructions. + mdebug Target Var(TARGET_DEBUG_MODE) Undocumented @@ -529,3 +533,6 @@ Enum(mips_lib_setting) String(small) Value(MIPS_LIB_SMALL) EnumValue Enum(mips_lib_setting) String(tiny) Value(MIPS_LIB_TINY) + +mforbidden-slots +Target Undocumented Var(TARGET_FORBIDDEN_SLOTS) Init(1) diff --git a/gcc/config/mips/ml-img-elf b/gcc/config/mips/ml-img-elf index 91204f825ed..744d2194c7b 100644 --- a/gcc/config/mips/ml-img-elf +++ b/gcc/config/mips/ml-img-elf @@ -10,3 +10,7 @@ mipsel-r6-hard-newlib/lib64 mipsel-r6-soft-newlib/lib mipsel-r6-soft-newlib/lib32 mipsel-r6-soft-newlib/lib64 +micromips-r6-hard-newlib/lib +micromipsel-r6-hard-newlib/lib +micromips-r6-soft-newlib/lib +micromipsel-r6-soft-newlib/lib diff --git a/gcc/config/mips/ml-img-linux b/gcc/config/mips/ml-img-linux index c9a58272f55..ca60d1817e6 100644 --- a/gcc/config/mips/ml-img-linux +++ b/gcc/config/mips/ml-img-linux @@ -8,3 +8,7 @@ mipsel-r6-hard/lib mipsel-r6-soft/lib mipsel-r6-hard/lib32 mipsel-r6-hard/lib64 +micromips-r6-hard/lib +micromips-r6-soft/lib +micromipsel-r6-hard/lib +micromipsel-r6-soft/lib diff --git a/gcc/config/mips/t-mips-multi b/gcc/config/mips/t-mips-multi index b6797a98811..633b64b42b5 100644 --- a/gcc/config/mips/t-mips-multi +++ b/gcc/config/mips/t-mips-multi @@ -107,6 +107,23 @@ MULTILIB_REQUIRED += mips64r6/mabi=64/EL/msoft-float/mnan=2008 MULTILIB_OSDIRNAMES += mips64r6/mabi.64/EL/msoft-float/mnan.2008= MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!mipsel-r6-soft$(is_newlib)/lib64 +# microMIPS32R6 - We will not include any 64 bit microMIPS combinations +MULTILIB_REQUIRED += mips32r6/mmicromips/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r6/mmicromips/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r6-hard$(is_newlib)/lib +MULTILIB_REQUIRED += mips32r6/mmicromips/mabi=32/EB/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r6/mmicromips/mabi.32/EB/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r6-soft$(is_newlib)/lib + +MULTILIB_REQUIRED += mips32r6/mmicromips/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r6/mmicromips/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r6-hard$(is_newlib) +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)/lib +MULTILIB_REQUIRED += mips32r6/mmicromips/mabi=32/EL/msoft-float/mnan=2008 +MULTILIB_OSDIRNAMES += mips32r6/mmicromips/mabi.32/EL/msoft-float/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r6-soft$(is_newlib) +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)/lib + # MIPS32R2/MIPS64R2 MULTILIB_REQUIRED += mips32r2/mabi=32/EB MULTILIB_OSDIRNAMES += mips32r2/mabi.32/EB=!mips-r2-hard$(is_newlib)/lib @@ -379,6 +396,19 @@ MULTILIB_REUSE += mclib.tiny/mips32r2/mabi.32/EL/msoft-float=mclib.tiny/ MULTILIB_REUSE := $(MULTILIB_REUSE)mips64r2/mabi.32/EL/msoft-float # microMIPS Small/Tiny C library variants +MULTILIB_REQUIRED += mclib=small/mips32r6/mmicromips/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mmicromips/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r6-hard-small/lib +MULTILIB_REQUIRED += mclib=small/mips32r6/mmicromips/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mmicromips/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r6-hard-small/lib +MULTILIB_REQUIRED += mclib=small/mips32r6/mmicromips/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mmicromips/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r6-soft-small/lib +MULTILIB_REQUIRED += mclib=small/mips32r6/mmicromips/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.small/mips32r6/mmicromips/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r6-soft-small/lib + MULTILIB_REQUIRED += mclib=small/mips32r2/mmicromips/mabi=32/EB/mnan=2008 MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mmicromips/mabi.32/EB/mnan.2008= MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-hard-nan2008-small @@ -394,6 +424,19 @@ MULTILIB_REQUIRED += mclib=small/mips32r2/mmicromips/mabi=32/EL/msoft-float MULTILIB_OSDIRNAMES += mclib.small/mips32r2/mmicromips/mabi.32/EL/msoft-float= MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r2-soft-small/lib +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mmicromips/mabi=32/EB/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mmicromips/mabi.32/EB/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r6-hard-tiny/lib +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mmicromips/mabi=32/EL/mnan=2008 +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mmicromips/mabi.32/EL/mnan.2008= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r6-hard-tiny/lib +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mmicromips/mabi=32/EB/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mmicromips/mabi.32/EB/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r6-soft-tiny/lib +MULTILIB_REQUIRED += mclib=tiny/mips32r6/mmicromips/mabi=32/EL/msoft-float +MULTILIB_OSDIRNAMES += mclib.tiny/mips32r6/mmicromips/mabi.32/EL/msoft-float= +MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromipsel-r6-soft-tiny/lib + MULTILIB_REQUIRED += mclib=tiny/mips32r2/mmicromips/mabi=32/EB/mnan=2008 MULTILIB_OSDIRNAMES += mclib.tiny/mips32r2/mmicromips/mabi.32/EB/mnan.2008= MULTILIB_OSDIRNAMES := $(MULTILIB_OSDIRNAMES)!micromips-r2-hard-nan2008-tiny/lib diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index aa979c3c2fd..aac7a0b75cd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -28195,7 +28195,7 @@ The processor names are: @samp{gs464e}, @samp{gs264e}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, -@samp{m5100}, @samp{m5101}, +@samp{m5100}, @samp{m5101}, @samp{m6201}, @samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3}, @samp{orion}, @samp{p5600}, @samp{p6600}, diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 25ded86f0d1..0b2bb72ea32 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2992,9 +2992,14 @@ Floating-point zero. An address that can be used in a non-macro load or store. @item ZC -A memory operand whose address is formed by a base register and offset -that is suitable for use in instructions with the same addressing mode -as @code{ll} and @code{sc}. +When compiling R6 code, this constraint matches a memory operand whose +address is formed from a base register and a 9-bit offset. +When compiling microMIPS code, this constraint matches a memory operand +whose address is formed from a base register and a 12-bit offset. +When not compiling for microMIPS nor R6, @code{ZC} is equivalent to +@code{R}. +These operands can be used for instructions such as @code{ll} and +@code{sc}. @item ZD An address suitable for a @code{prefetch} instruction, or for any other diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index e028bc93b40..bce662842f2 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -1437,7 +1437,6 @@ proc mips-dg-options { args } { } } if { $isa_rev > 5 } { - mips_make_test_option options "-mno-dsp" mips_make_test_option options "-mno-mips16" if { [mips_have_test_option_p options "-mdsp"] } { mips_make_test_option options "-mfp64" From patchwork Fri Jan 31 17:13:25 2025 Content-Type: text/plain; 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Cherry-picked adb95984114b7636ee15f2ba79f94b028c8b35b2 from https://github.com/MIPS/gcc Signed-off-by: Andrew Bennett Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.md | 1 + gcc/config/mips/mips.opt | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index f67fa2e66be..bf8a1217ee9 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5871,6 +5871,7 @@ be careful not to allocate a new register if we've reached the reload pass. */ if (TARGET_MIPS16 + && !TARGET_DEBUG_D_MODE && optimize && CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 8 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 201a9650915..64c3dca4cc2 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -131,7 +131,7 @@ mdebug Target Var(TARGET_DEBUG_MODE) Undocumented mdebugd -Target Var(TARGET_DEBUG_D_MODE) Undocumented +Target Var(TARGET_DEBUG_D_MODE) Undocumented Init(1) meb Target RejectNegative Mask(BIG_ENDIAN) From patchwork Fri Jan 31 17:13:26 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:13:26 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 14/61] MIPS: Add support for -mdead-loads Thread-Topic: [PATCH 14/61] MIPS: Add support for -mdead-loads Thread-Index: AQHbdANw9K1jq0Py6UWnq7+B/HoCCg== Date: Fri, 31 Jan 2025 17:13:26 +0000 Message-ID: <20250131171232.1018281-16-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|PR3PR09MB5379:EE_ x-ms-office365-filtering-correlation-id: e0e3262e-1f53-47d6-b954-08dd421a9340 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Cherry-picked a9a9df621143d9cac0e898f2a0bedd98b4db8ae4 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/loongson-mmi.md | 2 +- gcc/config/mips/mips-msa.md | 2 +- gcc/config/mips/mips-protos.h | 2 +- gcc/config/mips/mips.cc | 33 ++++++++++++++------ gcc/config/mips/mips.md | 54 ++++++++++++++++----------------- gcc/config/mips/mips.opt | 4 +++ gcc/doc/invoke.texi | 13 ++++++++ 7 files changed, 71 insertions(+), 39 deletions(-) diff --git a/gcc/config/mips/loongson-mmi.md b/gcc/config/mips/loongson-mmi.md index 4d958730139..39682eeaeb6 100644 --- a/gcc/config/mips/loongson-mmi.md +++ b/gcc/config/mips/loongson-mmi.md @@ -112,7 +112,7 @@ [(set (match_operand:VWHB 0 "nonimmediate_operand" "=m,f,d,f, d, m, d") (match_operand:VWHB 1 "move_operand" "f,m,f,dYG,dYG,dYG,m"))] "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "fpstore,fpload,mfc,mtc,move,store,load") (set_attr "mode" "DI")]) diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 976f296402e..f6edd5897a4 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -680,7 +680,7 @@ [(set (match_operand:MSA 0 "nonimmediate_operand" "=f,f,R,*d,*f") (match_operand:MSA 1 "move_operand" "fYGYI,R,f,*f,*d"))] "ISA_HAS_MSA" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert") (set_attr "mode" "")]) diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 96e084e6e64..c514c0711de 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -222,7 +222,7 @@ extern bool mips_split_128bit_move_p (rtx, rtx); extern void mips_split_msa_copy_d (rtx, rtx, rtx, rtx (*)(rtx, rtx, rtx)); extern void mips_split_msa_insert_d (rtx, rtx, rtx, rtx); extern void mips_split_msa_fill_d (rtx, rtx); -extern const char *mips_output_move (rtx, rtx); +extern const char *mips_output_move (rtx, rtx, rtx); extern bool mips_cfun_has_cprestore_slot_p (void); extern bool mips_cprestore_address_p (rtx, bool); extern void mips_save_gp_to_cprestore_slot (rtx, rtx, rtx, rtx); diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 069c7ef6a42..4c719fbaed5 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -5374,7 +5374,7 @@ mips_split_move_insn (rtx dest, rtx src, rtx insn) that SRC is operand 1 and DEST is operand 0. */ const char * -mips_output_move (rtx dest, rtx src) +mips_output_move (rtx insn, rtx dest, rtx src) { enum rtx_code dest_code = GET_CODE (dest); enum rtx_code src_code = GET_CODE (src); @@ -5502,14 +5502,29 @@ mips_output_move (rtx dest, rtx src) } if (src_code == MEM) - switch (GET_MODE_SIZE (mode)) - { - case 1: return "lbu\t%0,%1"; - case 2: return "lhu\t%0,%1"; - case 4: return "lw\t%0,%1"; - case 8: return "ld\t%0,%1"; - default: gcc_unreachable (); - } + { + if (TARGET_DEAD_LOADS + && MEM_VOLATILE_P (src) + && find_regno_note (insn, REG_UNUSED, REGNO (dest)) + && !TARGET_MIPS16) + switch (GET_MODE_SIZE (mode)) + { + case 1: return "lbu\t$0,%1"; + case 2: return "lhu\t$0,%1"; + case 4: return "lw\t$0,%1"; + case 8: return "ld\t$0,%1"; + default: gcc_unreachable (); + } + else + switch (GET_MODE_SIZE (mode)) + { + case 1: return "lbu\t%0,%1"; + case 2: return "lhu\t%0,%1"; + case 4: return "lw\t%0,%1"; + case 8: return "ld\t%0,%1"; + default: gcc_unreachable (); + } + } if (src_code == CONST_INT) { diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index bf8a1217ee9..b1e55428682 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4882,7 +4882,7 @@ "!TARGET_64BIT && !TARGET_MIPS16 && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore") (set (attr "mode") (if_then_else (eq_attr "move_type" "imul") @@ -4895,7 +4895,7 @@ "!TARGET_64BIT && TARGET_MIPS16 && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") (set_attr "mode" "DI")]) @@ -4905,7 +4905,7 @@ "TARGET_64BIT && !TARGET_MIPS16 && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore") (set_attr "mode" "DI")]) @@ -4915,7 +4915,7 @@ "TARGET_64BIT && TARGET_MIPS16 && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") (set_attr "mode" "DI")]) @@ -4983,7 +4983,7 @@ "!TARGET_MIPS16 && (register_operand (operands[0], mode) || reg_or_0_operand (operands[1], mode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore") (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*") (set_attr "mode" "SI")]) @@ -4994,7 +4994,7 @@ "TARGET_MIPS16 && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") (set_attr "mode" "SI")]) @@ -5124,7 +5124,7 @@ "!TARGET_MIPS16 && (register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") (set_attr "mode" "HI")]) @@ -5135,7 +5135,7 @@ "TARGET_MIPS16 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") (set_attr "mode" "HI")]) @@ -5200,7 +5200,7 @@ "!TARGET_MIPS16 && (register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") (set_attr "mode" "QI")]) @@ -5211,7 +5211,7 @@ "TARGET_MIPS16 && (register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") (set_attr "mode" "QI")]) @@ -5257,7 +5257,7 @@ [(set (match_operand:CCF 0 "nonimmediate_operand" "=f,f,m") (match_operand:CCF 1 "nonimmediate_operand" "f,m,f"))] "ISA_HAS_CCF" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "fmove,fpload,fpstore")]) (define_insn "*movsf_hardfloat" @@ -5266,7 +5266,7 @@ "TARGET_HARD_FLOAT && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "SF")]) @@ -5276,7 +5276,7 @@ "TARGET_SOFT_FLOAT && !TARGET_MIPS16 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") (set_attr "mode" "SF")]) @@ -5286,7 +5286,7 @@ "TARGET_MIPS16 && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,load,store") (set_attr "mode" "SF")]) @@ -5307,7 +5307,7 @@ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && (register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "DF")]) @@ -5317,7 +5317,7 @@ "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16 && (register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") (set_attr "mode" "DF")]) @@ -5327,7 +5327,7 @@ "TARGET_MIPS16 && (register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,load,store") (set_attr "mode" "DF")]) @@ -5349,7 +5349,7 @@ && !TARGET_MIPS16 && (register_operand (operands[0], TImode) || reg_or_0_operand (operands[1], TImode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo") (set (attr "mode") (if_then_else (eq_attr "move_type" "imul") @@ -5454,7 +5454,7 @@ && TARGET_PAIRED_SINGLE_FLOAT && (register_operand (operands[0], V2SFmode) || reg_or_0_operand (operands[1], V2SFmode))" - { return mips_output_move (operands[0], operands[1]); } + { return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "DF")]) @@ -5535,7 +5535,7 @@ "TARGET_HARD_FLOAT" { operands[0] = mips_subword (operands[0], 0); - return mips_output_move (operands[0], operands[1]); + return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "mtc,fpload") (set_attr "mode" "")]) @@ -5550,7 +5550,7 @@ "TARGET_HARD_FLOAT" { operands[0] = mips_subword (operands[0], 1); - return mips_output_move (operands[0], operands[1]); + return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "mtc,fpload") (set_attr "mode" "")]) @@ -5565,7 +5565,7 @@ "TARGET_HARD_FLOAT" { operands[1] = mips_subword (operands[1], INTVAL (operands[2])); - return mips_output_move (operands[0], operands[1]); + return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "move_type" "mfc,fpstore") (set_attr "mode" "")]) @@ -6947,7 +6947,7 @@ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")] UNSPEC_COP0))] "" -{ return mips_output_move (operands[0], operands[1]); } +{ return mips_output_move (insn, operands[0], operands[1]); } [(set_attr "type" "mtc,mfc") (set_attr "mode" "SI")]) @@ -7954,16 +7954,16 @@ However, order of the loads need to be checked for correctness. */ if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1])) { - output_asm_insn (mips_output_move (operands[0], operands[1]), + output_asm_insn (mips_output_move (insn, operands[0], operands[1]), operands); - output_asm_insn (mips_output_move (operands[2], operands[3]), + output_asm_insn (mips_output_move (insn, operands[2], operands[3]), &operands[2]); } else { - output_asm_insn (mips_output_move (operands[2], operands[3]), + output_asm_insn (mips_output_move (insn, operands[2], operands[3]), &operands[2]); - output_asm_insn (mips_output_move (operands[0], operands[1]), + output_asm_insn (mips_output_move (insn, operands[0], operands[1]), operands); } return ""; diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 64c3dca4cc2..28b8de216fe 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -536,3 +536,7 @@ Enum(mips_lib_setting) String(tiny) Value(MIPS_LIB_TINY) mforbidden-slots Target Undocumented Var(TARGET_FORBIDDEN_SLOTS) Init(1) + +mdead-loads +Target Var(TARGET_DEAD_LOADS) Init(0) +Redirect dead loads to $0 to avoid spurious output dependencies. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index aac7a0b75cd..636aea39e53 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1153,6 +1153,7 @@ Objective-C and Objective-C++ Dialects}. -membedded-data -mno-embedded-data -muninit-const-in-rodata -mno-uninit-const-in-rodata -mcode-readable=@var{setting} +-mdead-loads -mno-dead-loads -msplit-addresses -mno-split-addresses -mexplicit-relocs -mno-explicit-relocs -mexplicit-relocs=@var{release} @@ -28837,6 +28838,18 @@ SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM. @end table +@opindex mdead-loads +@opindex mno-dead-loads +@item -mdead-loads +@itemx -mno-dead-loads +Apply (do not apply) special handling to avoid output dependency stalls +for volatile loads where the result is unused. Volatile loads tend +to be high latency as they represent access to special data or hardware. +When the result of such a load is unused then there may be an output +dependency stall if the result register is reused soon after the load. +For MIPS32 a dead load will be redirected to @code{$0} to avoid the output +dependency. + @opindex msplit-addresses @opindex mno-split-addresses @item -msplit-addresses From patchwork Fri Jan 31 17:13:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105754 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BB0ED3858401 for ; Fri, 31 Jan 2025 17:29:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on20705.outbound.protection.outlook.com [IPv6:2a01:111:f403:2614::705]) by sourceware.org (Postfix) with ESMTPS id D75463858C56 for ; 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The new parameters (defaulted to 0) mean to disable these limitations with -Os. NUMBER could be set to something like 4-32 to see the impact. The main reason that smaller functions are treated as cold or unlikely is the function cgraph_maybe_hot_edge_p () always returning FALSE for -Os. Cherry-picked c38d7e548cbb3defb141efb528cb356333e8eb7a from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/ipa-inline.cc | 4 +++- gcc/params.opt | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/gcc/ipa-inline.cc b/gcc/ipa-inline.cc index fe8efa9a157..1a2a62b73cd 100644 --- a/gcc/ipa-inline.cc +++ b/gcc/ipa-inline.cc @@ -820,7 +820,8 @@ want_early_inline_function_p (struct cgraph_edge *e) if (!want_inline || growth <= param_max_inline_insns_size) ; - else if (!e->maybe_hot_p ()) + else if (!e->maybe_hot_p () + && growth > param_early_inlining_insns_cold) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, e->call_stmt, @@ -1060,6 +1061,7 @@ want_inline_small_function_p (struct cgraph_edge *e, bool report) } /* If call is cold, do not inline when function body would grow. */ else if (!e->maybe_hot_p () + && growth > param_max_inline_insns_small_and_cold && (growth >= inline_insns_single (e->caller, false, false) || growth_positive_p (callee, e, growth))) { diff --git a/gcc/params.opt b/gcc/params.opt index 7c572774df2..edb62a221fb 100644 --- a/gcc/params.opt +++ b/gcc/params.opt @@ -130,6 +130,10 @@ Maximum size (in bytes) of objects tracked bytewise by dead store elimination. Common Joined UInteger Var(param_early_inlining_insns) Init(6) Optimization Param Maximal estimated growth of function body caused by early inlining of single call. +-param=early-inlining-insns-cold= +Common Joined UInteger Var(param_early_inlining_insns_cold) Init(0) Optimization Param +Maximal estimated growth of function body caused by early inlining of cold call. + -param=fsm-scale-path-stmts= Common Joined UInteger Var(param_fsm_scale_path_stmts) Init(2) IntegerRange(1, 10) Param Optimization Scale factor to apply to the number of statements in a threading path crossing a loop backedge when comparing to max-jump-thread-duplication-stmts. @@ -573,6 +577,10 @@ The maximum number of instructions when inlining for size. Common Joined UInteger Var(param_max_inline_insns_small) Optimization Param The maximum number of instructions when automatically inlining small functions. +-param=max-inline-insns-small-and-cold= +Common Joined UInteger Var(param_max_inline_insns_small_and_cold) Optimization Init(0) Param +The maximum number of instructions in a small and cold function eligible for inlining. + -param=max-inline-recursive-depth= Common Joined UInteger Var(param_max_inline_recursive_depth) Optimization Init(8) Param The maximum depth of recursive inlining for inline functions. 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+struct mips_sdata_entry +{ + char *var; + struct mips_sdata_entry *next; +}; + +static struct mips_sdata_entry *mips_sdata_opt_list; + +static struct mips_sdata_entry * +mips_read_list (const char * filename) +{ + FILE *fd; + char line[256]; + struct mips_sdata_entry *current = NULL; + struct mips_sdata_entry *head = NULL; + + if (filename == NULL) + return NULL; + fd = fopen (filename, "r"); + if (fd == NULL) + { + error ("Bad filename for -msdata-opt-list: %s\n", filename); + return NULL; + } + + while (fgets (line, sizeof (line), fd)) + { + struct mips_sdata_entry *entry; + entry = (struct mips_sdata_entry *)xmalloc ( + sizeof (struct mips_sdata_entry)); + entry->var = xstrdup (line); + if (entry->var[strlen (entry->var)-1] == '\n') + entry->var[strlen (entry->var)-1] = '\0'; + entry->next = NULL; + if (head == NULL) + current = head = entry; + else + current = current->next = entry; + } + fclose (fd); + return head; +} + +static bool +mips_find_list (const char *var, struct mips_sdata_entry *list) +{ + while (list != NULL) + { + if (strcmp (list->var, var) == 0) + return true; + list = list->next; + } + + return false; +} + /* A table describing all the processors GCC knows about; see mips-cpus.def for details. */ static const struct mips_cpu_info mips_cpu_info_table[] = { @@ -1533,6 +1589,30 @@ mips_insert_attributes (tree decl, tree *attributes) if (compression_flags) error ("%qs attribute only applies to functions", mips_get_compress_on_name (nocompression_flags)); + + if (TREE_CODE (decl) == VAR_DECL + && is_global_var (decl) + && DECL_NAME (decl) + && mips_find_list (IDENTIFIER_POINTER (DECL_NAME (decl)), + mips_sdata_opt_list)) + { + tree attr_args; + if (mips_sdata_section_num > -1) + { + char sec_name[13]; + sprintf (sec_name, ".sdata_%d", mips_sdata_section_num); + attr_args = build_tree_list (NULL_TREE, + build_string (strlen (sec_name), + sec_name)); + } + else + attr_args = build_tree_list (NULL_TREE, + build_string (6, ".sdata")); + + *attributes = tree_cons (get_identifier ("section"), + attr_args, + *attributes); + } } else { @@ -9804,6 +9884,70 @@ mips_encode_section_info (tree decl, rtx rtl, int first) } } +/* Implement TARGET_ASM_UNIQUE_SECTION. */ + +void +mips_asm_unique_section (tree decl, int reloc) +{ + default_unique_section (decl, reloc); + + const char *name = DECL_SECTION_NAME (decl); + + if (mips_sdata_section_num > -1 + && (strncmp (".sdata", name, 6) == 0 + || strncmp (".sbss", name, 5) == 0)) + { + char *sec_name = (char*) alloca (strlen (name) + 5); + if (strncmp (".sdata", name, 6) == 0) + sprintf (sec_name, ".sdata_%d%s", mips_sdata_section_num, name + 6); + else + sprintf (sec_name, ".sbss_%d%s", mips_sdata_section_num, name + 5); + + set_decl_section_name (decl, sec_name); + } +} + +/* Implement TARGET_ASM_SELECT_SECTION. */ + +static section * +mips_asm_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align) +{ + char * sec_name; + section *s; + + s = default_elf_select_section (exp, reloc, align); + + if (mips_sdata_section_num > -1 + && (s->named.common.flags & SECTION_NAMED) + && (strncmp (".sdata", s->named.name, 6) == 0 + || strncmp (".sbss", s->named.name, 5) == 0)) + { + sec_name = (char*) alloca (strlen (s->named.name) + 5); + if (strncmp (".sdata", s->named.name, 6) == 0) + sprintf (sec_name, ".sdata_%d%s", mips_sdata_section_num, + s->named.name + 6); + else + sprintf (sec_name, ".sbss_%d%s", mips_sdata_section_num, + s->named.name + 5); + s = get_section (sec_name, s->named.common.flags, exp); + } + return s; +} + +/* Implement TARGET_SECTION_TYPE_FLAGS. */ + +unsigned int +mips_section_type_flags (tree decl, const char *name, int reloc) +{ + unsigned int flags = default_section_type_flags (decl, name, reloc); + + if (mips_sdata_section_num > -1 + && strncmp (name, ".sbss_", 6) == 0) + flags |= SECTION_BSS; + + return flags; +} + /* Implement TARGET_SELECT_RTX_SECTION. */ static section * @@ -9839,7 +9983,9 @@ mips_in_small_data_p (const_tree decl) /* Reject anything that isn't in a known small-data section. */ name = DECL_SECTION_NAME (decl); - if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0) + if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0 + && strncmp (name, ".sdata_", 7) != 0 + && strncmp (name, ".sbss_", 6) != 0) return false; /* If a symbol is defined externally, the assembler will use the @@ -20518,6 +20664,8 @@ mips_option_override (void) if (TARGET_FLIP_MIPS16) TARGET_INTERLINK_COMPRESSED = 1; + mips_sdata_opt_list = mips_read_list (mips_sdata_opt_list_file); + /* Set the small data limit. */ mips_small_data_threshold = (OPTION_SET_P (g_switch_value) ? g_switch_value @@ -21067,6 +21215,9 @@ mips_option_override (void) if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900) REAL_MODE_FORMAT (SFmode) = &spu_single_format; + if (mips_sdata_section_num >= 1000) + error ("Number for -msdata-num must be between 0 and 999"); + mips_register_frame_header_opt (); } @@ -23721,6 +23872,14 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) #undef TARGET_C_MODE_FOR_FLOATING_TYPE #define TARGET_C_MODE_FOR_FLOATING_TYPE mips_c_mode_for_floating_type +#undef TARGET_ASM_SELECT_SECTION +#define TARGET_ASM_SELECT_SECTION mips_asm_select_section + +#undef TARGET_ASM_UNIQUE_SECTION +#define TARGET_ASM_UNIQUE_SECTION mips_asm_unique_section + +#undef TARGET_SECTION_TYPE_FLAGS +#define TARGET_SECTION_TYPE_FLAGS mips_section_type_flags struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 28b8de216fe..ca7d064dd6e 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -540,3 +540,11 @@ Target Undocumented Var(TARGET_FORBIDDEN_SLOTS) Init(1) mdead-loads Target Var(TARGET_DEAD_LOADS) Init(0) Redirect dead loads to $0 to avoid spurious output dependencies. + +msdata-num= +Target RejectNegative Joined UInteger Var(mips_sdata_section_num) Init(-1) +Place all gp relative data in sdata section number NUM. + +msdata-opt-list= +Target RejectNegative Joined Var(mips_sdata_opt_list_file) +msdata-opt-list=FILE Use to specify variables to go in the .sdata section. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 636aea39e53..d3b0187daff 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1151,6 +1151,8 @@ Objective-C and Objective-C++ Dialects}. -G@var{num} -mlocal-sdata -mno-local-sdata -mextern-sdata -mno-extern-sdata -mgpopt -mno-gopt -membedded-data -mno-embedded-data +-msdata-num=@var{num} +-msdata-opt-list=@var{file} -muninit-const-in-rodata -mno-uninit-const-in-rodata -mcode-readable=@var{setting} -mdead-loads -mno-dead-loads @@ -28806,6 +28808,40 @@ next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems. +@opindex msdata-num +@item -msdata-num=@var{num} +Use a numbered small data section instead of the default to enable multiple +small data areas within one executable. This feature is for advanced users +only and requires very careful management of where data is accessed. The +aim is to allow code which executes solely within one software context to +use a unique small data area. + +Compilation units should be grouped such that all units within a group can +share a small data section. The @code{num} value should be set to the same +number for all related modules. Any data that is shared between contexts +will need to be explicitly placed in a named section using +@code{__attribute__((section (".my_shared_data")))}. Alternatively use the +@option{-mno-extern-sdata} option to ensure that the compiler does not +automatically place global data in the small data section and instead +use the @option{-msdata-opt-list} option to explicitly place some global +data in the small data section where it is only used by one context. + +It is the user's responsibility to ensure that the global pointer for any +given software context is set to point at the appropriate small data area. +It is also the user's responsibility to ensure that data placed in one +software context's small data area is not accessed using the small data +model from a different software context as the application may not link. +Linker support for this feature is also required and should be enabled +using @option{-Wl,--user-defined-sdata-sections}. + +@opindex msdata-opt-list +@item -msdata-opt-list +Read a list of data variables from a file that must be accessed using the +small data model. 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Fri, 31 Jan 2025 17:13:27 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 17/61] Add -munique-sections feature Thread-Topic: [PATCH 17/61] Add -munique-sections feature Thread-Index: AQHbdANxxX6D6JVo0UOkZI0ZnGzRZg== Date: Fri, 31 Jan 2025 17:13:27 +0000 Message-ID: <20250131171232.1018281-19-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|PR3PR09MB5379:EE_ x-ms-office365-filtering-correlation-id: 352a061f-981f-40a0-84ac-08dd421a941e x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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(mips_read_list): Update prototype and error message. (ultimate_transparent_alias_target): New function. Copied from varasm.c. (mips_asm_unique_section): Update to rename unique sections. (mips_option_override): Read the unique_sections file. * config/mips/mips.opt: Add -munique-sections option. * doc/invoke.texi: Document -munique-sections * varasm.cc (resolve_unique_section): Try to create a unique section even for explicitly provided section names. (default_unique_section): Do nothing if a section is already set. gcc/testsuite/ * gcc.target/mips/mips.exp: Support -munique-sections. (mips-dg-options): Translate filename argument to -munique-sections. * gcc.target/mips/unique-sections-bad.c: New file. * gcc.target/mips/unique-sections.c: Likewise. * gcc.target/mips/unique-sections.txt: Likewise. Cherry-picked 9cd38c0b698287caff43d0aac3c963bb425391d8 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 54 +++++++++++++++++-- gcc/config/mips/mips.opt | 4 ++ gcc/doc/invoke.texi | 10 ++++ gcc/testsuite/gcc.target/mips/mips.exp | 18 +++++++ .../gcc.target/mips/unique-sections-bad.c | 3 ++ .../gcc.target/mips/unique-sections.c | 15 ++++++ .../gcc.target/mips/unique-sections.txt | 3 ++ gcc/varasm.cc | 11 ++++ 8 files changed, 114 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/unique-sections-bad.c create mode 100644 gcc/testsuite/gcc.target/mips/unique-sections.c create mode 100644 gcc/testsuite/gcc.target/mips/unique-sections.txt diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 6e48feeb560..55d06b87c0d 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -647,9 +647,10 @@ struct mips_sdata_entry }; static struct mips_sdata_entry *mips_sdata_opt_list; +static struct mips_sdata_entry *mips_unique_sections_list; static struct mips_sdata_entry * -mips_read_list (const char * filename) +mips_read_list (const char * filename, const char *opt_name) { FILE *fd; char line[256]; @@ -661,7 +662,7 @@ mips_read_list (const char * filename) fd = fopen (filename, "r"); if (fd == NULL) { - error ("Bad filename for -msdata-opt-list: %s\n", filename); + error ("Bad filename for %s: %s\n", opt_name, filename); return NULL; } @@ -9884,16 +9885,57 @@ mips_encode_section_info (tree decl, rtx rtl, int first) } } +/* This should be the same as ultimate_transparent_alias_target from + gcc/varasm.c. */ + +static inline tree +ultimate_transparent_alias_target (tree *alias) +{ + tree target = *alias; + + if (IDENTIFIER_TRANSPARENT_ALIAS (target)) + { + gcc_assert (TREE_CHAIN (target)); + target = ultimate_transparent_alias_target (&TREE_CHAIN (target)); + gcc_assert (! IDENTIFIER_TRANSPARENT_ALIAS (target) + && ! TREE_CHAIN (target)); + *alias = target; + } + + return target; +} + /* Implement TARGET_ASM_UNIQUE_SECTION. */ void mips_asm_unique_section (tree decl, int reloc) { + const char *old_secname = DECL_SECTION_NAME (decl); + + if (old_secname != NULL + && mips_find_list (old_secname, mips_unique_sections_list)) + { + tree id = DECL_ASSEMBLER_NAME (decl); + ultimate_transparent_alias_target (&id); + const char *name = IDENTIFIER_POINTER (id); + name = targetm.strip_name_encoding (name); + + /* We may end up here twice for data symbols, + so we need to prevent renaming sections twice. */ + char *suffix = ACONCAT ((".", name, NULL)); + if (strstr (old_secname, suffix) == NULL) + { + char *new_secname = ACONCAT ((old_secname, suffix, NULL)); + set_decl_section_name (decl, new_secname); + } + } + default_unique_section (decl, reloc); const char *name = DECL_SECTION_NAME (decl); - if (mips_sdata_section_num > -1 + if (old_secname == NULL + && mips_sdata_section_num > -1 && (strncmp (".sdata", name, 6) == 0 || strncmp (".sbss", name, 5) == 0)) { @@ -20664,7 +20706,11 @@ mips_option_override (void) if (TARGET_FLIP_MIPS16) TARGET_INTERLINK_COMPRESSED = 1; - mips_sdata_opt_list = mips_read_list (mips_sdata_opt_list_file); + mips_sdata_opt_list = mips_read_list (mips_sdata_opt_list_file, + "-msdata-opt-list"); + + mips_unique_sections_list = mips_read_list (mips_unique_sections_file, + "-munique-sections"); /* Set the small data limit. */ mips_small_data_threshold = (OPTION_SET_P (g_switch_value) diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index ca7d064dd6e..e0a305aec22 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -548,3 +548,7 @@ Place all gp relative data in sdata section number NUM. msdata-opt-list= Target RejectNegative Joined Var(mips_sdata_opt_list_file) msdata-opt-list=FILE Use to specify variables to go in the .sdata section. + +munique-sections= +Target RejectNegative Joined Var(mips_unique_sections_file) +munique-sections=FILE Use to specify sections that should be made unique. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d3b0187daff..952baf872ec 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1153,6 +1153,7 @@ Objective-C and Objective-C++ Dialects}. -membedded-data -mno-embedded-data -msdata-num=@var{num} -msdata-opt-list=@var{file} +-munique-sections=@var{file} -muninit-const-in-rodata -mno-uninit-const-in-rodata -mcode-readable=@var{setting} -mdead-loads -mno-dead-loads @@ -28842,6 +28843,15 @@ small data model. This is equivalent to adding For this option to take effect on uninitialised globals then @option{-fno-common} must also be used. +@opindex -munique-sections +@item -munique-sections +Read a list of section names from a file that specify which of the explicitly +named sections should have unique names. This is the equivalent of adding +@code{__attribute__((section ("section_name.symbol_name")))} to the source code +declaration. +Having a data symbol which is matched by both @option{-msdata-opt-list} and +@option{-munique-sections} will cause a compilation error. + @opindex muninit-const-in-rodata @opindex mno-uninit-const-in-rodata @item -muninit-const-in-rodata diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index bce662842f2..b0825ca4339 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -315,6 +315,7 @@ foreach option { nan r10k-cache-barrier tune + unique-sections } { lappend mips_option_groups $option "-m$option=.*" } @@ -1038,6 +1039,23 @@ proc mips-dg-options { args } { } } + # Pass an absolute file path to -munique-sections=. + set unq_sec_test_option_p [mips_test_option_p options unique-sections] + + if { $unq_sec_test_option_p } { + set unq_sec [mips_option options unique-sections] + if { ![regexp {=.*$} $unq_sec filename] } { + error "Unrecognized specification: $unq_sec" + } + set filename [string trimleft $filename "="] + + global srcdir + global subdir + set new_unq_sec "-munique-sections=$srcdir/$subdir/$filename" + + set options(option,[mips_option_group $new_unq_sec]) $new_unq_sec + } + # Handle dependencies between the test options and the optimization ones. mips_option_dependency options "-fno-unroll-loops" "-fno-unroll-all-loops" mips_option_dependency options "-pg" "-fno-omit-frame-pointer" diff --git a/gcc/testsuite/gcc.target/mips/unique-sections-bad.c b/gcc/testsuite/gcc.target/mips/unique-sections-bad.c new file mode 100644 index 00000000000..be75ffd999b --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/unique-sections-bad.c @@ -0,0 +1,3 @@ +/* { dg-do compile } */ +/* { dg-options "-munique-sections=non-existent-file.txt" } */ +/* { dg-error "Bad filename for -munique-sections:" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/mips/unique-sections.c b/gcc/testsuite/gcc.target/mips/unique-sections.c new file mode 100644 index 00000000000..7f2ca62ec1a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/unique-sections.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-munique-sections=unique-sections.txt" } */ +/* { dg-final { scan-assembler "\t.section\tfoo.f" } } */ +/* { dg-final { scan-assembler "\t.section\tfoof" } } */ +/* { dg-final { scan-assembler "\t.section\tbar.h" } } */ +/* { dg-final { scan-assembler "\t.section\tbaz" } } */ +/* { dg-final { scan-assembler "\t.section\tbar.k" } } */ + +int __attribute__((section("foo"))) f (void) { return 0; } +int __attribute__((section("foof"))) g (void) { return 0; } +int __attribute__((section("bar"))) h (void) { return 0; } +int __attribute__((section("baz"))) i (void) { return 0; } +int j (void) { return 0; } +int __attribute__((section("bar"))) k; +int l; diff --git a/gcc/testsuite/gcc.target/mips/unique-sections.txt b/gcc/testsuite/gcc.target/mips/unique-sections.txt new file mode 100644 index 00000000000..b16db8d3be9 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/unique-sections.txt @@ -0,0 +1,3 @@ +foo +bar +none diff --git a/gcc/varasm.cc b/gcc/varasm.cc index 0712b486029..db603e44e55 100644 --- a/gcc/varasm.cc +++ b/gcc/varasm.cc @@ -491,6 +491,12 @@ resolve_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED, symtab_node::get (decl)->call_for_symbol_and_aliases (set_implicit_section, NULL, true); } + + /* Allow target specific handling of unique sections even if an explicit + section name is used. */ + else if (DECL_SECTION_NAME (decl) != NULL + && targetm_common.have_named_sections) + targetm.asm_out.unique_section (decl, reloc); } #ifdef BSS_SECTION_ASM_OP @@ -7353,6 +7359,11 @@ default_unique_section (tree decl, int reloc) char *string; tree id; + /* If the symbol has a section name assigned at this point, then it is the + name of a user-specified unique section and we should leave it alone. */ + if (DECL_SECTION_NAME (decl) != NULL) + return; + switch (categorize_decl_for_section (decl, reloc)) { case SECCAT_TEXT: From patchwork Fri Jan 31 17:13:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105758 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D5FC73857820 for ; Fri, 31 Jan 2025 17:33:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on20725.outbound.protection.outlook.com [IPv6:2a01:111:f403:2613::725]) by sourceware.org (Postfix) with ESMTPS id E82503858CDB for ; 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This option takes a file which has one function per line followed by a whitespace (space/tab) followed by one or more attributes. Supported attributes are O2, Os, code-read=pcrel, always_inline, noinline, mips16, nomips16, epi, longcall. Attributes are applied to functions that the compiler sees, so functions listed that the compiler doesn't see are ignored. Now understands the majority of function attributes. These are: O1, O2, O3, Os, mips16, nomips16, always_inline, noinline, unused, used, far, near, hot, cold, code_readable, alias, aligned, alloc_size, alloc_align, assume_aligned, artifical, constructor, const, deprecated, destructor, error, flatten, gnu_inline, interrupt, keep_interrupts_masked, long_call, leaf, noclone, noreturn, malloc, nonnull, nothrow, optimize, returns_nonnull, returns_twice, section, pure, use_debug_exception_return, use_shadow_register_set, visibility, warning, warn_unused_result, weak, weakref. Syntax of attributes that take arguments is like: alias ("O2") or nonnull (1,2) Attach unknown attributes anyway. Cherry-picked e2ff99868adedb1a563ee69b3076838dd7ae4450 from https://github.com/MIPS/gcc Signed-off-by: Simon Dardis Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 609 +++++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips.opt | 4 + gcc/doc/invoke.texi | 33 +++ 3 files changed, 646 insertions(+) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 55d06b87c0d..32fe62ce79b 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -697,6 +697,524 @@ mips_find_list (const char *var, struct mips_sdata_entry *list) return false; } +/* Argument type descriptor. */ + +enum mips_func_opt_list_arg_t +{ + FOL_ARG_NONE, + FOL_ARG_STRING, + FOL_ARG_SINGLE_NUM, + FOL_ARG_OPTIONAL_NUM_LIST, + FOL_ARG_NUM_ONE_OR_TWO, + FOL_ARG_OPTIONAL_STRING, + FOL_ARG_OPTIONAL_NUM, + FOL_ARG_UNKNOWN +}; + +/* Collisons for FUNC_OPT_LIST. Rather that just relying on the middle to + complain, check at parse time so we can produce accurate diagnositics. */ + +enum mips_fol_collides +{ + FOLC_O1, + FOLC_O2, + FOLC_O3, + FOLC_OS, + FOLC_MIPS16, + FOLC_NOMIPS16, + FOLC_ALWAYS_INLINE, + FOLC_NOINLINE, + FOLC_UNUSED, + FOLC_USED, + FOLC_FAR, + FOLC_NEAR, + FOLC_HOT, + FOLC_COLD, + FOLC_END +}; + +/* Part of FUNC_OPT_LIST. Use a tuple to record the name to be matched against + which GCC uses internally, an optional second string if the name is required + to be an argument of a different attribute and a bitmask describing which + other entries collide with this entry. */ + +struct attr_desc +{ + const char * optstring; + const char * maintype; + enum mips_func_opt_list_arg_t arg_type; + int collisions; +}; + +/* This table encodes the strings to match against for parsing func-opt-list, + an optional string which the first is argument of, e.g. optimize ("O2") + and the colliding attributes. */ + +static const struct attr_desc mips_func_opt_list_strings[] = { + {"O1", "optimize", FOL_ARG_NONE, + 1 << FOLC_O2 | 1 << FOLC_O3 | 1 << FOLC_OS }, + {"O2", "optimize", FOL_ARG_NONE, + 1 << FOLC_O1 | 1 << FOLC_O3 | 1 << FOLC_OS }, + {"O3", "optimize", FOL_ARG_NONE, + 1 << FOLC_O1 | 1 << FOLC_O2 | 1 << FOLC_OS }, + {"Os", "optimize", FOL_ARG_NONE, + 1 << FOLC_O1 | 1 << FOLC_O2 | 1 << FOLC_O3 }, + {"mips16", 0, FOL_ARG_NONE, 1 << FOLC_NOMIPS16 }, + {"nomips16", 0, FOL_ARG_NONE, 1 << FOLC_MIPS16 }, + {"always_inline", 0, FOL_ARG_NONE, 1 << FOLC_NOINLINE }, + {"noinline", 0, FOL_ARG_NONE, 1 << FOLC_ALWAYS_INLINE }, + {"unused", 0, FOL_ARG_NONE, 1 << FOLC_USED }, + {"used", 0, FOL_ARG_NONE, 1 << FOLC_UNUSED }, + {"far", 0, FOL_ARG_NONE, 1 << FOLC_NEAR }, + {"near", 0, FOL_ARG_NONE, 1 << FOLC_FAR }, + {"hot", 0, FOL_ARG_NONE, 1 << FOLC_COLD }, + {"cold", 0, FOL_ARG_NONE, 1 << FOLC_HOT }, + {"code_readable", 0, FOL_ARG_STRING, 0 }, + {"alias", 0, FOL_ARG_STRING, 0 }, + {"aligned", 0, FOL_ARG_SINGLE_NUM, 0}, + {"alloc_size", 0, FOL_ARG_NUM_ONE_OR_TWO, 0}, + {"alloc_align", 0, FOL_ARG_SINGLE_NUM, 0}, + {"assume_aligned", 0, FOL_ARG_NUM_ONE_OR_TWO, 0}, + {"artifical", 0, FOL_ARG_NONE, 0 }, + {"constructor", 0, FOL_ARG_OPTIONAL_NUM, 0}, + {"const", 0, FOL_ARG_NONE, 0 }, + {"deprecated", 0, FOL_ARG_OPTIONAL_STRING, 0}, + {"destructor", 0, FOL_ARG_OPTIONAL_NUM, 0}, + {"error", 0, FOL_ARG_OPTIONAL_STRING, 0}, + {"flatten", 0, FOL_ARG_NONE, 0 }, + {"gnu_inline", 0, FOL_ARG_NONE, 0 }, + {"interrupt", 0, FOL_ARG_NONE, 0 }, + {"keep_interrupts_masked", 0, FOL_ARG_NONE, 0 }, + {"long_call", 0, FOL_ARG_NONE, 0 }, + {"leaf", 0, FOL_ARG_NONE, 0 }, + {"noclone", 0, FOL_ARG_NONE, 0 }, + {"noreturn", 0, FOL_ARG_NONE, 0 }, + {"malloc", 0, FOL_ARG_NONE, 0 }, + {"nonnull", 0, FOL_ARG_OPTIONAL_NUM_LIST, 0 }, + {"nothrow", 0, FOL_ARG_NONE, 0 }, + {"optimize", 0, FOL_ARG_STRING, 0 }, + {"returns_nonnull", 0, FOL_ARG_NONE, 0 }, + {"returns_twice", 0, FOL_ARG_NONE, 0 }, + {"section", 0, FOL_ARG_STRING, 0 }, + {"pure", 0, FOL_ARG_NONE, 0 }, + {"use_debug_exception_return", 0, FOL_ARG_NONE, 0 }, + {"use_shadow_register_set", 0, FOL_ARG_NONE, 0 }, + {"visibility", 0, FOL_ARG_STRING, 0 }, + {"warning", 0, FOL_ARG_OPTIONAL_STRING, 0 }, + {"warn_unused_result", 0, FOL_ARG_NONE, 0 }, + {"weak", 0, FOL_ARG_NONE, 0 }, + {"weakref", 0, FOL_ARG_NONE, 0 }, + /* End of table marker, FOL_ARG_NONE is required to stop the attribute + argument parsing. */ + {"\0", 0, FOL_ARG_UNKNOWN, 0 }, +}; + +/* Argument list... */ + +struct GTY ((chain_next ("%h.next"))) mips_func_opt_list_arg +{ + char * GTY ((skip (""))) arg; + unsigned int optimization; + mips_func_opt_list_arg_t arg_type; + struct mips_func_opt_list_arg * next; +}; + +/* Unknown attribute list. */ + +struct GTY ((chain_next ("%h.next"))) mips_func_opt_unknown_list +{ + char * GTY ((skip (""))) attribute; + struct mips_func_opt_list_arg * args; + struct mips_func_opt_unknown_list * next; +}; + +/* ... For this. */ + +struct GTY ((chain_next ("%h.next"))) mips_func_opt_list +{ + char * GTY ((skip (""))) func_name; + sbitmap attributes; + struct mips_func_opt_unknown_list * unknowns; + struct mips_func_opt_list_arg * args; + struct mips_func_opt_list * next; +}; + +/* Head of the function optimization list. */ + +static struct GTY ((chain_next ("%h.next"))) +mips_func_opt_list * mips_fn_opt_list; + +/* Search the func-opt-list for func's entry and return it. */ + +static struct mips_func_opt_list * +mips_func_opt_list_find (const char * func) +{ + struct mips_func_opt_list * i; + for (i = mips_fn_opt_list; i != NULL; i = i->next) + if (strcmp (i->func_name, func) == 0) + return i; + + return NULL; +} + +/* Check if OPT conflicts with the current attributes of f. Return + the entry corresponding the existing attribute that conflicts. */ + +static int +mips_fol_attr_conflicts (struct mips_func_opt_list * f, + unsigned int opt) +{ + /* Trival case: opt has no conflicting attrs / leave for the middle end to + diagnose. */ + if (opt > FOLC_END) + return 0; + + for (int i = 0; i < FOLC_END; i++) + if (bitmap_bit_p (f->attributes, i) + && ((1 << i) & mips_func_opt_list_strings[opt].collisions)) + return i; + + return 0; +} + +#define MATCH_WHITESPACE(A) ISSPACE (A) +#define MATCH_EMPTYSTRING(A) (A == '\n' || A == 0 || A == EOF) + +/* Subroutinue for below. */ + +static void +mips_func_opt_list_parse_arg_1 (const char * line, + struct mips_func_opt_list * f, + unsigned int pos, + unsigned int length, + unsigned int opt) +{ + struct mips_func_opt_list_arg * arg + = (struct mips_func_opt_list_arg *)xcalloc (1, + sizeof (struct mips_func_opt_list_arg)); + + arg->arg = xstrndup (&(line[pos]), length); + arg->optimization = opt; + arg->next = f->args; + + if (mips_func_opt_list_strings[opt].optstring == 0) + f->unknowns->args = arg; + else + f->args = arg; +} + +/* Parse an argument of an attribute of the form: + ("string") or (N<,N,N,...>) + and attach it to the passed struct mips_func_opt_list. + Return the position: either just after ')' or the start of next + word. */ + +static unsigned int +mips_func_opt_list_parse_arg (const char * line, struct mips_func_opt_list * f, + unsigned int opt, unsigned int pos, + const char * file, int lineno) +{ + enum mips_func_opt_list_arg_t arg_type; + arg_type = mips_func_opt_list_strings[opt].arg_type; + unsigned int length = 0; + unsigned int arg_count = 0; + + if (arg_type == FOL_ARG_NONE) + return pos; + + /* Match "+(" */ + while (MATCH_WHITESPACE (line[pos])) + pos++; + + if (MATCH_EMPTYSTRING (line[pos]) + || line[pos] != '(') + { + if (line[pos] != '(' + && (arg_type == FOL_ARG_OPTIONAL_NUM_LIST + || arg_type == FOL_ARG_OPTIONAL_STRING + || arg_type == FOL_ARG_OPTIONAL_NUM + || arg_type == FOL_ARG_UNKNOWN)) + return pos; + else + error ("%s:%d:%d: Expected '('", file, lineno, pos); + } + + pos += 1; + while (MATCH_WHITESPACE (line[pos]) + && !MATCH_EMPTYSTRING (line[pos])) + pos++; + + /* Handle the case of an unknown optimization. Despite not knowing the + format of the arguments, we assume its either a string or an list of + numbers. Peek at the input to correct arg_type. */ + + if (arg_type == FOL_ARG_UNKNOWN) + { + if (line[pos] == '\"') + arg_type = FOL_ARG_STRING; + else + arg_type = FOL_ARG_OPTIONAL_NUM_LIST; + } + + switch (arg_type) + { + /* Parse something of the form ("") and add to e->args. */ + case FOL_ARG_OPTIONAL_STRING: + case FOL_ARG_STRING: + if (MATCH_EMPTYSTRING (line[pos]) + || line[pos] != '\"') + /* Unexpected line end. */ + error ("%s:%d:%d: Expected '\"'", file, lineno, pos); + + pos += 1; + + while (!MATCH_EMPTYSTRING (line[pos+length]) + && line[pos+length] != '\"') + length += 1; + + mips_func_opt_list_parse_arg_1 (line, f, pos, length, opt); + + pos += length + 1; + break; + + /* Parse something of the form (N<,N,N,N,..>) and add them individually + to e->args. */ + case FOL_ARG_SINGLE_NUM: + case FOL_ARG_OPTIONAL_NUM: + case FOL_ARG_OPTIONAL_NUM_LIST: + case FOL_ARG_NUM_ONE_OR_TWO: + while (1) + { + while (ISDIGIT (line[pos+length])) + length++; + + mips_func_opt_list_parse_arg_1 (line, f, pos, length, opt); + pos += length; + length = 0; + arg_count++; + + while (MATCH_WHITESPACE (line[pos])) + pos++; + + if (MATCH_EMPTYSTRING (line[pos]) + && (line[pos] != ',' + || line[pos] != ')')) + error ("%s:%d:%d: Expected ',' or ')'", file, lineno, pos); + + if (line[pos] == ',' + && (arg_type == FOL_ARG_SINGLE_NUM + || (arg_type == FOL_ARG_NUM_ONE_OR_TWO + && arg_count > 2))) + error ("%s:%d:%d: Unexpected ','", file, lineno, pos); + + if (line[pos] == ')') + break; + + pos += 1; + while (MATCH_WHITESPACE (line[pos])) + pos++; + } + break; + default: + gcc_unreachable (); + } + + while (MATCH_WHITESPACE (line[pos]) + && !MATCH_EMPTYSTRING (line[pos])) + pos++; + + /* Unmatched ')'. */ + if (MATCH_EMPTYSTRING (line[pos]) + || line[pos] != ')') + error ("%s:%d:%d: Expected ')'", file, lineno, pos); + + pos += 1; + + return pos; +} + +/* Read a line and return a struct describing attributes for the function. + Odd case: If the function has already appeared in mips_fn_opt_list update + the entry in place but return NULL, otherwise we may end up building a + circular list. Error out nicely when: misspelled optimization, conflicting + attributes. */ + +static struct mips_func_opt_list * +mips_func_opt_list_read_line (const char * line, const char * file, int lineno) +{ + size_t identifier_length = 0; + unsigned int opt = 0; + struct mips_func_opt_list * fl = NULL; + unsigned int pos = 0; + bool matched = false; + bool update = false; + + /* Take all leading whitespace. */ + while (MATCH_WHITESPACE (line[pos])) + pos++; + + if (MATCH_EMPTYSTRING (line[pos])) + return NULL; + + /* Take all non-whitespace for the function name. */ + while (!MATCH_WHITESPACE (line[pos + identifier_length]) + && !MATCH_EMPTYSTRING (line[pos + identifier_length])) + identifier_length++; + + /* Construct a new struct mips_func_opt_list temporarily and search for an + existing entry. Use existing entry over a new one. */ + fl = (struct mips_func_opt_list *) + xcalloc (1, sizeof (struct mips_func_opt_list)); + fl->func_name = xstrndup (&line[pos], identifier_length); + if (mips_func_opt_list_find (fl->func_name) == NULL) + { + fl->args = NULL; + fl->unknowns = NULL; + fl->next = NULL; + fl->attributes = sbitmap_alloc (sizeof (mips_func_opt_list_strings) + / sizeof (struct attr_desc)); + bitmap_clear (fl->attributes); + } + else + { + char * n = fl->func_name; + free (fl); + fl = mips_func_opt_list_find (n); + free (n); + update = true; + } + + pos += identifier_length; + identifier_length = 0; + + /* Warn for */ + if (MATCH_EMPTYSTRING (line[pos])) + { + warning (OPT_Wattributes, "%s:%d: No optimizations specified for %qs", + file, lineno, fl->func_name); + return NULL; + } + + /* Parse a (possibly empty) list of attributes. */ + while (1) + { + while (MATCH_WHITESPACE (line[pos])) + pos++; + + if (MATCH_EMPTYSTRING (line[pos])) + { + if (update) + return NULL; + else + return fl; + } + + /* Parse and match an attribute. Warn and blame -mfunc-opt-list= if + the attributes are known to conflict. The middle-end will complain as + well, but won't be able to blame the source properly. */ + while (!MATCH_WHITESPACE (line[pos + identifier_length]) + && !MATCH_EMPTYSTRING (line[pos + identifier_length]) + && line[pos + identifier_length] != '(') + identifier_length++; + + for (opt = 0; *mips_func_opt_list_strings[opt].optstring != 0; opt++) + { + if (mips_func_opt_list_strings[opt].optstring != 0 + && strncmp (mips_func_opt_list_strings[opt].optstring, &(line[pos]), + identifier_length) == 0) + { + int conflict_attr = mips_fol_attr_conflicts (fl, opt); + if (conflict_attr) + warning (OPT_Wattributes, "%s:%d:%d: Attribute %qs cannot be" + " applied to function %qs as it has the conflicting " + "attribute %qs", file, lineno, pos, + mips_func_opt_list_strings[opt].optstring, + fl->func_name, + mips_func_opt_list_strings[conflict_attr].optstring); + + bitmap_set_bit (fl->attributes, opt); + matched = true; + break; + } + } + + /* Correctly blame the unknown attribute. */ + if (!matched) + { + struct mips_func_opt_unknown_list * e + = (struct mips_func_opt_unknown_list*) + xcalloc (1, sizeof (struct mips_func_opt_unknown_list)); + e->next = fl->unknowns; + e->attribute = xstrndup (&(line[pos]), identifier_length); + warning (OPT_Wattributes, "%s:%d:%d: Unknown attribute %qs for %qs", + file, lineno, pos, e->attribute, fl->func_name); + fl->unknowns = e; + } + + matched = false; + pos += identifier_length; + identifier_length = 0; + + /* Parse any arguments if required, get new position. */ + pos = mips_func_opt_list_parse_arg (line, fl, opt, pos, file, lineno); + } +} + +#undef MATCH_WHITESPACE +#undef MATCH_EMPTYSTRING + +/* Entry point for FUNC_OPT_LIST. Grab the conents of a file and build + a list of functions with a bitmap describing attributes desired. */ + +static void +mips_func_opt_list_read () +{ + FILE * fd; + int lineno = 0; + char line[512]; + struct mips_func_opt_list *trial = NULL; + + unsigned int i; + cl_deferred_option *opt; + vec *v; + v = (vec *) mips_func_opt_list_file; + + FOR_EACH_VEC_ELT (*v, i, opt) + { + if (opt->opt_index != OPT_mfunc_opt_list_) + continue; + + const char * filename = opt->arg; + if (filename == NULL) + continue; + + fd = fopen (filename, "r"); + if (fd == NULL) + { + error ("Cannot read %qs for -mfunc-opt-list=\n", filename); + return; + } + + while (fgets (line, sizeof (line), fd)) + { + trial = mips_func_opt_list_read_line ((const char *)&line, + filename, lineno); + lineno++; + + /* trial can be null if we didn't read a well formed line or if an + update in place occurred. Otherwise insert new entry at the head + of the list. */ + if (trial) + { + trial->next = mips_fn_opt_list; + mips_fn_opt_list = trial; + } + } + + fclose (fd); + } +} + /* A table describing all the processors GCC knows about; see mips-cpus.def for details. */ static const struct mips_cpu_info mips_cpu_info_table[] = { @@ -1569,6 +2087,86 @@ mips_comp_type_attributes (const_tree type1, const_tree type2) return 1; } +/* Return a tree of the arguments of an attribute list. */ + +static tree +mips_insert_fol_args (struct mips_func_opt_list_arg * args, + unsigned int optimization, + mips_func_opt_list_arg_t arg_type) +{ + tree ret = NULL; + for (; args; args = args->next) + if (args->optimization == optimization) + { + tree arg; + if (arg_type == FOL_ARG_OPTIONAL_STRING + || arg_type == FOL_ARG_STRING) + arg = build_string (strlen (args->arg), args->arg); + else + arg = build_int_cst (NULL, atoi (args->arg)); + + if (ret == NULL) + ret = build_tree_list (NULL_TREE, arg); + else + ret = chainon (ret, build_tree_list (NULL_TREE, arg)); + } + return ret; +} + +/* Implement -mfunc-opt-list. With the struct of optmizations and attributes, + insert the attributes. */ + +static void +mips_insert_fol_attributes (struct mips_func_opt_list * func_opt_list, + tree *attributes) +{ + for (int i = 0; *mips_func_opt_list_strings[i].optstring != 0; i++) + if (bitmap_bit_p (func_opt_list->attributes, i)) + { + const char * opstr = mips_func_opt_list_strings[i].optstring; + const char * maintype = mips_func_opt_list_strings[i].maintype; + int l = strlen (opstr); + + tree attr_args = NULL; + if (mips_func_opt_list_strings[i].arg_type != FOL_ARG_NONE) + attr_args = mips_insert_fol_args (func_opt_list->args, i, + mips_func_opt_list_strings[i].arg_type); + + /* Some strange logic: If .maintype == 0, .optstring is the + attribute. Otherwise the actual attribute is + .maintype (".optstring"). */ + if (mips_func_opt_list_strings[i].maintype == 0) + { + *attributes = tree_cons (get_identifier (opstr), attr_args, + *attributes); + } + else + { attr_args = build_tree_list (NULL_TREE, + build_string (l, opstr)); + + *attributes = tree_cons (get_identifier (maintype), attr_args, + *attributes); + } + } + + if (func_opt_list->unknowns) + { + struct mips_func_opt_unknown_list * l = func_opt_list->unknowns; + while (l) + { + tree attr_args = NULL; + if (l->args) + attr_args = mips_insert_fol_args (l->args, l->args->optimization, + l->args->arg_type); + + *attributes = tree_cons (get_identifier (l->attribute), attr_args, + *attributes); + l = l->next; + } + + } +} + /* Implement TARGET_INSERT_ATTRIBUTES. */ static void @@ -1631,6 +2229,14 @@ mips_insert_attributes (tree decl, tree *attributes) error ("%qE cannot have both %qs and %qs attributes", DECL_NAME (decl), "mips16", "micromips"); + if (mips_fn_opt_list) + { + struct mips_func_opt_list * func_opt_list + = mips_func_opt_list_find (IDENTIFIER_POINTER (DECL_NAME (decl))); + if (func_opt_list) + mips_insert_fol_attributes (func_opt_list, attributes); + } + if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl) && compression_flags == 0 @@ -20712,6 +21318,9 @@ mips_option_override (void) mips_unique_sections_list = mips_read_list (mips_unique_sections_file, "-munique-sections"); + if (mips_func_opt_list_file) + mips_func_opt_list_read (); + /* Set the small data limit. */ mips_small_data_threshold = (OPTION_SET_P (g_switch_value) ? g_switch_value diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index e0a305aec22..012ca91560f 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -552,3 +552,7 @@ msdata-opt-list=FILE Use to specify variables to go in the .sdata section. munique-sections= Target RejectNegative Joined Var(mips_unique_sections_file) munique-sections=FILE Use to specify sections that should be made unique. + +mfunc-opt-list= +Target RejectNegative Joined Var(mips_func_opt_list_file) Init(0) Defer +mfunc-opt-list=FILE Use to specify per function optimizations. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 952baf872ec..cd84cafafd5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1147,6 +1147,7 @@ Objective-C and Objective-C++ Dialects}. -msmartmips -mno-smartmips -mpaired-single -mno-paired-single -mdmx -mno-mdmx -mips3d -mno-mips3d -mmt -mno-mt -mllsc -mno-llsc +-mfunc-opt-list=@var{file} -mlong64 -mlong32 -msym32 -mno-sym32 -G@var{num} -mlocal-sdata -mno-local-sdata -mextern-sdata -mno-extern-sdata -mgpopt -mno-gopt @@ -28709,6 +28710,38 @@ Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. @itemx -mno-loongson-ext2 Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions. +@opindex mfunc-opt-list +@item -mfunc-opt-list= +Read a list of functions from a file and apply a series of attributes to +them as if they had been specified in the source file. The format of the +file is plain text with one function per line. The first non-whitespace +word of each line is the function name, followed by whitespace, then a +whitespace separated list of function attributes. Attributes are written +in the same format as they appear in the parentheses of the __attribute__ +directive. + +For example: +@smallexample +foo mips16 optimize ("Os") +bar always_inline +@end smallexample + +The following attributes are recognised: +@smallexample +alias, aligned, alloc_size, alloc_align, always_inline, artifical, +assume_aligned, code_readable, cold, const, constructor, deprecated, +destructor, error, far, flatten, gnu_inline, hot, interrupt, +keep_interrupts_masked, leaf, long_call, malloc, mips16, near, noclone, +noinline, nomips16, nonnull, noreturn, nothrow, optimize, pure, +returns_nonnull, returns_twice, section, unused, used, +use_debug_exception_return, use_shadow_register_set, visibility, warning, +warn_unused_result, weak, weakref. +@end smallexample + +Unrecognised attributes will produce a warning diagnostic giving the location +where it was found in the list. A second diagnostic will be produced citing +the name of the function and unknown attribute. + @opindex mlong64 @item -mlong64 Force @code{long} types to be 64 bits wide. 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A memcpy strictly less than this value will be considered for inlining. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_block_move): Add support to control size of inlined memcpy. * config/mips/mips.opt (mblockmov-limit): New option. Cherry-picked cf1e4960a4f80301e4c8f71a35cbbc8fef1ce6fd from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 21 ++++++++++++--------- gcc/config/mips/mips.opt | 3 +++ 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 32fe62ce79b..d9c913f2e23 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -9360,16 +9360,19 @@ mips_expand_block_move (rtx dest, rtx src, rtx length) || MEM_ALIGN (dest) < MIPS_MIN_MOVE_MEM_ALIGN)) return false; - if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER) + if (mips_movmem_limit == -1 || INTVAL (length) < mips_movmem_limit) { - mips_block_move_straight (dest, src, INTVAL (length)); - return true; - } - else if (optimize) - { - mips_block_move_loop (dest, src, INTVAL (length), - MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); - return true; + if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER) + { + mips_block_move_straight (dest, src, INTVAL (length)); + return true; + } + else if (optimize) + { + mips_block_move_loop (dest, src, INTVAL (length), + MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); + return true; + } } return false; diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 012ca91560f..a4b93de924d 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -556,3 +556,6 @@ munique-sections=FILE Use to specify sections that should be made unique. mfunc-opt-list= Target RejectNegative Joined Var(mips_func_opt_list_file) Init(0) Defer mfunc-opt-list=FILE Use to specify per function optimizations. + +mblockmov-limit= +Target RejectNegative Undocumented Joined UInteger Var(mips_movmem_limit) Init(-1) From patchwork Fri Jan 31 17:13:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105765 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B96573857B8F for ; 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Also occasional generation of LHU/LBU appeared where the original value was not already in memory. Performance results are showing wild and unexpected variation which appears to correlate with the way in which ZEH/ZEB handling is or is not implemented. Support all forms tried so far with a hidden option defaulting to the preferred method. - Check to see if it is safe to use the SAVE/RESTORE instruction in a function. - Add interaptiv-mr2 architecture with COPYW/UCOPYW. - Add -muse-copyw-ucopyw option (hidden from help). - Disable tests at -O0 due to introducing a frame: SAVE/RESTORE end up introducing a frame owing to saving more data than strictly necessary. gcc/ * config/mips/mips.cc (mips_option_override): Set default for TARGET_USE_COPYW_UCOPYW. * config/mips/mips.h (ISA_HAS_COPY): Update to reference TARGET_USE_COPYW_UCOPYW. * config/mips/mips.opt (-muse-copyw-ucopyw): New hidden option. * config/mips/mips-cpus.def: Set PTF_AVOID_BRANCHLIKELY_ALWAYS flag for interAptiv-mr2 CPU. gcc/testsuite/ * gcc.target/mips/iamr2.c: New test. * gcc.target/mips/memcpy-3.c: New test. * gcc.target/mips/memcpy-4.c: Likewise. * gcc.target/mips/mips.exp: Accept -muse-copyw-ucopyw and isa=interaptiv-mr2. (mips-dg-init): Add memcpy option. * gcc.target/mips/r10k-cache-barrier-9.c: Skip test for -O0. * gcc.target/mips/stack-1.c: Likewise. Cherry-picked 01dbcc401881f2e4ed063fe43406f8670e4e0cac, 34e4b01b6e6afea14f51c093520c58e7eb3ddb66, 3475f16f5ce9d1247758f5d3a858af5163116d71 and aecf341540d1462145eaf47e3cfa7e7780ee7adc from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek Signed-off-by: Matthew Fortune Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/24k.md | 68 ++-- gcc/config/mips/mips-cpus.def | 2 + gcc/config/mips/mips-protos.h | 3 +- gcc/config/mips/mips-tables.opt | 57 ++-- gcc/config/mips/mips.cc | 300 ++++++++++++++++-- gcc/config/mips/mips.h | 35 +- gcc/config/mips/mips.md | 94 +++++- gcc/config/mips/mips.opt | 6 + gcc/config/mips/predicates.md | 2 +- gcc/doc/invoke.texi | 2 +- gcc/testsuite/gcc.target/mips/iamr2.c | 51 +++ gcc/testsuite/gcc.target/mips/memcpy-3.c | 14 + gcc/testsuite/gcc.target/mips/memcpy-4.c | 14 + gcc/testsuite/gcc.target/mips/mips.exp | 6 + .../gcc.target/mips/r10k-cache-barrier-9.c | 1 + gcc/testsuite/gcc.target/mips/stack-1.c | 1 + 16 files changed, 557 insertions(+), 99 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/iamr2.c create mode 100644 gcc/testsuite/gcc.target/mips/memcpy-3.c create mode 100644 gcc/testsuite/gcc.target/mips/memcpy-4.c diff --git a/gcc/config/mips/24k.md b/gcc/config/mips/24k.md index 1d09c929ab4..8e49456eac0 100644 --- a/gcc/config/mips/24k.md +++ b/gcc/config/mips/24k.md @@ -41,7 +41,7 @@ ;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs (define_insn_reservation "r24k_int_load" 2 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "load")) "r24k_iss+r24k_ixu_arith") @@ -53,7 +53,7 @@ ;; (movn/movz is not matched, we'll need to split condmov to ;; differentiate between integer/float moves) (define_insn_reservation "r24k_int_arith" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt")) "r24k_iss+r24k_ixu_arith") @@ -61,13 +61,13 @@ ;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx ;; 3a. jr/jalr consumer (define_insn_reservation "r24k_int_jump" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "call,jump")) "r24k_iss+r24k_ixu_arith") ;; 3b. branch consumer (define_insn_reservation "r24k_int_branch" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "branch")) "r24k_iss+r24k_ixu_arith") @@ -75,38 +75,38 @@ ;; 4. MDU: fully pipelined multiplier ;; mult - delivers result to hi/lo in 1 cycle (pipelined) (define_insn_reservation "r24k_int_mult" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "imul")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") ;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined) (define_insn_reservation "r24k_int_madd" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "imadd")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") ;; mul - delivers result to gpr in 5 cycles (define_insn_reservation "r24k_int_mul3" 5 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "imul3")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5") ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles (define_insn_reservation "r24k_int_mfhilo" 5 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "mfhi,mflo")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass (define_insn_reservation "r24k_int_mthilo" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "mthi,mtlo")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and ;; 8bit, but is tricky to identify. (define_insn_reservation "r24k_int_div" 36 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "idiv")) "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36") @@ -114,21 +114,21 @@ ;; 5. Cop: cfc1, di, ei, mfc0, mtc0 ;; (Disabled until we add proper cop0 support) ;;(define_insn_reservation "r24k_int_cop" 3 -;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") +;; (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") ;; (eq_attr "type" "cop0")) ;; "r24k_iss+r24k_ixu_arith") ;; 6. Store (define_insn_reservation "r24k_int_store" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "store")) "r24k_iss+r24k_ixu_arith") ;; 7. Multiple instructions (define_insn_reservation "r24k_int_multi" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "multi")) "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)") @@ -137,14 +137,14 @@ ;; rtls. They do not really affect scheduling latency, (blockage affects ;; scheduling via log links, but not used here). (define_insn_reservation "r24k_int_unknown" 0 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "unknown,atomic,syncloop")) "r24k_iss") ;; 9. Prefetch (define_insn_reservation "r24k_int_prefetch" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "prefetch,prefetchx")) "r24k_iss+r24k_ixu_arith") @@ -211,31 +211,31 @@ ;; packrl, pick, preceq, preceu, precequ, precrq, precrqu, raddu, rddsp, repl, ;; replv, shll, shllv, shra, shrav, shrl, shrlv, subq, subu, wrdsp (define_insn_reservation "r24k_dsp_alu" 2 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "dspalu,dspalusat")) "r24k_iss+r24k_ixu_arith") ;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq (define_insn_reservation "r24k_dsp_mac" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "dspmac")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") ;; dpaq_sa, dpsq_sa, maq_sa (define_insn_reservation "r24k_dsp_mac_sat" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "dspmacsat")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") ;; extp, extpdp, extpdpv, extpv, extr, extrv (define_insn_reservation "r24k_dsp_acc_ext" 5 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "accext")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") ;; mthlip, shilo, shilov (define_insn_reservation "r24k_dsp_acc_mod" 1 - (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") + (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1,interaptiv_mr2") (eq_attr "type" "accmod")) "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") @@ -435,37 +435,37 @@ ;; fadd, fabs, fneg (define_insn_reservation "r24kf1_1_fadd" 4 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (eq_attr "type" "fadd,fabs,fneg")) "r24kf1_1_fpu_iss") ;; fmove, fcmove (define_insn_reservation "r24kf1_1_fmove" 4 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (eq_attr "type" "fmove,condmove")) "r24kf1_1_fpu_iss") ;; fload (define_insn_reservation "r24kf1_1_fload" 3 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (eq_attr "type" "fpload,fpidxload")) "r24kf1_1_fpu_iss") ;; fstore (define_insn_reservation "r24kf1_1_fstore" 1 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (eq_attr "type" "fpstore")) "r24kf1_1_fpu_iss") ;; fmul, fmadd (define_insn_reservation "r24kf1_1_fmul_sf" 4 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "fmul,fmadd") (eq_attr "mode" "SF"))) "r24kf1_1_fpu_iss") (define_insn_reservation "r24kf1_1_fmul_df" 5 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "fmul,fmadd") (eq_attr "mode" "DF"))) "r24kf1_1_fpu_iss,r24k_fpu_arith") @@ -473,27 +473,27 @@ ;; fdiv, fsqrt, frsqrt (define_insn_reservation "r24kf1_1_fdiv_sf" 17 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "fdiv,fsqrt,frsqrt") (eq_attr "mode" "SF"))) "r24kf1_1_fpu_iss,(r24k_fpu_arith*13)") (define_insn_reservation "r24kf1_1_fdiv_df" 32 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "fdiv,fsqrt") (eq_attr "mode" "DF"))) "r24kf1_1_fpu_iss,(r24k_fpu_arith*28)") ;; frsqrt (define_insn_reservation "r24kf1_1_frsqrt_df" 35 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "frsqrt") (eq_attr "mode" "DF"))) "r24kf1_1_fpu_iss,(r24k_fpu_arith*30)") ;; fcmp (define_insn_reservation "r24kf1_1_fcmp" 2 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (eq_attr "type" "fcmp")) "r24kf1_1_fpu_iss") @@ -502,28 +502,28 @@ ;; fcvt (cvt.d.s, cvt.[sd].[wl]) (define_insn_reservation "r24kf1_1_fcvt_i2f_s2d" 4 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "fcvt") (eq_attr "cnv_mode" "I2S,I2D,S2D"))) "r24kf1_1_fpu_iss") ;; fcvt (cvt.s.d) (define_insn_reservation "r24kf1_1_fcvt_s2d" 6 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "fcvt") (eq_attr "cnv_mode" "D2S"))) "r24kf1_1_fpu_iss") ;; fcvt (cvt.[wl].[sd], etc) (define_insn_reservation "r24kf1_1_fcvt_f2i" 5 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (and (eq_attr "type" "fcvt") (eq_attr "cnv_mode" "S2I,D2I"))) "r24kf1_1_fpu_iss") ;; fxfer (mfc1, mfhc1, mtc1, mthc1) (define_insn_reservation "r24kf1_1_fxfer" 2 - (and (eq_attr "cpu" "24kf1_1") + (and (eq_attr "cpu" "24kf1_1,interaptiv_mr2") (eq_attr "type" "mfc,mtc")) "r24kf1_1_fpu_iss") diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 50843480b03..b52a609e12a 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -145,6 +145,8 @@ MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("interaptiv-mr2", PROCESSOR_INTERAPTIV_MR2, MIPS_ISA_MIPS32R3, + PTF_AVOID_BRANCHLIKELY_ALWAYS) /* MIPS32 Release 5 processors. */ MIPS_CPU ("p5600", PROCESSOR_P5600, MIPS_ISA_MIPS32R5, (PTF_AVOID_BRANCHLIKELY_SPEED diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index c514c0711de..6b8f2370752 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -242,7 +242,8 @@ extern bool mips_get_pic_call_symbol (rtx *, int); extern void mips_set_return_address (rtx, rtx); extern bool mips_move_by_pieces_p (unsigned HOST_WIDE_INT, unsigned int); extern bool mips_store_by_pieces_p (unsigned HOST_WIDE_INT, unsigned int); -extern bool mips_expand_block_move (rtx, rtx, rtx); +extern bool mips_expand_block_move (rtx, rtx, rtx, rtx); +extern bool mips16_expand_copy (rtx, rtx, rtx, rtx); extern void mips_expand_synci_loop (rtx, rtx); extern void mips_init_cumulative_args (CUMULATIVE_ARGS *, tree); diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index c26009cfb5c..9f5da087bbd 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -634,83 +634,86 @@ EnumValue Enum(mips_arch_opt_value) String(interaptiv) Value(85) Canonical EnumValue -Enum(mips_arch_opt_value) String(p5600) Value(86) Canonical +Enum(mips_arch_opt_value) String(interaptiv-mr2) Value(86) Canonical EnumValue -Enum(mips_arch_opt_value) String(m5100) Value(87) Canonical +Enum(mips_arch_opt_value) String(p5600) Value(87) Canonical EnumValue -Enum(mips_arch_opt_value) String(m5101) Value(88) Canonical +Enum(mips_arch_opt_value) String(m5100) Value(88) Canonical EnumValue -Enum(mips_arch_opt_value) String(m6201) Value(89) Canonical +Enum(mips_arch_opt_value) String(m5101) Value(89) Canonical EnumValue -Enum(mips_arch_opt_value) String(5kc) Value(90) Canonical +Enum(mips_arch_opt_value) String(m6201) Value(90) Canonical EnumValue -Enum(mips_arch_opt_value) String(r5kc) Value(90) +Enum(mips_arch_opt_value) String(5kc) Value(91) Canonical EnumValue -Enum(mips_arch_opt_value) String(5kf) Value(91) Canonical +Enum(mips_arch_opt_value) String(r5kc) Value(91) EnumValue -Enum(mips_arch_opt_value) String(r5kf) Value(91) +Enum(mips_arch_opt_value) String(5kf) Value(92) Canonical EnumValue -Enum(mips_arch_opt_value) String(20kc) Value(92) Canonical +Enum(mips_arch_opt_value) String(r5kf) Value(92) EnumValue -Enum(mips_arch_opt_value) String(r20kc) Value(92) +Enum(mips_arch_opt_value) String(20kc) Value(93) Canonical EnumValue -Enum(mips_arch_opt_value) String(sb1) Value(93) Canonical +Enum(mips_arch_opt_value) String(r20kc) Value(93) EnumValue -Enum(mips_arch_opt_value) String(sb1a) Value(94) Canonical +Enum(mips_arch_opt_value) String(sb1) Value(94) Canonical EnumValue -Enum(mips_arch_opt_value) String(sr71000) Value(95) Canonical +Enum(mips_arch_opt_value) String(sb1a) Value(95) Canonical EnumValue -Enum(mips_arch_opt_value) String(sr71k) Value(95) +Enum(mips_arch_opt_value) String(sr71000) Value(96) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlr) Value(96) Canonical +Enum(mips_arch_opt_value) String(sr71k) Value(96) EnumValue -Enum(mips_arch_opt_value) String(loongson3a) Value(97) Canonical +Enum(mips_arch_opt_value) String(xlr) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(gs464) Value(98) Canonical +Enum(mips_arch_opt_value) String(loongson3a) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(gs464e) Value(99) Canonical +Enum(mips_arch_opt_value) String(gs464) Value(99) Canonical EnumValue -Enum(mips_arch_opt_value) String(gs264e) Value(100) Canonical +Enum(mips_arch_opt_value) String(gs464e) Value(100) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(101) Canonical +Enum(mips_arch_opt_value) String(gs264e) Value(101) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(102) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(102) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(103) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(103) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(104) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(104) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(105) Canonical +Enum(mips_arch_opt_value) String(octeon3) Value(105) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6400) Value(106) Canonical +Enum(mips_arch_opt_value) String(xlp) Value(106) Canonical EnumValue -Enum(mips_arch_opt_value) String(i6500) Value(107) Canonical +Enum(mips_arch_opt_value) String(i6400) Value(107) Canonical EnumValue -Enum(mips_arch_opt_value) String(p6600) Value(108) Canonical +Enum(mips_arch_opt_value) String(i6500) Value(108) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(p6600) Value(109) Canonical diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index d9c913f2e23..9808fda286c 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -106,7 +106,7 @@ along with GCC; see the file COPYING3. If not see to save and restore registers, and to allocate and deallocate the top part of the frame. */ #define MIPS_MAX_FIRST_STACK_STEP \ - (!TARGET_COMPRESSION ? 0x7ff0 \ + (!TARGET_COMPRESSION && !TARGET_USE_SAVE_RESTORE ? 0x7ff0 \ : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \ : TARGET_64BIT ? 0x100 : 0x400) @@ -1413,6 +1413,19 @@ static const struct mips_rtx_cost_data 1, /* branch_cost */ 4 /* memory_latency */ }, + { /* INTERAPTIV_MR2 (identical to 24KF1_1) */ + COSTS_N_INSNS (4), /* fp_add */ + COSTS_N_INSNS (4), /* fp_mult_sf */ + COSTS_N_INSNS (5), /* fp_mult_df */ + COSTS_N_INSNS (17), /* fp_div_sf */ + COSTS_N_INSNS (32), /* fp_div_df */ + COSTS_N_INSNS (5), /* int_mult_si */ + COSTS_N_INSNS (5), /* int_mult_di */ + COSTS_N_INSNS (41), /* int_div_si */ + COSTS_N_INSNS (41), /* int_div_di */ + 1, /* branch_cost */ + 4 /* memory_latency */ + }, { /* Loongson-2E */ DEFAULT_COSTS }, @@ -1752,7 +1765,7 @@ static const struct mips_rtx_cost_data COSTS_N_INSNS (68), /* int_div_di */ 1, /* branch_cost */ 4 /* memory_latency */ - } + } }; static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool); @@ -2454,7 +2467,10 @@ mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value) /* Either this is a simple LUI/ORI pair, or clearing the lowest 16 bits gives a value with at least 17 trailing zeros. */ i = mips_build_integer (codes, high); - codes[i].code = IOR; + if (ISA_HAS_MIPS16E2 && (value & 0x8000) == 0) + codes[i].code = PLUS; + else + codes[i].code = IOR; codes[i].value = value & 0xffff; } return i + 1; @@ -4660,7 +4676,7 @@ mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context) /* Return true if OP refers to small data symbols directly, not through a LO_SUM. CONTEXT is the context in which X appears. */ -static int +static bool mips_small_data_pattern_1 (rtx x, enum mips_symbol_context context) { subrtx_var_iterator::array_type array; @@ -4760,6 +4776,11 @@ mips16_constant_cost (int code, HOST_WIDE_INT x) return COSTS_N_INSNS (1); return -1; + case IOR: + if (ISA_HAS_MIPS16E2 && SMALL_OPERAND_UNSIGNED (x)) + return COSTS_N_INSNS (1); + return -1; + case LEU: /* Like LE, but reject the always-true case. */ if (x == -1) @@ -6060,6 +6081,15 @@ mips_split_move_insn (rtx dest, rtx src, rtx insn) /* Return the appropriate instructions to move SRC into DEST. Assume that SRC is operand 1 and DEST is operand 0. */ +bool +mips_constant_pool_symbol_in_sdata (rtx x, enum mips_symbol_context context) +{ + enum mips_symbol_type symbol_type; + return (mips_symbolic_constant_p (x, context, &symbol_type) + && symbol_type == SYMBOL_GP_RELATIVE + && CONSTANT_POOL_ADDRESS_P (x)); +} + const char * mips_output_move (rtx insn, rtx dest, rtx src) { @@ -6234,7 +6264,13 @@ mips_output_move (rtx insn, rtx dest, rtx src) } if (src_code == HIGH) - return (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? "#" : "lui\t%0,%h1"; + { + if (mips_constant_pool_symbol_in_sdata (XEXP (src, 0), + SYMBOL_CONTEXT_MEM)) + return "move\t%0,$28"; + + return (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? "#" : "lui\t%0,%h1"; + } if (CONST_GP_P (src)) return "move\t%0,%1"; @@ -9133,6 +9169,10 @@ mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, return false; if (align < BITS_PER_WORD) return size < UNITS_PER_WORD; + /* It is more profitable to use COPYW for at least 2 words. */ + if (ISA_HAS_COPY + && align >= BITS_PER_WORD && size >= 2 * UNITS_PER_WORD) + return false; return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT; } @@ -9202,7 +9242,8 @@ mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align) Assume that the areas do not overlap. */ static void -mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) +mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length, + HOST_WIDE_INT alignment ATTRIBUTE_UNUSED) { HOST_WIDE_INT offset, delta; unsigned HOST_WIDE_INT bits; @@ -9302,6 +9343,7 @@ mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, static void mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, + HOST_WIDE_INT alignment, HOST_WIDE_INT bytes_per_iter) { rtx_code_label *label; @@ -9325,7 +9367,7 @@ mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, emit_label (label); /* Emit the loop body. */ - mips_block_move_straight (dest, src, bytes_per_iter); + mips_block_move_straight (dest, src, bytes_per_iter, alignment); /* Move on to the next block. */ mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); @@ -9340,36 +9382,176 @@ mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, /* Mop up any left-over bytes. */ if (leftover) - mips_block_move_straight (dest, src, leftover); + mips_block_move_straight (dest, src, leftover, alignment); else /* Temporary fix for PR79150. */ emit_insn (gen_nop ()); } +/* Expand a cpymemsi instruction using the mips16 copy instruction. */ + +bool +mips16_expand_copy (rtx dest, rtx src, rtx length, rtx alignment) +{ + rtx base_dest, base_src; + rtx temp; + HOST_WIDE_INT offset_dest, offset_src; + int word_count, byte_count, offset = 0; + rtx first_dest = dest, first_src = src; + rtx xdest = XEXP (dest, 0); + rtx xsrc = XEXP (src, 0); + int align = INTVAL (alignment); + bool word_by_pieces_p = false; + + if (!ISA_HAS_COPY) + return false; + + gcc_assert (!TARGET_64BIT); + gcc_assert (MEM_P (src) && MEM_P (dest)); + + if (!CONST_INT_P (length)) + return false; + + byte_count = INTVAL (length); + + if (byte_count > (mips_movmem_limit == -1 + ? MIPS_MAX_MOVE_BYTES_STRAIGHT + : mips_movmem_limit)) + return false; + + if (byte_count >= MIPS_MAX_MOVE_BYTES_STRAIGHT + && align < 4) + return false; + + word_count = byte_count / UNITS_PER_WORD; + byte_count = byte_count % UNITS_PER_WORD; + + mips_split_plus (xdest, &base_dest, &offset_dest); + mips_split_plus (xsrc, &base_src, &offset_src); + + /* In some cases, it's better to move by pieces rather than generating + COPYW/UCOPYW: + 1. Copying 4 bytes when both dest and src are aligned but base+offset is + likely to be squashed. + 2. Copying 4 bytes when the lowest alignment is 2-bytes iff the offsets + are not the same or multiples of 16 bytes. */ + + /* Case (1). */ + if (word_count == 1 + && MEM_ALIGN (dest) >= 4 * BITS_PER_UNIT + && MEM_ALIGN (src) >= 4 * BITS_PER_UNIT + && (offset_dest >= 0 || offset_src >= 0)) + word_by_pieces_p = true; + + /* Case (2). */ + if (word_count == 1 && align >= 2 + && !(offset_src == offset_dest && offset_src % 16 != 0)) + word_by_pieces_p = true; + + if (word_by_pieces_p) + { + rtx src2 = adjust_address (src, BLKmode, offset); + rtx dest2 = adjust_address (dest, BLKmode, offset); + move_by_pieces (dest2, src2, 4, INTVAL (alignment), RETURN_BEGIN); + offset += 4; + word_count = 0; + } + + if (word_count > 0 && !REG_P (XEXP (dest, 0))) + { + rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); + first_dest = replace_equiv_address (first_dest, dest_reg); + } + + if (word_count > 0 && !REG_P (XEXP (src, 0))) + { + rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); + first_src = replace_equiv_address (first_src, src_reg); + } + + while (word_count > 0) + { + int new_word_count, new_offset; + rtx adj_src, adj_dest; + + new_offset = offset; + new_word_count = word_count >= 4 ? 4 : word_count; + + /* Using a COPYW dst,src,*,1 instruction causes the core to stall + so we generate a lw/sw sequence to get around this core bug. */ + if (new_word_count == 1 && align >= 4) + { + temp = gen_reg_rtx (SImode); + adj_src = adjust_address (first_src, Pmode, new_offset); + adj_dest = adjust_address (first_dest, Pmode, new_offset); + mips_emit_move (temp, adj_src); + mips_emit_move (adj_dest, temp); + } + else + { + adj_src = adjust_address (first_src, BLKmode, new_offset); + adj_dest = adjust_address (first_dest, BLKmode, new_offset); + set_mem_size (adj_src, new_word_count * 4); + set_mem_size (adj_dest, new_word_count * 4); + emit_insn (gen_mips16_copy (adj_dest, adj_src, GEN_INT (new_offset), + GEN_INT (new_word_count), alignment)); + } + + offset += new_word_count * 4; + word_count = word_count >= 4 ? word_count - 4 : 0; + + if (offset > 496) + { + rtx dest_reg = copy_addr_to_reg (XEXP (adj_dest, 0)); + rtx src_reg = copy_addr_to_reg (XEXP (adj_src, 0)); + first_dest = replace_equiv_address (first_dest, dest_reg); + first_src = replace_equiv_address (first_src, src_reg); + offset = 0; + } + } + + if (byte_count > 0) + { + rtx src2 = adjust_address (src, BLKmode, offset); + rtx dest2 = adjust_address (dest, BLKmode, offset); + move_by_pieces (dest2, src2, byte_count, align, RETURN_BEGIN); + } + + return true; +} + /* Expand a cpymemsi instruction, which copies LENGTH bytes from - memory reference SRC to memory reference DEST. */ + memory reference SRC to memory reference DEST. The lowest alignment + of SRC and DEST is specified by ALIGNMENT. */ bool -mips_expand_block_move (rtx dest, rtx src, rtx length) +mips_expand_block_move (rtx dest, rtx src, rtx length, rtx alignment) { if (!CONST_INT_P (length)) return false; + if (TARGET_MIPS16 && !ISA_HAS_COPY) + return false; + if (mips_isa_rev >= 6 && !ISA_HAS_UNALIGNED_ACCESS - && (MEM_ALIGN (src) < MIPS_MIN_MOVE_MEM_ALIGN - || MEM_ALIGN (dest) < MIPS_MIN_MOVE_MEM_ALIGN)) + && !(INTVAL (alignment) * BITS_PER_UNIT >= MIPS_MIN_MOVE_MEM_ALIGN + || ISA_HAS_COPY)) return false; if (mips_movmem_limit == -1 || INTVAL (length) < mips_movmem_limit) { - if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER) + if (ISA_HAS_COPY) + return mips16_expand_copy (dest, src, length, alignment); + else if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER) { - mips_block_move_straight (dest, src, INTVAL (length)); + mips_block_move_straight (dest, src, INTVAL (length), + INTVAL (alignment)); return true; } else if (optimize) { mips_block_move_loop (dest, src, INTVAL (length), + INTVAL (alignment), MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); return true; } @@ -12287,6 +12469,8 @@ mips_compute_frame_info (void) struct mips_frame_info *frame; HOST_WIDE_INT offset, size; unsigned int regno, i; + int global_reg_used; + int local_reg_used; /* Skip re-computing the frame info after reload completed. */ if (reload_completed) @@ -12401,10 +12585,61 @@ mips_compute_frame_info (void) frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); } + /* The SAVE and RESTORE instructions have two ranges of registers: + $a3-$a0 and $s2-$s8. If we save one register in the range, we must + save all later registers too. This can cause problems if the user has + placed a global value into a register that falls into one of these + ranges and the function uses a callee saved register that also in the + same range. In this case the global value could be accidently saved + and restored on function entry and exit which means any changes made to + its value in the function will be lost. + + The code below checks for this case, and if it is found it turns off + the use of the SAVE/RESTORE instruction in this function. + + This approach is not optimal because it should really just check that + the number of the register used for the global value occurs before + one of the callee saved registers. However as the use of forcing global + values into a register is small it is fine to use the unoptimal version + of the code for the moment. */ + cfun->machine->safe_to_use_save_restore = true; + + global_reg_used = 0; + local_reg_used = 0; + + for (i = 0 ; i < ARRAY_SIZE (mips16e_s2_s8_regs) ; i++) + { + regno = mips16e_s2_s8_regs[i]; + if (global_regs[regno]) + global_reg_used = 1; + + if (BITSET_P (frame->mask, regno)) + local_reg_used = 1; + } + + if (global_reg_used && local_reg_used) + cfun->machine->safe_to_use_save_restore = false; + + global_reg_used = 0; + local_reg_used = 0; + + for (i = 0 ; i < ARRAY_SIZE (mips16e_a0_a3_regs) ; i++) + { + regno = mips16e_a0_a3_regs[i]; + if (global_regs[regno]) + global_reg_used = 1; + + if (BITSET_P (frame->mask, regno)) + local_reg_used = 1; + } + + if (global_reg_used && local_reg_used) + cfun->machine->safe_to_use_save_restore = false; + /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers: $a3-$a0 and $s2-$s8. If we save one register in the range, we must save all later registers too. */ - if (GENERATE_MIPS16E_SAVE_RESTORE) + if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->safe_to_use_save_restore) { mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs, ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp); @@ -13495,7 +13730,9 @@ mips_expand_prologue (void) HOST_WIDE_INT step1; step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP); - if (GENERATE_MIPS16E_SAVE_RESTORE) + if (GENERATE_MIPS16E_SAVE_RESTORE + && !cfun->machine->interrupt_handler_p + && cfun->machine->safe_to_use_save_restore) { HOST_WIDE_INT offset; unsigned int mask, regno; @@ -13945,7 +14182,9 @@ mips_expand_epilogue (bool sibcall_p) emit_insn (gen_blockage ()); mips_epilogue.cfa_restore_sp_offset = step2; - if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0) + if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0 + && !cfun->machine->interrupt_handler_p + && cfun->machine->safe_to_use_save_restore) { unsigned int regno, mask; HOST_WIDE_INT offset; @@ -21555,6 +21794,32 @@ mips_option_override (void) "-mcompact-branches=never"); } + /* Enable the use of interAptiv MIPS32 SAVE/RESTORE instructions. */ + if (TARGET_USE_SAVE_RESTORE == -1) + { + if (TARGET_INTERAPTIV_MR2) + TARGET_USE_SAVE_RESTORE = 1; + else + TARGET_USE_SAVE_RESTORE = 0; + } + else if (TARGET_USE_SAVE_RESTORE + && !TARGET_INTERAPTIV_MR2) + error ("unsupported combination: %qs %s", + mips_arch_info->name, "-muse-save-restore"); + + /* Enable the use of interAptiv MIPS16 COPYW/UCOPYW instructions. */ + if (TARGET_USE_COPYW_UCOPYW == -1) + { + if (TARGET_INTERAPTIV_MR2) + TARGET_USE_COPYW_UCOPYW = 1; + else + TARGET_USE_COPYW_UCOPYW = 0; + } + else if (TARGET_USE_COPYW_UCOPYW + && !TARGET_INTERAPTIV_MR2) + error ("unsupported combination: %qs %s", + mips_arch_info->name, "-muse-copyw_ucopyw"); + /* Require explicit relocs for MIPS R6 onwards. This enables simplification of the compact branch and jump support through the backend. */ if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6) @@ -24221,7 +24486,6 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) return false; } - /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 70a7b2032dc..b727074bf53 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -265,7 +265,11 @@ struct mips_cpu_info { /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= MIPS_ISA_MIPS32) /* Generate mips16e register save/restore sequences. */ -#define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) +#define GENERATE_MIPS16E_SAVE_RESTORE ((GENERATE_MIPS16E \ + || (TARGET_USE_SAVE_RESTORE \ + && !TARGET_MICROMIPS \ + && TARGET_SOFT_FLOAT)) \ + && mips_abi == ABI_32) /* True if we're generating a form of MIPS16 code in which general text loads are allowed. */ @@ -319,6 +323,7 @@ struct mips_cpu_info { || mips_arch == PROCESSOR_SB1A) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) #define TARGET_XLP (mips_arch == PROCESSOR_XLP) +#define TARGET_INTERAPTIV_MR2 (mips_arch == PROCESSOR_INTERAPTIV_MR2) /* Scheduling target defines. */ #define TUNE_20KC (mips_tune == PROCESSOR_20KC) @@ -431,6 +436,8 @@ struct mips_cpu_info { for (p = macro; *p != 0; p++) \ if (*p == '+') \ *p = 'P'; \ + else if (*p == '-') \ + *p = '_'; \ else \ *p = TOUPPER (*p); \ \ @@ -844,7 +851,7 @@ struct mips_cpu_info { %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ |march=34k*|march=74k*|march=m14k*|march=1004k* \ |march=interaptiv: -mips32r2} \ - %{march=mips32r3: -mips32r3} \ + %{march=mips32r3|march=interaptiv-mr2: -mips32r3} \ %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \ %{march=mips32r6|march=m6201: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ @@ -963,10 +970,12 @@ struct mips_cpu_info { #define MIPS_ASE_DSP_SPEC \ "%{!mno-dsp: \ %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \ - |march=interaptiv: -mdsp} \ + |march=interaptiv*: -mdsp} \ %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" \ "%{!mforbidden-slots: \ - %{mips32r6|mips64r6:%{mmicromips:-mno-forbidden-slots}}}" + %{mips32r6|mips64r6:%{mmicromips:-mno-forbidden-slots}}}" \ + "%{!mno-mips16e2: \ + %{march=interaptiv-mr2: -mmips16e2}}" #define MIPS_ASE_LOONGSON_MMI_SPEC \ "%{!mno-loongson-mmi: \ @@ -1334,6 +1343,10 @@ struct mips_cpu_info { #define ISA_HAS_MIPS16E2 (TARGET_MIPS16 && TARGET_MIPS16E2 \ && !TARGET_64BIT) +/* The interAptiv MR2 COPYW/UCOPYW instructions are available. */ +#define ISA_HAS_COPY (TARGET_MIPS16 && TARGET_INTERAPTIV_MR2 \ + && TARGET_USE_COPYW_UCOPYW) + /* True if the result of a load is not available to the next instruction. A nop will then be needed between instructions like "lw $4,..." and "addiu $4,$4,1". */ @@ -1501,6 +1514,7 @@ struct mips_cpu_info { %{mtune=*}" \ FP_ASM_SPEC "\ %{mmips16e2} \ +%{mmips16-copy:-mmips16cp} \ %(subtarget_asm_spec)" /* Extra switches sometimes passed to the linker. */ @@ -2733,7 +2747,6 @@ typedef struct mips_args { do not truncate the shift amount at all. */ #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI) - /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ @@ -3143,7 +3156,9 @@ while (0) /* The maximum number of bytes that can be copied by one iteration of a cpymemsi loop; see mips_block_move_loop. */ #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \ - (UNITS_PER_WORD * 4) + (ISA_HAS_COPY \ + ? UNITS_PER_WORD * 4 * 4 \ + : UNITS_PER_WORD * 4) /* The maximum number of bytes that can be copied by a straight-line implementation of cpymemsi; see mips_block_move_straight. We want @@ -3174,7 +3189,9 @@ while (0) #define MOVE_RATIO(speed) \ (HAVE_cpymemsi \ - ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ + ? (ISA_HAS_COPY \ + ? MIPS_MAX_MOVE_BYTES_STRAIGHT / 4 / MOVE_MAX \ + : MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX) \ : MIPS_CALL_RATIO / 2) /* For CLEAR_RATIO, when optimizing for size, give a better estimate @@ -3435,6 +3452,10 @@ struct GTY(()) machine_function { /* True if the function should generate hazard barrier return. */ bool use_hazard_barrier_return_p; + + /* True if we are safe to use SAVE/RESTORE instruction in the + prologue/epilogue. */ + bool safe_to_use_save_restore; }; #endif diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index b1e55428682..21f31a5595a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -35,6 +35,7 @@ 74kf2_1 74kf1_1 74kf3_2 + interaptiv_mr2 loongson_2e loongson_2f gs464 @@ -4332,7 +4333,7 @@ (sign_extract:GPR (match_operand:BLK 1 "memory_operand") (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand")))] - "ISA_HAS_LWL_LWR" + "ISA_HAS_LWL_LWR || ISA_HAS_MIPS16E2" { if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], INTVAL (operands[2]), @@ -4369,7 +4370,7 @@ (zero_extract:GPR (match_operand:BLK 1 "memory_operand") (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand")))] - "ISA_HAS_LWL_LWR" + "ISA_HAS_LWL_LWR || ISA_HAS_MIPS16E2" { if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], INTVAL (operands[2]), @@ -4445,7 +4446,7 @@ (match_operand 1 "const_int_operand") (match_operand 2 "const_int_operand")) (match_operand:GPR 3 "reg_or_0_operand"))] - "ISA_HAS_LWL_LWR" + "ISA_HAS_LWL_LWR || ISA_HAS_MIPS16E2" { if (mips_expand_ins_as_unaligned_store (operands[0], operands[3], INTVAL (operands[1]), @@ -4891,7 +4892,7 @@ (define_insn "*movdi_32bit_mips16" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") - (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))] + (match_operand:DI 1 "move_operand" "d,d,y,i,N,m,d,*x"))] "!TARGET_64BIT && TARGET_MIPS16 && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" @@ -4919,6 +4920,74 @@ [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") (set_attr "mode" "DI")]) +;; Operand 0 is the register containing the destination address +;; Operand 1 is the register containing the source address +;; Operand 2 is a byte offset to use for both the source and dest addresses +;; Operand 3 is the number of words to copy (1,2,3, or 4) +;; Operand 4 is a constant integer value for the known alignment. + +(define_expand "mips16_copy" + [(parallel + [(set (match_operand 0 "" "") + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (use (match_operand 3 "" "")) + (use (match_operand 4 "" "")) + (clobber (reg:SI 12)) + (clobber (reg:SI 13)) + (clobber (reg:SI 14)) + (clobber (reg:SI 15))])] + "ISA_HAS_COPY" + { + /* Using a COPYW dst,src,*,1 instruction causes the core to stall + so we can not use mips16_copy in this case. */ + gcc_assert (!(INTVAL (operands[3]) == 1 && INTVAL (operands[4]) >= 4)); + }) + +(define_insn "" + [(set (mem:BLK (match_operand:SI 0 "register_operand" "d")) + (mem:BLK (match_operand:SI 1 "register_operand" "d"))) + (use (match_operand:SI 2 "const_int_operand")) + (use (match_operand:SI 3 "const_int_operand")) + (use (match_operand:SI 4 "const_int_operand")) + (clobber (reg:SI 12)) + (clobber (reg:SI 13)) + (clobber (reg:SI 14)) + (clobber (reg:SI 15))] + "ISA_HAS_COPY" + { + if (INTVAL (operands[4]) < 4) + return "ucopyw\t%0,%1,%2,%3"; + else + return "copyw\t%0,%1,%2,%3"; + } + [(set_attr "move_type" "store") + (set_attr "mode" "SI") + (set_attr "extended_mips16" "yes")]) + +(define_insn "mips16_copy_ofs" + [(set (mem:BLK (plus:SI (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 2 "const_int_operand"))) + (mem:BLK (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_dup 2)))) + (use (match_dup 2)) + (use (match_operand:SI 3 "const_int_operand")) + (use (match_operand:SI 4 "const_int_operand")) + (clobber (reg:SI 12)) + (clobber (reg:SI 13)) + (clobber (reg:SI 14)) + (clobber (reg:SI 15))] + "ISA_HAS_COPY" + { + if (INTVAL (operands[4]) < 4) + return "ucopyw\t%0,%1,%2,%3"; + else + return "copyw\t%0,%1,%2,%3"; + } + [(set_attr "move_type" "store") + (set_attr "mode" "SI") + (set_attr "extended_mips16" "yes")]) + ;; On the mips16, we can split ld $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. @@ -5426,7 +5495,11 @@ (define_split [(set (match_operand 0 "d_operand") (match_operand 1 "const_int_operand"))] - "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" + "TARGET_MIPS16 && reload_completed + && (ISA_HAS_MIPS16E2 + ? SMALL_OPERAND_UNSIGNED (-INTVAL (operands[1])) + && INTVAL (operands[1]) != 0 + : INTVAL (operands[1]) < 0)" [(set (match_dup 2) (match_dup 3)) (set (match_dup 2) @@ -5842,12 +5915,12 @@ (match_operand:BLK 1 "general_operand")) (use (match_operand:SI 2 "")) (use (match_operand:SI 3 "const_int_operand"))])] - "!TARGET_MIPS16 && !TARGET_MEMCPY" + "(!TARGET_MIPS16 || ISA_HAS_COPY) && !TARGET_MEMCPY" { - if (mips_expand_block_move (operands[0], operands[1], operands[2])) + if (mips_expand_block_move (operands[0], operands[1], + operands[2], operands[3])) DONE; - else - FAIL; + FAIL; }) ;; @@ -7779,7 +7852,8 @@ && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)" { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); } [(set_attr "type" "arith") - (set_attr "extended_mips16" "yes")]) + (set_attr "extended_mips16" "yes") + (set_attr "can_delay" "no")]) ;; Thread-Local Storage diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index a4b93de924d..c5a3addbc55 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -559,3 +559,9 @@ mfunc-opt-list=FILE Use to specify per function optimizations. mblockmov-limit= Target RejectNegative Undocumented Joined UInteger Var(mips_movmem_limit) Init(-1) + +muse-save-restore +Target Undocumented Var(TARGET_USE_SAVE_RESTORE) Init(-1) + +muse-copyw-ucopyw +Target Undocumented Var(TARGET_USE_COPYW_UCOPYW) Init(-1) diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index a64900d25ef..31cc57af435 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -578,7 +578,7 @@ (and (match_code "ne") (not (match_test "TARGET_MIPS16"))))) (define_predicate "small_data_pattern" - (and (match_code "set,parallel,unspec,unspec_volatile,prefetch") + (and (match_code "set,parallel,prefetch") (match_test "mips_small_data_pattern_p (op)"))) (define_predicate "mem_noofs_operand" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cd84cafafd5..d607f8e430c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -28195,7 +28195,7 @@ The processor names are: @samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2}, @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{i6400}, @samp{i6500}, -@samp{interaptiv}, +@samp{interaptiv}, @samp{interaptiv-mr2}, @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{gs464}, @samp{gs464e}, @samp{gs264e}, @samp{m4k}, diff --git a/gcc/testsuite/gcc.target/mips/iamr2.c b/gcc/testsuite/gcc.target/mips/iamr2.c new file mode 100644 index 00000000000..40e425ddcd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/iamr2.c @@ -0,0 +1,51 @@ +/* { dg-options "-march=interaptiv-mr2 -mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2 -mno-memcpy" } */ + +/* Test UCOPYW. */ + +/* { dg-final { scan-assembler "test01:.*\tucopyw\t.*\tucopyw\t.*test01\n" } } */ +/* { dg-final { scan-assembler-times "\tucopyw\t" 2 } } */ +struct node01 +{ + int i; + int j; + int k; + int l; + int a; + int b; + int c; + int d; +} __attribute__ ((packed)); + +struct node01 dst01; +struct node01 src01; + +void +test01 (void) +{ + dst01 = src01; +} + +/* Test COPYW. */ + +/* { dg-final { scan-assembler "test02:.*\tcopyw\t.*\tcopyw\t.*test02\n" } } */ +/* { dg-final { scan-assembler-times "\tcopyw\t" 2 } } */ +struct node02 +{ + int i; + int j; + int k; + int l; + int a; + int b; + int c; + int d; +}; + +struct node02 dst02; +struct node02 src02; + +void +test02 (void) +{ + dst02 = src02; +} diff --git a/gcc/testsuite/gcc.target/mips/memcpy-3.c b/gcc/testsuite/gcc.target/mips/memcpy-3.c new file mode 100644 index 00000000000..cf1b073c9ae --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/memcpy-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "isa=interaptiv-mr2 -mno-memcpy (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "" } { "" } } */ + +char * ref = "123456789012"; + +__attribute__((mips16)) +void +f1 (int *p) +{ + __builtin_memcpy (p, ref, 12); +} + +/* { dg-final { scan-assembler "\tucopyw\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/memcpy-4.c b/gcc/testsuite/gcc.target/mips/memcpy-4.c new file mode 100644 index 00000000000..fc4f3761c9a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/memcpy-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "isa=interaptiv-mr2 -mno-memcpy -mno-use-copyw-ucopyw (-mips16)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "" } { "" } } */ + +char * ref = "123456789012"; + +__attribute__((mips16)) +void +f1 (int *p) +{ + __builtin_memcpy (p, ref, 12); +} + +/* { dg-final { scan-assembler-not "\tucopyw\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index b0825ca4339..3907fe2a778 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -289,6 +289,7 @@ foreach option { long-calls lxc1-sxc1 madd4 + memcpy paired-single plt shared @@ -303,6 +304,7 @@ foreach option { loongson-ext loongson-ext2 mips16e2 + use-copyw-ucopyw } { lappend mips_option_groups $option "-m(no-|)$option" } @@ -1135,6 +1137,10 @@ proc mips-dg-options { args } { if { ![regexp {^-march=p5600} $arch] } { set arch "-march=p5600" } + } elseif { [string equal $spec "isa=interaptiv-mr2"] } { + if { ![regexp {^-march=interaptiv-mr2} $arch] } { + set arch "-march=interaptiv-mr2" + } } else { if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)$} \ $spec dummy prop relation value nocpus] } { diff --git a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c index 2516b663ca1..103dd82caa1 100644 --- a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c +++ b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c @@ -1,4 +1,5 @@ /* { dg-options "-mr10k-cache-barrier=store -G8 -w" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ /* Test that out-of-range stores to components of static objects are protected by a cache barrier. */ diff --git a/gcc/testsuite/gcc.target/mips/stack-1.c b/gcc/testsuite/gcc.target/mips/stack-1.c index 5f25c21a0a9..227e6c9201b 100644 --- a/gcc/testsuite/gcc.target/mips/stack-1.c +++ b/gcc/testsuite/gcc.target/mips/stack-1.c @@ -1,3 +1,4 @@ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ /* { dg-final { scan-assembler "\td?addiu\t(\\\$sp,)?\\\$sp,\[1-9\]" } } */ /* { dg-final { scan-assembler "\tlw\t" } } */ /* { dg-final { scan-assembler-not "\td?addiu\t(\\\$sp,)?\\\$sp,\[1-9\].*\tlw\t" } } */ From patchwork Fri Jan 31 17:13:29 2025 Content-Type: text/plain; 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Secondly, create a MIPS specific version in the gcc.target/mips. This will only execute for a MIPS ISA less than R6. Cherry-picked c8b051cdbb1d5b166293513b0360d3d67cf31eb9 from https://github.com/MIPS/gcc Signed-off-by: Andrew Bennett Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.dg/memcpy-4.c | 7 +------ gcc/testsuite/gcc.target/mips/memcpy-2.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/memcpy-2.c diff --git a/gcc/testsuite/gcc.dg/memcpy-4.c b/gcc/testsuite/gcc.dg/memcpy-4.c index 4c726f0ad74..b17b369c5c6 100644 --- a/gcc/testsuite/gcc.dg/memcpy-4.c +++ b/gcc/testsuite/gcc.dg/memcpy-4.c @@ -1,13 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-rtl-expand" } */ +/* { dg-options "-O2" } */ -#ifdef __mips -__attribute__((nomips16)) -#endif void f1 (char *p) { __builtin_memcpy (p, "12345", 5); } - -/* { dg-final { scan-rtl-dump "mem/u.*mem/u" "expand" { target mips*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/mips/memcpy-2.c b/gcc/testsuite/gcc.target/mips/memcpy-2.c new file mode 100644 index 00000000000..df0cd18c2b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/memcpy-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "isa_rev<=5 -fdump-rtl-expand" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-Os" } { "" } } */ + +__attribute__((nomips16)) +void +f1 (char *p) +{ + __builtin_memcpy (p, "12345", 5); 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Fri, 31 Jan 2025 17:13:30 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 22/61] Add -minline-intermix to ignore mips16/nomips16 Thread-Topic: [PATCH 22/61] Add -minline-intermix to ignore mips16/nomips16 Thread-Index: AQHbdANzD8F15wjef0Ouu4QDbPsiAA== Date: Fri, 31 Jan 2025 17:13:30 +0000 Message-ID: <20250131171232.1018281-24-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: 5d5c6aed-f39e-4114-0aff-08dd421a95d0 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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The format of this attribute is __attribute__((inline_intermix(yes|no))). gcc/ * doc/extend.texi: Document inline_intermix. * config/mips/mips.cc (mips_attribute_table): Add inline_intermix. (mips_handle_inline_intermix_attr): New function. (mips_get_inline_intermix_attr): Likewise. (mips_can_inline_p): Use mips_get_inline_intermix_attr. gcc/testsuite/ * gcc.target/mips/mips.exp: Add -m[no-]inline-intermix. * gcc.target/mips/inline-intermix-1.c: New file. * gcc.target/mips/inline-intermix-2.c: Likewise. * gcc.target/mips/inline-intermix-3.c: Likewise. * gcc.target/mips/inline-intermix-4.c: Likewise. Cherry-picked 02c76fc61198186af09fd9c4c0ef7352ab6511ad and ae484b9431e5bd407e09b66392a1882b6878e4de from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 72 ++++++++++++++++++- gcc/config/mips/mips.opt | 4 ++ gcc/doc/extend.texi | 17 +++++ gcc/doc/invoke.texi | 12 ++++ .../gcc.target/mips/inline-intermix-1.c | 13 ++++ .../gcc.target/mips/inline-intermix-2.c | 13 ++++ .../gcc.target/mips/inline-intermix-3.c | 13 ++++ .../gcc.target/mips/inline-intermix-4.c | 13 ++++ gcc/testsuite/gcc.target/mips/mips.exp | 1 + 9 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/mips/inline-intermix-1.c create mode 100644 gcc/testsuite/gcc.target/mips/inline-intermix-2.c create mode 100644 gcc/testsuite/gcc.target/mips/inline-intermix-3.c create mode 100644 gcc/testsuite/gcc.target/mips/inline-intermix-4.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 9808fda286c..e8ed002dfed 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -607,6 +607,7 @@ const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { }; static tree mips_handle_code_readable_attr (tree *, tree, tree, int, bool *); +static tree mips_handle_inline_intermix_attr (tree *, tree, tree, int, bool *); static tree mips_handle_interrupt_attr (tree *, tree, tree, int, bool *); static tree mips_handle_use_shadow_register_set_attr (tree *, tree, tree, int, bool *); @@ -627,6 +628,8 @@ TARGET_GNU_ATTRIBUTES (mips_attribute_table, { { "nomips16", 0, 0, true, false, false, false, NULL, NULL }, { "micromips", 0, 0, true, false, false, false, NULL, NULL }, { "nomicromips", 0, 0, true, false, false, false, NULL, NULL }, + { "inline_intermix", 0, 1, true, false, false, false, + mips_handle_inline_intermix_attr, NULL }, { "nocompression", 0, 0, true, false, false, false, NULL, NULL }, { "code_readable", 0, 1, true, false, false, false, mips_handle_code_readable_attr, NULL }, @@ -770,6 +773,7 @@ static const struct attr_desc mips_func_opt_list_strings[] = { {"hot", 0, FOL_ARG_NONE, 1 << FOLC_COLD }, {"cold", 0, FOL_ARG_NONE, 1 << FOLC_HOT }, {"code_readable", 0, FOL_ARG_STRING, 0 }, + {"inline_intermix", 0, FOL_ARG_STRING, 0 }, {"alias", 0, FOL_ARG_STRING, 0 }, {"aligned", 0, FOL_ARG_SINGLE_NUM, 0}, {"alloc_size", 0, FOL_ARG_NUM_ONE_OR_TWO, 0}, @@ -1917,6 +1921,71 @@ mips_use_debug_exception_return_p (tree type) TYPE_ATTRIBUTES (type)) != NULL; } +/* Verify the arguments to an inline_intermix attribute. */ + +static tree +mips_handle_inline_intermix_attr (tree *node ATTRIBUTE_UNUSED, tree name, + tree args, int flags ATTRIBUTE_UNUSED, + bool *no_add_attrs) +{ + if (!is_attribute_p ("inline_intermix", name) || args == NULL) + return NULL_TREE; + + if (TREE_CODE (TREE_VALUE (args)) != STRING_CST) + { + warning (OPT_Wattributes, + "%qE attribute requires a string argument", name); + *no_add_attrs = true; + } + else if (strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "no") != 0 + && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "yes") != 0) + { + warning (OPT_Wattributes, + "argument to %qE attribute is neither no nor yes", name); + *no_add_attrs = true; + } + + return NULL_TREE; +} + +/* Determine the inline_intermix setting for a function if it has one. + When inline_intermix is used without an argument it is the same as + inline_intermix=yes. */ + +static bool +mips_get_inline_intermix_attr (tree decl) +{ + tree attr; + + if (decl == NULL) + return TARGET_INLINE_INTERMIX; + + attr = lookup_attribute ("inline_intermix", DECL_ATTRIBUTES (decl)); + + if (attr != NULL) + { + if (TREE_VALUE (attr) != NULL_TREE) + { + const char * str; + + str = TREE_STRING_POINTER (TREE_VALUE (TREE_VALUE (attr))); + if (strcmp (str, "no") == 0) + return false; + else if (strcmp (str, "yes") == 0) + return true; + + /* mips_handle_inline_intermix_attr will have verified the + arguments are correct before adding the attribute. */ + gcc_unreachable (); + } + + /* No argument is the same as inline_intermix=true like the + command line option -minline-intermix. */ + return true; + } + + return TARGET_INLINE_INTERMIX; +} /* Verify the arguments to a code_readable attribute. */ @@ -2294,7 +2363,8 @@ mips_merge_decl_attributes (tree olddecl, tree newdecl) static bool mips_can_inline_p (tree caller, tree callee) { - if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller)) + if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller) + && !mips_get_inline_intermix_attr (callee)) return false; return default_target_can_inline_p (caller, callee); } diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index c5a3addbc55..222fdbfaf96 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -565,3 +565,7 @@ Target Undocumented Var(TARGET_USE_SAVE_RESTORE) Init(-1) muse-copyw-ucopyw Target Undocumented Var(TARGET_USE_COPYW_UCOPYW) Init(-1) + +minline-intermix +Target Var(TARGET_INLINE_INTERMIX) +Allow inlining even if the compression flags differ between caller and callee. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index c566474074d..76ebdf97a98 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6005,6 +6005,23 @@ This function attribute instructs the compiler to generate a hazard barrier return that clears all execution and instruction hazards while returning, instead of generating a normal return instruction. +@item inline_intermix +@cindex @code{inline_intermix} function attribute, MIPS +On MIPS targets, you can use the @code{inline_intermix} attribute to override +the default inlining rule that prevents functions with different ISAs being +inlined. This can be helpful when the ISA selection is made for performance +or code density reasons instead of fundamental dependency on a specific ISA. +The attribute takes a single optional argument: + +@table @samp +@item no +The function must not be inlined into a function with a different ISA. +@item yes +The function can be inlined into a function with a different ISA. +@end table + +If there is no argument supplied, the default of @code{"yes"} applies. + @item code_readable @cindex @code{code_readable} function attribute, MIPS For MIPS targets that support PC-relative addressing modes, this attribute diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d607f8e430c..3560a7920a7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1125,6 +1125,7 @@ Objective-C and Objective-C++ Dialects}. -mips16 -mno-mips16 -mflip-mips16 -minterlink-compressed -mno-interlink-compressed -minterlink-mips16 -mno-interlink-mips16 +-minline-intermix -mno-inline-intermix -mabi=@var{abi} -mabicalls -mno-abicalls -mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot -mgp32 -mgp64 -mfp32 -mfpxx -mfp64 -mhard-float -msoft-float @@ -28363,6 +28364,17 @@ Aliases of @option{-minterlink-compressed} and @option{-mno-interlink-compressed}. These options predate the microMIPS ASE and are retained for backwards compatibility. +@opindex minline-intermix +@opindex mno-inline-intermix +@item -minline-intermix +@itemx -mno-inline-intermix +Enable inlining of functions which have opposing mips16/nomips16 attributes. +This is useful when using the mips16 attribute to balance code size and +performance so that a function will be compressed when not inlined or +vice-versa. When using this option it is necessary to protect functions +that cannot be compiled as MIPS16 with a noinline attribute to ensure +they are not inlined into a MIPS16 function. + @opindex mabi @item -mabi=32 @itemx -mabi=o64 diff --git a/gcc/testsuite/gcc.target/mips/inline-intermix-1.c b/gcc/testsuite/gcc.target/mips/inline-intermix-1.c new file mode 100644 index 00000000000..f4e0c7ffa1f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-intermix-1.c @@ -0,0 +1,13 @@ +/* { dg-options "-mips16 -mabi=32" } */ + +__attribute__((nomips16, always_inline)) +inline int foo() /* { dg-error "target specific option mismatch" } */ +{ + return 1; +} + +int bar() +{ + return foo(); +} + diff --git a/gcc/testsuite/gcc.target/mips/inline-intermix-2.c b/gcc/testsuite/gcc.target/mips/inline-intermix-2.c new file mode 100644 index 00000000000..c0b0102941d --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-intermix-2.c @@ -0,0 +1,13 @@ +/* { dg-options "-mips16 -mabi=32" } */ + +__attribute__((nomips16, always_inline, inline_intermix)) +inline int foo() +{ + return 1; +} + +int bar() +{ + return foo(); +} + diff --git a/gcc/testsuite/gcc.target/mips/inline-intermix-3.c b/gcc/testsuite/gcc.target/mips/inline-intermix-3.c new file mode 100644 index 00000000000..bc947315fb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-intermix-3.c @@ -0,0 +1,13 @@ +/* { dg-options "-mips16 -mabi=32 -minline-intermix" } */ + +__attribute__((nomips16, always_inline)) +inline int foo() +{ + return 1; +} + +int bar() +{ + return foo(); +} + diff --git a/gcc/testsuite/gcc.target/mips/inline-intermix-4.c b/gcc/testsuite/gcc.target/mips/inline-intermix-4.c new file mode 100644 index 00000000000..8c58284b477 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-intermix-4.c @@ -0,0 +1,13 @@ +/* { dg-options "-mips16 -mabi=32 -minline-intermix" } */ + +__attribute__((nomips16, always_inline, inline_intermix("no"))) +inline int foo() /* { dg-error "target specific option mismatch" } */ +{ + return 1; +} + +int bar() +{ + return foo(); +} + diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 3907fe2a778..dade793b306 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -285,6 +285,7 @@ foreach option { fix-r10000 fix-vr4130 gpopt + inline-intermix local-sdata long-calls lxc1-sxc1 From patchwork Fri Jan 31 17:13:31 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:13:31 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , mfortune , Robert Suchanek , Steve Ellcey , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 23/61] Add offset shrinking pass (-mshrink-offsets) Thread-Topic: [PATCH 23/61] Add offset shrinking pass (-mshrink-offsets) Thread-Index: AQHbdANz78LltqcwI0yYIA3KRqmNmQ== Date: Fri, 31 Jan 2025 17:13:31 +0000 Message-ID: <20250131171232.1018281-25-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: ceadf413-57aa-4db4-70e6-08dd421a9686 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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This approach is slightly diverged from the original concept. It tries to adjust the base pointer to a common value and keep the costing lower than original by trying to find the best common value to trigger more 16-bit instructions. Although this works, the magic includes zero adjustments when no best common value is found. This will need more digging as to why the code size is better. Some initial cases show indexed loads/stores prevented but replaced with normal loads/stores with offsets close to zero, hence, more potential for 16-bit load/store. gcc/ChangeLog: * config/mips/mips.cc (offset_cmp): New function. (get_size_cost): Likewise. (get_total_cost): Likewise. (calculate_offsets_cost): Likewise. (mark_mem): Likewise. (dump_modified_offsets): Likewise. (get_best_offset): Likewise. (adjust_base_offset): Likewise. (make_pass_shrink_mips_offsets): (class pass_shrink_mips_offsets): New class. (pass_shrink_mips_offsets::execute): New method. (mips_option_override): Enable offset shrinking pass. * config/mips/mips.opt (mshrink-offsets): New option. * doc/invoke.texi: Document the new option. Cherry-picked 4c4fc03fdcad57d052a29e163ca961ae7cf913ed from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek Signed-off-by: Steve Ellcey Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 379 +++++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips.opt | 4 + gcc/doc/invoke.texi | 11 ++ 3 files changed, 394 insertions(+) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index e8ed002dfed..56e0d4ba021 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -68,6 +68,8 @@ along with GCC; see the file COPYING3. If not see #include "rtl-iter.h" #include "flags.h" #include "opts.h" +#include "tm-constrs.h" +#include "print-rtl.h" /* This file should be included last. */ #include "target-def.h" @@ -21583,6 +21585,369 @@ mips_set_tune (const struct mips_cpu_info *info) } } +typedef struct mem_offset_def +{ + HOST_WIDE_INT offset; + HOST_WIDE_INT modified_offset; + basic_block bb; + machine_mode mode; + rtx insn; +} mem_offset_def_t; + +typedef struct mem_offset_def *mem_offset_info; + +typedef struct offset_entry : free_ptr_hash +{ + /* We hash by. */ + int base_regno; + + /* Store. */ + int orig_cost; + int best_cost; + HOST_WIDE_INT best_offset; + vec offsets; + + /* hash table support. */ + static inline hashval_t hash (const offset_entry *v) + { return (hashval_t) v->base_regno; }; + static bool equal (const offset_entry *v, const offset_entry *c) + { return (v->base_regno == c->base_regno); }; + static void remove (offset_entry *) + {}; +} offset_entry_t; + +static int +offset_cmp (const void *x, const void *y) +{ + const mem_offset_info p1 = *((const mem_offset_info *) x); + const mem_offset_info p2 = *((const mem_offset_info *) y); + if (p1->offset < p2->offset) + return -1; + if (p1->offset > p2->offset) + return 1; + return 0; +} + +/* This is only an approximate optimistic size cost as we cannot decide + whether we use 16-bit or 32-bit before register allocation. */ +static int +get_size_cost (HOST_WIDE_INT offset, machine_mode mode) +{ + /* If the offset does not fit, it is likely to be split. */ + switch (mode) + { + case E_QImode: + if (mips_unsigned_immediate_p (offset, 5, 0)) + return 2; + else if (SMALL_OPERAND (offset)) + return 4; + else + return 8; + case E_HImode: + if (mips_unsigned_immediate_p (offset, 5, 1)) + return 2; + else if (SMALL_OPERAND (offset)) + return 4; + else + return 8; + case E_SImode: + if (mips_unsigned_immediate_p (offset, 5, 2)) + return 2; + else if (SMALL_OPERAND (offset)) + return 4; + else + return 8; + default: + return 4; + } +} + +static int +get_total_cost (offset_entry *info, HOST_WIDE_INT mod_offset) +{ + int i; + mem_offset_info m; + HOST_WIDE_INT cost; + + cost = 0; + for (i = 0; info->offsets.iterate (i, &m); i++) + cost += get_size_cost (m->offset - mod_offset, m->mode); + return cost; +} + +int +calculate_offsets_cost (offset_entry **slot, + void *data ATTRIBUTE_UNUSED) +{ + int i; + mem_offset_info m; + offset_entry *info = *slot; + HOST_WIDE_INT prev_offset; + + info->offsets.qsort (offset_cmp); + + info->best_cost = info->orig_cost = get_total_cost (info, 0); + prev_offset = 0; + for (i = 0; info->offsets.iterate (i, &m); i++) + { + /* The initial adjustment will cost us one ADD instruction. */ + int cur_cost = 4; + + if (m->offset == prev_offset) + continue; + + cur_cost += get_total_cost (info, m->offset); + + if (cur_cost < info->best_cost) + { + info->best_cost = cur_cost; + info->best_offset = m->offset; + + if (dump_file) + fprintf (dump_file, + "Potential savings of %d bytes by adding %ld to r%d\n", + info->orig_cost - info->best_cost, -info->best_offset, + info->base_regno); + } + prev_offset = m->offset; + } + + return 1; +} + +static void +mark_mem (rtx_insn *insn, rtx mem, basic_block bb, + hash_table * offset_table) +{ + rtx base; + HOST_WIDE_INT offset; + offset_entry **slot; + offset_entry *info; + offset_entry xinfo; + mem_offset_info oi; + + mips_split_plus (XEXP (mem, 0), &base, &offset); + if (REG_P (base)) + { + if (dump_file) + { + fprintf (dump_file, "Marking r%d in insn %d\n", REGNO (base), + INSN_UID (insn)); + dump_rtl_slim (dump_file, insn, NULL, 1, 0); + } + xinfo.base_regno = REGNO (base); + slot = offset_table->find_slot (&xinfo, INSERT); + info = *slot; + if (!info) + { + /* Make new entry. */ + *slot = info = XNEW (offset_entry_t); + info->base_regno = REGNO (base); + info->offsets = vNULL; + info->orig_cost = 0; + info->best_offset = 0; + } + oi = XNEW (mem_offset_def_t); + oi->offset = offset; + oi->modified_offset = 0; + oi->bb = bb; + oi->mode = GET_MODE (mem); + oi->insn = insn; + info->offsets.safe_push (oi); + } +} + +static void +dump_modified_offsets (hash_table * offset_table) +{ + offset_entry xinfo; + offset_entry *info; + mem_offset_info m; + int i, j, n; + n = max_reg_num (); + for (i = 0; i < n; i++) + { + if (i >= FIRST_PSEUDO_REGISTER) + { + xinfo.base_regno = i; + info = offset_table->find (&xinfo); + if (info) + { + fprintf (dump_file,"Offsets for r%d [",i); + for (j = 0; info->offsets.iterate (j, &m); j++) + fprintf (dump_file, "%ld(%ld)%s", + m->offset, info->best_offset, i == n ? "" : " "); + fprintf (dump_file, "] total_orig_cost=%d\n", info->orig_cost); + } + } + } +} + +static rtx +get_best_offset (rtx_insn *insn, rtx x, + hash_table * offset_table) +{ + rtx base; + HOST_WIDE_INT offset; + offset_entry xinfo; + offset_entry *info; + + if (MEM_P (x)) + x = XEXP (x, 0); + + mips_split_plus (x, &base, &offset); + + if (REG_P (base) + && (REGNO (base) >= FIRST_PSEUDO_REGISTER)) + { + xinfo.base_regno = REGNO (base); + info = offset_table->find (&xinfo); + + if (info + /* Normally we wouldn't allow checking for equal cost and a zero + offset adjustment. This is strange but this gives the best code + size in average case but here we go... */ + && info->best_cost <= info->orig_cost) + { + rtx new_reg, new_set; + machine_mode mode; + + if (dump_file) + fprintf (dump_file, + "Adjusting r%d in insn %d by %ld\n", + REGNO (base), INSN_UID (insn), info->best_offset); + mode = GET_MODE (base); + new_reg = gen_reg_rtx (mode); + new_set = gen_rtx_SET (new_reg, + gen_rtx_PLUS (mode, base, + GEN_INT (info->best_offset))); + emit_insn_before (new_set, insn); + return (gen_rtx_PLUS (mode, new_reg, + GEN_INT (offset - info->best_offset))); + } + } + + return NULL_RTX; +} + +static void +adjust_base_offset (rtx_insn *insn, hash_table * offset_table) +{ + rtx set, new_src, new_dest, new_rtx, *src, *dest; + set = single_set (insn); + + if (set) + { + src = &SET_SRC (set); + dest = &SET_DEST (set); + if (GET_CODE (*src) == ZERO_EXTEND) + src = &XEXP (*src, 0); + if (GET_CODE (*dest) == ZERO_EXTEND) + dest = &XEXP (*dest, 0); + } + + if (set && MEM_P (*dest) && INTEGRAL_MODE_P (GET_MODE (*dest))) + { + new_dest = get_best_offset (insn, *dest, offset_table); + if (new_dest) + { + new_rtx = simplify_replace_rtx (*dest, XEXP (*dest, 0), new_dest); + validate_change (insn, dest, new_rtx, 0); + } + } + + if (set && MEM_P (*src) && INTEGRAL_MODE_P (GET_MODE (*src))) + { + new_src = get_best_offset (insn, *src, offset_table); + if (new_src) + { + new_rtx = simplify_replace_rtx (*src, XEXP (*src, 0), new_src); + validate_change (insn, src, new_rtx, 0); + } + } +} + +namespace { + +const pass_data pass_data_shrink_mips_offsets = +{ + RTL_PASS, /* type */ + "shrink_offsets", /* name */ + OPTGROUP_NONE, /* optinfo_flags */ + TV_NONE, /* tv_id */ + PROP_cfglayout, /* properties_required */ + 0, /* properties_provided */ + 0, /* properties_destroyed */ + 0, /* todo_flags_start */ + TODO_df_finish /* todo_flags_finish */ +}; + +class pass_shrink_mips_offsets : public rtl_opt_pass +{ + public: + pass_shrink_mips_offsets (gcc::context *ctxt) + : rtl_opt_pass (pass_data_shrink_mips_offsets, ctxt) + {} + + /* opt_pass methods: */ + virtual bool gate (function *) + { + return TARGET_MIPS16 && TARGET_SHRINK_OFFSETS; + } + virtual unsigned int execute (function *); + }; // class pass_shrink_mips_offsets + +} // anon namespace + +unsigned int +pass_shrink_mips_offsets::execute (function *f ATTRIBUTE_UNUSED) +{ + hash_table *offset_table = new hash_table (10); + basic_block bb; + rtx_insn *insn; + rtx set; + + FOR_EACH_BB_FN (bb, cfun) + FOR_BB_INSNS (bb, insn) + { + set = single_set (insn); + if (set) + { + rtx src = SET_SRC (set); + rtx dest = SET_DEST (set); + + if (GET_CODE (src) == ZERO_EXTEND) + src = XEXP (src, 0); + if (GET_CODE (dest) == ZERO_EXTEND) + dest = XEXP (dest, 0); + + if (MEM_P (src)) + mark_mem (insn, src, bb, offset_table); + if (MEM_P (dest)) + mark_mem (insn, dest, bb, offset_table); + } + } + + offset_table->traverse (NULL); + + if (dump_file) + dump_modified_offsets (offset_table); + + FOR_EACH_BB_FN (bb, cfun) + FOR_BB_INSNS (bb, insn) + adjust_base_offset (insn, offset_table); + + delete offset_table; + + return 0; +} + +rtl_opt_pass * +make_pass_shrink_mips_offsets (gcc::context *ctxt) +{ + return new pass_shrink_mips_offsets (ctxt); +} + /* Implement TARGET_OPTION_OVERRIDE. */ static void @@ -21933,6 +22298,9 @@ mips_option_override (void) if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0) target_flags |= MASK_VR4130_ALIGN; + if (optimize_size && (target_flags_explicit & MASK_SHRINK_OFFSETS) == 0) + target_flags |= MASK_SHRINK_OFFSETS; + /* Prefer a call to memcpy over inline code when optimizing for size, though see MOVE_RATIO in mips.h. */ if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) @@ -22212,6 +22580,17 @@ mips_option_override (void) error ("Number for -msdata-num must be between 0 and 999"); mips_register_frame_header_opt (); + + new_pass = make_pass_shrink_mips_offsets (g); + /* May not be the right place for this, but..... */ + static struct register_pass_info shrink_mips_offsets_info = { + new_pass, /* pass */ + "cse1", /* reference_pass_name */ + 1, /* ref_pass_instance_number */ + PASS_POS_INSERT_BEFORE /* po_op */ + }; + + register_pass (&shrink_mips_offsets_info); } /* Swap the register information for registers I and I + 1, which diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 222fdbfaf96..fa6ecd988a6 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -481,6 +481,10 @@ mgrow-frame-downwards Target Var(TARGET_FRAME_GROWS_DOWNWARDS) Init(1) Undocumented Change the behaviour to grow the frame downwards. +mshrink-offsets +Target Mask(SHRINK_OFFSETS) +Shrink offsets in MIPS16 code to avoid extended loads and stores. + noasmopt Driver diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3560a7920a7..b2e11a7fd0d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1159,6 +1159,7 @@ Objective-C and Objective-C++ Dialects}. -muninit-const-in-rodata -mno-uninit-const-in-rodata -mcode-readable=@var{setting} -mdead-loads -mno-dead-loads +-mshrink-offsets -mno-shrink-offsets -msplit-addresses -mno-split-addresses -mexplicit-relocs -mno-explicit-relocs -mexplicit-relocs=@var{release} @@ -28941,6 +28942,16 @@ dependency stall if the result register is reused soon after the load. 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Fri, 31 Jan 2025 17:13:32 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Jaydeep Patil , Prachi Godbole , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 24/61] P5600: Option -msched-weight added Thread-Topic: [PATCH 24/61] P5600: Option -msched-weight added Thread-Index: AQHbdANz1QuxE/zSAkiuUC208BkUOg== Date: Fri, 31 Jan 2025 17:13:31 +0000 Message-ID: <20250131171232.1018281-26-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: d8c276e4-f475-4206-f267-08dd421a96b8 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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see the file COPYING3. If not see /* This file should be included last. */ #include "target-def.h" +/* Definitions used in ready queue reordering for first scheduling pass. */ + +static int *level = NULL; +static int *consumer_luid = NULL; + +#define LEVEL(INSN) \ + level[INSN_UID ((INSN))] + +#define CONSUMER_LUID(INSN) \ + consumer_luid[INSN_UID ((INSN))] + /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ #define UNSPEC_ADDRESS_P(X) \ (GET_CODE (X) == UNSPEC \ @@ -16737,6 +16748,220 @@ mips_74k_agen_reorder (rtx_insn **ready, int nready) break; } } + +/* These functions are called when -msched-weight is set. */ + +/* Find register born in given X if any. */ + +static int +find_reg_born (rtx x) +{ + if (GET_CODE (x) == CLOBBER) + return 1; + + if (GET_CODE (x) == SET) + { + if (REG_P (SET_DEST (x)) && reg_mentioned_p (SET_DEST (x), SET_SRC (x))) + return 0; + return 1; + } + return 0; +} + +/* Calculate register weight for given INSN. */ + +static int +get_weight (rtx insn) +{ + int weight = 0; + rtx x; + + /* Increment weight for each register born here. */ + x = PATTERN (insn); + weight = find_reg_born (x); + + if (GET_CODE (x) == PARALLEL) + { + int i; + for (i = XVECLEN (x, 0) - 1; i >= 0; i--) + { + x = XVECEXP (PATTERN (insn), 0, i); + weight += find_reg_born (x); + } + } + + /* Decrement weight for each register that dies here. */ + for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) + { + if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED) + { + rtx note = XEXP (x, 0); + if (REG_P (note)) + weight--; + } + } + return weight; +} + +/* TARGET_SCHED_WEIGHT helper function. + Allocate and initialize global data. */ + +static void +mips_weight_init_global (int old_max_uid) +{ + level = (int *) xcalloc (old_max_uid, sizeof (int)); + consumer_luid = (int *) xcalloc (old_max_uid, sizeof (int)); +} + +/* Implement TARGET_SCHED_INIT_GLOBAL. */ + +static void +mips_sched_init_global (FILE *dump ATTRIBUTE_UNUSED, + int verbose ATTRIBUTE_UNUSED, + int old_max_uid) +{ + if (!reload_completed && TARGET_SCHED_WEIGHT) + mips_weight_init_global (old_max_uid); +} + +/* TARGET_SCHED_WEIGHT helper function. Called for each basic block + with dependency chain information in HEAD and TAIL. + Calculates LEVEL for each INSN from its forward dependencies + and finds out UID of first consumer instruction (CONSUMER_LUID) of INSN. */ + +static void +mips_weight_evaluation (rtx_insn *head, rtx_insn *tail) +{ + sd_iterator_def sd_it; + dep_t dep; + rtx_insn *prev_head, *insn; + rtx x; + prev_head = PREV_INSN (head); + + for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) + if (INSN_P (insn)) + { + FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) + { + x = DEP_CON (dep); + if (! DEBUG_INSN_P (x)) + { + if (LEVEL (x) > LEVEL (insn)) + LEVEL (insn) = LEVEL (x); + CONSUMER_LUID (insn) = INSN_LUID (x); + } + } + LEVEL (insn)++; + } +} + +/* Implement TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK. */ + +static void +mips_evaluation_hook (rtx_insn *head, rtx_insn *tail) +{ + if (!reload_completed && TARGET_SCHED_WEIGHT) + mips_weight_evaluation (head, tail); +} + +/* Implement TARGET_SCHED_SET_SCHED_FLAGS. + Enables DONT_BREAK_DEPENDENCIES for the first scheduling pass. + It prevents breaking of dependencies on mem/inc pair in the first pass + which would otherwise increase stalls. */ + +static void +mips_set_sched_flags (spec_info_t spec_info ATTRIBUTE_UNUSED) +{ + if (!reload_completed && TARGET_SCHED_WEIGHT) + { + unsigned int *flags = &(current_sched_info->flags); + *flags |= DONT_BREAK_DEPENDENCIES; + } +} + +static void +mips_weight_finish_global () +{ + if (level != NULL) + free (level); + + if (consumer_luid != NULL) + free (consumer_luid); +} + +/* Implement TARGET_SCHED_FINISH_GLOBAL. */ + +static void +mips_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED, + int verbose ATTRIBUTE_UNUSED) +{ + if (!reload_completed && TARGET_SCHED_WEIGHT) + mips_weight_finish_global (); +} + + +/* This is a TARGET_SCHED_WEIGHT (option -msched-weight) helper function + which is called during reordering of instructions in the first pass + of the scheduler. The function swaps the instruction at (NREADY - 1) + of the READY list with another instruction in READY list as per + the following algorithm. The scheduler then picks the instruction + at READY[NREADY - 1] and schedules it. + + Every instruction is assigned with a value LEVEL. + [See: mips_weight_evaluation ().] + + 1. INSN with highest LEVEL is chosen to be scheduled next, ties broken by + 1a. Choosing INSN that is used early in the flow or + 1b. Choosing INSN with greater INSN_TICK. + + 2. Choose INSN having less LEVEL number iff, + 2a. It is used early and + 2b. Has greater INSN_TICK and + 2c. Contributes less to the register pressure. */ + +static void +mips_sched_weight (rtx_insn **ready, int nready) +{ + int max_level = LEVEL (ready[nready-1]), toswap = nready-1; + int i; +#define INSN_TICK(INSN) (HID (INSN)->tick) + + for (i = nready - 2; i >= 0; i--) + { + rtx_insn *insn = ready[i]; + if (LEVEL (insn) == max_level) + { + if (INSN_PRIORITY (insn) >= INSN_PRIORITY (ready[toswap])) + { + if (CONSUMER_LUID (insn) < CONSUMER_LUID (ready[toswap])) + toswap = i; + } + else if (INSN_TICK (insn) > INSN_TICK (ready[toswap])) + toswap = i; + } + if (LEVEL (insn) > max_level) + { + max_level = LEVEL (insn); + toswap = i; + } + if (LEVEL (insn) < max_level) + { + if (CONSUMER_LUID (insn) < CONSUMER_LUID (ready[toswap]) + && INSN_TICK (insn) > INSN_TICK (ready[toswap]) + && get_weight (insn) < get_weight (ready[toswap])) + toswap = i; + } + } + + if (toswap != (nready-1)) + { + rtx_insn *temp = ready[nready-1]; + ready[nready-1] = ready[toswap]; + ready[toswap] = temp; + } +#undef INSN_TICK +} + /* Implement TARGET_SCHED_INIT. */ @@ -16774,6 +16999,11 @@ mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, if (TUNE_74K) mips_74k_agen_reorder (ready, *nreadyp); + + if (! reload_completed + && TARGET_SCHED_WEIGHT + && *nreadyp > 1) + mips_sched_weight (ready, *nreadyp); } /* Implement TARGET_SCHED_REORDER. */ @@ -25252,6 +25482,18 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) #undef TARGET_SECTION_TYPE_FLAGS #define TARGET_SECTION_TYPE_FLAGS mips_section_type_flags +#undef TARGET_SCHED_INIT_GLOBAL +#define TARGET_SCHED_INIT_GLOBAL mips_sched_init_global + +#undef TARGET_SCHED_FINISH_GLOBAL +#define TARGET_SCHED_FINISH_GLOBAL mips_sched_finish_global + +#undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK +#define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK mips_evaluation_hook + +#undef TARGET_SCHED_SET_SCHED_FLAGS +#define TARGET_SCHED_SET_SCHED_FLAGS mips_set_sched_flags + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-mips.h" diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index fa6ecd988a6..d162702c220 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -573,3 +573,6 @@ Target Undocumented Var(TARGET_USE_COPYW_UCOPYW) Init(-1) minline-intermix Target Var(TARGET_INLINE_INTERMIX) Allow inlining even if the compression flags differ between caller and callee. + +msched-weight +Target Var(TARGET_SCHED_WEIGHT) Undocumented From patchwork Fri Jan 31 17:13:32 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:13:32 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 25/61] Fix negative offset memory addressing Thread-Topic: [PATCH 25/61] Fix negative offset memory addressing Thread-Index: AQHbdAN0LZv9q0XgWkShkVVZmuRF5A== Date: Fri, 31 Jan 2025 17:13:32 +0000 Message-ID: <20250131171232.1018281-27-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: fbc670e9-e1fa-40e0-5ae0-08dd421a96e3 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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The code to break dependencies does not appear to provide a win under any circumstance and is often harmful. Disable it completely pending further investigation. gcc/ * config/mips/mips.cc (mips_set_sched_flags): Set DONT_BREAK_DEPENDENCIES unconditionally. Cherry-picked f732af3ad1a393d2f2e708f0d7c469a093049d01 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 55339d577fb..508435cc9eb 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -16872,11 +16872,8 @@ mips_evaluation_hook (rtx_insn *head, rtx_insn *tail) static void mips_set_sched_flags (spec_info_t spec_info ATTRIBUTE_UNUSED) { - if (!reload_completed && TARGET_SCHED_WEIGHT) - { - unsigned int *flags = &(current_sched_info->flags); - *flags |= DONT_BREAK_DEPENDENCIES; - } + unsigned int *flags = &(current_sched_info->flags); + *flags |= DONT_BREAK_DEPENDENCIES; } static void From patchwork Fri Jan 31 17:13:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105781 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E5DD53858405 for ; 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(mips_block_move_straight): Bond insns where possible. (mips_for_each_saved_gpr_and_fpr): Save/restore registers with increasing offsets if load store pairs optimisation is enabled. (mips_expand_prologue): Bond insns in the prologue. (mips_expand_epilogue): Bond insns in the epilogue. (mips_multipass_dfa_lookahead): Fix sched_fusion with compiler checking enabled. (mips_sched_fusion_priority): New static function. (mips_avoid_hazard): Check if instruction is not in forbidden slot. (mips_reorg_process_insns): Likewise. (mips_option_override): Disable schedule_fusion for MSA. (mips_load_store_p): New function. (mips_load_store_insn_p): Likewise. (mips_load_store_bond_insns_in_range): Likewise. (mips_load_store_bonding_p): Remove load_p argument. (mips_load_store_bonding_insn_p): Add more rules for bonding. (TARGET_SCHED_FUSION_PRIORITY): Define macro. * config/mips/mips.md (can_forbidden): New attribute. (JOIN_MODE): Add DI mode to the mode iterator. (join2_load_store): Change this to named pattern. Add 0 operand to constraints. Add `can_forbidden' attribute. (*join2_loadhi): Add `can_forbidden' attribute. * config/mips/predicates.md (nonimmediate_or_0_operand): New predicate. Cherry-picked 65c0efe581901a706fbe2d4a9d96337090ac220a and 4a2432906766a48b7f3f9aaad8a1358604ce2f88 from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips-protos.h | 2 +- gcc/config/mips/mips.cc | 399 ++++++++++++++++++++++++++++++++-- gcc/config/mips/mips.md | 28 ++- gcc/config/mips/predicates.md | 5 + 4 files changed, 404 insertions(+), 30 deletions(-) diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 6b8f2370752..1ec6f386f5f 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -379,7 +379,7 @@ extern bool mips_epilogue_uses (unsigned int); extern void mips_final_prescan_insn (rtx_insn *, rtx *, int); extern int mips_trampoline_code_size (void); extern void mips_function_profiler (FILE *); -extern bool mips_load_store_bonding_p (rtx *, machine_mode, bool); +extern bool mips_load_store_bonding_p (rtx *, machine_mode); typedef rtx (*mulsidi3_gen_fn) (rtx, rtx, rtx); #ifdef RTX_CODE diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 508435cc9eb..36ce297085b 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -1790,6 +1790,9 @@ static int mips_register_move_cost (machine_mode, reg_class_t, reg_class_t); static unsigned int mips_function_arg_boundary (machine_mode, const_tree); static rtx mips_gen_const_int_vector_shuffle (machine_mode, int); +static bool mips_load_store_insn_p (rtx_insn *, rtx *, + HOST_WIDE_INT *, bool *); +static void mips_load_store_bond_insns (); /* This hash table keeps track of implicit "mips16" and "nomips16" attributes for -mflip_mips16. It maps decl names onto a boolean mode setting. */ @@ -9398,6 +9401,9 @@ mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length, move_by_pieces (dest, src, length - offset, MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), RETURN_BEGIN); } + + if (ENABLE_LD_ST_PAIRS) + mips_load_store_bond_insns (); } /* Helper function for doing a loop-based block operation on memory @@ -13279,8 +13285,9 @@ mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, machine_mode fpr_mode; int regno; const struct mips_frame_info *frame = &cfun->machine->frame; - HOST_WIDE_INT offset; + HOST_WIDE_INT offset, offset_dec; unsigned int mask; + bool increasing_order_p = false; /* Save registers starting from high to low. The debuggers prefer at least the return register be stored at func+4, and also it allows us not to @@ -13292,20 +13299,53 @@ mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, if (TARGET_MICROMIPS) umips_build_save_restore (fn, &mask, &offset); - for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) + if (ENABLE_LD_ST_PAIRS) + increasing_order_p = true; + + if (BITSET_P (mask, (regno = GP_REG_LAST - GP_REG_FIRST))) + { + /* Record the ra offset for use by mips_function_profiler. */ + if (regno == RETURN_ADDR_REGNUM) + cfun->machine->frame.ra_fp_offset = offset + sp_offset; + mips_save_restore_reg (word_mode, regno, offset, fn); + offset -= UNITS_PER_WORD; + } + + if (increasing_order_p) + { + offset_dec = 0; + for (regno = GP_REG_LAST - 1; regno >= GP_REG_FIRST; regno--) + if (BITSET_P (mask, regno - GP_REG_FIRST)) + offset_dec += UNITS_PER_WORD; + offset -= (offset_dec - UNITS_PER_WORD); + } + + for (regno = GP_REG_LAST - 1; regno >= GP_REG_FIRST; regno--) if (BITSET_P (mask, regno - GP_REG_FIRST)) { - /* Record the ra offset for use by mips_function_profiler. */ - if (regno == RETURN_ADDR_REGNUM) - cfun->machine->frame.ra_fp_offset = offset + sp_offset; mips_save_restore_reg (word_mode, regno, offset, fn); - offset -= UNITS_PER_WORD; + if (increasing_order_p) + offset += UNITS_PER_WORD; + else + offset -= UNITS_PER_WORD; } /* This loop must iterate over the same space as its companion in mips_compute_frame_info. */ offset = cfun->machine->frame.fp_sp_offset - sp_offset; fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode); + + if (increasing_order_p) + { + offset_dec = 0; + for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1; + regno >= FP_REG_FIRST; + regno -= MAX_FPRS_PER_FMT) + if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) + offset_dec += GET_MODE_SIZE (fpr_mode); + offset -= (offset_dec - GET_MODE_SIZE (fpr_mode)); + } + for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1; regno >= FP_REG_FIRST; regno -= MAX_FPRS_PER_FMT) @@ -13321,7 +13361,10 @@ mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, } else mips_save_restore_reg (fpr_mode, regno, offset, fn); - offset -= GET_MODE_SIZE (fpr_mode); + if (increasing_order_p) + offset += GET_MODE_SIZE (fpr_mode); + else + offset -= GET_MODE_SIZE (fpr_mode); } } @@ -14078,6 +14121,9 @@ mips_expand_prologue (void) the call to mcount. */ if (crtl->profile) emit_insn (gen_blockage ()); + + if (ENABLE_LD_ST_PAIRS) + mips_load_store_bond_insns (); } /* Attach all pending register saves to the previous instruction. @@ -14430,6 +14476,9 @@ mips_expand_epilogue (bool sibcall_p) emit_insn_before (gen_mips_di (), insn); emit_insn_before (gen_mips_ehb (), insn); } + + if (ENABLE_LD_ST_PAIRS) + mips_load_store_bond_insns (); } /* Return nonzero if this function is known to have a null epilogue. @@ -16486,6 +16535,9 @@ mips_dfa_post_advance_cycle (void) static int mips_multipass_dfa_lookahead (void) { + if (sched_fusion) + return 0; + /* Can schedule up to 4 of the 6 function units in any one cycle. */ if (TUNE_SB1) return 4; @@ -16876,6 +16928,48 @@ mips_set_sched_flags (spec_info_t spec_info ATTRIBUTE_UNUSED) *flags |= DONT_BREAK_DEPENDENCIES; } +/* Implement the TARGET_SCHED_FUSION_PRIORITY hook. */ + +static void +mips_sched_fusion_priority (rtx_insn *insn, int max_pri, + int *fusion_pri, int *pri) +{ + int tmp; + bool is_load; + rtx base; + HOST_WIDE_INT offset; + + gcc_assert (INSN_P (insn)); + + tmp = max_pri - 1; + if (!mips_load_store_insn_p (insn, &base, &offset, &is_load)) + { + *pri = tmp; + *fusion_pri = tmp; + return; + } + + /* Load goes first. */ + if (is_load) + *fusion_pri = tmp - 1; + else + *fusion_pri = tmp - 2; + + tmp /= 2; + + /* INSN with smaller base register goes first. */ + tmp -= ((REGNO (base) & 0xff) << 20); + + /* INSN with smaller offset goes first. */ + if (offset >= 0) + tmp -= (offset & 0xfffff); + else + tmp += ((-offset) & 0xfffff); + + *pri = tmp; + return; +} + static void mips_weight_finish_global () { @@ -20791,7 +20885,7 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, imply it is not actually a compact branch anyway) and the current insn is not an inline asm, and can't go in a delay slot. */ else if (TARGET_FORBIDDEN_SLOTS && *fs_delay - && get_attr_can_delay (insn) == CAN_DELAY_NO + && get_attr_can_forbidden (insn) == CAN_FORBIDDEN_NO && GET_CODE (PATTERN (after)) != SEQUENCE && GET_CODE (pattern) != ASM_INPUT && asm_noperands (pattern) < 0) @@ -21007,7 +21101,8 @@ mips_reorg_process_insns (void) && ((next_active && INSN_P (next_active) && GET_CODE (PATTERN (next_active)) != SEQUENCE - && get_attr_can_delay (next_active) == CAN_DELAY_YES) + && (get_attr_can_forbidden (next_active) + == CAN_FORBIDDEN_YES)) || !optimize_size)) { /* To hide a potential pipeline bubble, if we scan backwards @@ -22615,6 +22710,11 @@ mips_option_override (void) if (ISA_HAS_MSA && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI)) error ("%<-mmsa%> must be used with %<-mfp64%> and %<-mhard-float%>"); + /* Disable fusion for MSA as it can significantly interfere and schedule + loads too close to their use. */ + if (ISA_HAS_MSA) + flag_schedule_fusion = 0; + /* Make sure that -mpaired-single is only used on ISAs that support it. We must disable it otherwise since it relies on other ISA properties like ISA_HAS_8CC having their normal values. */ @@ -23258,12 +23358,96 @@ umips_load_store_pair_p_1 (bool load_p, bool swap_p, return true; } +/* Return TRUE if OPERANDS represents a load or store of address in + the form of [BASE+OFFSET] that can be later bonded. LOAD_P is set to TRUE + if it's a load. Return FALSE otherwise. */ + +static bool +mips_load_store_p (rtx *operands, rtx *base, HOST_WIDE_INT *offset, + bool *load_p) +{ + rtx mem; + rtx dest = operands[0]; + rtx src = operands[1]; + + if ((GET_CODE (src) == REG || src == const0_rtx) + && GET_CODE ((mem = dest)) == MEM) + *load_p = false; + else if (GET_CODE ((mem = src)) == MEM && GET_CODE (dest) == REG) + *load_p = true; + else + return false; + + mips_split_plus (XEXP (mem, 0), base, offset); + + if (GET_CODE (*base) != REG) + return false; + + if (*load_p && MEM_VOLATILE_P (mem)) + return false; + + return true; +} + +/* Return TRUE if INSN represents a load or store of address in the form of + [BASE+OFFSET] that can be later bonded. LOAD_P is set to TRUE + if it's a load. Return FALSE otherwise. */ + +static bool +mips_load_store_insn_p (rtx_insn *insn, rtx *base, HOST_WIDE_INT *offset, + bool *load_p) +{ + rtx op[2], x; + + gcc_assert (INSN_P (insn)); + + x = PATTERN (insn); + if (GET_CODE (x) != SET) + return false; + + op[0] = SET_DEST (x); + op[1] = SET_SRC (x); + return mips_load_store_p (op, base, offset, load_p); +} + +/* Return TRUE if operands OPERANDS represent two consecutive instructions + than can be bonded as load-load/store-store pair in mode MODE. + Return FALSE otherwise. */ + bool -mips_load_store_bonding_p (rtx *operands, machine_mode mode, bool load_p) +mips_load_store_bonding_p (rtx *operands, machine_mode mode) { rtx reg1, reg2, mem1, mem2, base1, base2; enum reg_class rc1, rc2; HOST_WIDE_INT offset1, offset2; + bool load_p, load_p2; + + /* Check the supported modes. */ + switch (mode) + { + case E_HImode: + case E_SImode: + break; + case E_DImode: + if (!TARGET_64BIT) + return false; + break; + case E_SFmode: + if (!TARGET_HARD_FLOAT) + return false; + break; + case E_DFmode: + if (!(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)) + return false; + break; + default: + return false; + } + + if (!mips_load_store_p (&operands[0], &base1, &offset1, &load_p) + || !mips_load_store_p (&operands[2], &base2, &offset2, &load_p2) + || load_p != load_p2) + return false; if (load_p) { @@ -23280,12 +23464,17 @@ mips_load_store_bonding_p (rtx *operands, machine_mode mode, bool load_p) mem2 = operands[2]; } + if (MEM_ALIGN (mem1) < GET_MODE_BITSIZE (GET_MODE (mem1)) + || MEM_ALIGN (mem2) < GET_MODE_BITSIZE (GET_MODE (mem2))) + return false; + if (mips_address_insns (XEXP (mem1, 0), mode, false) == 0 || mips_address_insns (XEXP (mem2, 0), mode, false) == 0) return false; - mips_split_plus (XEXP (mem1, 0), &base1, &offset1); - mips_split_plus (XEXP (mem2, 0), &base2, &offset2); + if ((!REG_P (reg1) && reg1 != const0_rtx) + || (!REG_P (reg2) && reg2 != const0_rtx)) + return false; /* Base regs do not match. */ if (!REG_P (base1) || !rtx_equal_p (base1, base2)) @@ -23295,29 +23484,196 @@ mips_load_store_bonding_p (rtx *operands, machine_mode mode, bool load_p) loads if second load clobbers base register. However, hardware does not support such bonding. */ if (load_p - && (REGNO (reg1) == REGNO (base1) - || (REGNO (reg2) == REGNO (base1)))) + && ((REG_P (reg1) && REGNO (reg1) == REGNO (base1)) + || (REG_P (reg2) && REGNO (reg2) == REGNO (base1)))) return false; /* Loading in same registers. */ if (load_p + && REG_P (reg1) && REG_P (reg2) && REGNO (reg1) == REGNO (reg2)) return false; - /* The loads/stores are not of same type. */ - rc1 = REGNO_REG_CLASS (REGNO (reg1)); - rc2 = REGNO_REG_CLASS (REGNO (reg2)); - if (rc1 != rc2 - && !reg_class_subset_p (rc1, rc2) - && !reg_class_subset_p (rc2, rc1)) + /* Check if the loads/stores are of the same mode. */ + if (GET_MODE (mem1) != GET_MODE (mem2)) return false; + /* The loads/stores are not of same type. */ + if (reload_completed + && reg1 != const0_rtx + && reg2 != const0_rtx) + { + rc1 = REGNO_REG_CLASS (REGNO (reg1)); + rc2 = REGNO_REG_CLASS (REGNO (reg2)); + if (rc1 != rc2 + && !reg_class_subset_p (rc1, rc2) + && !reg_class_subset_p (rc2, rc1)) + return false; + } + if (abs (offset1 - offset2) != GET_MODE_SIZE (mode)) return false; return true; } +/* Return TRUE if INSN1 and INSN2 can be bonded, FALSE otherwise. */ + +bool +mips_load_store_bonding_insn_p (rtx insn1, rtx insn2) +{ + rtx operands[4]; + rtx pat1, pat2; + + gcc_assert (INSN_P (insn1) && INSN_P (insn2)); + + pat1 = PATTERN (insn1); + pat2 = PATTERN (insn2); + + if (GET_CODE (pat1) == SET && GET_CODE (pat2) == SET) + { + machine_mode mode; + + operands[0] = SET_DEST (pat1); + operands[1] = SET_SRC (pat1); + operands[2] = SET_DEST (pat2); + operands[3] = SET_SRC (pat2); + + /* We take the mode from either SET_DESTs and the remaining operands + and modes will be checked later. */ + mode = GET_MODE (operands[0]); + + return mips_load_store_bonding_p (operands, mode); + } + + return false; +} + +/* Find and bond load/store pairs in range FROM to TO. */ + +static void +mips_load_store_bond_insns_in_range (rtx_insn *from, rtx_insn *to) +{ + rtx_insn *cur, *next; + + if (!ENABLE_LD_ST_PAIRS) + return; + + if (from == NULL || to == NULL || from == to) + return; + + for (cur = from, next = NEXT_INSN (from); + next; + cur = next, next = NEXT_INSN (next)) + { + if (INSN_P (cur) && INSN_P (next) + && mips_load_store_bonding_insn_p (cur, next)) + { + rtx_insn *bonded; + int code; + rtx base1, base2; + HOST_WIDE_INT offset1, offset2; + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); + + XVECEXP (par, 0, 0) = PATTERN (cur); + XVECEXP (par, 0, 1) = PATTERN (next); + + bonded = emit_insn_before (par, cur); + code = recog_memoized (bonded); + + if (code < 0) + { + delete_insn (bonded); + continue; + } + + base1 = base2 = NULL_RTX; + + if (GET_CODE (SET_SRC (single_set (cur))) == REG + && GET_CODE (SET_DEST (single_set (cur))) == MEM) + { + mips_split_plus (XEXP (SET_DEST (single_set (cur)), 0), + &base1, &offset1); + mips_split_plus (XEXP (SET_DEST (single_set (next)), 0), + &base2, &offset2); + } + + if (base1 != NULL_RTX + && GET_CODE (base1) == REG + && REGNO (base1) == STACK_POINTER_REGNUM) + { + rtx dwarf, dwarf1 = NULL_RTX, dwarf2 = NULL_RTX; + rtx note1, note2; + int len = 0; + int dwarf_index = 0; + + gcc_assert (base2 != NULL_RTX && GET_CODE (base2) == REG + && REGNO (base2) == STACK_POINTER_REGNUM); + + if ((note1 = find_reg_note (cur, REG_FRAME_RELATED_EXPR, 0))) + { + dwarf1 = XEXP (note1, 0); + if (GET_CODE (dwarf1) == PARALLEL) + len += XVECLEN (dwarf1, 0); + else + len += 1; + } + + if ((note2 = find_reg_note (next, REG_FRAME_RELATED_EXPR, 0))) + { + dwarf2 = XEXP (note2, 0); + if (GET_CODE (dwarf2) == PARALLEL) + len += XVECLEN (dwarf2, 0); + else + len += 1; + } + + dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (len)); + + if (dwarf1 && GET_CODE (dwarf1) == PARALLEL) + { + int i; + for (i = 0 ; i < XVECLEN (dwarf1, 0) ; i++) + { + XVECEXP (dwarf, 0, dwarf_index++) = XVECEXP (dwarf1, + 0, i); + } + } + else if (dwarf1) + XVECEXP (dwarf, 0, dwarf_index++) = dwarf1; + + if (dwarf2 && GET_CODE (dwarf2) == PARALLEL) + { + int i; + for (i = 0 ; i < XVECLEN (dwarf2, 0) ; i++) + { + XVECEXP (dwarf, 0, dwarf_index++) = XVECEXP (dwarf2, + 0, i); + } + } + else if (dwarf2) + XVECEXP (dwarf, 0, dwarf_index++) = dwarf2; + + RTX_FRAME_RELATED_P (bonded) = 1; + add_reg_note (bonded, REG_FRAME_RELATED_EXPR, dwarf); + } + + remove_insn (cur); + remove_insn (next); + cur = bonded; + next = bonded; + } + } +} + +/* Find and bond load/store pairs for the entire sequence. */ + +static void +mips_load_store_bond_insns () +{ + mips_load_store_bond_insns_in_range (get_insns (), get_last_insn ()); +} + /* OPERANDS describes the operands to a pair of SETs, in the order dest1, src1, dest2, src2. Return true if the operands can be used in an LWP or SWP instruction; LOAD_P says which. */ @@ -25491,6 +25847,9 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) #undef TARGET_SCHED_SET_SCHED_FLAGS #define TARGET_SCHED_SET_SCHED_FLAGS mips_set_sched_flags +#undef TARGET_SCHED_FUSION_PRIORITY +#define TARGET_SCHED_FUSION_PRIORITY mips_sched_fusion_priority + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-mips.h" diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 21f31a5595a..814692aecf1 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -786,6 +786,12 @@ (const_string "yes") (const_string "no"))) +;; Can the instruction be put into a forbidden slot? +(define_attr "can_forbidden" "no,yes" + (if_then_else (eq_attr "can_delay" "yes") + (const_string "yes") + (const_string "no"))) + ;; Attribute defining whether or not we can use the branch-likely ;; instructions. (define_attr "branch_likely" "no,yes" @@ -817,6 +823,7 @@ (define_mode_iterator MOVEP2 [SI SF]) (define_mode_iterator JOIN_MODE [HI SI + (DI "TARGET_64BIT") (SF "TARGET_HARD_FLOAT") (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")]) @@ -8015,12 +8022,13 @@ (set_attr "insn_count" "3")]) ;; Match paired HI/SI/SF/DFmode load/stores. -(define_insn "*join2_load_store" +(define_insn "join2_load_store" [(set (match_operand:JOIN_MODE 0 "nonimmediate_operand" "=d,f,m,m") - (match_operand:JOIN_MODE 1 "nonimmediate_operand" "m,m,d,f")) + (match_operand:JOIN_MODE 1 "nonimmediate_or_0_operand" "m,m,dJ,f")) (set (match_operand:JOIN_MODE 2 "nonimmediate_operand" "=d,f,m,m") - (match_operand:JOIN_MODE 3 "nonimmediate_operand" "m,m,d,f"))] - "ENABLE_LD_ST_PAIRS && reload_completed" + (match_operand:JOIN_MODE 3 "nonimmediate_or_0_operand" "m,m,dJ,f"))] + "ENABLE_LD_ST_PAIRS + && mips_load_store_bonding_p (operands, mode)" { bool load_p = (which_alternative == 0 || which_alternative == 1); /* Reg-renaming pass reuses base register if it is dead after bonded loads. @@ -8043,6 +8051,7 @@ return ""; } [(set_attr "move_type" "load,fpload,store,fpstore") + (set_attr "can_forbidden" "yes") (set_attr "insn_count" "2,2,2,2")]) ;; 2 HI/SI/SF/DF loads are joined. @@ -8055,7 +8064,7 @@ (set (match_operand:JOIN_MODE 2 "register_operand") (match_operand:JOIN_MODE 3 "non_volatile_mem_operand"))] "ENABLE_LD_ST_PAIRS - && mips_load_store_bonding_p (operands, mode, true)" + && mips_load_store_bonding_p (operands, mode)" [(parallel [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) @@ -8066,11 +8075,11 @@ ;; P5600 does not support bonding of two SBs, hence QI mode is not included. (define_peephole2 [(set (match_operand:JOIN_MODE 0 "memory_operand") - (match_operand:JOIN_MODE 1 "register_operand")) + (match_operand:JOIN_MODE 1 "reg_or_0_operand")) (set (match_operand:JOIN_MODE 2 "memory_operand") - (match_operand:JOIN_MODE 3 "register_operand"))] + (match_operand:JOIN_MODE 3 "reg_or_0_operand"))] "ENABLE_LD_ST_PAIRS - && mips_load_store_bonding_p (operands, mode, false)" + && mips_load_store_bonding_p (operands, mode)" [(parallel [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) @@ -8102,6 +8111,7 @@ return ""; } [(set_attr "move_type" "load") + (set_attr "can_forbidden" "yes") (set_attr "insn_count" "2")]) ;; @@ -8153,7 +8163,7 @@ (set (match_operand:SI 2 "register_operand") (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand")))] "ENABLE_LD_ST_PAIRS - && mips_load_store_bonding_p (operands, HImode, true)" + && mips_load_store_bonding_p (operands, HImode)" [(parallel [(set (match_dup 0) (any_extend:SI (match_dup 1))) (set (match_dup 2) diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index 31cc57af435..604b1676f2b 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -120,6 +120,11 @@ (match_test "ISA_HAS_MIPS16E2"))) (match_operand 0 "register_operand"))) +(define_predicate "nonimmediate_or_0_operand" + (ior (and (match_operand 0 "const_0_operand") + (not (match_test "TARGET_MIPS16"))) + (match_operand 0 "nonimmediate_operand"))) + (define_predicate "const_1_operand" (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST1_RTX (GET_MODE (op))"))) From patchwork Fri Jan 31 17:13:33 2025 Content-Type: text/plain; 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(ISA_HAS_RINT): Likewise. * config/mips/mips.md (unspec): Add UNSPEC_FCLASS and UNSPEC_FRINT. (type) Add fclass and frint. (fnma4): Enable for ISA_HAS_FUSED_MADDF. (fnma4_msubf): New define_insn. (fmax_a_): Likewise. (fmin_a_): Likewise. (fclass_): Likewise. (frint_): Likewise. * config/mips/i6400.md (i6400_fpu_minmax): Include fclass type. (i6400_fpu_fadd): Include frint type. * config/mips/p6600.md (p6600_fpu_fadd): Include frint type. (p6600_fpu_fabs): Include fclass type. Cherry-picked bbc81087aa0e307aaf262021c40473644ed2a9b2 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/i6400.md | 6 ++-- gcc/config/mips/mips.h | 4 +++ gcc/config/mips/mips.md | 61 ++++++++++++++++++++++++++++++++++++++-- gcc/config/mips/p6600.md | 4 +-- 4 files changed, 67 insertions(+), 8 deletions(-) diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md index d6f691ee217..4a2361667abd 100644 --- a/gcc/config/mips/i6400.md +++ b/gcc/config/mips/i6400.md @@ -219,16 +219,16 @@ (eq_attr "type" "fabs,fneg,fmove")) "i6400_fpu_short, i6400_fpu_apu") -;; min, max +;; min, max, min_a, max_a, class (define_insn_reservation "i6400_fpu_minmax" 2 (and (eq_attr "cpu" "i6400") - (eq_attr "type" "fminmax")) + (eq_attr "type" "fminmax,fclass")) "i6400_fpu_short+i6400_fpu_logic") ;; fadd, fsub, fcvt (define_insn_reservation "i6400_fpu_fadd" 4 (and (eq_attr "cpu" "i6400") - (eq_attr "type" "fadd,fcvt")) + (eq_attr "type" "fadd,fcvt,frint")) "i6400_fpu_long, i6400_fpu_apu") ;; fmul diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index b727074bf53..efd23a262f9 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1291,6 +1291,10 @@ struct mips_cpu_info { #define ISA_HAS_FMIN_FMAX (mips_isa_rev >= 6) +#define ISA_HAS_FCLASS (mips_isa_rev >= 6) + +#define ISA_HAS_RINT (mips_isa_rev >= 6) + /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 814692aecf1..7d27e7d4b20 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -102,6 +102,8 @@ ;; Floating-point unspecs. UNSPEC_FMIN UNSPEC_FMAX + UNSPEC_FCLASS + UNSPEC_FRINT ;; HI/LO moves. UNSPEC_MFHI @@ -395,7 +397,7 @@ shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, frsqrt,frsqrt1,frsqrt2,fminmax,dspmac,dspmacsat,accext,accmod,dspalu, - dspalusat,multi,atomic,syncloop,nop,ghost,multimem, + dspalusat,multi,atomic,syncloop,nop,ghost,multimem,fclass,frint, simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd, simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp, simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill, @@ -2656,8 +2658,9 @@ (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand")) (match_operand:ANYF 2 "register_operand") (match_operand:ANYF 3 "register_operand")))] - "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4) - && !HONOR_SIGNED_ZEROS (mode)") + "((ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4) + && !HONOR_SIGNED_ZEROS (mode)) + || ISA_HAS_FUSED_MADDF") (define_insn "*fnma4_nmsub3" [(set (match_operand:ANYF 0 "register_operand" "=f") @@ -2679,6 +2682,16 @@ [(set_attr "type" "fmadd") (set_attr "mode" "")]) +(define_insn "*fnma4_msubf" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) + (match_operand:ANYF 2 "register_operand" "f") + (match_operand:ANYF 3 "register_operand" "0")))] + "ISA_HAS_FUSED_MADDF" + "msubf.\t%0,%1,%2" + [(set_attr "type" "fmadd") + (set_attr "mode" "")]) + ;; fnms is defined as: (fma (neg op1) op2 (neg op3)) ;; ((-op1) * op2) - op3 ==> -(op1 * op2) - op3 ==> -((op1 * op2) + op3) ;; The mips nmadd instructions implement -((op1 * op2) + op3) @@ -8156,6 +8169,48 @@ [(set_attr "type" "fminmax") (set_attr "mode" "")]) +(define_insn "fmax_a_" + [(set (match_operand:SCALARF 0 "register_operand" "=f") + (if_then_else + (gt (abs:SCALARF (match_operand:SCALARF 1 "register_operand" "f")) + (abs:SCALARF (match_operand:SCALARF 2 "register_operand" "f"))) + (match_dup 1) + (match_dup 2)))] + "ISA_HAS_FMIN_FMAX" + "maxa.\t%0,%1,%2" + [(set_attr "type" "fminmax") + (set_attr "mode" "")]) + +(define_insn "fmin_a_" + [(set (match_operand:SCALARF 0 "register_operand" "=f") + (if_then_else + (lt (abs:SCALARF (match_operand:SCALARF 1 "register_operand" "f")) + (abs:SCALARF (match_operand:SCALARF 2 "register_operand" "f"))) + (match_dup 1) + (match_dup 2)))] + "ISA_HAS_FMIN_FMAX" + "mina.\t%0,%1,%2" + [(set_attr "type" "fminmax") + (set_attr "mode" "")]) + +(define_insn "fclass_" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] + UNSPEC_FCLASS))] + "ISA_HAS_FCLASS" + "fclass.\t%0,%1" + [(set_attr "type" "fclass") + (set_attr "mode" "")]) + +(define_insn "frint_" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] + UNSPEC_FRINT))] + "ISA_HAS_RINT" + "rint.\t%0,%1" + [(set_attr "type" "frint") + (set_attr "mode" "")]) + ;; 2 HI loads are joined. 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It appears that a series of unfortunate events causes a wrong instruction to be placed in the delay slot: 1. The branch is not optimised away during expansion. It has a diamond shape so the unreachable case falls through. 2. The block reordering pass moves the basic block elsewhere. 3. The eager delay slot filler (EDSF): a. It initially skips all the consecutive labels, ignoring barriers, until it finds an instruction. This is done by design. Similarly what first_active_target_insn() does. b. The branch now points to a load for the branch taken case. c. The arithmetic shift left instruction is not placed in the slot because the EDSF detects that there is a conflict with the resource usage (because of a set $4, $4 being referenced or both but very likely because it's referenced). d. As (c) failed, another attempt is taken and the other thread/path explored. This time it succeeds as, at least it appears that, the reverse search for the branch taken path looks for the beginning of the basic block and it does not see that $4 is also used. The lack of referencing $4 by the shift is likely to be the cause of not seeing the usage. e. As (d) succeeded, the load is "legitimately" placed in the delay slot. Perhaps this is a vague description but this is more and less what is happening. The fix attempts to treat the unreachable block (that represents __builtin_unreachable) in a special way: 1. The label is not skipped if it is a label with a barrier only. Notes and debug instructions are ignored. This prevents redirecting the jump to a wrong place that seemed to be treated as a valid redirection. Since the behaviour of such branching is undefined, we don't want to analyse the taken path. 2. The first_active_target_insn() must recognize the unreachable block and not to go beyond the barrier for the same reason as above. 3. With this in place, the eager delay slot filler uses the correct instruction. We don't care where the branch branches to as the behaviour of the program is undefined. The slot is not filled letting the assembler to do the right thing (.set noreorder/reorder are not emitted). gcc/ * reorg.cc (label_with_barrier_p): New function. (skip_consecutive_labels): Use it. Don't skip the label if an empty block is found. (first_active_target_insn): Likewise. Don't ignore the empty block when searching for the next active instruction. Cherry-picked 3667d07c7f0512e8996eab9ab75efc79ac1827c2 from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/reorg.cc | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/gcc/reorg.cc b/gcc/reorg.cc index 68bf30801cf..91a752b7d4a 100644 --- a/gcc/reorg.cc +++ b/gcc/reorg.cc @@ -113,6 +113,30 @@ along with GCC; see the file COPYING3. If not see These functions are now only used here in reorg.cc, and have therefore been moved here to avoid inadvertent misuse elsewhere in the compiler. */ +/* Return true if a LABEL is followed by a BARRIER. Ignore notes and debug + instructions. */ + +static bool +label_with_barrier_p (rtx_insn *label) +{ + bool empty_bb = true; + + if (GET_CODE (label) != CODE_LABEL) + empty_bb = false; + else + label = NEXT_INSN (label); + + while (!BARRIER_P (label) && empty_bb) + { + if (!(DEBUG_INSN_P (label) + || NOTE_P (label))) + empty_bb = false; + label = NEXT_INSN (label); + } + + return empty_bb; +} + /* Return the last label to mark the same position as LABEL. Return LABEL itself if it is null or any return rtx. */ @@ -140,6 +164,8 @@ skip_consecutive_labels (rtx label_or_return) for (insn = label; insn != 0 && !INSN_P (insn) && !BARRIER_P (insn); insn = NEXT_INSN (insn)) + if (LABEL_P (insn) && label_with_barrier_p (insn)) + break; if (LABEL_P (insn)) label = insn; @@ -230,6 +256,8 @@ first_active_target_insn (rtx insn) { if (ANY_RETURN_P (insn)) return insn; + if (LABEL_P (insn) && label_with_barrier_p ((rtx_insn *)insn)) + return NULL_RTX; return next_active_insn (as_a (insn)); } From patchwork Fri Jan 31 17:13:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105760 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 160B73857B9E for ; Fri, 31 Jan 2025 17:35:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 160B73857B9E Authentication-Results: sourceware.org; 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Don't force integer mode pseudos into GR_REGS (and likewise for float mode pseudos and FP_REGS) if both the allocno class and best cost class are ALL_REGS to prevent inefficient scattered complex load with MSA. gcc/testsuite/ * gcc.target/mips/msa-scattered-load.c: New. Cherry-picked 1996aa906aeb4f958b77bb12aa60745ca9962fa2, 5314c36e83e9f8e13144b3a991e392d152514938 and e9b42ac26ee8eeea0f5ca5a54b3b2dca5a69dd71 from https://github.com/MIPS/gcc Signed-off-by: Simon Dardis Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 16 ++++++++++++--- .../gcc.target/mips/msa-scattered-load.c | 20 +++++++++++++++++++ 2 files changed, 33 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/msa-scattered-load.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 36ce297085b..1fa727c2ff5 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -25347,7 +25347,7 @@ mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED, static reg_class_t mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class, - reg_class_t best_class ATTRIBUTE_UNUSED) + reg_class_t best_class) { /* LRA will allocate an FPR for an integer mode pseudo instead of spilling to memory if an FPR is present in the allocno class. It is rare that @@ -25357,7 +25357,9 @@ mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class, to reload into FPRs in LRA. Such reloads are sometimes eliminated and sometimes only partially eliminated. We choose to take this penalty in order to eliminate usage of FPRs in code that does not use floating - point data. + point data. In the case when IRA computes both allocno class and best + cost class as ALL_REGS, do not force integer mode pseudo into GR_REGS + as it is probably best to be placed into FPR. This change has a similar effect to increasing the cost of FPR->GPR register moves for integer modes so that they are higher than the cost @@ -25366,8 +25368,16 @@ mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class, This is also similar to forbidding integer mode values in FPRs entirely but this would lead to an inconsistency in the integer to/from float instructions that say integer mode values must be placed in FPRs. */ - if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS) + if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS + && allocno_class != best_class) return GR_REGS; + + /* Likewise for the mirror case of floating mode pseudos being allocated in + a GPR. */ + if (FLOAT_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS + && allocno_class != best_class) + return FP_REGS; + return allocno_class; } diff --git a/gcc/testsuite/gcc.target/mips/msa-scattered-load.c b/gcc/testsuite/gcc.target/mips/msa-scattered-load.c new file mode 100644 index 00000000000..f42574ae772 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-scattered-load.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp64 -mhard-float -mmsa" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +#include +#include +#include + +void pgather2cf1(const float complex* from, v4f32* pv, size_t stride) { + v4f32 v; + v[0] = crealf(from[0]); + v[1] = cimagf(from[0]); + v[2] = crealf(from[stride]); + v[3] = cimagf(from[stride]); + *pv = v; +} + +/* { dg-final { scan-assembler-not "mfc1" } } */ +/* { dg-final { scan-assembler-not "mtc1" } } */ + From patchwork Fri Jan 31 17:13:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105772 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6DBA8385782C for ; Fri, 31 Jan 2025 17:50:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6DBA8385782C Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=NdAX9dJ6 X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2070f.outbound.protection.outlook.com [IPv6:2a01:111:f403:260c::70f]) by sourceware.org (Postfix) with ESMTPS id 035663858429 for ; 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Fri, 31 Jan 2025 17:14:05 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 30/61] MSA: Make MSA and microMIPS R5 unsupported Thread-Topic: [PATCH 30/61] MSA: Make MSA and microMIPS R5 unsupported Thread-Index: AQHbdAN2PvSOuJ9BCk+PXfHSYtji/w== Date: Fri, 31 Jan 2025 17:13:35 +0000 Message-ID: <20250131171232.1018281-32-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|AS2PR09MB6367:EE_ x-ms-office365-filtering-correlation-id: 00d0e523-f0d8-435e-0e25-08dd421aaab0 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Cherry-picked 1009d6ff7a8d3b56e0224a6b193c5a7b3c29aa5f from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 1fa727c2ff5..3185fa9633e 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -22551,6 +22551,9 @@ mips_option_override (void) "-mcompact-branches=never"); } + if (is_micromips && TARGET_MSA) + error ("unsupported combination: %s", "-mmicromips -mmsa"); + /* Enable the use of interAptiv MIPS32 SAVE/RESTORE instructions. */ if (TARGET_USE_SAVE_RESTORE == -1) { From patchwork Fri Jan 31 17:13:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105763 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 483983858C66 for ; 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- else if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER) + else if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER + /* We increase slightly the maximum number of bytes in + a straight-line block if the source and destination + are aligned to the register width. */ + || (!optimize_size + && INTVAL (alignment) == UNITS_PER_WORD + && INTVAL (length) <= MIPS_MAX_MOVE_MEM_STRAIGHT)) { mips_block_move_straight (dest, src, INTVAL (length), INTVAL (alignment)); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index efd23a262f9..0245287f9bf 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -3171,6 +3171,11 @@ while (0) #define MIPS_MAX_MOVE_BYTES_STRAIGHT \ (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) +/* The maximum number of bytes that can be copied by any expanded block move; + see mips_expand_block_move. */ +#define MIPS_MAX_MOVE_MEM_STRAIGHT \ + (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 3) + /* The base cost of a memcpy call, for MOVE_RATIO and friends. These values were determined experimentally by benchmarking with CSiBE. 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This is often better than the 4 LIs and 4 SBs that we would generate when storing by pieces. */ if (align <= BITS_PER_UNIT) - return size < 4; + return size < 4 || !ISA_HAS_LWL_LWR; /* If the data is 2-byte aligned, then: @@ -9321,7 +9321,9 @@ mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align) (c4) A block move of 8 bytes can use two LW/SW sequences or a single LD/SD sequence, and in these cases we've traditionally preferred the memory copy over the more bulky constant moves. */ - return size < 8; + return (size < 8 + || (align < 4 * BITS_PER_UNIT + && !ISA_HAS_LWL_LWR)); } /* Emit straight-line code to move LENGTH bytes from SRC to DEST. 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Fri, 31 Jan 2025 17:14:06 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 33/61] Testsuite: Fix insn-*.c tests from trunk Thread-Topic: [PATCH 33/61] Testsuite: Fix insn-*.c tests from trunk Thread-Index: AQHbdAN2txx3ZQJI9U23cHwTAAi5Lw== Date: Fri, 31 Jan 2025 17:13:36 +0000 Message-ID: <20250131171232.1018281-35-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|AS2PR09MB6367:EE_ x-ms-office365-filtering-correlation-id: c52b6377-95df-4635-f633-08dd421aab1b x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Ensure insn-casesi.c and insn-tablejump.c can be executed. Move the micromips/mips16 selection into the file as per function attributes so that there is no requirement on having a full micromips or mips16 runtime to execute the test. gcc/testsuite/ * gcc.target/mips/insn-tablejump.c: Force o32 ABI as we do not really support n32/n64 microMIPS. Require micromips support but not the command line option. * gcc.target/mips/insn-casesi.c: Require mips16 support but not the command line option. Cherry-picked e7aaf244857638adeb9d1eb5207dbe2842cbe81d from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.target/mips/insn-casesi.c | 6 +++--- gcc/testsuite/gcc.target/mips/insn-tablejump.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/testsuite/gcc.target/mips/insn-casesi.c b/gcc/testsuite/gcc.target/mips/insn-casesi.c index 2b4c9f21986..03d13070460 100644 --- a/gcc/testsuite/gcc.target/mips/insn-casesi.c +++ b/gcc/testsuite/gcc.target/mips/insn-casesi.c @@ -1,7 +1,7 @@ /* { dg-do run } */ -/* { dg-options "-mips16 -mcode-readable=yes" } */ +/* { dg-options "(-mips16) -mabi=32 -mcode-readable=yes" } */ -int __attribute__ ((noinline)) +MIPS16 int __attribute__ ((noinline)) frob (int i) { switch (i) @@ -22,7 +22,7 @@ frob (int i) return i; } -int +MIPS16 int main (int argc, char **argv) { asm ("" : "+r" (argc)); diff --git a/gcc/testsuite/gcc.target/mips/insn-tablejump.c b/gcc/testsuite/gcc.target/mips/insn-tablejump.c index ecba154b9e0..271108a3ed6 100644 --- a/gcc/testsuite/gcc.target/mips/insn-tablejump.c +++ b/gcc/testsuite/gcc.target/mips/insn-tablejump.c @@ -1,7 +1,7 @@ /* { dg-do run } */ -/* { dg-options "-mmicromips" } */ +/* { dg-options "(-mmicromips) -mabi=32" } */ -int __attribute__ ((noinline)) +MICROMIPS int __attribute__ ((noinline)) frob (int i) { switch (i) @@ -22,7 +22,7 @@ frob (int i) return i; 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float a; -float + +NOMIPS16 float foo () { float b = a + 1.0f; diff --git a/gcc/testsuite/gcc.target/mips/call-clobbered-3.c b/gcc/testsuite/gcc.target/mips/call-clobbered-3.c index 3a9e8d883fc..cca94bdd5ba 100644 --- a/gcc/testsuite/gcc.target/mips/call-clobbered-3.c +++ b/gcc/testsuite/gcc.target/mips/call-clobbered-3.c @@ -4,7 +4,7 @@ void bar (void); float a; -float +NOMIPS16 float foo () { float b = a + 1.0f; diff --git a/gcc/testsuite/gcc.target/mips/call-clobbered-5.c b/gcc/testsuite/gcc.target/mips/call-clobbered-5.c index c7cd7cac7dd..b9ca58746f6 100644 --- a/gcc/testsuite/gcc.target/mips/call-clobbered-5.c +++ b/gcc/testsuite/gcc.target/mips/call-clobbered-5.c @@ -4,7 +4,7 @@ void bar (void); float a; -float +NOMIPS16 float foo () { float b = a + 1.0f; diff --git a/gcc/testsuite/gcc.target/mips/ds-schedule-2.c b/gcc/testsuite/gcc.target/mips/ds-schedule-2.c index 6c5de5dac92..3cb3c593765 100644 --- a/gcc/testsuite/gcc.target/mips/ds-schedule-2.c +++ b/gcc/testsuite/gcc.target/mips/ds-schedule-2.c @@ -1,4 +1,4 @@ -/* { dg-options "-mcompact-branches=never -mno-abicalls -G4" } */ +/* { dg-options "-mcompact-branches=never -mno-mips16 -mno-abicalls -G4" } */ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-O1" "-Os" } { "" } } */ /* { dg-final { scan-assembler "beq.*\n\tlw" } } */ /* { dg-final { scan-assembler-times "\\(foo\\)" 2 } } */ @@ -19,7 +19,7 @@ int foo; extern void t (int, int, int*); -void +NOMIPS16 void f (struct list **ptr) { if (gr) diff --git a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c index 083e1524450..d8412f17876 100644 --- a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c +++ b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c @@ -2,7 +2,7 @@ int foo; int bar; -void __attribute__ ((interrupt)) +NOMIPS16 void __attribute__ ((interrupt)) isr (void) { if (!foo) diff --git a/gcc/testsuite/gcc.target/mips/movdf-1.c b/gcc/testsuite/gcc.target/mips/movdf-1.c index f0267d00e97..5fe61807d56 100644 --- a/gcc/testsuite/gcc.target/mips/movdf-1.c +++ b/gcc/testsuite/gcc.target/mips/movdf-1.c @@ -4,7 +4,7 @@ void bar (void); -double +NOMIPS16 double foo (int x, double a) { return a; diff --git a/gcc/testsuite/gcc.target/mips/movdf-2.c b/gcc/testsuite/gcc.target/mips/movdf-2.c index 175b61c7e77..0e52c9fec7a 100644 --- a/gcc/testsuite/gcc.target/mips/movdf-2.c +++ b/gcc/testsuite/gcc.target/mips/movdf-2.c @@ -4,7 +4,7 @@ void bar (void); -double +NOMIPS16 double foo (int x, double a) { return a; diff --git a/gcc/testsuite/gcc.target/mips/movdf-3.c b/gcc/testsuite/gcc.target/mips/movdf-3.c index 5db52c9487b..f1dd2abf5ec 100644 --- a/gcc/testsuite/gcc.target/mips/movdf-3.c +++ b/gcc/testsuite/gcc.target/mips/movdf-3.c @@ -4,7 +4,7 @@ void bar (void); -double +NOMIPS16 double foo (int x, double a) { return a; diff --git a/gcc/testsuite/gcc.target/mips/msa-builtins.c b/gcc/testsuite/gcc.target/mips/msa-builtins.c index 6a146b3e6ae..932cc8db961 100644 --- a/gcc/testsuite/gcc.target/mips/msa-builtins.c +++ b/gcc/testsuite/gcc.target/mips/msa-builtins.c @@ -1,6 +1,6 @@ /* Test builtins for MIPS MSA ASE instructions */ /* { dg-do compile } */ -/* { dg-options "-mfp64 -mhard-float -mmsa" } */ +/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */ /* { dg-final { scan-assembler-times "msa_addv_b:.*addv\\.b.*msa_addv_b" 1 } } */ /* { dg-final { scan-assembler-times "msa_addv_h:.*addv\\.h.*msa_addv_h" 1 } } */ @@ -641,182 +641,182 @@ #define FN(NAME, T) FN_EVAL (NAME, T) /* MSA Arithmetic builtins. */ -#define ADDV(T) NOMIPS16 T FN (addv, T ## _DF) (T i, T j) { return BUILTIN (addv, T ## _DF) (i, j); } -#define ADDVI(T) NOMIPS16 T FN (addvi, T ## _DF) (T i) { return BUILTIN (addvi, T ## _DF) (i, U5MAX); } -#define ADD_A(T) NOMIPS16 T FN (add_a, T ## _DF) (T i, T j) { return BUILTIN (add_a, T ## _DF) (i, j); } -#define ADDS_A(T) NOMIPS16 T FN (adds_a, T ## _DF) (T i, T j) { return BUILTIN (adds_a, T ## _DF) (i, j); } -#define ADDS_S(T) NOMIPS16 T FN (adds_s, T ## _DF) (T i, T j) { return BUILTIN (adds_s, T ## _DF) (i, j); } -#define ADDS_U(T) NOMIPS16 T FN (adds_u, T ## _DF) (T i, T j) { return BUILTIN (adds_u, T ## _DF) (i, j); } -#define HADD_S(T) NOMIPS16 T ## _DBL FN (hadd_s, T ## _DDF) (T i, T j) { return BUILTIN (hadd_s, T ## _DDF) (i, j); } -#define HADD_U(T) NOMIPS16 T ## _DBL FN (hadd_u, T ## _DDF) (T i, T j) { return BUILTIN (hadd_u, T ## _DDF) (i, j); } -#define ASUB_S(T) NOMIPS16 T FN (asub_s, T ## _DF) (T i, T j) { return BUILTIN (asub_s, T ## _DF) (i, j); } -#define ASUB_U(T) NOMIPS16 T FN (asub_u, T ## _DF) (T i, T j) { return BUILTIN (asub_u, T ## _DF) (i, j); } -#define AVE_S(T) NOMIPS16 T FN (ave_s, T ## _DF) (T i, T j) { return BUILTIN (ave_s, T ## _DF) (i, j); } -#define AVE_U(T) NOMIPS16 T FN (ave_u, T ## _DF) (T i, T j) { return BUILTIN (ave_u, T ## _DF) (i, j); } -#define AVER_S(T) NOMIPS16 T FN (aver_s, T ## _DF) (T i, T j) { return BUILTIN (aver_s, T ## _DF) (i, j); } -#define AVER_U(T) NOMIPS16 T FN (aver_u, T ## _DF) (T i, T j) { return BUILTIN (aver_u, T ## _DF) (i, j); } -#define DOTP_S(T) NOMIPS16 T ## _DBL FN (dotp_s, T ## _DDF) (T i, T j) { return BUILTIN (dotp_s, T ## _DDF) (i, j); } -#define DOTP_U(T) NOMIPS16 T ## _DBL FN (dotp_u, T ## _DDF) (T i, T j) { return BUILTIN (dotp_u, T ## _DDF) (i, j); } -#define DPADD_S(T) NOMIPS16 T ## _DBL FN (dpadd_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_s, T ## _DDF) (i, j, k); } -#define DPADD_U(T) NOMIPS16 T ## _DBL FN (dpadd_u, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_u, T ## _DDF) (i, j, k); } -#define DPSUB_S(T) NOMIPS16 T ## _DBL FN (dpsub_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpsub_s, T ## _DDF) (i, j, k); } -#define DPSUB_U(T) NOMIPS16 T ## _SDBL FN (dpsub_u, T ## _DDF) (T ## _SDBL i, T j, T k) { return BUILTIN (dpsub_u, T ## _DDF) (i, j, k); } -#define DIV_S(T) NOMIPS16 T FN (div_s, T ## _DF) (T i, T j) { return BUILTIN (div_s, T ## _DF) (i, j); } -#define DIV_U(T) NOMIPS16 T FN (div_u, T ## _DF) (T i, T j) { return BUILTIN (div_u, T ## _DF) (i, j); } -#define MADDV(T) NOMIPS16 T FN (maddv, T ## _DF) (T i, T j, T k) { return BUILTIN (maddv, T ## _DF) (i, j, k); } -#define MAX_A(T) NOMIPS16 T FN (max_a, T ## _DF) (T i, T j) { return BUILTIN (max_a, T ## _DF) (i, j); } -#define MIN_A(T) NOMIPS16 T FN (min_a, T ## _DF) (T i, T j) { return BUILTIN (min_a, T ## _DF) (i, j); } -#define MAX_S(T) NOMIPS16 T FN (max_s, T ## _DF) (T i, T j) { return BUILTIN (max_s, T ## _DF) (i, j); } -#define MAXI_S(T) NOMIPS16 T FN (maxi_s, T ## _DF) (T i) { return BUILTIN (maxi_s, T ## _DF) (i, S5MAX); } -#define MAX_U(T) NOMIPS16 T FN (max_u, T ## _DF) (T i, T j) { return BUILTIN (max_u, T ## _DF) (i, j); } -#define MAXI_U(T) NOMIPS16 T FN (maxi_u, T ## _DF) (T i) { return BUILTIN (maxi_u, T ## _DF) (i, S5MAX); } -#define MIN_S(T) NOMIPS16 T FN (min_s, T ## _DF) (T i, T j) { return BUILTIN (min_s, T ## _DF) (i, j); } -#define MINI_S(T) NOMIPS16 T FN (mini_s, T ## _DF) (T i) { return BUILTIN (mini_s, T ## _DF) (i, S5MAX); } -#define MIN_U(T) NOMIPS16 T FN (min_u, T ## _DF) (T i, T j) { return BUILTIN (min_u, T ## _DF) (i, j); } -#define MINI_U(T) NOMIPS16 T FN (mini_u, T ## _DF) (T i) { return BUILTIN (mini_u, T ## _DF) (i, S5MAX); } -#define MSUBV(T) NOMIPS16 T FN (msubv, T ## _DF) (T i, T j, T k) { return BUILTIN (msubv, T ## _DF) (i, j, k); } -#define MULV(T) NOMIPS16 T FN (mulv, T ## _DF) (T i, T j) { return BUILTIN (mulv, T ## _DF) (i, j); } -#define MOD_S(T) NOMIPS16 T FN (mod_s, T ## _DF) (T i, T j) { return BUILTIN (mod_s, T ## _DF) (i, j); } -#define MOD_U(T) NOMIPS16 T FN (mod_u, T ## _DF) (T i, T j) { return BUILTIN (mod_u, T ## _DF) (i, j); } -#define SAT_S(T) NOMIPS16 T FN (sat_s, T ## _DF) (T i) { return BUILTIN (sat_s, T ## _DF) (i, 7); } -#define SAT_U(T) NOMIPS16 T FN (sat_u, T ## _DF) (T i) { return BUILTIN (sat_u, T ## _DF) (i, 7); } -#define SUBS_S(T) NOMIPS16 T FN (subs_s, T ## _DF) (T i, T j) { return BUILTIN (subs_s, T ## _DF) (i, j); } -#define SUBS_U(T) NOMIPS16 T FN (subs_u, T ## _DF) (T i, T j) { return BUILTIN (subs_u, T ## _DF) (i, j); } -#define HSUB_S(T) NOMIPS16 T ## _DBL FN (hsub_s, T ## _DDF) (T i, T j) { return BUILTIN (hsub_s, T ## _DDF) (i, j); } -#define HSUB_U(T) NOMIPS16 T ## _SDBL FN (hsub_u, T ## _DDF) (T i, T j) { return BUILTIN (hsub_u, T ## _DDF) (i, j); } -#define SUBSUU_S(T) NOMIPS16 T ## _S FN (subsuu_s, T ## _DF) (T i, T j) { return BUILTIN (subsuu_s, T ## _DF) (i, j); } -#define SUBSUS_U(T) NOMIPS16 T FN (subsus_u, T ## _DF) (T i, T ## _S j) { return BUILTIN (subsus_u, T ## _DF) (i, j); } -#define SUBV(T) NOMIPS16 T FN (subv, T ## _DF) (T i, T j) { return BUILTIN (subv, T ## _DF) (i, j); } -#define SUBVI(T) NOMIPS16 T FN (subvi, T ## _DF) (T i) { return BUILTIN (subvi, T ## _DF) (i, U5MAX); } +#define ADDV(T) T FN (addv, T ## _DF) (T i, T j) { return BUILTIN (addv, T ## _DF) (i, j); } +#define ADDVI(T) T FN (addvi, T ## _DF) (T i) { return BUILTIN (addvi, T ## _DF) (i, U5MAX); } +#define ADD_A(T) T FN (add_a, T ## _DF) (T i, T j) { return BUILTIN (add_a, T ## _DF) (i, j); } +#define ADDS_A(T) T FN (adds_a, T ## _DF) (T i, T j) { return BUILTIN (adds_a, T ## _DF) (i, j); } +#define ADDS_S(T) T FN (adds_s, T ## _DF) (T i, T j) { return BUILTIN (adds_s, T ## _DF) (i, j); } +#define ADDS_U(T) T FN (adds_u, T ## _DF) (T i, T j) { return BUILTIN (adds_u, T ## _DF) (i, j); } +#define HADD_S(T) T ## _DBL FN (hadd_s, T ## _DDF) (T i, T j) { return BUILTIN (hadd_s, T ## _DDF) (i, j); } +#define HADD_U(T) T ## _DBL FN (hadd_u, T ## _DDF) (T i, T j) { return BUILTIN (hadd_u, T ## _DDF) (i, j); } +#define ASUB_S(T) T FN (asub_s, T ## _DF) (T i, T j) { return BUILTIN (asub_s, T ## _DF) (i, j); } +#define ASUB_U(T) T FN (asub_u, T ## _DF) (T i, T j) { return BUILTIN (asub_u, T ## _DF) (i, j); } +#define AVE_S(T) T FN (ave_s, T ## _DF) (T i, T j) { return BUILTIN (ave_s, T ## _DF) (i, j); } +#define AVE_U(T) T FN (ave_u, T ## _DF) (T i, T j) { return BUILTIN (ave_u, T ## _DF) (i, j); } +#define AVER_S(T) T FN (aver_s, T ## _DF) (T i, T j) { return BUILTIN (aver_s, T ## _DF) (i, j); } +#define AVER_U(T) T FN (aver_u, T ## _DF) (T i, T j) { return BUILTIN (aver_u, T ## _DF) (i, j); } +#define DOTP_S(T) T ## _DBL FN (dotp_s, T ## _DDF) (T i, T j) { return BUILTIN (dotp_s, T ## _DDF) (i, j); } +#define DOTP_U(T) T ## _DBL FN (dotp_u, T ## _DDF) (T i, T j) { return BUILTIN (dotp_u, T ## _DDF) (i, j); } +#define DPADD_S(T) T ## _DBL FN (dpadd_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_s, T ## _DDF) (i, j, k); } +#define DPADD_U(T) T ## _DBL FN (dpadd_u, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpadd_u, T ## _DDF) (i, j, k); } +#define DPSUB_S(T) T ## _DBL FN (dpsub_s, T ## _DDF) (T ## _DBL i, T j, T k) { return BUILTIN (dpsub_s, T ## _DDF) (i, j, k); } +#define DPSUB_U(T) T ## _SDBL FN (dpsub_u, T ## _DDF) (T ## _SDBL i, T j, T k) { return BUILTIN (dpsub_u, T ## _DDF) (i, j, k); } +#define DIV_S(T) T FN (div_s, T ## _DF) (T i, T j) { return BUILTIN (div_s, T ## _DF) (i, j); } +#define DIV_U(T) T FN (div_u, T ## _DF) (T i, T j) { return BUILTIN (div_u, T ## _DF) (i, j); } +#define MADDV(T) T FN (maddv, T ## _DF) (T i, T j, T k) { return BUILTIN (maddv, T ## _DF) (i, j, k); } +#define MAX_A(T) T FN (max_a, T ## _DF) (T i, T j) { return BUILTIN (max_a, T ## _DF) (i, j); } +#define MIN_A(T) T FN (min_a, T ## _DF) (T i, T j) { return BUILTIN (min_a, T ## _DF) (i, j); } +#define MAX_S(T) T FN (max_s, T ## _DF) (T i, T j) { return BUILTIN (max_s, T ## _DF) (i, j); } +#define MAXI_S(T) T FN (maxi_s, T ## _DF) (T i) { return BUILTIN (maxi_s, T ## _DF) (i, S5MAX); } +#define MAX_U(T) T FN (max_u, T ## _DF) (T i, T j) { return BUILTIN (max_u, T ## _DF) (i, j); } +#define MAXI_U(T) T FN (maxi_u, T ## _DF) (T i) { return BUILTIN (maxi_u, T ## _DF) (i, S5MAX); } +#define MIN_S(T) T FN (min_s, T ## _DF) (T i, T j) { return BUILTIN (min_s, T ## _DF) (i, j); } +#define MINI_S(T) T FN (mini_s, T ## _DF) (T i) { return BUILTIN (mini_s, T ## _DF) (i, S5MAX); } +#define MIN_U(T) T FN (min_u, T ## _DF) (T i, T j) { return BUILTIN (min_u, T ## _DF) (i, j); } +#define MINI_U(T) T FN (mini_u, T ## _DF) (T i) { return BUILTIN (mini_u, T ## _DF) (i, S5MAX); } +#define MSUBV(T) T FN (msubv, T ## _DF) (T i, T j, T k) { return BUILTIN (msubv, T ## _DF) (i, j, k); } +#define MULV(T) T FN (mulv, T ## _DF) (T i, T j) { return BUILTIN (mulv, T ## _DF) (i, j); } +#define MOD_S(T) T FN (mod_s, T ## _DF) (T i, T j) { return BUILTIN (mod_s, T ## _DF) (i, j); } +#define MOD_U(T) T FN (mod_u, T ## _DF) (T i, T j) { return BUILTIN (mod_u, T ## _DF) (i, j); } +#define SAT_S(T) T FN (sat_s, T ## _DF) (T i) { return BUILTIN (sat_s, T ## _DF) (i, 7); } +#define SAT_U(T) T FN (sat_u, T ## _DF) (T i) { return BUILTIN (sat_u, T ## _DF) (i, 7); } +#define SUBS_S(T) T FN (subs_s, T ## _DF) (T i, T j) { return BUILTIN (subs_s, T ## _DF) (i, j); } +#define SUBS_U(T) T FN (subs_u, T ## _DF) (T i, T j) { return BUILTIN (subs_u, T ## _DF) (i, j); } +#define HSUB_S(T) T ## _DBL FN (hsub_s, T ## _DDF) (T i, T j) { return BUILTIN (hsub_s, T ## _DDF) (i, j); } +#define HSUB_U(T) T ## _SDBL FN (hsub_u, T ## _DDF) (T i, T j) { return BUILTIN (hsub_u, T ## _DDF) (i, j); } +#define SUBSUU_S(T) T ## _S FN (subsuu_s, T ## _DF) (T i, T j) { return BUILTIN (subsuu_s, T ## _DF) (i, j); } +#define SUBSUS_U(T) T FN (subsus_u, T ## _DF) (T i, T ## _S j) { return BUILTIN (subsus_u, T ## _DF) (i, j); } +#define SUBV(T) T FN (subv, T ## _DF) (T i, T j) { return BUILTIN (subv, T ## _DF) (i, j); } +#define SUBVI(T) T FN (subvi, T ## _DF) (T i) { return BUILTIN (subvi, T ## _DF) (i, U5MAX); } /* MSA Bitwise builtins. */ -#define AND(T) NOMIPS16 T FN (and, v) (T i, T j) { return BUILTIN (and, v) (i, j); } -#define ANDI(T) NOMIPS16 T FN (andi, T ## _DF) (T i) { return BUILTIN (andi, T ## _DF) (i, 252); } -#define BCLR(T) NOMIPS16 T FN (bclr, T ## _DF) (T i, T j) { return BUILTIN (bclr, T ## _DF) (i, j); } -#define BCLRI(T) NOMIPS16 T FN (bclri, T ## _DF) (T i) { return BUILTIN (bclri, T ## _DF) (i, 0); } -#define BINSL(T) NOMIPS16 T FN (binsl, T ## _DF) (T i, T j, T k) { return BUILTIN (binsl, T ## _DF) (i, j, k); } -#define BINSLI(T) NOMIPS16 T FN (binsli, T ## _DF) (T i, T j) { return BUILTIN (binsli, T ## _DF) (i, j, 0); } -#define BINSR(T) NOMIPS16 T FN (binsr, T ## _DF) (T i, T j, T k) { return BUILTIN (binsr, T ## _DF) (i, j, k); } -#define BINSRI(T) NOMIPS16 T FN (binsri, T ## _DF) (T i, T j) { return BUILTIN (binsri, T ## _DF) (i, j, 0); } -#define BMNZ(T) NOMIPS16 T FN (bmnz, v) (T i, T j, T k) { return BUILTIN (bmnz, v) (i, j, k); } -#define BMNZI(T) NOMIPS16 T FN (bmnzi, T ## _DF) (T i, T j) { return BUILTIN (bmnzi, T ## _DF) (i, j, 254); } -#define BMZ(T) NOMIPS16 T FN (bmz, v) (T i, T j, T k) { return BUILTIN (bmz, v) (i, j, k); } -#define BMZI(T) NOMIPS16 T FN (bmzi, T ## _DF) (T i, T j) { return BUILTIN (bmzi, T ## _DF) (i, j, 254); } -#define BNEG(T) NOMIPS16 T FN (bneg, T ## _DF) (T i, T j) { return BUILTIN (bneg, T ## _DF) (i, j); } -#define BNEGI(T) NOMIPS16 T FN (bnegi, T ## _DF) (T i) { return BUILTIN (bnegi, T ## _DF) (i, 0); } -#define BSEL(T) NOMIPS16 T FN (bsel, v) (T i, T j, T k) { return BUILTIN (bsel, v) (i, j, k); } -#define BSELI(T) NOMIPS16 T FN (bseli, T ## _DF) (T i, T j) { return BUILTIN (bseli, T ## _DF) (i, j, U8MAX-1); } -#define BSET(T) NOMIPS16 T FN (bset, T ## _DF) (T i, T j) { return BUILTIN (bset, T ## _DF) (i, j); } -#define BSETI(T) NOMIPS16 T FN (bseti, T ## _DF) (T i) { return BUILTIN (bseti, T ## _DF) (i, 0); } -#define NLOC(T) NOMIPS16 T FN (nloc, T ## _DF) (T i) { return BUILTIN (nloc, T ## _DF) (i); } -#define NLZC(T) NOMIPS16 T FN (nlzc, T ## _DF) (T i) { return BUILTIN (nlzc, T ## _DF) (i); } -#define NOR(T) NOMIPS16 T FN (nor, v) (T i, T j) { return BUILTIN (nor, v) (i, j); } -#define NORI(T) NOMIPS16 T FN (nori, T ## _DF) (T i) { return BUILTIN (nori, T ## _DF) (i, 254); } -#define PCNT(T) NOMIPS16 T FN (pcnt, T ## _DF) (T i) { return BUILTIN (pcnt, T ## _DF) (i); } -#define OR(T) NOMIPS16 T FN (or, v) (T i, T j) { return BUILTIN (or, v) (i, j); } -#define ORI(T) NOMIPS16 T FN (ori, T ## _DF) (T i) { return BUILTIN (ori, T ## _DF) (i, 252); } -#define XOR(T) NOMIPS16 T FN (xor, v) (T i, T j) { return BUILTIN (xor, v) (i, j); } -#define XORI(T) NOMIPS16 T FN (xori, T ## _DF) (T i) { return BUILTIN (xori, T ## _DF) (i, 254); } -#define SLL(T) NOMIPS16 T FN (sll, T ## _DF) (T i, T j) { return BUILTIN (sll, T ## _DF) (i, j); } -#define SLLI(T) NOMIPS16 T FN (slli, T ## _DF) (T i) { return BUILTIN (slli, T ## _DF) (i, 1); } -#define SRA(T) NOMIPS16 T FN (sra, T ## _DF) (T i, T j) { return BUILTIN (sra, T ## _DF) (i, j); } -#define SRAI(T) NOMIPS16 T FN (srai, T ## _DF) (T i) { return BUILTIN (srai, T ## _DF) (i, 1); } -#define SRAR(T) NOMIPS16 T FN (srar, T ## _DF) (T i, T j) { return BUILTIN (srar, T ## _DF) (i, j); } -#define SRARI(T) NOMIPS16 T FN (srari, T ## _DF) (T i) { return BUILTIN (srari, T ## _DF) (i, 0); } -#define SRL(T) NOMIPS16 T FN (srl, T ## _DF) (T i, T j) { return BUILTIN (srl, T ## _DF) (i, j); } -#define SRLI(T) NOMIPS16 T FN (srli, T ## _DF) (T i) { return BUILTIN (srli, T ## _DF) (i, 1); } -#define SRLR(T) NOMIPS16 T FN (srlr, T ## _DF) (T i, T j) { return BUILTIN (srlr, T ## _DF) (i, j); } -#define SRLRI(T) NOMIPS16 T FN (srlri, T ## _DF) (T i) { return BUILTIN (srlri, T ## _DF) (i, 0); } +#define AND(T) T FN (and, v) (T i, T j) { return BUILTIN (and, v) (i, j); } +#define ANDI(T) T FN (andi, T ## _DF) (T i) { return BUILTIN (andi, T ## _DF) (i, 252); } +#define BCLR(T) T FN (bclr, T ## _DF) (T i, T j) { return BUILTIN (bclr, T ## _DF) (i, j); } +#define BCLRI(T) T FN (bclri, T ## _DF) (T i) { return BUILTIN (bclri, T ## _DF) (i, 0); } +#define BINSL(T) T FN (binsl, T ## _DF) (T i, T j, T k) { return BUILTIN (binsl, T ## _DF) (i, j, k); } +#define BINSLI(T) T FN (binsli, T ## _DF) (T i, T j) { return BUILTIN (binsli, T ## _DF) (i, j, 0); } +#define BINSR(T) T FN (binsr, T ## _DF) (T i, T j, T k) { return BUILTIN (binsr, T ## _DF) (i, j, k); } +#define BINSRI(T) T FN (binsri, T ## _DF) (T i, T j) { return BUILTIN (binsri, T ## _DF) (i, j, 0); } +#define BMNZ(T) T FN (bmnz, v) (T i, T j, T k) { return BUILTIN (bmnz, v) (i, j, k); } +#define BMNZI(T) T FN (bmnzi, T ## _DF) (T i, T j) { return BUILTIN (bmnzi, T ## _DF) (i, j, 254); } +#define BMZ(T) T FN (bmz, v) (T i, T j, T k) { return BUILTIN (bmz, v) (i, j, k); } +#define BMZI(T) T FN (bmzi, T ## _DF) (T i, T j) { return BUILTIN (bmzi, T ## _DF) (i, j, 254); } +#define BNEG(T) T FN (bneg, T ## _DF) (T i, T j) { return BUILTIN (bneg, T ## _DF) (i, j); } +#define BNEGI(T) T FN (bnegi, T ## _DF) (T i) { return BUILTIN (bnegi, T ## _DF) (i, 0); } +#define BSEL(T) T FN (bsel, v) (T i, T j, T k) { return BUILTIN (bsel, v) (i, j, k); } +#define BSELI(T) T FN (bseli, T ## _DF) (T i, T j) { return BUILTIN (bseli, T ## _DF) (i, j, U8MAX-1); } +#define BSET(T) T FN (bset, T ## _DF) (T i, T j) { return BUILTIN (bset, T ## _DF) (i, j); } +#define BSETI(T) T FN (bseti, T ## _DF) (T i) { return BUILTIN (bseti, T ## _DF) (i, 0); } +#define NLOC(T) T FN (nloc, T ## _DF) (T i) { return BUILTIN (nloc, T ## _DF) (i); } +#define NLZC(T) T FN (nlzc, T ## _DF) (T i) { return BUILTIN (nlzc, T ## _DF) (i); } +#define NOR(T) T FN (nor, v) (T i, T j) { return BUILTIN (nor, v) (i, j); } +#define NORI(T) T FN (nori, T ## _DF) (T i) { return BUILTIN (nori, T ## _DF) (i, 254); } +#define PCNT(T) T FN (pcnt, T ## _DF) (T i) { return BUILTIN (pcnt, T ## _DF) (i); } +#define OR(T) T FN (or, v) (T i, T j) { return BUILTIN (or, v) (i, j); } +#define ORI(T) T FN (ori, T ## _DF) (T i) { return BUILTIN (ori, T ## _DF) (i, 252); } +#define XOR(T) T FN (xor, v) (T i, T j) { return BUILTIN (xor, v) (i, j); } +#define XORI(T) T FN (xori, T ## _DF) (T i) { return BUILTIN (xori, T ## _DF) (i, 254); } +#define SLL(T) T FN (sll, T ## _DF) (T i, T j) { return BUILTIN (sll, T ## _DF) (i, j); } +#define SLLI(T) T FN (slli, T ## _DF) (T i) { return BUILTIN (slli, T ## _DF) (i, 1); } +#define SRA(T) T FN (sra, T ## _DF) (T i, T j) { return BUILTIN (sra, T ## _DF) (i, j); } +#define SRAI(T) T FN (srai, T ## _DF) (T i) { return BUILTIN (srai, T ## _DF) (i, 1); } +#define SRAR(T) T FN (srar, T ## _DF) (T i, T j) { return BUILTIN (srar, T ## _DF) (i, j); } +#define SRARI(T) T FN (srari, T ## _DF) (T i) { return BUILTIN (srari, T ## _DF) (i, 0); } +#define SRL(T) T FN (srl, T ## _DF) (T i, T j) { return BUILTIN (srl, T ## _DF) (i, j); } +#define SRLI(T) T FN (srli, T ## _DF) (T i) { return BUILTIN (srli, T ## _DF) (i, 1); } +#define SRLR(T) T FN (srlr, T ## _DF) (T i, T j) { return BUILTIN (srlr, T ## _DF) (i, j); } +#define SRLRI(T) T FN (srlri, T ## _DF) (T i) { return BUILTIN (srlri, T ## _DF) (i, 0); } /* MSA Floating-Point Arithmetic builtins. */ -#define FADD(T) NOMIPS16 T FN (fadd, T ## _DF) (T i, T j) { return BUILTIN (fadd, T ## _DF) (i, j); } -#define FDIV(T) NOMIPS16 T FN (fdiv, T ## _DF) (T i, T j) { return BUILTIN (fdiv, T ## _DF) (i, j); } -#define FEXP2(T) NOMIPS16 T FN (fexp2, T ## _DF) (T i, T ## _FEXP2 j) { return BUILTIN (fexp2, T ## _DF) (i, j); } -#define FLOG2(T) NOMIPS16 T FN (flog2, T ## _DF) (T i) { return BUILTIN (flog2, T ## _DF) (i); } -#define FMADD(T) NOMIPS16 T FN (fmadd, T ## _DF) (T i, T j, T k) { return BUILTIN (fmadd, T ## _DF) (i, j, k); } -#define FMSUB(T) NOMIPS16 T FN (fmsub, T ## _DF) (T i, T j, T k) { return BUILTIN (fmsub, T ## _DF) (i, j, k); } -#define FMAX(T) NOMIPS16 T FN (fmax, T ## _DF) (T i, T j) { return BUILTIN (fmax, T ## _DF) (i, j); } -#define FMIN(T) NOMIPS16 T FN (fmin, T ## _DF) (T i, T j) { return BUILTIN (fmin, T ## _DF) (i, j); } -#define FMAX_A(T) NOMIPS16 T FN (fmax_a, T ## _DF) (T i, T j) { return BUILTIN (fmax_a, T ## _DF) (i, j); } -#define FMIN_A(T) NOMIPS16 T FN (fmin_a, T ## _DF) (T i, T j) { return BUILTIN (fmin_a, T ## _DF) (i, j); } -#define FMUL(T) NOMIPS16 T FN (fmul, T ## _DF) (T i, T j) { return BUILTIN (fmul, T ## _DF) (i, j); } -#define FRCP(T) NOMIPS16 T FN (frcp, T ## _DF) (T i) { return BUILTIN (frcp, T ## _DF) (i); } -#define FRINT(T) NOMIPS16 T FN (frint, T ## _DF) (T i) { return BUILTIN (frint, T ## _DF) (i); } -#define FRSQRT(T) NOMIPS16 T FN (frsqrt, T ## _DF) (T i) { return BUILTIN (frsqrt, T ## _DF) (i); } -#define FSQRT(T) NOMIPS16 T FN (fsqrt, T ## _DF) (T i) { return BUILTIN (fsqrt, T ## _DF) (i); } -#define FSUB(T) NOMIPS16 T FN (fsub, T ## _DF) (T i, T j) { return BUILTIN (fsub, T ## _DF) (i, j); } +#define FADD(T) T FN (fadd, T ## _DF) (T i, T j) { return BUILTIN (fadd, T ## _DF) (i, j); } +#define FDIV(T) T FN (fdiv, T ## _DF) (T i, T j) { return BUILTIN (fdiv, T ## _DF) (i, j); } +#define FEXP2(T) T FN (fexp2, T ## _DF) (T i, T ## _FEXP2 j) { return BUILTIN (fexp2, T ## _DF) (i, j); } +#define FLOG2(T) T FN (flog2, T ## _DF) (T i) { return BUILTIN (flog2, T ## _DF) (i); } +#define FMADD(T) T FN (fmadd, T ## _DF) (T i, T j, T k) { return BUILTIN (fmadd, T ## _DF) (i, j, k); } +#define FMSUB(T) T FN (fmsub, T ## _DF) (T i, T j, T k) { return BUILTIN (fmsub, T ## _DF) (i, j, k); } +#define FMAX(T) T FN (fmax, T ## _DF) (T i, T j) { return BUILTIN (fmax, T ## _DF) (i, j); } +#define FMIN(T) T FN (fmin, T ## _DF) (T i, T j) { return BUILTIN (fmin, T ## _DF) (i, j); } +#define FMAX_A(T) T FN (fmax_a, T ## _DF) (T i, T j) { return BUILTIN (fmax_a, T ## _DF) (i, j); } +#define FMIN_A(T) T FN (fmin_a, T ## _DF) (T i, T j) { return BUILTIN (fmin_a, T ## _DF) (i, j); } +#define FMUL(T) T FN (fmul, T ## _DF) (T i, T j) { return BUILTIN (fmul, T ## _DF) (i, j); } +#define FRCP(T) T FN (frcp, T ## _DF) (T i) { return BUILTIN (frcp, T ## _DF) (i); } +#define FRINT(T) T FN (frint, T ## _DF) (T i) { return BUILTIN (frint, T ## _DF) (i); } +#define FRSQRT(T) T FN (frsqrt, T ## _DF) (T i) { return BUILTIN (frsqrt, T ## _DF) (i); } +#define FSQRT(T) T FN (fsqrt, T ## _DF) (T i) { return BUILTIN (fsqrt, T ## _DF) (i); } +#define FSUB(T) T FN (fsub, T ## _DF) (T i, T j) { return BUILTIN (fsub, T ## _DF) (i, j); } /* MSA Floating-Point Compare builtins. */ -#define FCLASS(T) NOMIPS16 T ## _FRES FN (fclass, T ## _DF) (T i) { return BUILTIN (fclass, T ## _DF) (i); } -#define FCAF(T) NOMIPS16 T ## _FRES FN (fcaf, T ## _DF) (T i, T j) { return BUILTIN (fcaf, T ## _DF) (i, j); } -#define FCUN(T) NOMIPS16 T ## _FRES FN (fcun, T ## _DF) (T i, T j) { return BUILTIN (fcun, T ## _DF) (i, j); } -#define FCOR(T) NOMIPS16 T ## _FRES FN (fcor, T ## _DF) (T i, T j) { return BUILTIN (fcor, T ## _DF) (i, j); } -#define FCEQ(T) NOMIPS16 T ## _FRES FN (fceq, T ## _DF) (T i, T j) { return BUILTIN (fceq, T ## _DF) (i, j); } -#define FCUNE(T) NOMIPS16 T ## _FRES FN (fcune, T ## _DF) (T i, T j) { return BUILTIN (fcune, T ## _DF) (i, j); } -#define FCUEQ(T) NOMIPS16 T ## _FRES FN (fcueq, T ## _DF) (T i, T j) { return BUILTIN (fcueq, T ## _DF) (i, j); } -#define FCNE(T) NOMIPS16 T ## _FRES FN (fcne, T ## _DF) (T i, T j) { return BUILTIN (fcne, T ## _DF) (i, j); } -#define FCLT(T) NOMIPS16 T ## _FRES FN (fclt, T ## _DF) (T i, T j) { return BUILTIN (fclt, T ## _DF) (i, j); } -#define FCULT(T) NOMIPS16 T ## _FRES FN (fcult, T ## _DF) (T i, T j) { return BUILTIN (fcult, T ## _DF) (i, j); } -#define FCLE(T) NOMIPS16 T ## _FRES FN (fcle, T ## _DF) (T i, T j) { return BUILTIN (fcle, T ## _DF) (i, j); } -#define FCULE(T) NOMIPS16 T ## _FRES FN (fcule, T ## _DF) (T i, T j) { return BUILTIN (fcule, T ## _DF) (i, j); } -#define FSAF(T) NOMIPS16 T ## _FRES FN (fsaf, T ## _DF) (T i, T j) { return BUILTIN (fsaf, T ## _DF) (i, j); } -#define FSUN(T) NOMIPS16 T ## _FRES FN (fsun, T ## _DF) (T i, T j) { return BUILTIN (fsun, T ## _DF) (i, j); } -#define FSOR(T) NOMIPS16 T ## _FRES FN (fsor, T ## _DF) (T i, T j) { return BUILTIN (fsor, T ## _DF) (i, j); } -#define FSEQ(T) NOMIPS16 T ## _FRES FN (fseq, T ## _DF) (T i, T j) { return BUILTIN (fseq, T ## _DF) (i, j); } -#define FSUNE(T) NOMIPS16 T ## _FRES FN (fsune, T ## _DF) (T i, T j) { return BUILTIN (fsune, T ## _DF) (i, j); } -#define FSUEQ(T) NOMIPS16 T ## _FRES FN (fsueq, T ## _DF) (T i, T j) { return BUILTIN (fsueq, T ## _DF) (i, j); } -#define FSNE(T) NOMIPS16 T ## _FRES FN (fsne, T ## _DF) (T i, T j) { return BUILTIN (fsne, T ## _DF) (i, j); } -#define FSLT(T) NOMIPS16 T ## _FRES FN (fslt, T ## _DF) (T i, T j) { return BUILTIN (fslt, T ## _DF) (i, j); } -#define FSULT(T) NOMIPS16 T ## _FRES FN (fsult, T ## _DF) (T i, T j) { return BUILTIN (fsult, T ## _DF) (i, j); } -#define FSLE(T) NOMIPS16 T ## _FRES FN (fsle, T ## _DF) (T i, T j) { return BUILTIN (fsle, T ## _DF) (i, j); } -#define FSULE(T) NOMIPS16 T ## _FRES FN (fsule, T ## _DF) (T i, T j) { return BUILTIN (fsule, T ## _DF) (i, j); } +#define FCLASS(T) T ## _FRES FN (fclass, T ## _DF) (T i) { return BUILTIN (fclass, T ## _DF) (i); } +#define FCAF(T) T ## _FRES FN (fcaf, T ## _DF) (T i, T j) { return BUILTIN (fcaf, T ## _DF) (i, j); } +#define FCUN(T) T ## _FRES FN (fcun, T ## _DF) (T i, T j) { return BUILTIN (fcun, T ## _DF) (i, j); } +#define FCOR(T) T ## _FRES FN (fcor, T ## _DF) (T i, T j) { return BUILTIN (fcor, T ## _DF) (i, j); } +#define FCEQ(T) T ## _FRES FN (fceq, T ## _DF) (T i, T j) { return BUILTIN (fceq, T ## _DF) (i, j); } +#define FCUNE(T) T ## _FRES FN (fcune, T ## _DF) (T i, T j) { return BUILTIN (fcune, T ## _DF) (i, j); } +#define FCUEQ(T) T ## _FRES FN (fcueq, T ## _DF) (T i, T j) { return BUILTIN (fcueq, T ## _DF) (i, j); } +#define FCNE(T) T ## _FRES FN (fcne, T ## _DF) (T i, T j) { return BUILTIN (fcne, T ## _DF) (i, j); } +#define FCLT(T) T ## _FRES FN (fclt, T ## _DF) (T i, T j) { return BUILTIN (fclt, T ## _DF) (i, j); } +#define FCULT(T) T ## _FRES FN (fcult, T ## _DF) (T i, T j) { return BUILTIN (fcult, T ## _DF) (i, j); } +#define FCLE(T) T ## _FRES FN (fcle, T ## _DF) (T i, T j) { return BUILTIN (fcle, T ## _DF) (i, j); } +#define FCULE(T) T ## _FRES FN (fcule, T ## _DF) (T i, T j) { return BUILTIN (fcule, T ## _DF) (i, j); } +#define FSAF(T) T ## _FRES FN (fsaf, T ## _DF) (T i, T j) { return BUILTIN (fsaf, T ## _DF) (i, j); } +#define FSUN(T) T ## _FRES FN (fsun, T ## _DF) (T i, T j) { return BUILTIN (fsun, T ## _DF) (i, j); } +#define FSOR(T) T ## _FRES FN (fsor, T ## _DF) (T i, T j) { return BUILTIN (fsor, T ## _DF) (i, j); } +#define FSEQ(T) T ## _FRES FN (fseq, T ## _DF) (T i, T j) { return BUILTIN (fseq, T ## _DF) (i, j); } +#define FSUNE(T) T ## _FRES FN (fsune, T ## _DF) (T i, T j) { return BUILTIN (fsune, T ## _DF) (i, j); } +#define FSUEQ(T) T ## _FRES FN (fsueq, T ## _DF) (T i, T j) { return BUILTIN (fsueq, T ## _DF) (i, j); } +#define FSNE(T) T ## _FRES FN (fsne, T ## _DF) (T i, T j) { return BUILTIN (fsne, T ## _DF) (i, j); } +#define FSLT(T) T ## _FRES FN (fslt, T ## _DF) (T i, T j) { return BUILTIN (fslt, T ## _DF) (i, j); } +#define FSULT(T) T ## _FRES FN (fsult, T ## _DF) (T i, T j) { return BUILTIN (fsult, T ## _DF) (i, j); } +#define FSLE(T) T ## _FRES FN (fsle, T ## _DF) (T i, T j) { return BUILTIN (fsle, T ## _DF) (i, j); } +#define FSULE(T) T ## _FRES FN (fsule, T ## _DF) (T i, T j) { return BUILTIN (fsule, T ## _DF) (i, j); } /* MSA Floating-Point Conversion builtins. */ -#define FEXUPL(T) NOMIPS16 T FN (fexupl, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupl, T ## _DF) (i); } -#define FEXUPR(T) NOMIPS16 T FN (fexupr, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupr, T ## _DF) (i); } -#define FEXDO(T) NOMIPS16 T ## _FCNV FN (fexdo, T ## _HDF) (T i, T j) { return BUILTIN (fexdo, T ## _HDF) (i, j); } -#define FFINT_S(T) NOMIPS16 T FN (ffint_s, T ## _DF) (T ## _FSINT i) { return BUILTIN (ffint_s, T ## _DF) (i); } -#define FFINT_U(T) NOMIPS16 T FN (ffint_u, T ## _DF) (T ## _FUINT i) { return BUILTIN (ffint_u, T ## _DF) (i); } -#define FFQL(T) NOMIPS16 T FN (ffql, T ## _DF) (T ## _FFP i) { return BUILTIN (ffql, T ## _DF) (i); } -#define FFQR(T) NOMIPS16 T FN (ffqr, T ## _DF) (T ## _FFP i) { return BUILTIN (ffqr, T ## _DF) (i); } -#define FTINT_S(T) NOMIPS16 T ## _FSINT FN (ftint_s, T ## _DF) (T i) { return BUILTIN (ftint_s, T ## _DF) (i); } -#define FTINT_U(T) NOMIPS16 T ## _FUINT FN (ftint_u, T ## _DF) (T i) { return BUILTIN (ftint_u, T ## _DF) (i); } -#define FTRUNC_S(T) NOMIPS16 T ## _FSINT FN (ftrunc_s, T ## _DF) (T i) { return BUILTIN (ftrunc_s, T ## _DF) (i); } -#define FTRUNC_U(T) NOMIPS16 T ## _FUINT FN (ftrunc_u, T ## _DF) (T i) { return BUILTIN (ftrunc_u, T ## _DF) (i); } -#define FTQ(T) NOMIPS16 T ## _FFP FN (ftq, T ## _HDF) (T i, T j) { return BUILTIN (ftq, T ## _HDF) (i, j); } +#define FEXUPL(T) T FN (fexupl, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupl, T ## _DF) (i); } +#define FEXUPR(T) T FN (fexupr, T ## _DF) (T ## _FCNV i) { return BUILTIN (fexupr, T ## _DF) (i); } +#define FEXDO(T) T ## _FCNV FN (fexdo, T ## _HDF) (T i, T j) { return BUILTIN (fexdo, T ## _HDF) (i, j); } +#define FFINT_S(T) T FN (ffint_s, T ## _DF) (T ## _FSINT i) { return BUILTIN (ffint_s, T ## _DF) (i); } +#define FFINT_U(T) T FN (ffint_u, T ## _DF) (T ## _FUINT i) { return BUILTIN (ffint_u, T ## _DF) (i); } +#define FFQL(T) T FN (ffql, T ## _DF) (T ## _FFP i) { return BUILTIN (ffql, T ## _DF) (i); } +#define FFQR(T) T FN (ffqr, T ## _DF) (T ## _FFP i) { return BUILTIN (ffqr, T ## _DF) (i); } +#define FTINT_S(T) T ## _FSINT FN (ftint_s, T ## _DF) (T i) { return BUILTIN (ftint_s, T ## _DF) (i); } +#define FTINT_U(T) T ## _FUINT FN (ftint_u, T ## _DF) (T i) { return BUILTIN (ftint_u, T ## _DF) (i); } +#define FTRUNC_S(T) T ## _FSINT FN (ftrunc_s, T ## _DF) (T i) { return BUILTIN (ftrunc_s, T ## _DF) (i); } +#define FTRUNC_U(T) T ## _FUINT FN (ftrunc_u, T ## _DF) (T i) { return BUILTIN (ftrunc_u, T ## _DF) (i); } +#define FTQ(T) T ## _FFP FN (ftq, T ## _HDF) (T i, T j) { return BUILTIN (ftq, T ## _HDF) (i, j); } /* MSA Fixed-Point Multiplication builtins. */ -#define MADD_Q(T) NOMIPS16 T ## _FFP FN (madd_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (madd_q, T ## _HDF) (i, j, k); } -#define MADDR_Q(T) NOMIPS16 T ## _FFP FN (maddr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (maddr_q, T ## _HDF) (i, j, k); } -#define MSUB_Q(T) NOMIPS16 T ## _FFP FN (msub_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msub_q, T ## _HDF) (i, j, k); } -#define MSUBR_Q(T) NOMIPS16 T ## _FFP FN (msubr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msubr_q, T ## _HDF) (i, j, k); } -#define MUL_Q(T) NOMIPS16 T ## _FFP FN (mul_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mul_q, T ## _HDF) (i, j); } -#define MULR_Q(T) NOMIPS16 T ## _FFP FN (mulr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mulr_q, T ## _HDF) (i, j); } +#define MADD_Q(T) T ## _FFP FN (madd_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (madd_q, T ## _HDF) (i, j, k); } +#define MADDR_Q(T) T ## _FFP FN (maddr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (maddr_q, T ## _HDF) (i, j, k); } +#define MSUB_Q(T) T ## _FFP FN (msub_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msub_q, T ## _HDF) (i, j, k); } +#define MSUBR_Q(T) T ## _FFP FN (msubr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j, T ## _FFP k) { return BUILTIN (msubr_q, T ## _HDF) (i, j, k); } +#define MUL_Q(T) T ## _FFP FN (mul_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mul_q, T ## _HDF) (i, j); } +#define MULR_Q(T) T ## _FFP FN (mulr_q, T ## _HDF) (T ## _FFP i, T ## _FFP j) { return BUILTIN (mulr_q, T ## _HDF) (i, j); } /* MSA Compare builtins. */ -#define CEQ(T) NOMIPS16 T FN (ceq, T ## _DF) (T i, T j) { return BUILTIN (ceq, T ## _DF) (i, j); } -#define CEQI(T) NOMIPS16 T FN (ceqi, T ## _DF) (T i) { return BUILTIN (ceqi, T ## _DF) (i, 0); } -#define CLE_S(T) NOMIPS16 T FN (cle_s, T ## _DF) (T i, T j) { return BUILTIN (cle_s, T ## _DF) (i, j); } -#define CLEI_S(T) NOMIPS16 T FN (clei_s, T ## _DF) (T i) { return BUILTIN (clei_s, T ## _DF) (i, 0); } -#define CLE_U(T) NOMIPS16 T ## _CMP FN (cle_u, T ## _DF) (T i, T j) { return BUILTIN (cle_u, T ## _DF) (i, j); } -#define CLEI_U(T) NOMIPS16 T ## _CMP FN (clei_u, T ## _DF) (T i) { return BUILTIN (clei_u, T ## _DF) (i, 10); } -#define CLT_S(T) NOMIPS16 T FN (clt_s, T ## _DF) (T i, T j) { return BUILTIN (clt_s, T ## _DF) (i, j); } -#define CLTI_S(T) NOMIPS16 T FN (clti_s, T ## _DF) (T i) { return BUILTIN (clti_s, T ## _DF) (i, 0); } -#define CLT_U(T) NOMIPS16 T ## _CMP FN (clt_u, T ## _DF) (T i, T j) { return BUILTIN (clt_u, T ## _DF) (i, j); } -#define CLTI_U(T) NOMIPS16 T ## _CMP FN (clti_u, T ## _DF) (T i) { return BUILTIN (clti_u, T ## _DF) (i, 0); } +#define CEQ(T) T FN (ceq, T ## _DF) (T i, T j) { return BUILTIN (ceq, T ## _DF) (i, j); } +#define CEQI(T) T FN (ceqi, T ## _DF) (T i) { return BUILTIN (ceqi, T ## _DF) (i, 0); } +#define CLE_S(T) T FN (cle_s, T ## _DF) (T i, T j) { return BUILTIN (cle_s, T ## _DF) (i, j); } +#define CLEI_S(T) T FN (clei_s, T ## _DF) (T i) { return BUILTIN (clei_s, T ## _DF) (i, 0); } +#define CLE_U(T) T ## _CMP FN (cle_u, T ## _DF) (T i, T j) { return BUILTIN (cle_u, T ## _DF) (i, j); } +#define CLEI_U(T) T ## _CMP FN (clei_u, T ## _DF) (T i) { return BUILTIN (clei_u, T ## _DF) (i, 10); } +#define CLT_S(T) T FN (clt_s, T ## _DF) (T i, T j) { return BUILTIN (clt_s, T ## _DF) (i, j); } +#define CLTI_S(T) T FN (clti_s, T ## _DF) (T i) { return BUILTIN (clti_s, T ## _DF) (i, 0); } +#define CLT_U(T) T ## _CMP FN (clt_u, T ## _DF) (T i, T j) { return BUILTIN (clt_u, T ## _DF) (i, j); } +#define CLTI_U(T) T ## _CMP FN (clti_u, T ## _DF) (T i) { return BUILTIN (clti_u, T ## _DF) (i, 0); } /* MSA Branch builtins. */ -#define BNZV(T) NOMIPS16 int FN (bnz, v) (T i) { return BUILTIN (bnz, v) (i); } -#define BZV(T) NOMIPS16 int FN (bz, v) (T i) { return BUILTIN (bz, v) (i); } -#define BNZ(T) NOMIPS16 int FN (bnz, T ## _DF) (T i) { return BUILTIN (bnz, T ## _DF) (i); } -#define BZ(T) NOMIPS16 int FN (bz, T ## _DF) (T i) { return BUILTIN (bz, T ## _DF) (i); } +#define BNZV(T) int FN (bnz, v) (T i) { return BUILTIN (bnz, v) (i); } +#define BZV(T) int FN (bz, v) (T i) { return BUILTIN (bz, v) (i); } +#define BNZ(T) int FN (bnz, T ## _DF) (T i) { return BUILTIN (bnz, T ## _DF) (i); } +#define BZ(T) int FN (bz, T ## _DF) (T i) { return BUILTIN (bz, T ## _DF) (i); } /* MSA Load/Store and Move builtins. */ #define CFCMSA() int msa_cfcmsa () { return __builtin_msa_cfcmsa(0x1f); } #define CTCMSA() void msa_ctcmsa (int i) { return __builtin_msa_ctcmsa(0x1f, i); } #define LD(T) T FN (ld, T ## _DF) (char *i) { return BUILTIN (ld, T ## _DF) (i, 0); } #define LDI(T) T FN (ldi, T ## _DF) () { return BUILTIN (ldi, T ## _DF) (123); } -#define MOVE(T) NOMIPS16 T FN (move, v) (T i) { return BUILTIN (move, v) (i); } +#define MOVE(T) T FN (move, v) (T i) { return BUILTIN (move, v) (i); } #define SPLAT(T) T FN (splat, T ## _DF) (T i, int j) { return BUILTIN (splat, T ## _DF) (i, j); } #define SPLATI(T) T FN (splati, T ## _DF) (T i) { return BUILTIN (splati, T ## _DF) (i, 1); } #define FILL(T) T FN (fill, T ## _DF) (int i) { return BUILTIN (fill, T ## _DF) (i); } @@ -829,16 +829,16 @@ #define ST(T) void FN (st, T ## _DF) (T i, char *j) { BUILTIN (st, T ## _DF) (i, j, -64); } /* MSA Element Permute builtins. */ -#define ILVEV(T) NOMIPS16 T FN (ilvev, T ## _DF) (T i, T j) { return BUILTIN (ilvev, T ## _DF) (i, j); } -#define ILVOD(T) NOMIPS16 T FN (ilvod, T ## _DF) (T i, T j) { return BUILTIN (ilvod, T ## _DF) (i, j); } -#define ILVL(T) NOMIPS16 T FN (ilvl, T ## _DF) (T i, T j) { return BUILTIN (ilvl, T ## _DF) (i, j); } -#define ILVR(T) NOMIPS16 T FN (ilvr, T ## _DF) (T i, T j) { return BUILTIN (ilvr, T ## _DF) (i, j); } -#define PCKEV(T) NOMIPS16 T FN (pckev, T ## _DF) (T i, T j) { return BUILTIN (pckev, T ## _DF) (i, j); } -#define PCKOD(T) NOMIPS16 T FN (pckod, T ## _DF) (T i, T j) { return BUILTIN (pckod, T ## _DF) (i, j); } -#define SHF(T) NOMIPS16 T FN (shf, T ## _DF) (T i) { return BUILTIN (shf, T ## _DF) (i, 127); } -#define SLD(T) NOMIPS16 T FN (sld, T ## _DF) (T i, T j, int k) { return BUILTIN (sld, T ## _DF) (i, j, k); } -#define SLDI(T) NOMIPS16 T FN (sldi, T ## _DF) (T i, T j) { return BUILTIN (sldi, T ## _DF) (i, j, 1); } -#define VSHF(T) NOMIPS16 T FN (vshf, T ## _DF) (T i, T j, T k) { return BUILTIN (vshf, T ## _DF) (i, j, k); } +#define ILVEV(T) T FN (ilvev, T ## _DF) (T i, T j) { return BUILTIN (ilvev, T ## _DF) (i, j); } +#define ILVOD(T) T FN (ilvod, T ## _DF) (T i, T j) { return BUILTIN (ilvod, T ## _DF) (i, j); } +#define ILVL(T) T FN (ilvl, T ## _DF) (T i, T j) { return BUILTIN (ilvl, T ## _DF) (i, j); } +#define ILVR(T) T FN (ilvr, T ## _DF) (T i, T j) { return BUILTIN (ilvr, T ## _DF) (i, j); } +#define PCKEV(T) T FN (pckev, T ## _DF) (T i, T j) { return BUILTIN (pckev, T ## _DF) (i, j); } +#define PCKOD(T) T FN (pckod, T ## _DF) (T i, T j) { return BUILTIN (pckod, T ## _DF) (i, j); } +#define SHF(T) T FN (shf, T ## _DF) (T i) { return BUILTIN (shf, T ## _DF) (i, 127); } +#define SLD(T) T FN (sld, T ## _DF) (T i, T j, int k) { return BUILTIN (sld, T ## _DF) (i, j, k); } +#define SLDI(T) T FN (sldi, T ## _DF) (T i, T j) { return BUILTIN (sldi, T ## _DF) (i, j, 1); } +#define VSHF(T) T FN (vshf, T ## _DF) (T i, T j, T k) { return BUILTIN (vshf, T ## _DF) (i, j, k); } /* GCC builtins that generate MSA instructions. */ #define SHUFFLE1_S(T) T FN (gcc_1_s_vshf, T ## _DF) (T i, T mask) { return __builtin_shuffle (i, mask); } diff --git a/gcc/testsuite/gcc.target/mips/msa.c b/gcc/testsuite/gcc.target/mips/msa.c index 62d0606dfef..8647b6d9530 100644 --- a/gcc/testsuite/gcc.target/mips/msa.c +++ b/gcc/testsuite/gcc.target/mips/msa.c @@ -1,6 +1,6 @@ /* Test MIPS MSA ASE instructions */ /* { dg-do compile } */ -/* { dg-options "-mfp64 -mhard-float -mmsa -fexpensive-optimizations -fcommon" } */ +/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa -fexpensive-optimizations -fcommon" } */ /* { dg-skip-if "madd and msub need combine" { *-*-* } { "-O0" } { "" } } */ /* { dg-final { scan-assembler-times "\t.comm\tv16i8_\\d+,16,16" 3 } } */ @@ -485,11 +485,11 @@ float imm_f = 37.0; #define DECLARE(TYPE) TYPE TYPE ## _0, TYPE ## _1, TYPE ## _2; -#define RETURN(TYPE) NOMIPS16 TYPE test0_ ## TYPE () { return TYPE ## _0; } -#define ASSIGN(TYPE) NOMIPS16 void test1_ ## TYPE (TYPE i) { TYPE ## _1 = i; } -#define ADD(TYPE) NOMIPS16 TYPE test2_ ## TYPE (TYPE i, TYPE j) { return i + j; } -#define SUB(TYPE) NOMIPS16 TYPE test3_ ## TYPE (TYPE i, TYPE j) { return i - j; } -#define MUL(TYPE) NOMIPS16 TYPE test4_ ## TYPE (TYPE i, TYPE j) { return i * j; } +#define RETURN(TYPE) TYPE test0_ ## TYPE () { return TYPE ## _0; } +#define ASSIGN(TYPE) void test1_ ## TYPE (TYPE i) { TYPE ## _1 = i; } +#define ADD(TYPE) TYPE test2_ ## TYPE (TYPE i, TYPE j) { return i + j; } +#define SUB(TYPE) TYPE test3_ ## TYPE (TYPE i, TYPE j) { return i - j; } +#define MUL(TYPE) TYPE test4_ ## TYPE (TYPE i, TYPE j) { return i * j; } #define DIV(TYPE) TYPE test5_ ## TYPE (TYPE i, TYPE j) { return i / j; } #define MOD(TYPE) TYPE test6_ ## TYPE (TYPE i, TYPE j) { return i % j; } #define MINUS(TYPE) TYPE test7_ ## TYPE (TYPE i) { return -i; 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The option based ISA min/max code only triggers if there is no isa level request. gcc/testsuite/ * gcc.target/mips/call-clobbered-1.c: Use HAS_LDC ghost option instead of isa>=2. Cherry-picked e9df15b1a308aa8a10473c820f35d628fa8f2efb from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.target/mips/call-clobbered-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/mips/call-clobbered-1.c b/gcc/testsuite/gcc.target/mips/call-clobbered-1.c index 8880ad13684..2e0521318f4 100644 --- a/gcc/testsuite/gcc.target/mips/call-clobbered-1.c +++ b/gcc/testsuite/gcc.target/mips/call-clobbered-1.c @@ -1,6 +1,6 @@ /* Check that we handle call-clobbered FPRs correctly. */ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ -/* { dg-options "isa>=2 -mabi=32 -mfpxx -mhard-float -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19" } */ +/* { dg-options "(HAS_LDC) -mabi=32 -mfpxx -mhard-float -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19" } */ void bar (void); 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Fri, 31 Jan 2025 17:14:07 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 36/61] Testsuite: Disable the time-profiler-2.c test Thread-Topic: [PATCH 36/61] Testsuite: Disable the time-profiler-2.c test Thread-Index: AQHbdAN3Tm30ppYWIk20GFD/hrzMpA== Date: Fri, 31 Jan 2025 17:13:38 +0000 Message-ID: <20250131171232.1018281-38-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|AS2PR09MB6367:EE_ x-ms-office365-filtering-correlation-id: 887e3e27-e06f-485e-d671-08dd421aab8d x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Cherry-picked 7c5a494a31c72ee3285ffae9fda738aa875869b9 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.dg/tree-prof/time-profiler-2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/gcc.dg/tree-prof/time-profiler-2.c b/gcc/testsuite/gcc.dg/tree-prof/time-profiler-2.c index eed0b1dd08d..bcf9adf1b09 100644 --- a/gcc/testsuite/gcc.dg/tree-prof/time-profiler-2.c +++ b/gcc/testsuite/gcc.dg/tree-prof/time-profiler-2.c @@ -1,4 +1,5 @@ /* { dg-options "-O2 -fdump-ipa-profile -fno-ipa-vrp" } */ +/* { dg-skip-if "This test is unstable for MIPS " { "mips*-*-*" } } */ #include From patchwork Fri Jan 31 17:13:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105779 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1F12F385770D for ; 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The non-conformant patterns used in these tests cannot set the ISA mode bit and may attempt to directly call the variable which triggers an error from the assembler about calling a different ISA mode. gcc/testsuite/ * gcc.c-torture/compile/20020129-1.c: Skip for MIPS16/microMIPS. * gcc.c-torture/compile/pr37433-1.c: Likewise. * gcc.c-torture/compile/pr37433.c: Likewise. * lib/target-supports.exp (check_effective_target_mips_compressed): New function. Cherry-picked 97f2d5c6403c0cb8b65e059349ec18ffc9505bfd from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.c-torture/compile/20020129-1.c | 5 +++++ gcc/testsuite/gcc.c-torture/compile/pr37433-1.c | 5 +++++ gcc/testsuite/gcc.c-torture/compile/pr37433.c | 5 +++++ gcc/testsuite/lib/target-supports.exp | 10 ++++++++++ 4 files changed, 25 insertions(+) diff --git a/gcc/testsuite/gcc.c-torture/compile/20020129-1.c b/gcc/testsuite/gcc.c-torture/compile/20020129-1.c index c14ac07655e..d06bcb0976d 100644 --- a/gcc/testsuite/gcc.c-torture/compile/20020129-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/20020129-1.c @@ -2,6 +2,11 @@ /* { dg-require-effective-target indirect_calls } */ +/* MIPS compressed ISAs require the LSB of an address to indicate which + ISA mode to use. This test cannot do that and raises an assembler + warning (binutils 2.29 onwards) of a branch to a different ISA. */ +/* { dg-skip-if "" { mips_compressed } } */ + typedef struct { long long a[10]; diff --git a/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c b/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c index 48a57b637d7..5948b3d740a 100644 --- a/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/pr37433-1.c @@ -1,5 +1,10 @@ /* { dg-require-effective-target indirect_calls } */ +/* MIPS compressed ISAs require the LSB of an address to indicate which + ISA mode to use. This test cannot do that and raises an assembler + warning (binutils 2.29 onwards) of a branch to a different ISA. */ +/* { dg-skip-if "" { mips_compressed } } */ + void regex_subst(void) { const void *subst = ""; diff --git a/gcc/testsuite/gcc.c-torture/compile/pr37433.c b/gcc/testsuite/gcc.c-torture/compile/pr37433.c index 95d168afa2f..69e622132af 100644 --- a/gcc/testsuite/gcc.c-torture/compile/pr37433.c +++ b/gcc/testsuite/gcc.c-torture/compile/pr37433.c @@ -1,5 +1,10 @@ /* { dg-require-effective-target indirect_calls } */ + +/* MIPS compressed ISAs require the LSB of an address to indicate which + ISA mode to use. This test cannot do that and raises an assembler + warning (binutils 2.29 onwards) of a branch to a different ISA. */ +/* { dg-skip-if "" { mips_compressed } } */ int regex_subst(void) { const void *subst = ""; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index fd58682cae3..4f005c5a7d2 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1514,6 +1514,16 @@ proc check_effective_target_mips64 { } { }] } +# Return true if the target is using a compressed MIPS ISA. + +proc check_effective_target_mips_compressed { } { + return [check_no_compiler_messages mips_compressed assembly { + #if !defined (__mips_micromips) && !defined (__mips16) + #error !__mips_micromips && !__mips16 + #endif + }] +} + # Return true if the target is a MIPS target that does not produce # MIPS16 code. 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Fri, 31 Jan 2025 17:14:07 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Matthew Fortune , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 38/61] MIPSR6: Mark R6 unaligned access Thread-Topic: [PATCH 38/61] MIPSR6: Mark R6 unaligned access Thread-Index: AQHbdAN4h0eGDe3E2UWPryA6uzY/Gw== Date: Fri, 31 Jan 2025 17:13:39 +0000 Message-ID: <20250131171232.1018281-40-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|AS2PR09MB6367:EE_ x-ms-office365-filtering-correlation-id: 718e4704-6fec-42a3-1964-08dd421aabdc x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Cherry-picked 42be7aa50f3b04a88768e08c000cfe7923f22b0f from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index a1208bcef69..dcb4b9f9f99 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -6255,9 +6255,15 @@ mips_output_move (rtx insn, rtx dest, rtx src) switch (GET_MODE_SIZE (mode)) { case 1: return "sb\t%z1,%0"; - case 2: return "sh\t%z1,%0"; - case 4: return "sw\t%z1,%0"; - case 8: return "sd\t%z1,%0"; + case 2: return ((MEM_ALIGN (dest) >= BITS_PER_UNIT * 2) + ? "sh\t%z1,%0" + : "sh\t%z1,%0 # unaligned"); + case 4: return ((MEM_ALIGN (dest) >= BITS_PER_UNIT * 4) + ? "sw\t%z1,%0" + : "sw\t%z1,%0 # unaligned"); + case 8: return ((MEM_ALIGN (dest) >= BITS_PER_UNIT * 8) + ? "sd\t%z1,%0" + : "sd\t%z1,%0 # unaligned"); default: gcc_unreachable (); } } @@ -6313,18 +6319,30 @@ mips_output_move (rtx insn, rtx dest, rtx src) switch (GET_MODE_SIZE (mode)) { case 1: return "lbu\t$0,%1"; - case 2: return "lhu\t$0,%1"; - case 4: return "lw\t$0,%1"; - case 8: return "ld\t$0,%1"; + case 2: return ((MEM_ALIGN (src) >= BITS_PER_UNIT * 2) + ? "lhu\t$0,%1" + : "lhu\t$0,%1 # unaligned"); + case 4: return ((MEM_ALIGN (src) >= BITS_PER_UNIT * 4) + ? "lw\t$0,%1" + : "lw\t$0,%1 # unaligned"); + case 8: return ((MEM_ALIGN (src) >= BITS_PER_UNIT * 8) + ? "ld\t$0,%1" + : "ld\t$0,%1 # unaligned"); default: gcc_unreachable (); } else switch (GET_MODE_SIZE (mode)) { case 1: return "lbu\t%0,%1"; - case 2: return "lhu\t%0,%1"; - case 4: return "lw\t%0,%1"; - case 8: return "ld\t%0,%1"; + case 2: return ((MEM_ALIGN (src) >= BITS_PER_UNIT * 2) + ? "lhu\t%0,%1" + : "lhu\t%0,%1 # unaligned"); + case 4: return ((MEM_ALIGN (src) >= BITS_PER_UNIT * 4) + ? "lw\t%0,%1" + : "lw\t%0,%1 # unaligned"); + case 8: return ((MEM_ALIGN (src) >= BITS_PER_UNIT * 8) + ? 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It is possible for a load/store accessing the stack via a copy of the stack pointer to be moved across the epilogue meaning that it accesses stack that is no longer allocated. This leads to a situation where the code is unsafe in the event of an interrupt where the same stack is used for interrupt handling. gcc/ * config/mips/mips.cc (mips_frame_barrier): Upgrade to a full blockage. Cherry-picked 0c240da6f6032bd19348b97148d25c05ba2e8356 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index dcb4b9f9f99..57a858aca39 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -13626,7 +13626,7 @@ mips_output_function_epilogue (FILE *) static void mips_frame_barrier (void) { - emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx)); + emit_insn (gen_blockage ()); } From patchwork Fri Jan 31 17:13:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105773 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1596B385770A for ; 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Cherry-picked 180f74c8ebdf13ddac806695d0333af7b924c402 from https://github.com/MIPS/gcc Signed-off-by: Jaydeep Patil Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.md | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7d27e7d4b20..159fc2e2615 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1830,6 +1830,19 @@ ;; Split *mul_acc_si if both the source and destination accumulator ;; values are GPRs. +(define_split + [(set (match_operand:SI 0 "d_operand") + (plus:SI (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand")) + (match_operand:SI 3 "d_operand"))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && ISA_HAS_R6MUL" + [(set (match_dup 5) + (mult:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))] + "") + (define_split [(set (match_operand:SI 0 "d_operand") (plus:SI (mult:SI (match_operand:SI 1 "d_operand") @@ -2052,6 +2065,19 @@ ;; Split *mul_sub_si if both the source and destination accumulator ;; values are GPRs. +(define_split + [(set (match_operand:SI 0 "d_operand") + (minus:SI (match_operand:SI 1 "d_operand") + (mult:SI (match_operand:SI 2 "d_operand") + (match_operand:SI 3 "d_operand")))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && ISA_HAS_R6MUL" + [(set (match_dup 5) + (mult:SI (match_dup 2) (match_dup 3))) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))] + "") + (define_split [(set (match_operand:SI 0 "d_operand") (minus:SI (match_operand:SI 1 "d_operand") From patchwork Fri Jan 31 17:13:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105794 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1B1C6385770E for ; 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The lightweight fix for shrink-wrapping being inhibited by -mgpopt just clears the global pointer from being related to the prologue and only affects shrink wrapping. Cherry-picked 4ea3a82b5e8e23591d79a9ca63018acceb53c2a5 from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 57a858aca39..10f302e0790 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -25497,6 +25497,15 @@ mips_c_mode_for_floating_type (enum tree_index ti) return default_mode_for_floating_type (ti); } +/* Implement TARGET_SET_UP_BY_PROLOGUE. */ + +static void +mips_set_up_by_prologue (hard_reg_set_container *regs) +{ + if (!TARGET_USE_GOT && TARGET_GPOPT) + CLEAR_HARD_REG_BIT (regs->set, GLOBAL_POINTER_REGNUM); +} + void mips_bit_clear_info (enum machine_mode mode, unsigned HOST_WIDE_INT m, int *start_pos, int *size) @@ -25634,6 +25643,9 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) #undef TARGET_IN_SMALL_DATA_P #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p +#undef TARGET_SET_UP_BY_PROLOGUE +#define TARGET_SET_UP_BY_PROLOGUE mips_set_up_by_prologue + #undef TARGET_MACHINE_DEPENDENT_REORG #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg From patchwork Fri Jan 31 17:13:40 2025 Content-Type: text/plain; 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These reloads happens because of different modes making elimination non-trivial. Cherry-picked 85462a9dbf8d659bfb0417d354a0a4f9cd4b8e07 from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 159fc2e2615..1243f20f344 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5254,6 +5254,18 @@ [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") (set_attr "mode" "HI")]) +(define_peephole2 + [(set (match_operand:HI 0 "register_operand") + (match_operand:HI 1 "register_operand")) + (set (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "register_operand"))] + "TARGET_MIPS16 + && REGNO (operands[1]) == REGNO (operands[2]) + && REGNO (operands[0]) == REGNO (operands[3]) + && peep2_reg_dead_p (2, operands[3])" + [(const_int 0)] + "") + ;; On the mips16, we can split lh $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. @@ -5330,6 +5342,18 @@ [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") (set_attr "mode" "QI")]) +(define_peephole2 + [(set (match_operand:QI 0 "register_operand") + (match_operand:QI 1 "register_operand")) + (set (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "register_operand"))] + "TARGET_MIPS16 + && REGNO (operands[1]) == REGNO (operands[2]) + && REGNO (operands[0]) == REGNO (operands[3]) + && peep2_reg_dead_p (2, operands[3])" + [(const_int 0)] + "") + ;; On the mips16, we can split lb $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. 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Cherry-picked 7a9286a94817badb312e3bb2b4a7a83b8b3fa28a from https://github.com/MIPS/gcc Signed-off-by: Matthew Fortune Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c index 5c89e3f8698..5097ae8bf11 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c @@ -27,4 +27,4 @@ foo () but the loop reads only one element at a time, and DOM cannot resolve these. The same happens on powerpc depending on the SIMD support available. */ -/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* mmix-knuth-mmixware } || { { { lp64 && { powerpc*-*-* sparc*-*-* } } || aarch64_sve } || { arm*-*-* && { ! arm_neon } } } } } } } */ +/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* mmix-knuth-mmixware } || { { { lp64 && { mips*-*-* powerpc*-*-* sparc*-*-* } } || aarch64_sve } || { arm*-*-* && { ! arm_neon } } } } } } } */ From patchwork Fri Jan 31 17:13:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105789 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7FC583858416 for ; Fri, 31 Jan 2025 18:09:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7FC583858416 Authentication-Results: sourceware.org; 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We currently allow this mode change to be no-op on MSA registers. This works on little-endian because MSA register layout matches that of vector value in memory. This breaks on big-endian because ordering of bytes within the lane depends of target endianes. We now conservatively disallow direct MSA register mode change via TARGET_CAN_CHANGE_MODE_CLASS making it go through memory. gcc/ * config/mips/mips-msa.md (UNSPEC_MSA_CHANGE_MODE): New unspec. (msa_change_mode): New expand pattern. (msa_change_mode_): New insn pattern. * config/mips/mips.cc (mips_split_128bit_move): Replace MSA mode changing uses of simplify_gen_subreg with gen_rtx_REG. (mips_split_msa_copy_d): Ditto. (mips_split_msa_insert_d): Ditto. (mips_split_msa_fill_d): Ditto. (mips_can_change_mode_class): Disallow change of MSA modes with different lane width on big-endian targets. (mips_expand_vec_unpack): Use gen_msa_change_mode instead of gen_lowpart for MSA modes. Cherry-picked c00d34621429f31926e0c72e027b0c1028d046f0 from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips-msa.md | 37 +++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips.cc | 29 ++++++++++++++++++----------- 2 files changed, 55 insertions(+), 11 deletions(-) diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index f6edd5897a4..5ac4fa4bf24 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -90,6 +90,7 @@ UNSPEC_MSA_SUBSUU_S UNSPEC_MSA_SUBSUS_U UNSPEC_MSA_VSHF + UNSPEC_MSA_CHANGE_MODE ]) ;; All vector modes with 128 bits. @@ -2930,3 +2931,39 @@ const0_rtx)); DONE; }) + +;; On big-endian targets we cannot use subregs to refer to MSA register +;; in different mode. See mips_can_change_mode_class. +(define_expand "msa_change_mode" + [(match_operand 0 "register_operand") + (match_operand 1 "register_operand")] + "ISA_HAS_MSA" +{ + gcc_assert (MSA_SUPPORTED_MODE_P (GET_MODE (operands[0])) + && MSA_SUPPORTED_MODE_P (GET_MODE (operands[1]))); + + if (!TARGET_BIG_ENDIAN) + emit_move_insn (operands[0], + gen_lowpart (GET_MODE (operands[0]), operands[1])); + else + emit_move_insn (operands[0], + gen_rtx_UNSPEC (GET_MODE (operands[0]), + gen_rtvec (1, operands[1]), + UNSPEC_MSA_CHANGE_MODE)); + DONE; +}) + +(define_insn_and_split "msa_change_mode_" + [(set (match_operand:MSA 0 "register_operand" "=f") + (unspec:MSA [(match_operand 1 "register_operand" "f")] + UNSPEC_MSA_CHANGE_MODE))] + "ISA_HAS_MSA && TARGET_BIG_ENDIAN + && MSA_SUPPORTED_MODE_P (GET_MODE (operands[1]))" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 1))] +{ + operands[1] = gen_rtx_REG (mode, REGNO (operands[1])); +} + [(set_attr "move_type" "fmove") + (set_attr "mode" "")]) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 10f302e0790..e0b357a651a 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -5998,12 +5998,12 @@ mips_split_128bit_move (rtx dest, rtx src) if (!TARGET_64BIT) { if (GET_MODE (dest) != V4SImode) - new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0); + new_dest = gen_rtx_REG (V4SImode, REGNO (dest)); } else { if (GET_MODE (dest) != V2DImode) - new_dest = simplify_gen_subreg (V2DImode, dest, GET_MODE (dest), 0); + new_dest = gen_rtx_REG (V2DImode, REGNO (dest)); } for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode); @@ -6026,12 +6026,12 @@ mips_split_128bit_move (rtx dest, rtx src) if (!TARGET_64BIT) { if (GET_MODE (src) != V4SImode) - new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0); + new_src = gen_rtx_REG (V4SImode, REGNO (src)); } else { if (GET_MODE (src) != V2DImode) - new_src = simplify_gen_subreg (V2DImode, src, GET_MODE (src), 0); + new_src = gen_rtx_REG (V2DImode, REGNO (src)); } for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode); @@ -6087,7 +6087,8 @@ mips_split_msa_copy_d (rtx dest, rtx src, rtx index, from the higher index. */ rtx low = mips_subword (dest, false); rtx high = mips_subword (dest, true); - rtx new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0); + + rtx new_src = gen_rtx_REG (V4SImode, REGNO (src)); emit_insn (gen_fn (low, new_src, GEN_INT (INTVAL (index) * 2))); emit_insn (gen_fn (high, new_src, GEN_INT (INTVAL (index) * 2 + 1))); @@ -6108,8 +6109,8 @@ mips_split_msa_insert_d (rtx dest, rtx src1, rtx index, rtx src2) from the higher index. */ rtx low = mips_subword (src2, false); rtx high = mips_subword (src2, true); - rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0); - rtx new_src1 = simplify_gen_subreg (V4SImode, src1, GET_MODE (src1), 0); + rtx new_dest = gen_rtx_REG (V4SImode, REGNO (dest)); + rtx new_src1 = gen_rtx_REG (V4SImode, REGNO (src1)); i = exact_log2 (INTVAL (index)); gcc_assert (i != -1); @@ -6141,7 +6142,7 @@ mips_split_msa_fill_d (rtx dest, rtx src) low = mips_subword (src, false); high = mips_subword (src, true); } - rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0); + rtx new_dest = gen_rtx_REG (V4SImode, REGNO (dest)); emit_insn (gen_msa_fill_w (new_dest, low)); emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 1))); emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 3))); @@ -14774,9 +14775,15 @@ mips_can_change_mode_class (machine_mode from, && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to)) return true; - /* Allow conversions between different MSA vector modes. */ + /* Allow conversions between different MSA vector modes. + On big-endian targets the MSA register layout doesn't + match its memory layout, so we disallow mode change that + would result in lane width change. */ if (MSA_SUPPORTED_MODE_P (from) && MSA_SUPPORTED_MODE_P (to)) - return true; + { + return !TARGET_BIG_ENDIAN + || (GET_MODE_UNIT_SIZE (from) == GET_MODE_UNIT_SIZE (to)); + } /* Otherwise, there are several problems with changing the modes of values in floating-point registers: @@ -24584,7 +24591,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p) dest = gen_reg_rtx (imode); emit_insn (unpack (dest, operands[1], tmp)); - emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest)); 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Fri, 31 Jan 2025 17:14:09 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , dragan.mladjenovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 45/61] Test float32-basic.c fails with -mabi=64 -EB Thread-Topic: [PATCH 45/61] Test float32-basic.c fails with -mabi=64 -EB Thread-Index: AQHbdAN6MaPYCWnRdEKUPLxj+o3ZYg== Date: Fri, 31 Jan 2025 17:13:42 +0000 Message-ID: <20250131171232.1018281-47-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|AS2PR09MB6367:EE_ x-ms-office365-filtering-correlation-id: 93e042c2-935b-454c-7754-08dd421aacfe x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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On N32/64, the callee side expects it to be at offset 0 inside of 8-byte slot, which matches float behavior when passed on stack as named argument. Because of this, we need to make sure that _Float32 value resides in upper 32 bits on big-endian when passed in register as varargs parameter. In order to accomplish this, the BLOCK_REG_PADDING macro is extended with parameter NAMED whose value can be interpreted as follows 1: request for padding of known named argument 0: request for padding of known unnamed argument -1: request for padding in unknown context Cherry-picked e8414cb48566bf5db33d24c6310d9558cd3b3fc0 from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/calls.cc | 7 ++++--- gcc/config/aarch64/aarch64-protos.h | 2 +- gcc/config/aarch64/aarch64.cc | 8 ++++---- gcc/config/aarch64/aarch64.h | 7 ++++--- gcc/config/arm/arm-protos.h | 2 +- gcc/config/arm/arm.cc | 6 +++--- gcc/config/arm/arm.h | 4 ++-- gcc/config/c6x/c6x-protos.h | 2 +- gcc/config/c6x/c6x.cc | 5 +++-- gcc/config/c6x/c6x.h | 5 +++-- gcc/config/mips/mips-protos.h | 2 +- gcc/config/mips/mips.cc | 15 +++++++++++---- gcc/config/mips/mips.h | 4 ++-- gcc/config/nios2/nios2-protos.h | 2 +- gcc/config/nios2/nios2.cc | 2 +- gcc/config/nios2/nios2.h | 4 ++-- gcc/config/pa/pa.h | 2 +- gcc/config/rs6000/aix.h | 2 +- gcc/config/rs6000/darwin.h | 2 +- gcc/config/rs6000/freebsd64.h | 2 +- gcc/config/rs6000/linux64.h | 2 +- gcc/expr.cc | 4 ++-- gcc/function.cc | 10 +++++----- 23 files changed, 56 insertions(+), 45 deletions(-) diff --git a/gcc/calls.cc b/gcc/calls.cc index f67067acad4..69b5cfe51bf 100644 --- a/gcc/calls.cc +++ b/gcc/calls.cc @@ -1229,7 +1229,7 @@ store_unaligned_arguments_into_pseudos (struct arg_data *args, int num_actuals) if (bytes < UNITS_PER_WORD #ifdef BLOCK_REG_PADDING && (BLOCK_REG_PADDING (args[i].mode, - TREE_TYPE (args[i].tree_value), 1) + TREE_TYPE (args[i].tree_value), 1, -1) == PAD_DOWNWARD) #else && BYTES_BIG_ENDIAN @@ -1586,7 +1586,8 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED, end it should be padded. */ args[i].locate.where_pad = BLOCK_REG_PADDING (arg.mode, type, - int_size_in_bytes (type) <= UNITS_PER_WORD); + int_size_in_bytes (type) <= UNITS_PER_WORD, + argpos < n_named_args); #endif /* Update ARGS_SIZE, the total stack space for args so far. */ @@ -4432,7 +4433,7 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value, argvec[count].locate.where_pad = BLOCK_REG_PADDING (arg.mode, NULL_TREE, known_le (GET_MODE_SIZE (arg.mode), - UNITS_PER_WORD)); + UNITS_PER_WORD), 1); #endif targetm.calls.function_arg_advance (args_so_far, arg); diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 05d3258abf7..4b05c6936a9 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -917,7 +917,7 @@ char *aarch64_output_simd_xor_imm (rtx, unsigned); char *aarch64_output_sve_mov_immediate (rtx); char *aarch64_output_sve_ptrues (rtx); -bool aarch64_pad_reg_upward (machine_mode, const_tree, bool); +bool aarch64_pad_reg_upward (machine_mode, const_tree, bool, int); bool aarch64_regno_ok_for_base_p (int, bool); bool aarch64_regno_ok_for_index_p (int, bool); bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail); diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 00bcf18ae97..999a0000dac 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -7501,7 +7501,7 @@ aarch64_function_arg_padding (machine_mode mode, const_tree type) return PAD_UPWARD; } -/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). +/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST, NAMED). It specifies padding for the last (may also be the only) element of a block move between registers and memory. If @@ -7525,7 +7525,7 @@ aarch64_function_arg_padding (machine_mode mode, const_tree type) bool aarch64_pad_reg_upward (machine_mode mode, const_tree type, - bool first ATTRIBUTE_UNUSED) + bool first ATTRIBUTE_UNUSED, int named ATTRIBUTE_UNUSED) { /* Aside from pure scalable types, small composite types are always @@ -21556,7 +21556,7 @@ aarch64_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, if (BYTES_BIG_ENDIAN && ag_size < UNITS_PER_VREG) adjust = UNITS_PER_VREG - ag_size; } - else if (BLOCK_REG_PADDING (mode, type, 1) == PAD_DOWNWARD + else if (BLOCK_REG_PADDING (mode, type, 1, 0) == PAD_DOWNWARD && size < UNITS_PER_VREG) { adjust = UNITS_PER_VREG - size; @@ -21596,7 +21596,7 @@ aarch64_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, dw_align = true; } - if (BLOCK_REG_PADDING (mode, type, 1) == PAD_DOWNWARD + if (BLOCK_REG_PADDING (mode, type, 1, 0) == PAD_DOWNWARD && size < UNITS_PER_WORD) { adjust = UNITS_PER_WORD - size; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index f07b2c49f0d..510d81bb3ee 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -1127,7 +1127,7 @@ enum arm_pcs /* We can't use machine_mode inside a generator file because it - hasn't been created yet; we shouldn't be using any code that + hasn't been created yet; we shouldn't be using any code that needs the real definition though, so this ought to be safe. */ #ifdef GENERATOR_FILE #define MACHMODE int @@ -1175,8 +1175,9 @@ typedef struct } CUMULATIVE_ARGS; #endif -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ - (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ + (aarch64_pad_reg_upward (MODE, TYPE, FIRST, NAMED) \ + ? PAD_UPWARD : PAD_DOWNWARD) #define PAD_VARARGS_DOWN 0 diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 7311ad4d8e4..1301131964d 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -206,7 +206,7 @@ extern rtx arm_stack_protect_tls_canary_mem (bool); #if defined TREE_CODE extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); -extern bool arm_pad_reg_upward (machine_mode, tree, int); +extern bool arm_pad_reg_upward (machine_mode, tree, int, int); #endif extern int arm_apply_result_size (void); extern opt_machine_mode arm_get_mask_mode (machine_mode mode); diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 0f72f3a9031..75e5e6992ba 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -16944,14 +16944,14 @@ arm_function_arg_padding (machine_mode mode, const_tree type) } -/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). +/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST, NAMED). Return !BYTES_BIG_ENDIAN if the least significant byte of the register has useful data, and return the opposite if the most significant byte does. */ bool -arm_pad_reg_upward (machine_mode mode, - tree type, int first ATTRIBUTE_UNUSED) +arm_pad_reg_upward (machine_mode mode, tree type, + int first ATTRIBUTE_UNUSED, int named ATTRIBUTE_UNUSED) { if (TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN) { diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 13a90d854d2..cac0fe287a9 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1707,8 +1707,8 @@ typedef struct } CUMULATIVE_ARGS; #endif -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ - (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ + (arm_pad_reg_upward (MODE, TYPE, FIRST, NAMED) ? PAD_UPWARD : PAD_DOWNWARD) /* For AAPCS, padding should never be below the argument. For other ABIs, * mimic the default. */ diff --git a/gcc/config/c6x/c6x-protos.h b/gcc/config/c6x/c6x-protos.h index b9ed33c5632..9d43c8585e3 100644 --- a/gcc/config/c6x/c6x-protos.h +++ b/gcc/config/c6x/c6x-protos.h @@ -25,7 +25,7 @@ #ifdef RTX_CODE extern void c6x_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, int); -extern bool c6x_block_reg_pad_upward (machine_mode, const_tree, bool); +extern bool c6x_block_reg_pad_upward (machine_mode, const_tree, bool, int); extern bool c6x_legitimate_address_p_1 (machine_mode, rtx, bool, bool); extern bool c6x_mem_operand (rtx, enum reg_class, bool); diff --git a/gcc/config/c6x/c6x.cc b/gcc/config/c6x/c6x.cc index 20a1666a686..0e36f95d7c6 100644 --- a/gcc/config/c6x/c6x.cc +++ b/gcc/config/c6x/c6x.cc @@ -535,12 +535,13 @@ c6x_function_arg_advance (cumulative_args_t cum_v, const function_arg_info &) } -/* Return true if BLOCK_REG_PADDING (MODE, TYPE, FIRST) should return +/* Return true if BLOCK_REG_PADDING (MODE, TYPE, FIRST, NAMED) should return upward rather than downward. */ bool c6x_block_reg_pad_upward (machine_mode mode ATTRIBUTE_UNUSED, - const_tree type, bool first) + const_tree type, bool first, + int named ATTRIBUTE_UNUSED) { HOST_WIDE_INT size; diff --git a/gcc/config/c6x/c6x.h b/gcc/config/c6x/c6x.h index 1b16ff5e337..ea9b046feba 100644 --- a/gcc/config/c6x/c6x.h +++ b/gcc/config/c6x/c6x.h @@ -333,8 +333,9 @@ struct c6x_args { #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \ c6x_init_cumulative_args (&cum, fntype, libname, n_named_args) -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ - (c6x_block_reg_pad_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ + (c6x_block_reg_pad_upward (MODE, TYPE, FIRST, NAMED) \ + ? PAD_UPWARD : PAD_DOWNWARD) #define FUNCTION_ARG_REGNO_P(r) \ (((r) >= REG_A4 && (r) <= REG_A13) || ((r) >= REG_B4 && (r) <= REG_B13)) diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 1ec6f386f5f..2de7195f2b8 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -247,7 +247,7 @@ extern bool mips16_expand_copy (rtx, rtx, rtx, rtx); extern void mips_expand_synci_loop (rtx, rtx); extern void mips_init_cumulative_args (CUMULATIVE_ARGS *, tree); -extern bool mips_pad_reg_upward (machine_mode, tree); +extern bool mips_pad_reg_upward (machine_mode, tree, int, int); extern bool mips_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT, HOST_WIDE_INT, bool); diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index e0b357a651a..bd62b8b7823 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -7437,13 +7437,20 @@ mips_function_arg_padding (machine_mode mode, const_tree type) return PAD_DOWNWARD; } -/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN - if the least significant byte of the register has useful data. Return - the opposite if the most significant byte does. */ +/* Likewise BLOCK_REG_PADDING (MODE, TYPE, FIRST, NAMED). + Return !BYTES_BIG_ENDIAN if the least significant byte of the register has + useful data. Return the opposite if the most significant byte does. */ bool -mips_pad_reg_upward (machine_mode mode, tree type) +mips_pad_reg_upward (machine_mode mode, tree type, int first ATTRIBUTE_UNUSED, + int named) { + /* The _Float32 value has to be shifted into upper 32 bits when passed + as varags register parameter on big-endian NEWABI targets. */ + if (TARGET_NEWABI && TARGET_BIG_ENDIAN && named == 0 && mode == SFmode + && type != 0 && FLOAT_TYPE_P (type)) + return true; + /* No shifting is required for floating-point arguments. */ if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) return !BYTES_BIG_ENDIAN; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 0245287f9bf..6ed39af01e1 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2593,8 +2593,8 @@ typedef struct mips_args { #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ mips_init_cumulative_args (&CUM, FNTYPE) -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ - (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD) +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ + (mips_pad_reg_upward (MODE, TYPE, FIRST, NAMED) ? PAD_UPWARD : PAD_DOWNWARD) /* True if using EABI and varargs can be passed in floating-point registers. Under these conditions, we need a more complex form diff --git a/gcc/config/nios2/nios2-protos.h b/gcc/config/nios2/nios2-protos.h index 049480c4976..894f6b1beb2 100644 --- a/gcc/config/nios2/nios2-protos.h +++ b/gcc/config/nios2/nios2-protos.h @@ -65,7 +65,7 @@ extern bool gen_ldstwm_peep (bool, int, rtx, rtx *); extern void nios2_adjust_reg_alloc_order (void); -extern pad_direction nios2_block_reg_padding (machine_mode, tree, int); +extern pad_direction nios2_block_reg_padding (machine_mode, tree, int, int); #endif /* RTX_CODE */ diff --git a/gcc/config/nios2/nios2.cc b/gcc/config/nios2/nios2.cc index cb33c67ed2f..8f69c5001bf 100644 --- a/gcc/config/nios2/nios2.cc +++ b/gcc/config/nios2/nios2.cc @@ -3459,7 +3459,7 @@ nios2_function_arg_padding (machine_mode mode, const_tree type) pad_direction nios2_block_reg_padding (machine_mode mode, tree type, - int first ATTRIBUTE_UNUSED) + int first ATTRIBUTE_UNUSED, int named ATTRIBUTE_UNUSED) { return nios2_function_arg_padding (mode, type); } diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h index 88ad1667bc2..6b971d12c1f 100644 --- a/gcc/config/nios2/nios2.h +++ b/gcc/config/nios2/nios2.h @@ -287,8 +287,8 @@ typedef struct nios2_args #define PAD_VARARGS_DOWN \ (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ - (nios2_block_reg_padding ((MODE), (TYPE), (FIRST))) +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ + (nios2_block_reg_padding ((MODE), (TYPE), (FIRST), (NAMED))) #define FUNCTION_ARG_REGNO_P(REGNO) \ ((REGNO) >= FIRST_ARG_REGNO && (REGNO) <= LAST_ARG_REGNO) diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index fa6d05e101a..22721e5ede0 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -661,7 +661,7 @@ struct hppa_args {int words, nargs_prototype, incoming, indirect; }; We use a DImode register in the parallel for 5 to 7 byte structures so that there is only one element. This allows the object to be correctly padded. */ -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ targetm.calls.function_arg_padding ((MODE), (TYPE)) diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h index 7f6c45e3469..29c242fa30a 100644 --- a/gcc/config/rs6000/aix.h +++ b/gcc/config/rs6000/aix.h @@ -246,7 +246,7 @@ /* Specify padding for the last element of a block move between registers and memory. FIRST is nonzero if this is the only element. */ -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ (!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE)) /* Indicate that jump tables go in the text section. */ diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index bd5a016d080..1333872b429 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -441,7 +441,7 @@ /* Specify padding for the last element of a block move between registers and memory. FIRST is nonzero if this is the only element. */ -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ (!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE)) #define DOUBLE_INT_ASM_OP "\t.quad\t" diff --git a/gcc/config/rs6000/freebsd64.h b/gcc/config/rs6000/freebsd64.h index 627fd426134..cd0048d053a 100644 --- a/gcc/config/rs6000/freebsd64.h +++ b/gcc/config/rs6000/freebsd64.h @@ -172,7 +172,7 @@ extern int dot_symbols; /* Specify padding for the last element of a block move between registers and memory. FIRST is nonzero if this is the only element. */ -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ (!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE)) /* FreeBSD doesn't support saving and restoring 64-bit regs with a 32-bit diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 655d1054d76..0bbde2e280f 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -255,7 +255,7 @@ extern int dot_symbols; /* Specify padding for the last element of a block move between registers and memory. FIRST is nonzero if this is the only element. */ -#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST, NAMED) \ (!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE)) /* Linux doesn't support saving and restoring 64-bit regs in a 32-bit diff --git a/gcc/expr.cc b/gcc/expr.cc index caa1a72ba0b..db9861919f2 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -3020,7 +3020,7 @@ emit_group_load_1 (rtx *tmps, rtx dst, rtx orig_src, tree type, extract_bit_field loads to the lsb of the reg. */ if ( #ifdef BLOCK_REG_PADDING - BLOCK_REG_PADDING (GET_MODE (orig_src), type, i == start) + BLOCK_REG_PADDING (GET_MODE (orig_src), type, i == start, -1) == (BYTES_BIG_ENDIAN ? PAD_UPWARD : PAD_DOWNWARD) #else BYTES_BIG_ENDIAN @@ -3456,7 +3456,7 @@ emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, Move the fragment to the lsb if it's not already there. */ if ( #ifdef BLOCK_REG_PADDING - BLOCK_REG_PADDING (GET_MODE (orig_dst), type, i == start) + BLOCK_REG_PADDING (GET_MODE (orig_dst), type, i == start, -1) == (BYTES_BIG_ENDIAN ? PAD_UPWARD : PAD_DOWNWARD) #else BYTES_BIG_ENDIAN diff --git a/gcc/function.cc b/gcc/function.cc index bf74e1ea208..a4b1e1dc28c 100644 --- a/gcc/function.cc +++ b/gcc/function.cc @@ -2885,7 +2885,7 @@ assign_parm_setup_block_p (struct assign_parm_data_one *data) that are padded at the least significant end. */ if (REG_P (data->entry_parm) && known_lt (GET_MODE_SIZE (data->arg.mode), UNITS_PER_WORD) - && (BLOCK_REG_PADDING (data->passed_mode, data->arg.type, 1) + && (BLOCK_REG_PADDING (data->passed_mode, data->arg.type, 1, 1) == (BYTES_BIG_ENDIAN ? PAD_UPWARD : PAD_DOWNWARD))) return true; #endif @@ -3020,7 +3020,7 @@ assign_parm_setup_block (struct assign_parm_data_all *all, if (mode != BLKmode #ifdef BLOCK_REG_PADDING && (size == UNITS_PER_WORD - || (BLOCK_REG_PADDING (mode, data->arg.type, 1) + || (BLOCK_REG_PADDING (mode, data->arg.type, 1, 1) != (BYTES_BIG_ENDIAN ? PAD_UPWARD : PAD_DOWNWARD))) #endif ) @@ -3069,7 +3069,7 @@ assign_parm_setup_block (struct assign_parm_data_all *all, additional changes to work correctly. */ gcc_checking_assert (BYTES_BIG_ENDIAN && (BLOCK_REG_PADDING (mode, - data->arg.type, 1) + data->arg.type, 1, 1) == PAD_UPWARD)); int by = (UNITS_PER_WORD - size) * BITS_PER_UNIT; @@ -3090,7 +3090,7 @@ assign_parm_setup_block (struct assign_parm_data_all *all, handle all cases (e.g. SIZE == 3). */ else if (size != UNITS_PER_WORD #ifdef BLOCK_REG_PADDING - && (BLOCK_REG_PADDING (mode, data->arg.type, 1) + && (BLOCK_REG_PADDING (mode, data->arg.type, 1, 1) == PAD_DOWNWARD) #else && BYTES_BIG_ENDIAN @@ -3114,7 +3114,7 @@ assign_parm_setup_block (struct assign_parm_data_all *all, gcc_checking_assert (size > UNITS_PER_WORD); #ifdef BLOCK_REG_PADDING gcc_checking_assert (BLOCK_REG_PADDING (GET_MODE (mem), - data->arg.type, 0) + data->arg.type, 0, 1) == PAD_UPWARD); #endif emit_move_insn (mem, entry_parm); From patchwork Fri Jan 31 17:13:43 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:14:09 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , dragan.mladjenovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 46/61] nanoMIPS: unnecessary AND following an EXT Thread-Topic: [PATCH 46/61] nanoMIPS: unnecessary AND following an EXT Thread-Index: AQHbdAN6psR0NuKp40m11SSweWgd2g== Date: Fri, 31 Jan 2025 17:13:43 +0000 Message-ID: <20250131171232.1018281-48-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: af32db7f-3594-46db-ec64-08dd421aad28 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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This patch prevents this replacement in two new cases. A: (set (subreg:SI (reg:QI Y)) (zero_extract:SI Z (const_int 8) (const_int ?))) B: (set (reg:SI X) (zero_extend:SI (reg:QI Y))) C: (... (subreg:QI (reg:SI X)) ...) D: (... (reg:SI X) ...) A: (set (reg:SI Y) (zero_extract:SI Z (const_int 8) (const_int ?))) B: (set (reg:SI X) (zero_extend:SI (reg:QI Y))) C: (... (subreg:QI (reg:SI X)) ...) D: (... (reg:SI X) ...) gcc/ * fwprop.cc (free_load_extend): Renamed to ... (free_extend): Handle zero/sign_extract sources. (forward_propagate_subreg): Use free_extend. gcc/testsuite/ * gcc.target/mips/union-zext.c: New. Cherry-picked a76808b917661f102d4b5f6256f76a1a1e580676 from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/fwprop.cc | 38 ++++++++++++++++++---- gcc/testsuite/gcc.target/mips/union-zext.c | 29 +++++++++++++++++ 2 files changed, 60 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/union-zext.c diff --git a/gcc/fwprop.cc b/gcc/fwprop.cc index 8cba6b7ce9f..717415a4fb6 100644 --- a/gcc/fwprop.cc +++ b/gcc/fwprop.cc @@ -614,15 +614,14 @@ try_fwprop_subst (use_info *use, set_info *def, /* For the given single_set INSN, containing SRC known to be a ZERO_EXTEND or SIGN_EXTEND of a register, return true if INSN - is redundant due to the register being set by a LOAD_EXTEND_OP - load from memory. */ + is redundant due to the register being set by ZERO_EXTRACT or + SIGN_EXTRACT of appropriate size or by LOAD_EXTEND_OP load + from memory. */ static bool -free_load_extend (rtx src, insn_info *insn) +free_extend (rtx src, insn_info *insn) { rtx reg = XEXP (src, 0); - if (load_extend_op (GET_MODE (reg)) != GET_CODE (src)) - return false; def_info *def = nullptr; for (use_info *use : insn->uses ()) @@ -644,10 +643,35 @@ free_load_extend (rtx src, insn_info *insn) { rtx patt = PATTERN (def_rtl); - if (GET_CODE (patt) == SET + if (GET_CODE (patt) != SET) + return false; + +#ifdef LOAD_EXTEND_OP + if (LOAD_EXTEND_OP (GET_MODE (reg)) == GET_CODE (src) && GET_CODE (SET_SRC (patt)) == MEM && rtx_equal_p (SET_DEST (patt), reg)) return true; +#endif + + int extract_code = GET_CODE (src) == ZERO_EXTEND + ? ZERO_EXTRACT : SIGN_EXTRACT; + + if (GET_CODE (SET_SRC (patt)) == extract_code + && GET_MODE (SET_SRC (patt)) == GET_MODE (src) + && INTVAL (XEXP (SET_SRC (patt), 1)) + <= GET_MODE_BITSIZE (GET_MODE (reg)).to_constant ()) + { + if (GET_CODE (SET_DEST (patt)) == SUBREG + && GET_MODE (SET_DEST (patt)) == GET_MODE (src) + && rtx_equal_p (XEXP (SET_DEST (patt), 0), reg)) + return true; + + if (REG_P (SET_DEST (patt)) + && GET_MODE (SET_DEST (patt)) == GET_MODE (src) + && REGNO (SET_DEST (patt)) == REGNO (reg)) + return true; + } + } return false; } @@ -709,7 +733,7 @@ forward_propagate_subreg (use_info *use, set_info *def, && REG_P (XEXP (src, 0)) && REGNO (XEXP (src, 0)) >= FIRST_PSEUDO_REGISTER && GET_MODE (XEXP (src, 0)) == use_mode - && !free_load_extend (src, def->insn ()) + && !free_extend (src, def->insn ()) && (targetm.mode_rep_extended (int_use_mode, src_mode) != (int) GET_CODE (src))) return try_fwprop_subst (use, def, loc, use_reg, XEXP (src, 0)); diff --git a/gcc/testsuite/gcc.target/mips/union-zext.c b/gcc/testsuite/gcc.target/mips/union-zext.c new file mode 100644 index 00000000000..6728d415f5a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/union-zext.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "(HAS_INS) -mgp32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tandi\t"} } */ + +typedef struct bits +{ + unsigned B0:8, B1:8, B2:8, B3:8; +} bits_t; + +typedef union +{ + unsigned v; + bits_t b; +} bitfields_t; + +void * +strcpy (void *__restrict__ dst, const void *__restrict__ _a) +{ + unsigned x = *(unsigned *) _a; + bitfields_t bx; + bx.v = x; + + unsigned char v2 = (unsigned char) bx.b.B2; + ((unsigned char *) (dst))[2] = (v2); + if (v2 == 0) + return 0; + return dst; +} From patchwork Fri Jan 31 17:13:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105790 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7B9403858C60 for ; Fri, 31 Jan 2025 18:09:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2070d.outbound.protection.outlook.com [IPv6:2a01:111:f403:2613::70d]) by sourceware.org (Postfix) with ESMTPS id 08506385801B for ; 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Fri, 31 Jan 2025 17:14:10 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , dragan.mladjenovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 48/61] Performance degradation for iDCT-4M example Thread-Topic: [PATCH 48/61] Performance degradation for iDCT-4M example Thread-Index: AQHbdAN7NVyezCGj6kSb66TL9V/j6w== Date: Fri, 31 Jan 2025 17:13:44 +0000 Message-ID: <20250131171232.1018281-50-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: 99c73e7c-f7dd-419b-826f-08dd421aad9c x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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(mips_expand_vector_init): Detect init sequence that can be fused into a single load. * config/mips/mips.opt (mfuse-vect-init): New option. gcc/testsuite/ * gcc.target/mips/msa-fuse-vect-init.c: New file. Cherry-picked 4f440a87ad32b3549be8a0b89900d656ac70d4f8 and 1eb9d22dc480c962027eed522e0b26d0ebbd3e0b from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 61 +++++++++++++++++++ gcc/config/mips/mips.opt | 3 + .../gcc.target/mips/msa-fuse-vect-init.c | 18 ++++++ 3 files changed, 82 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/msa-fuse-vect-init.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index bd62b8b7823..51d9812151a 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -24873,6 +24873,57 @@ mips_expand_vi_general (machine_mode vmode, machine_mode imode, emit_move_insn (target, mem); } +/* Return true if elements of vector initialization list should be loaded + via single "fused" vector load. */ + +bool +mips_fuse_vect_init_p (machine_mode imode, unsigned nelt, rtx vals) +{ + unsigned i; + rtx base; + rtx base1; + rtx first; + rtx next; + HOST_WIDE_INT offset; + HOST_WIDE_INT offset1; + unsigned min_align = GET_MODE_BITSIZE (imode); + unsigned step_size = GET_MODE_SIZE (imode); + + if (!flag_fuse_vect_init) + return false; + + first = XVECEXP (vals, 0, 0); + + if (MEM_VOLATILE_P (first)) + return false; + + if (MEM_ALIGN (first) < min_align) + return false; + + if (GET_MODE (first) != imode) + return false; + + mips_split_plus (XEXP (first, 0), &base, &offset); + + if (!REG_P (base)) + return false; + + for (i = 1; i < nelt; ++i) + { + next = XVECEXP (vals, 0, i); + if (MEM_VOLATILE_P (next) + || MEM_ALIGN (next) < min_align + || GET_MODE (next) != imode) + return false; + mips_split_plus (XEXP (next, 0), &base1, &offset1); + if (!rtx_equal_p (base, base1) || (offset1 - offset) != step_size) + return false; + offset = offset1; + } + + return true; +} + /* Expand a vector initialization. */ void @@ -24883,6 +24934,7 @@ mips_expand_vector_init (rtx target, rtx vals) unsigned i, nelt = GET_MODE_NUNITS (vmode); unsigned nvar = 0, one_var = -1u; bool all_same = true; + bool all_mem = true; rtx x; for (i = 0; i < nelt; ++i) @@ -24890,6 +24942,8 @@ mips_expand_vector_init (rtx target, rtx vals) x = XVECEXP (vals, 0, i); if (!mips_constant_elt_p (x)) nvar++, one_var = i; + if (!MEM_P (x)) + all_mem = false; if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) all_same = false; } @@ -24950,6 +25004,13 @@ mips_expand_vector_init (rtx target, rtx vals) } else { + if (all_mem && mips_fuse_vect_init_p (imode, nelt, vals)) + { + rtx mem = widen_memory_access (XVECEXP (vals, 0, 0), vmode, 0); + emit_move_insn (target, mem); + return; + } + emit_move_insn (target, CONST0_RTX (vmode)); for (i = 0; i < nelt; ++i) diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index d162702c220..be347155286 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -576,3 +576,6 @@ Allow inlining even if the compression flags differ between caller and callee. msched-weight Target Var(TARGET_SCHED_WEIGHT) Undocumented + +mfuse-vect-init +Target Var(flag_fuse_vect_init) Undocumented Init(-1) diff --git a/gcc/testsuite/gcc.target/mips/msa-fuse-vect-init.c b/gcc/testsuite/gcc.target/mips/msa-fuse-vect-init.c new file mode 100644 index 00000000000..faa1ff4eee6 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-fuse-vect-init.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp64 -mhard-float -mmsa" } */ +/* { dg-additional-options "-mfuse-vect-init" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +typedef int v4i32 __attribute__ ((vector_size(16))); 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Fri, 31 Jan 2025 17:14:13 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , dragan.mladjenovic , Mihailo Stojanovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 49/61] Make rtl if-conversion more common Thread-Topic: [PATCH 49/61] Make rtl if-conversion more common Thread-Index: AQHbdAN77rXSzZMeikyQ+ox12VRXTg== Date: Fri, 31 Jan 2025 17:13:44 +0000 Message-ID: <20250131171232.1018281-51-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: e1bb4e41-59b3-43d6-1dbd-08dd421aaf1f x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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(mips_max_noce_ifcvt_seq_cost): New function. Decrease maximum permissible cost for the unconditional sequence which should be generated during if-conversion (for all non-r6 targets). This disables if-conversion for non-r6 targets in branch-cost-1.c test. (mips_noce_conversion_profitable_p): New function. (TARGET_MAX_NOCE_IFCVT_SEQ_COST): Define hook. (TARGET_NOCE_CONVERSION_PROFITABLE_P): Define hook. gcc/testsuite/ * gcc.target/mips/branch-cost-1.c: Disable for -Os. Cherry-picked 1d1ac2a7bdbb6a1ab1a90bfcd9fa6e8a96dcb316 and 8f596d9c4336e8f6e0a01fa22634989eda7d51da from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 65 +++++++++++++++++++ gcc/testsuite/gcc.target/mips/branch-cost-1.c | 2 +- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 51d9812151a..0b155c107c2 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -70,6 +70,7 @@ along with GCC; see the file COPYING3. If not see #include "opts.h" #include "tm-constrs.h" #include "print-rtl.h" +#include "ifcvt.h" /* This file should be included last. */ #include "target-def.h" @@ -5618,6 +5619,12 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code, } return false; + case IF_THEN_ELSE: + if (reg_or_0_operand (XEXP (x, 1), VOIDmode) + || reg_or_0_operand (XEXP (x, 2), VOIDmode)) + *total = 0; + return false; + default: return false; } @@ -25641,6 +25648,58 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) return false; } + +/* Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST. */ + +static unsigned int +mips_max_noce_ifcvt_seq_cost (edge e) +{ + bool predictable_p = predictable_edge_p (e); + + /* If we have a parameter set, use that, otherwise take a guess using + BRANCH_COST. */ + if (predictable_p) + { + if (OPTION_SET_P (param_max_rtl_if_conversion_predictable_cost)) + return param_max_rtl_if_conversion_predictable_cost; + } + else + { + if (OPTION_SET_P (param_max_rtl_if_conversion_unpredictable_cost)) + return param_max_rtl_if_conversion_unpredictable_cost; + } + + return BRANCH_COST (true, predictable_p) + * COSTS_N_INSNS (mips_isa_rev == 6 ? 4 : 3); +} + +/* Return true if SEQ is a good candidate as a replacement for the + if-convertible sequence described in IF_INFO. */ + +static bool +mips_noce_conversion_profitable_p (rtx_insn *seq, struct noce_if_info *if_info) +{ + bool speed = if_info->speed_p; + unsigned cost = 0; + rtx set; + + for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn)) + { + set = single_set (insn); + if (set) + cost += pattern_cost (set, speed); + else + cost++; + } + + if (cost <= if_info->original_cost) + return true; + /* When compiling for size, we can make a reasonably accurately guess + at the size growth. When compiling for speed, use the maximum. */ + return speed && cost <= if_info->max_seq_cost; +} + + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -25976,6 +26035,12 @@ mips_bit_clear_p (enum machine_mode mode, unsigned HOST_WIDE_INT m) #undef TARGET_SCHED_FUSION_PRIORITY #define TARGET_SCHED_FUSION_PRIORITY mips_sched_fusion_priority +#undef TARGET_MAX_NOCE_IFCVT_SEQ_COST +#define TARGET_MAX_NOCE_IFCVT_SEQ_COST mips_max_noce_ifcvt_seq_cost + +#undef TARGET_NOCE_CONVERSION_PROFITABLE_P +#define TARGET_NOCE_CONVERSION_PROFITABLE_P mips_noce_conversion_profitable_p + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-mips.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-cost-1.c b/gcc/testsuite/gcc.target/mips/branch-cost-1.c index 7f7ebbe5fc9..006a29a7361 100644 --- a/gcc/testsuite/gcc.target/mips/branch-cost-1.c +++ b/gcc/testsuite/gcc.target/mips/branch-cost-1.c @@ -1,5 +1,5 @@ /* { dg-options "-mbranch-cost=1 (HAS_MOVN)" } */ -/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os" } { "" } } */ NOMIPS16 int foo (int x, int y, int z, int k) { From patchwork Fri Jan 31 17:13:45 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:14:13 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Mihailo Stojanovic , Mihailo Stojanovic , Dragan Mladjenovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 50/61] Fix MSA SUBREG moves on big-endian targets Thread-Topic: [PATCH 50/61] Fix MSA SUBREG moves on big-endian targets Thread-Index: AQHbdAN8gTgUZuBJtUy6xCYMV7UYAQ== Date: Fri, 31 Jan 2025 17:13:45 +0000 Message-ID: <20250131171232.1018281-52-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: c58b04ef-e362-4a8d-6d98-08dd421aaf5b x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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It borrows heavily from [1] as Aarch64 has the same problem with SVE vectors. Conceptually, register bitconverts should act as the data has been stored to memory in one mode, and loaded from memory in the other. This isn't what happens on big-endian as vector load/store instructions are essentially mixed-endian with respect to the vector as a whole. The in-register representation of data must be changed so that the load/store round trip becomes valid. This is done by inserting one or two shuffle instructions for every SUBREG move, as previously implemented in [2] for LLVM. Even if the shuffle instructions weren't generated, constraint in mips_can_change_mode_class would force the conceptual memory reload of SUBREG move operand, which would generate correct, albeit very inefficient code. New msa_reg_predicate was created in order to forbig SUBREG operands in MSA patterns on big-endian targets. It weeds SUBREGs out of the instruction patterns into SUBREG->REG moves which are caught by the new msa_mov_subreg_be pattern and transformed in shuffle(s). As for the MSA calling convention, ABI states that compiling for MSA should not change the base ABIs vector calling convention, that is, MSA vectors passed of returned by value do not use the MSA vector registers. Instead, they are passed by general-purpose registers, as described by the ABI. Passing the vector argument requires splitting it into 2 (or 4) general-purpose registers and bitconverting it into V2DImode (or V4SImode). The solution boils down to the one presented for SUBREG moves: force every vector argument to the appropriate mode (V2DI or V4SI) so that the shuffle instruction(s) might be generated in order to conform to the calling convention. The same applies to vectors as return values. New testcases were added to check calling convention compliance for all possible combinations of MSA and non-MSA interlinking. gcc/ * config/mips/mips-msa.md: Replace register_operand predicate with msa_reg_operand in every pattern. (*msa_mov_subreg_be): New unspec. * config/mips/mips-protos.h (mips_split_msa_subreg_move): Declare. * config/mips/mips.cc (mips_maybe_expand_msa_subreg_move): New function. (mips_replace_reg_mode): Ditto. (mips_split_msa_subreg_move): Ditto. (mips_legitimize_move): Modify machine modes of MSA vectors which reside in general-purpose registers. Check whether SUBREG move can be replaced with shuffle(s). (mips_split_128bit_move): Replace explicit REG creation with mips_replace_reg_mode. (mips_split_msa_copy_d): Ditto. (mips_split_msa_insert_d): Ditto. (mips_split_msa_fill_d): Ditto. * config/mips/predicates.md (msa_reg_operand): New predicate. gcc/testsuite: * gcc.target/mips/inter/msa-inter.exp: New file. * gcc.target/mips/inter/msa_1.h: New test. * gcc.target/mips/inter/msa_1_main.c: New test. * gcc.target/mips/inter/msa_1_x.c: New test. * gcc.target/mips/inter/msa_1_y.c: New test. Cherry-picked 8c54834001d76ed3c76832b6a47dfcb7d62bb664 and ae63e81745e8a5c07812428ecda735320201d500 from https://github.com/MIPS/gcc Signed-off-by: Mihailo Stojanovic Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips-msa.md | 1056 +++++++++-------- gcc/config/mips/mips-protos.h | 2 + gcc/config/mips/mips.cc | 153 ++- gcc/config/mips/predicates.md | 5 + .../gcc.target/mips/inter/msa-inter.exp | 67 ++ gcc/testsuite/gcc.target/mips/inter/msa_1.h | 23 + .../gcc.target/mips/inter/msa_1_main.c | 8 + gcc/testsuite/gcc.target/mips/inter/msa_1_x.c | 35 + gcc/testsuite/gcc.target/mips/inter/msa_1_y.c | 14 + 9 files changed, 836 insertions(+), 527 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/inter/msa-inter.exp create mode 100644 gcc/testsuite/gcc.target/mips/inter/msa_1.h create mode 100644 gcc/testsuite/gcc.target/mips/inter/msa_1_main.c create mode 100644 gcc/testsuite/gcc.target/mips/inter/msa_1_x.c create mode 100644 gcc/testsuite/gcc.target/mips/inter/msa_1_y.c diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 5ac4fa4bf24..e2fdf8e191e 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -91,6 +91,7 @@ UNSPEC_MSA_SUBSUS_U UNSPEC_MSA_VSHF UNSPEC_MSA_CHANGE_MODE + UNSPEC_MSA_SUBREG_BE ]) ;; All vector modes with 128 bits. @@ -237,7 +238,7 @@ (V4SF "31") (V8SF "31")]) (define_expand "vec_init" - [(match_operand:MSA 0 "register_operand") + [(match_operand:MSA 0 "msa_reg_operand") (match_operand:MSA 1 "")] "ISA_HAS_MSA" { @@ -247,22 +248,22 @@ ;; pckev pattern with implicit type conversion. (define_insn "vec_pack_trunc_" - [(set (match_operand: 0 "register_operand" "=f") + [(set (match_operand: 0 "msa_reg_operand" "=f") (vec_concat: (truncate: - (match_operand:IMSA_DWH 1 "register_operand" "f")) + (match_operand:IMSA_DWH 1 "msa_reg_operand" "f")) (truncate: - (match_operand:IMSA_DWH 2 "register_operand" "f"))))] + (match_operand:IMSA_DWH 2 "msa_reg_operand" "f"))))] "ISA_HAS_MSA" "pckev.\t%w0,%w2,%w1" [(set_attr "type" "simd_permute") (set_attr "mode" "")]) (define_expand "vec_unpacks_hi_v4sf" - [(set (match_operand:V2DF 0 "register_operand" "=f") + [(set (match_operand:V2DF 0 "msa_reg_operand" "=f") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "f") + (match_operand:V4SF 1 "msa_reg_operand" "f") (match_dup 2))))] "ISA_HAS_MSA" { @@ -270,10 +271,10 @@ }) (define_expand "vec_unpacks_lo_v4sf" - [(set (match_operand:V2DF 0 "register_operand" "=f") + [(set (match_operand:V2DF 0 "msa_reg_operand" "=f") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "f") + (match_operand:V4SF 1 "msa_reg_operand" "f") (match_dup 2))))] "ISA_HAS_MSA" { @@ -281,8 +282,8 @@ }) (define_expand "vec_unpacks_hi_" - [(match_operand: 0 "register_operand") - (match_operand:IMSA_WHB 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:IMSA_WHB 1 "msa_reg_operand")] "ISA_HAS_MSA" { mips_expand_vec_unpack (operands, false/*unsigned_p*/, true/*high_p*/); @@ -290,8 +291,8 @@ }) (define_expand "vec_unpacks_lo_" - [(match_operand: 0 "register_operand") - (match_operand:IMSA_WHB 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:IMSA_WHB 1 "msa_reg_operand")] "ISA_HAS_MSA" { mips_expand_vec_unpack (operands, false/*unsigned_p*/, false/*high_p*/); @@ -299,8 +300,8 @@ }) (define_expand "vec_unpacku_hi_" - [(match_operand: 0 "register_operand") - (match_operand:IMSA_WHB 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:IMSA_WHB 1 "msa_reg_operand")] "ISA_HAS_MSA" { mips_expand_vec_unpack (operands, true/*unsigned_p*/, true/*high_p*/); @@ -308,8 +309,8 @@ }) (define_expand "vec_unpacku_lo_" - [(match_operand: 0 "register_operand") - (match_operand:IMSA_WHB 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:IMSA_WHB 1 "msa_reg_operand")] "ISA_HAS_MSA" { mips_expand_vec_unpack (operands, true/*unsigned_p*/, false/*high_p*/); @@ -317,8 +318,8 @@ }) (define_expand "vec_extract" - [(match_operand: 0 "register_operand") - (match_operand:IMSA 1 "register_operand") + [(match_operand: 0 "msa_reg_operand") + (match_operand:IMSA 1 "msa_reg_operand") (match_operand 2 "const__operand")] "ISA_HAS_MSA" { @@ -335,8 +336,8 @@ }) (define_expand "vec_extract" - [(match_operand: 0 "register_operand") - (match_operand:FMSA 1 "register_operand") + [(match_operand: 0 "msa_reg_operand") + (match_operand:FMSA 1 "msa_reg_operand") (match_operand 2 "const__operand")] "ISA_HAS_MSA" { @@ -363,9 +364,9 @@ }) (define_insn_and_split "msa_vec_extract_" - [(set (match_operand: 0 "register_operand" "=f") + [(set (match_operand: 0 "msa_reg_operand" "=f") (vec_select: - (match_operand:FMSA 1 "register_operand" "f") + (match_operand:FMSA 1 "msa_reg_operand" "f") (parallel [(const_int 0)])))] "ISA_HAS_MSA" "#" @@ -389,7 +390,7 @@ (set_attr "mode" "")]) (define_expand "vec_set" - [(match_operand:IMSA 0 "register_operand") + [(match_operand:IMSA 0 "msa_reg_operand") (match_operand: 1 "reg_or_0_operand") (match_operand 2 "const__operand")] "ISA_HAS_MSA" @@ -401,8 +402,8 @@ }) (define_expand "vec_set" - [(match_operand:FMSA 0 "register_operand") - (match_operand: 1 "register_operand") + [(match_operand:FMSA 0 "msa_reg_operand") + (match_operand: 1 "msa_reg_operand") (match_operand 2 "const__operand")] "ISA_HAS_MSA" { @@ -413,10 +414,10 @@ }) (define_expand "vcond_mask_" - [(match_operand:MSA 0 "register_operand") + [(match_operand:MSA 0 "msa_reg_operand") (match_operand:MSA 1 "reg_or_m1_operand") (match_operand:MSA 2 "reg_or_0_operand") - (match_operand:IMSA 3 "register_operand")] + (match_operand:IMSA 3 "msa_reg_operand")] "ISA_HAS_MSA && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))" { @@ -426,12 +427,12 @@ (define_expand "vcondu" - [(match_operand:MSA 0 "register_operand") + [(match_operand:MSA 0 "msa_reg_operand") (match_operand:MSA 1 "reg_or_m1_operand") (match_operand:MSA 2 "reg_or_0_operand") (match_operator 3 "" - [(match_operand:IMSA 4 "register_operand") - (match_operand:IMSA 5 "register_operand")])] + [(match_operand:IMSA 4 "msa_reg_operand") + (match_operand:IMSA 5 "msa_reg_operand")])] "ISA_HAS_MSA && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))" { @@ -440,12 +441,12 @@ }) (define_expand "vcond" - [(match_operand:MSA 0 "register_operand") + [(match_operand:MSA 0 "msa_reg_operand") (match_operand:MSA 1 "reg_or_m1_operand") (match_operand:MSA 2 "reg_or_0_operand") (match_operator 3 "" - [(match_operand:MSA_2 4 "register_operand") - (match_operand:MSA_2 5 "register_operand")])] + [(match_operand:MSA_2 4 "msa_reg_operand") + (match_operand:MSA_2 5 "msa_reg_operand")])] "ISA_HAS_MSA && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))" { @@ -454,10 +455,10 @@ }) (define_expand "vec_cmp" - [(match_operand: 0 "register_operand") + [(match_operand: 0 "msa_reg_operand") (match_operator 1 "" - [(match_operand:MSA 2 "register_operand") - (match_operand:MSA 3 "register_operand")])] + [(match_operand:MSA 2 "msa_reg_operand") + (match_operand:MSA 3 "msa_reg_operand")])] "ISA_HAS_MSA" { mips_expand_vec_cmp_expr (operands); @@ -465,10 +466,10 @@ }) (define_expand "vec_cmpu" - [(match_operand: 0 "register_operand") + [(match_operand: 0 "msa_reg_operand") (match_operator 1 "" - [(match_operand:IMSA 2 "register_operand") - (match_operand:IMSA 3 "register_operand")])] + [(match_operand:IMSA 2 "msa_reg_operand") + (match_operand:IMSA 3 "msa_reg_operand")])] "ISA_HAS_MSA" { mips_expand_vec_cmp_expr (operands); @@ -476,11 +477,11 @@ }) (define_insn "msa_insert_" - [(set (match_operand:MSA 0 "register_operand" "=f,f") + [(set (match_operand:MSA 0 "msa_reg_operand" "=f,f") (vec_merge:MSA (vec_duplicate:MSA (match_operand: 1 "reg_or_0_operand" "dJ,f")) - (match_operand:MSA 2 "register_operand" "0,0") + (match_operand:MSA 2 "msa_reg_operand" "0,0") (match_operand 3 "const__operand" "")))] "ISA_HAS_MSA" { @@ -496,11 +497,11 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:MSA_D 0 "register_operand") + [(set (match_operand:MSA_D 0 "msa_reg_operand") (vec_merge:MSA_D (vec_duplicate:MSA_D (match_operand: 1 "_operand")) - (match_operand:MSA_D 2 "register_operand") + (match_operand:MSA_D 2 "msa_reg_operand") (match_operand 3 "const__operand")))] "reload_completed && ISA_HAS_MSA && !TARGET_64BIT" [(const_int 0)] @@ -512,13 +513,13 @@ }) (define_insn "msa_insve_" - [(set (match_operand:MSA 0 "register_operand" "=f") + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") (vec_merge:MSA (vec_duplicate:MSA (vec_select: - (match_operand:MSA 1 "register_operand" "f") + (match_operand:MSA 1 "msa_reg_operand" "f") (parallel [(const_int 0)]))) - (match_operand:MSA 2 "register_operand" "0") + (match_operand:MSA 2 "msa_reg_operand" "0") (match_operand 3 "const__operand" "")))] "ISA_HAS_MSA" "insve.\t%w0[%y3],%w1[0]" @@ -527,11 +528,11 @@ ;; Operand 3 is a scalar. (define_insn "msa_insve__scalar" - [(set (match_operand:FMSA 0 "register_operand" "=f") + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") (vec_merge:FMSA (vec_duplicate:FMSA - (match_operand: 1 "register_operand" "f")) - (match_operand:FMSA 2 "register_operand" "0") + (match_operand: 1 "msa_reg_operand" "f")) + (match_operand:FMSA 2 "msa_reg_operand" "0") (match_operand 3 "const__operand" "")))] "ISA_HAS_MSA" "insve.\t%w0[%y3],%w1[0]" @@ -539,10 +540,10 @@ (set_attr "mode" "")]) (define_insn "msa_copy__" - [(set (match_operand: 0 "register_operand" "=d") + [(set (match_operand: 0 "msa_reg_operand" "=d") (any_extend: (vec_select: - (match_operand:IMSA_HB 1 "register_operand" "f") + (match_operand:IMSA_HB 1 "msa_reg_operand" "f") (parallel [(match_operand 2 "const__operand" "")]))))] "ISA_HAS_MSA" "copy_.\t%0,%w1[%2]" @@ -550,10 +551,10 @@ (set_attr "mode" "")]) (define_insn "msa_copy_u_w" - [(set (match_operand:DI 0 "register_operand" "=d") + [(set (match_operand:DI 0 "msa_reg_operand" "=d") (zero_extend:DI (vec_select:SI - (match_operand:V4SI 1 "register_operand" "f") + (match_operand:V4SI 1 "msa_reg_operand" "f") (parallel [(match_operand 2 "const_0_to_3_operand" "")]))))] "ISA_HAS_MSA && TARGET_64BIT" "copy_u.w\t%0,%w1[%2]" @@ -561,10 +562,10 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_copy_s__64bit" - [(set (match_operand:DI 0 "register_operand" "=d") + [(set (match_operand:DI 0 "msa_reg_operand" "=d") (sign_extend:DI (vec_select: - (match_operand:MSA_W 1 "register_operand" "f") + (match_operand:MSA_W 1 "msa_reg_operand" "f") (parallel [(match_operand 2 "const__operand" "")]))))] "ISA_HAS_MSA && TARGET_64BIT" "copy_s.\t%0,%w1[%2]" @@ -572,9 +573,9 @@ (set_attr "mode" "")]) (define_insn "msa_copy_s_" - [(set (match_operand: 0 "register_operand" "=d") + [(set (match_operand: 0 "msa_reg_operand" "=d") (vec_select: - (match_operand:MSA_W 1 "register_operand" "f") + (match_operand:MSA_W 1 "msa_reg_operand" "f") (parallel [(match_operand 2 "const__operand" "")])))] "ISA_HAS_MSA" "copy_s.\t%0,%w1[%2]" @@ -582,9 +583,9 @@ (set_attr "mode" "")]) (define_insn_and_split "msa_copy_s_" - [(set (match_operand: 0 "register_operand" "=d") + [(set (match_operand: 0 "msa_reg_operand" "=d") (vec_select: - (match_operand:MSA_D 1 "register_operand" "f") + (match_operand:MSA_D 1 "msa_reg_operand" "f") (parallel [(match_operand 2 "const__operand" "")])))] "ISA_HAS_MSA" { @@ -604,8 +605,8 @@ (set_attr "mode" "")]) (define_expand "abs2" - [(match_operand:IMSA 0 "register_operand" "=f") - (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))] + [(match_operand:IMSA 0 "msa_reg_operand" "=f") + (abs:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f"))] "ISA_HAS_MSA" { rtx reg = gen_reg_rtx (mode); @@ -615,9 +616,9 @@ }) (define_expand "neg2" - [(set (match_operand:IMSA 0 "register_operand") + [(set (match_operand:IMSA 0 "msa_reg_operand") (minus:IMSA (match_dup 2) - (match_operand:IMSA 1 "register_operand")))] + (match_operand:IMSA 1 "msa_reg_operand")))] "ISA_HAS_MSA" { rtx reg = gen_reg_rtx (mode); @@ -626,15 +627,15 @@ }) (define_insn "neg2" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (neg:FMSA (match_operand:FMSA 1 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (neg:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "bnegi.\t%w0,%w1," [(set_attr "type" "simd_bit") (set_attr "mode" "")]) (define_expand "msa_ldi" - [(match_operand:IMSA 0 "register_operand") + [(match_operand:IMSA 0 "msa_reg_operand") (match_operand 1 "const_imm10_operand")] "ISA_HAS_MSA" { @@ -647,10 +648,10 @@ }) (define_insn "vec_perm" - [(set (match_operand:MSA 0 "register_operand" "=f") - (unspec:MSA [(match_operand:MSA 1 "register_operand" "f") - (match_operand:MSA 2 "register_operand" "f") - (match_operand: 3 "register_operand" "0")] + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") + (unspec:MSA [(match_operand:MSA 1 "msa_reg_operand" "f") + (match_operand:MSA 2 "msa_reg_operand" "f") + (match_operand: 3 "msa_reg_operand" "0")] UNSPEC_MSA_VSHF))] "ISA_HAS_MSA" "vshf.\t%w0,%w2,%w1" @@ -698,7 +699,7 @@ ;; Offset load (define_expand "msa_ld_" - [(match_operand:MSA 0 "register_operand") + [(match_operand:MSA 0 "msa_reg_operand") (match_operand 1 "pmode_register_operand") (match_operand 2 "aq10_operand")] "ISA_HAS_MSA" @@ -711,7 +712,7 @@ ;; Offset store (define_expand "msa_st_" - [(match_operand:MSA 0 "register_operand") + [(match_operand:MSA 0 "msa_reg_operand") (match_operand 1 "pmode_register_operand") (match_operand 2 "aq10_operand")] "ISA_HAS_MSA" @@ -724,9 +725,9 @@ ;; Integer operations (define_insn "add3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f,f") (plus:IMSA - (match_operand:IMSA 1 "register_operand" "f,f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f,f") (match_operand:IMSA 2 "reg_or_vector_same_ximm5_operand" "f,Unv5,Uuv5")))] "ISA_HAS_MSA" { @@ -752,9 +753,9 @@ (set_attr "mode" "")]) (define_insn "sub3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") (minus:IMSA - (match_operand:IMSA 1 "register_operand" "f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))] "ISA_HAS_MSA" "@ @@ -765,74 +766,74 @@ (set_attr "mode" "")]) (define_insn "mul3" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (mult:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (mult:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "mulv.\t%w0,%w1,%w2" [(set_attr "type" "simd_mul") (set_attr "mode" "")]) (define_insn "msa_maddv_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (plus:IMSA (mult:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")) - (match_operand:IMSA 3 "register_operand" "0")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (plus:IMSA (mult:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")) + (match_operand:IMSA 3 "msa_reg_operand" "0")))] "ISA_HAS_MSA" "maddv.\t%w0,%w1,%w2" [(set_attr "type" "simd_mul") (set_attr "mode" "")]) (define_insn "msa_msubv_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (minus:IMSA (match_operand:IMSA 1 "register_operand" "0") - (mult:IMSA (match_operand:IMSA 2 "register_operand" "f") - (match_operand:IMSA 3 "register_operand" "f"))))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (minus:IMSA (match_operand:IMSA 1 "msa_reg_operand" "0") + (mult:IMSA (match_operand:IMSA 2 "msa_reg_operand" "f") + (match_operand:IMSA 3 "msa_reg_operand" "f"))))] "ISA_HAS_MSA" "msubv.\t%w0,%w2,%w3" [(set_attr "type" "simd_mul") (set_attr "mode" "")]) (define_insn "div3" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (div:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (div:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" { return mips_msa_output_division ("div_s.\t%w0,%w1,%w2", operands); } [(set_attr "type" "simd_div") (set_attr "mode" "")]) (define_insn "udiv3" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (udiv:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (udiv:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" { return mips_msa_output_division ("div_u.\t%w0,%w1,%w2", operands); } [(set_attr "type" "simd_div") (set_attr "mode" "")]) (define_insn "mod3" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (mod:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (mod:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" { return mips_msa_output_division ("mod_s.\t%w0,%w1,%w2", operands); } [(set_attr "type" "simd_div") (set_attr "mode" "")]) (define_insn "umod3" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (umod:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (umod:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" { return mips_msa_output_division ("mod_u.\t%w0,%w1,%w2", operands); } [(set_attr "type" "simd_div") (set_attr "mode" "")]) (define_insn "xor3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f,f") (xor:IMSA - (match_operand:IMSA 1 "register_operand" "f,f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f,f") (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] "ISA_HAS_MSA" "@ @@ -843,9 +844,9 @@ (set_attr "mode" "")]) (define_insn "ior3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f,f") (ior:IMSA - (match_operand:IMSA 1 "register_operand" "f,f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f,f") (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] "ISA_HAS_MSA" "@ @@ -856,9 +857,9 @@ (set_attr "mode" "")]) (define_insn "and3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f,f") (and:IMSA - (match_operand:IMSA 1 "register_operand" "f,f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f,f") (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))] "ISA_HAS_MSA" { @@ -883,17 +884,17 @@ (set_attr "mode" "")]) (define_insn "one_cmpl2" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (not:IMSA (match_operand:IMSA 1 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (not:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "nor.v\t%w0,%w1,%w1" [(set_attr "type" "simd_logic") (set_attr "mode" "TI")]) (define_insn "vlshr3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") (lshiftrt:IMSA - (match_operand:IMSA 1 "register_operand" "f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] "ISA_HAS_MSA" { @@ -906,9 +907,9 @@ (set_attr "mode" "")]) (define_insn "vashr3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") (ashiftrt:IMSA - (match_operand:IMSA 1 "register_operand" "f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] "ISA_HAS_MSA" { @@ -921,9 +922,9 @@ (set_attr "mode" "")]) (define_insn "vashl3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") (ashift:IMSA - (match_operand:IMSA 1 "register_operand" "f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] "ISA_HAS_MSA" { @@ -937,64 +938,64 @@ ;; Floating-point operations (define_insn "add3" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (plus:FMSA (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (plus:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "fadd.\t%w0,%w1,%w2" [(set_attr "type" "simd_fadd") (set_attr "mode" "")]) (define_insn "sub3" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (minus:FMSA (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (minus:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "fsub.\t%w0,%w1,%w2" [(set_attr "type" "simd_fadd") (set_attr "mode" "")]) (define_insn "mul3" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (mult:FMSA (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (mult:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "fmul.\t%w0,%w1,%w2" [(set_attr "type" "simd_fmul") (set_attr "mode" "")]) (define_insn "div3" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (div:FMSA (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (div:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "fdiv.\t%w0,%w1,%w2" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) (define_insn "fma4" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (fma:FMSA (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f") - (match_operand:FMSA 3 "register_operand" "0")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (fma:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f") + (match_operand:FMSA 3 "msa_reg_operand" "0")))] "ISA_HAS_MSA" "fmadd.\t%w0,%w1,%w2" [(set_attr "type" "simd_fmadd") (set_attr "mode" "")]) (define_insn "fnma4" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "register_operand" "f")) - (match_operand:FMSA 2 "register_operand" "f") - (match_operand:FMSA 3 "register_operand" "0")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f")) + (match_operand:FMSA 2 "msa_reg_operand" "f") + (match_operand:FMSA 3 "msa_reg_operand" "0")))] "ISA_HAS_MSA" "fmsub.\t%w0,%w1,%w2" [(set_attr "type" "simd_fmadd") (set_attr "mode" "")]) (define_insn "sqrt2" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (sqrt:FMSA (match_operand:FMSA 1 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (sqrt:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "fsqrt.\t%w0,%w1" [(set_attr "type" "simd_fdiv") @@ -1002,46 +1003,46 @@ ;; Built-in functions (define_insn "msa_add_a_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (plus:IMSA (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) - (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (plus:IMSA (abs:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f")) + (abs:IMSA (match_operand:IMSA 2 "msa_reg_operand" "f"))))] "ISA_HAS_MSA" "add_a.\t%w0,%w1,%w2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) (define_insn "msa_adds_a_" - [(set (match_operand:IMSA 0 "register_operand" "=f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") (ss_plus:IMSA - (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) - (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))] + (abs:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f")) + (abs:IMSA (match_operand:IMSA 2 "msa_reg_operand" "f"))))] "ISA_HAS_MSA" "adds_a.\t%w0,%w1,%w2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) (define_insn "ssadd3" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (ss_plus:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (ss_plus:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "adds_s.\t%w0,%w1,%w2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) (define_insn "usadd3" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (us_plus:IMSA (match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (us_plus:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "adds_u.\t%w0,%w1,%w2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) (define_insn "msa_asub_s_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_ASUB_S))] "ISA_HAS_MSA" "asub_s.\t%w0,%w1,%w2" @@ -1049,9 +1050,9 @@ (set_attr "mode" "")]) (define_insn "msa_asub_u_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_ASUB_U))] "ISA_HAS_MSA" "asub_u.\t%w0,%w1,%w2" @@ -1059,9 +1060,9 @@ (set_attr "mode" "")]) (define_insn "msa_ave_s_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_AVE_S))] "ISA_HAS_MSA" "ave_s.\t%w0,%w1,%w2" @@ -1069,9 +1070,9 @@ (set_attr "mode" "")]) (define_insn "msa_ave_u_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_AVE_U))] "ISA_HAS_MSA" "ave_u.\t%w0,%w1,%w2" @@ -1079,9 +1080,9 @@ (set_attr "mode" "")]) (define_insn "msa_aver_s_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_AVER_S))] "ISA_HAS_MSA" "aver_s.\t%w0,%w1,%w2" @@ -1089,9 +1090,9 @@ (set_attr "mode" "")]) (define_insn "msa_aver_u_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_AVER_U))] "ISA_HAS_MSA" "aver_u.\t%w0,%w1,%w2" @@ -1099,9 +1100,9 @@ (set_attr "mode" "")]) (define_insn "msa_bclr_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_BCLR))] "ISA_HAS_MSA" "bclr.\t%w0,%w1,%w2" @@ -1109,8 +1110,8 @@ (set_attr "mode" "")]) (define_insn "msa_bclri_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") (match_operand 2 "const__operand" "")] UNSPEC_MSA_BCLRI))] "ISA_HAS_MSA" @@ -1119,10 +1120,10 @@ (set_attr "mode" "")]) (define_insn "msa_binsl_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") - (match_operand:IMSA 2 "register_operand" "f") - (match_operand:IMSA 3 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "0") + (match_operand:IMSA 2 "msa_reg_operand" "f") + (match_operand:IMSA 3 "msa_reg_operand" "f")] UNSPEC_MSA_BINSL))] "ISA_HAS_MSA" "binsl.\t%w0,%w2,%w3" @@ -1130,9 +1131,9 @@ (set_attr "mode" "")]) (define_insn "msa_binsli_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") - (match_operand:IMSA 2 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "0") + (match_operand:IMSA 2 "msa_reg_operand" "f") (match_operand 3 "const__operand" "")] UNSPEC_MSA_BINSLI))] "ISA_HAS_MSA" @@ -1141,10 +1142,10 @@ (set_attr "mode" "")]) (define_insn "msa_binsr_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") - (match_operand:IMSA 2 "register_operand" "f") - (match_operand:IMSA 3 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "0") + (match_operand:IMSA 2 "msa_reg_operand" "f") + (match_operand:IMSA 3 "msa_reg_operand" "f")] UNSPEC_MSA_BINSR))] "ISA_HAS_MSA" "binsr.\t%w0,%w2,%w3" @@ -1152,9 +1153,9 @@ (set_attr "mode" "")]) (define_insn "msa_binsri_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") - (match_operand:IMSA 2 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "0") + (match_operand:IMSA 2 "msa_reg_operand" "f") (match_operand 3 "const__operand" "")] UNSPEC_MSA_BINSRI))] "ISA_HAS_MSA" @@ -1163,11 +1164,11 @@ (set_attr "mode" "")]) (define_insn "msa_bmnz_" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") - (ior:IMSA (and:IMSA (match_operand:IMSA 2 "register_operand" "f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") + (ior:IMSA (and:IMSA (match_operand:IMSA 2 "msa_reg_operand" "f,f") (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8")) (and:IMSA (not:IMSA (match_dup 3)) - (match_operand:IMSA 1 "register_operand" "0,0"))))] + (match_operand:IMSA 1 "msa_reg_operand" "0,0"))))] "ISA_HAS_MSA" "@ bmnz.v\t%w0,%w2,%w3 @@ -1176,11 +1177,11 @@ (set_attr "mode" "")]) (define_insn "msa_bmz_" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") (ior:IMSA (and:IMSA (not:IMSA (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8")) - (match_operand:IMSA 2 "register_operand" "f,f")) - (and:IMSA (match_operand:IMSA 1 "register_operand" "0,0") + (match_operand:IMSA 2 "msa_reg_operand" "f,f")) + (and:IMSA (match_operand:IMSA 1 "msa_reg_operand" "0,0") (match_dup 3))))] "ISA_HAS_MSA" "@ @@ -1190,9 +1191,9 @@ (set_attr "mode" "")]) (define_insn "msa_bneg_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_BNEG))] "ISA_HAS_MSA" "bneg.\t%w0,%w1,%w2" @@ -1200,8 +1201,8 @@ (set_attr "mode" "")]) (define_insn "msa_bnegi_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") (match_operand 2 "const_msa_branch_operand" "")] UNSPEC_MSA_BNEGI))] "ISA_HAS_MSA" @@ -1210,10 +1211,10 @@ (set_attr "mode" "")]) (define_insn "msa_bsel_" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") (ior:IMSA (and:IMSA (not:IMSA - (match_operand:IMSA 1 "register_operand" "0,0")) - (match_operand:IMSA 2 "register_operand" "f,f")) + (match_operand:IMSA 1 "msa_reg_operand" "0,0")) + (match_operand:IMSA 2 "msa_reg_operand" "f,f")) (and:IMSA (match_dup 1) (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))))] "ISA_HAS_MSA" @@ -1224,9 +1225,9 @@ (set_attr "mode" "")]) (define_insn "msa_bset_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_BSET))] "ISA_HAS_MSA" "bset.\t%w0,%w1,%w2" @@ -1234,8 +1235,8 @@ (set_attr "mode" "")]) (define_insn "msa_bseti_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") (match_operand 2 "const__operand" "")] UNSPEC_MSA_BSETI))] "ISA_HAS_MSA" @@ -1267,9 +1268,9 @@ (ltu "u")]) (define_insn "msa_c_" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") (ICC:IMSA - (match_operand:IMSA 1 "register_operand" "f,f") + (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_imm5_operand" "f,Uv5")))] "ISA_HAS_MSA" "@ @@ -1279,16 +1280,16 @@ (set_attr "mode" "")]) (define_insn "msa_dotp__d" - [(set (match_operand:V2DI 0 "register_operand" "=f") + [(set (match_operand:V2DI 0 "msa_reg_operand" "=f") (plus:V2DI (mult:V2DI (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "register_operand" "%f") + (match_operand:V4SI 1 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2)]))) (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "register_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2)])))) (mult:V2DI (any_extend:V2DI @@ -1303,17 +1304,17 @@ (set_attr "mode" "V2DI")]) (define_insn "msa_dotp__w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (plus:V4SI (mult:V4SI (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "register_operand" "%f") + (match_operand:V8HI 1 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "register_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -1331,19 +1332,19 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_dotp__h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (plus:V8HI (mult:V8HI (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 1 "register_operand" "%f") + (match_operand:V16QI 1 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)]))) (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 2 "register_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -1367,17 +1368,17 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_dpadd__d" - [(set (match_operand:V2DI 0 "register_operand" "=f") + [(set (match_operand:V2DI 0 "msa_reg_operand" "=f") (plus:V2DI (plus:V2DI (mult:V2DI (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "register_operand" "%f") + (match_operand:V4SI 2 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2)]))) (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 3 "register_operand" "f") + (match_operand:V4SI 3 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2)])))) (mult:V2DI (any_extend:V2DI @@ -1386,25 +1387,25 @@ (any_extend:V2DI (vec_select:V2SI (match_dup 3) (parallel [(const_int 1) (const_int 3)]))))) - (match_operand:V2DI 1 "register_operand" "0")))] + (match_operand:V2DI 1 "msa_reg_operand" "0")))] "ISA_HAS_MSA" "dpadd_.d\t%w0,%w2,%w3" [(set_attr "type" "simd_mul") (set_attr "mode" "V2DI")]) (define_insn "msa_dpadd__w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (plus:V4SI (plus:V4SI (mult:V4SI (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "register_operand" "%f") + (match_operand:V8HI 2 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 3 "register_operand" "f") + (match_operand:V8HI 3 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -1416,27 +1417,27 @@ (vec_select:V4HI (match_dup 3) (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))) - (match_operand:V4SI 1 "register_operand" "0")))] + (match_operand:V4SI 1 "msa_reg_operand" "0")))] "ISA_HAS_MSA" "dpadd_.w\t%w0,%w2,%w3" [(set_attr "type" "simd_mul") (set_attr "mode" "V4SI")]) (define_insn "msa_dpadd__h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (plus:V8HI (plus:V8HI (mult:V8HI (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 2 "register_operand" "%f") + (match_operand:V16QI 2 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)]))) (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 3 "register_operand" "f") + (match_operand:V16QI 3 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -1454,25 +1455,25 @@ (const_int 5) (const_int 7) (const_int 9) (const_int 11) (const_int 13) (const_int 15)]))))) - (match_operand:V8HI 1 "register_operand" "0")))] + (match_operand:V8HI 1 "msa_reg_operand" "0")))] "ISA_HAS_MSA" "dpadd_.h\t%w0,%w2,%w3" [(set_attr "type" "simd_mul") (set_attr "mode" "V8HI")]) (define_insn "msa_dpsub__d" - [(set (match_operand:V2DI 0 "register_operand" "=f") + [(set (match_operand:V2DI 0 "msa_reg_operand" "=f") (minus:V2DI - (match_operand:V2DI 1 "register_operand" "0") + (match_operand:V2DI 1 "msa_reg_operand" "0") (plus:V2DI (mult:V2DI (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "register_operand" "%f") + (match_operand:V4SI 2 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2)]))) (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 3 "register_operand" "f") + (match_operand:V4SI 3 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2)])))) (mult:V2DI (any_extend:V2DI @@ -1487,19 +1488,19 @@ (set_attr "mode" "V2DI")]) (define_insn "msa_dpsub__w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (minus:V4SI - (match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 1 "msa_reg_operand" "0") (plus:V4SI (mult:V4SI (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "register_operand" "%f") + (match_operand:V8HI 2 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 3 "register_operand" "f") + (match_operand:V8HI 3 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -1517,21 +1518,21 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_dpsub__h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (minus:V8HI - (match_operand:V8HI 1 "register_operand" "0") + (match_operand:V8HI 1 "msa_reg_operand" "0") (plus:V8HI (mult:V8HI (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 2 "register_operand" "%f") + (match_operand:V16QI 2 "msa_reg_operand" "%f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)]))) (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 3 "register_operand" "f") + (match_operand:V16QI 3 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -1555,8 +1556,8 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_fclass_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FMSA 1 "register_operand" "f")] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (unspec: [(match_operand:FMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_FCLASS))] "ISA_HAS_MSA" "fclass.\t%w0,%w1" @@ -1564,9 +1565,9 @@ (set_attr "mode" "")]) (define_insn "msa_fcaf_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (unspec: [(match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_FCAF))] "ISA_HAS_MSA" "fcaf.\t%w0,%w1,%w2" @@ -1574,9 +1575,9 @@ (set_attr "mode" "")]) (define_insn "msa_fcune_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (unspec: [(match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_FCUNE))] "ISA_HAS_MSA" "fcune.\t%w0,%w1,%w2" @@ -1615,18 +1616,18 @@ (UNSPEC_MSA_FSLT "fslt")]) (define_insn "msa__" - [(set (match_operand: 0 "register_operand" "=f") - (FCC: (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")))] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (FCC: (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" ".\t%w0,%w1,%w2" [(set_attr "type" "simd_fcmp") (set_attr "mode" "")]) (define_insn "msa__" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (unspec: [(match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")] FSC_UNS))] "ISA_HAS_MSA" ".\t%w0,%w1,%w2" @@ -1634,9 +1635,9 @@ (set_attr "mode" "")]) (define_insn "msa_fexp2_" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f") - (match_operand: 2 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand: 2 "msa_reg_operand" "f")] UNSPEC_MSA_FEXP2))] "ISA_HAS_MSA" "fexp2.\t%w0,%w1,%w2" @@ -1660,8 +1661,8 @@ (V2DF "D2I")]) (define_insn "float2" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (float:FMSA (match_operand: 1 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (float:FMSA (match_operand: 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "ffint_s.\t%w0,%w1" [(set_attr "type" "simd_fcvt") @@ -1669,9 +1670,9 @@ (set_attr "mode" "")]) (define_insn "floatuns2" - [(set (match_operand:FMSA 0 "register_operand" "=f") + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") (unsigned_float:FMSA - (match_operand: 1 "register_operand" "f")))] + (match_operand: 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "ffint_u.\t%w0,%w1" [(set_attr "type" "simd_fcvt") @@ -1683,8 +1684,8 @@ (V2DF "V4SI")]) (define_insn "msa_ffql_" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand: 1 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand: 1 "msa_reg_operand" "f")] UNSPEC_MSA_FFQL))] "ISA_HAS_MSA" "ffql.\t%w0,%w1" @@ -1693,8 +1694,8 @@ (set_attr "mode" "")]) (define_insn "msa_ffqr_" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand: 1 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand: 1 "msa_reg_operand" "f")] UNSPEC_MSA_FFQR))] "ISA_HAS_MSA" "ffqr.\t%w0,%w1" @@ -1703,7 +1704,7 @@ (set_attr "mode" "")]) (define_insn "msa_fill_" - [(set (match_operand:MSA 0 "register_operand" "=f,f") + [(set (match_operand:MSA 0 "msa_reg_operand" "=f,f") (vec_duplicate:MSA (match_operand: 1 "reg_or_0_operand" "d,J")))] "ISA_HAS_MSA" @@ -1720,9 +1721,9 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:MSA_D 0 "register_operand") + [(set (match_operand:MSA_D 0 "msa_reg_operand") (vec_duplicate:MSA_D - (match_operand: 1 "register_operand")))] + (match_operand: 1 "msa_reg_operand")))] "reload_completed && ISA_HAS_MSA && !TARGET_64BIT" [(const_int 0)] { @@ -1731,8 +1732,8 @@ }) (define_insn "msa_flog2_" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand:FMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_FLOG2))] "ISA_HAS_MSA" "flog2.\t%w0,%w1" @@ -1740,19 +1741,19 @@ (set_attr "mode" "")]) (define_insn "smax3" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (smax:FMSA (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (smax:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "fmax.\t%w0,%w1,%w2" [(set_attr "type" "simd_fminmax") (set_attr "mode" "")]) (define_insn "msa_fmax_a_" - [(set (match_operand:FMSA 0 "register_operand" "=f") + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") (if_then_else:FMSA - (gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f")) - (abs:FMSA (match_operand:FMSA 2 "register_operand" "f"))) + (gt (abs:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f")) + (abs:FMSA (match_operand:FMSA 2 "msa_reg_operand" "f"))) (match_dup 1) (match_dup 2)))] "ISA_HAS_MSA" @@ -1761,19 +1762,19 @@ (set_attr "mode" "")]) (define_insn "smin3" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (smin:FMSA (match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")))] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (smin:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "fmin.\t%w0,%w1,%w2" [(set_attr "type" "simd_fminmax") (set_attr "mode" "")]) (define_insn "msa_fmin_a_" - [(set (match_operand:FMSA 0 "register_operand" "=f") + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") (if_then_else:FMSA - (lt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f")) - (abs:FMSA (match_operand:FMSA 2 "register_operand" "f"))) + (lt (abs:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f")) + (abs:FMSA (match_operand:FMSA 2 "msa_reg_operand" "f"))) (match_dup 1) (match_dup 2)))] "ISA_HAS_MSA" @@ -1782,8 +1783,8 @@ (set_attr "mode" "")]) (define_insn "msa_frcp_" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand:FMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_FRCP))] "ISA_HAS_MSA" "frcp.\t%w0,%w1" @@ -1791,8 +1792,8 @@ (set_attr "mode" "")]) (define_insn "msa_frint_" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand:FMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_FRINT))] "ISA_HAS_MSA" "frint.\t%w0,%w1" @@ -1800,8 +1801,8 @@ (set_attr "mode" "")]) (define_insn "msa_frsqrt_" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand:FMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_FRSQRT))] "ISA_HAS_MSA" "frsqrt.\t%w0,%w1" @@ -1809,8 +1810,8 @@ (set_attr "mode" "")]) (define_insn "msa_ftint_s_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FMSA 1 "register_operand" "f")] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (unspec: [(match_operand:FMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_FTINT_S))] "ISA_HAS_MSA" "ftint_s.\t%w0,%w1" @@ -1819,8 +1820,8 @@ (set_attr "mode" "")]) (define_insn "msa_ftint_u_" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FMSA 1 "register_operand" "f")] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (unspec: [(match_operand:FMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_FTINT_U))] "ISA_HAS_MSA" "ftint_u.\t%w0,%w1" @@ -1829,8 +1830,8 @@ (set_attr "mode" "")]) (define_insn "fix_trunc2" - [(set (match_operand: 0 "register_operand" "=f") - (fix: (match_operand:FMSA 1 "register_operand" "f")))] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (fix: (match_operand:FMSA 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "ftrunc_s.\t%w0,%w1" [(set_attr "type" "simd_fcvt") @@ -1838,8 +1839,8 @@ (set_attr "mode" "")]) (define_insn "fixuns_trunc2" - [(set (match_operand: 0 "register_operand" "=f") - (unsigned_fix: (match_operand:FMSA 1 "register_operand" "f")))] + [(set (match_operand: 0 "msa_reg_operand" "=f") + (unsigned_fix: (match_operand:FMSA 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "ftrunc_u.\t%w0,%w1" [(set_attr "type" "simd_fcvt") @@ -1847,9 +1848,9 @@ (set_attr "mode" "")]) (define_insn "msa_ftq_h" - [(set (match_operand:V8HI 0 "register_operand" "=f") - (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")] + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") + (unspec:V8HI [(match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")] UNSPEC_MSA_FTQ))] "ISA_HAS_MSA" "ftq.h\t%w0,%w1,%w2" @@ -1858,9 +1859,9 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_ftq_w" - [(set (match_operand:V4SI 0 "register_operand" "=f") - (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f") - (match_operand:V2DF 2 "register_operand" "f")] + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") + (unspec:V4SI [(match_operand:V2DF 1 "msa_reg_operand" "f") + (match_operand:V2DF 2 "msa_reg_operand" "f")] UNSPEC_MSA_FTQ))] "ISA_HAS_MSA" "ftq.w\t%w0,%w1,%w2" @@ -1869,18 +1870,18 @@ (set_attr "mode" "V2DF")]) (define_insn "msa_h__h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (addsub:V8HI (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 1 "register_operand" "f") + (match_operand:V16QI 1 "msa_reg_operand" "f") (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7) (const_int 9) (const_int 11) (const_int 13) (const_int 15)]))) (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 2 "register_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -1891,16 +1892,16 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_h__w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (addsub:V4SI (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "register_operand" "f") + (match_operand:V8HI 1 "msa_reg_operand" "f") (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))) (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "register_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] "ISA_HAS_MSA" @@ -1909,15 +1910,15 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_h__d" - [(set (match_operand:V2DI 0 "register_operand" "=f") + [(set (match_operand:V2DI 0 "msa_reg_operand" "=f") (addsub:V2DI (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "register_operand" "f") + (match_operand:V4SI 1 "msa_reg_operand" "f") (parallel [(const_int 1) (const_int 3)]))) (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "register_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 2)])))))] "ISA_HAS_MSA" "h_.d\t%w0,%w1,%w2" @@ -1925,11 +1926,11 @@ (set_attr "mode" "V2DI")]) (define_insn "msa_ilvev_b" - [(set (match_operand:V16QI 0 "register_operand" "=f") + [(set (match_operand:V16QI 0 "msa_reg_operand" "=f") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "register_operand" "f") - (match_operand:V16QI 2 "register_operand" "f")) + (match_operand:V16QI 1 "msa_reg_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 16) (const_int 2) (const_int 18) (const_int 4) (const_int 20) @@ -1944,11 +1945,11 @@ (set_attr "mode" "V16QI")]) (define_insn "msa_ilvev_h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "register_operand" "f") - (match_operand:V8HI 2 "register_operand" "f")) + (match_operand:V8HI 1 "msa_reg_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 8) (const_int 2) (const_int 10) (const_int 4) (const_int 12) @@ -1959,11 +1960,11 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_ilvev_w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "f") - (match_operand:V4SI 2 "register_operand" "f")) + (match_operand:V4SI 1 "msa_reg_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] "ISA_HAS_MSA" @@ -1972,11 +1973,11 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_ilvev_w_f" - [(set (match_operand:V4SF 0 "register_operand" "=f") + [(set (match_operand:V4SF 0 "msa_reg_operand" "=f") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")) + (match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] "ISA_HAS_MSA" @@ -1985,11 +1986,11 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_ilvl_b" - [(set (match_operand:V16QI 0 "register_operand" "=f") + [(set (match_operand:V16QI 0 "msa_reg_operand" "=f") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "register_operand" "f") - (match_operand:V16QI 2 "register_operand" "f")) + (match_operand:V16QI 1 "msa_reg_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f")) (parallel [(const_int 8) (const_int 24) (const_int 9) (const_int 25) (const_int 10) (const_int 26) @@ -2004,11 +2005,11 @@ (set_attr "mode" "V16QI")]) (define_insn "msa_ilvl_h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "register_operand" "f") - (match_operand:V8HI 2 "register_operand" "f")) + (match_operand:V8HI 1 "msa_reg_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f")) (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13) (const_int 6) (const_int 14) @@ -2019,11 +2020,11 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_ilvl_w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "f") - (match_operand:V4SI 2 "register_operand" "f")) + (match_operand:V4SI 1 "msa_reg_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "ISA_HAS_MSA" @@ -2032,11 +2033,11 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_ilvl_w_f" - [(set (match_operand:V4SF 0 "register_operand" "=f") + [(set (match_operand:V4SF 0 "msa_reg_operand" "=f") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")) + (match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "ISA_HAS_MSA" @@ -2045,11 +2046,11 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_ilvl_d" - [(set (match_operand:V2DI 0 "register_operand" "=f") + [(set (match_operand:V2DI 0 "msa_reg_operand" "=f") (vec_select:V2DI (vec_concat:V4DI - (match_operand:V2DI 1 "register_operand" "f") - (match_operand:V2DI 2 "register_operand" "f")) + (match_operand:V2DI 1 "msa_reg_operand" "f") + (match_operand:V2DI 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 3)])))] "ISA_HAS_MSA" "ilvl.d\t%w0,%w2,%w1" @@ -2057,11 +2058,11 @@ (set_attr "mode" "V2DI")]) (define_insn "msa_ilvl_d_f" - [(set (match_operand:V2DF 0 "register_operand" "=f") + [(set (match_operand:V2DF 0 "msa_reg_operand" "=f") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "register_operand" "f") - (match_operand:V2DF 2 "register_operand" "f")) + (match_operand:V2DF 1 "msa_reg_operand" "f") + (match_operand:V2DF 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 3)])))] "ISA_HAS_MSA" "ilvl.d\t%w0,%w2,%w1" @@ -2069,11 +2070,11 @@ (set_attr "mode" "V2DF")]) (define_insn "msa_ilvod_b" - [(set (match_operand:V16QI 0 "register_operand" "=f") + [(set (match_operand:V16QI 0 "msa_reg_operand" "=f") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "register_operand" "f") - (match_operand:V16QI 2 "register_operand" "f")) + (match_operand:V16QI 1 "msa_reg_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 17) (const_int 3) (const_int 19) (const_int 5) (const_int 21) @@ -2088,11 +2089,11 @@ (set_attr "mode" "V16QI")]) (define_insn "msa_ilvod_h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "register_operand" "f") - (match_operand:V8HI 2 "register_operand" "f")) + (match_operand:V8HI 1 "msa_reg_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 9) (const_int 3) (const_int 11) (const_int 5) (const_int 13) @@ -2103,11 +2104,11 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_ilvod_w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "f") - (match_operand:V4SI 2 "register_operand" "f")) + (match_operand:V4SI 1 "msa_reg_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 5) (const_int 3) (const_int 7)])))] "ISA_HAS_MSA" @@ -2116,11 +2117,11 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_ilvod_w_f" - [(set (match_operand:V4SF 0 "register_operand" "=f") + [(set (match_operand:V4SF 0 "msa_reg_operand" "=f") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")) + (match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 5) (const_int 3) (const_int 7)])))] "ISA_HAS_MSA" @@ -2129,11 +2130,11 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_ilvr_b" - [(set (match_operand:V16QI 0 "register_operand" "=f") + [(set (match_operand:V16QI 0 "msa_reg_operand" "=f") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "register_operand" "f") - (match_operand:V16QI 2 "register_operand" "f")) + (match_operand:V16QI 1 "msa_reg_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 16) (const_int 1) (const_int 17) (const_int 2) (const_int 18) @@ -2148,11 +2149,11 @@ (set_attr "mode" "V16QI")]) (define_insn "msa_ilvr_h" - [(set (match_operand:V8HI 0 "register_operand" "=f") + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "register_operand" "f") - (match_operand:V8HI 2 "register_operand" "f")) + (match_operand:V8HI 1 "msa_reg_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9) (const_int 2) (const_int 10) @@ -2163,11 +2164,11 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_ilvr_w" - [(set (match_operand:V4SI 0 "register_operand" "=f") + [(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "f") - (match_operand:V4SI 2 "register_operand" "f")) + (match_operand:V4SI 1 "msa_reg_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "ISA_HAS_MSA" @@ -2176,11 +2177,11 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_ilvr_w_f" - [(set (match_operand:V4SF 0 "register_operand" "=f") + [(set (match_operand:V4SF 0 "msa_reg_operand" "=f") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")) + (match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "ISA_HAS_MSA" @@ -2189,11 +2190,11 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_ilvr_d" - [(set (match_operand:V2DI 0 "register_operand" "=f") + [(set (match_operand:V2DI 0 "msa_reg_operand" "=f") (vec_select:V2DI (vec_concat:V4DI - (match_operand:V2DI 1 "register_operand" "f") - (match_operand:V2DI 2 "register_operand" "f")) + (match_operand:V2DI 1 "msa_reg_operand" "f") + (match_operand:V2DI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 2)])))] "ISA_HAS_MSA" "ilvr.d\t%w0,%w2,%w1" @@ -2201,11 +2202,11 @@ (set_attr "mode" "V2DI")]) (define_insn "msa_ilvr_d_f" - [(set (match_operand:V2DF 0 "register_operand" "=f") + [(set (match_operand:V2DF 0 "msa_reg_operand" "=f") (vec_select:V2DF (vec_concat:V4DF - (match_operand:V2DF 1 "register_operand" "f") - (match_operand:V2DF 2 "register_operand" "f")) + (match_operand:V2DF 1 "msa_reg_operand" "f") + (match_operand:V2DF 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 2)])))] "ISA_HAS_MSA" "ilvr.d\t%w0,%w2,%w1" @@ -2213,10 +2214,10 @@ (set_attr "mode" "V2DF")]) (define_insn "msa_madd_q_" - [(set (match_operand:IMSA_WH 0 "register_operand" "=f") - (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") - (match_operand:IMSA_WH 2 "register_operand" "f") - (match_operand:IMSA_WH 3 "register_operand" "f")] + [(set (match_operand:IMSA_WH 0 "msa_reg_operand" "=f") + (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "msa_reg_operand" "0") + (match_operand:IMSA_WH 2 "msa_reg_operand" "f") + (match_operand:IMSA_WH 3 "msa_reg_operand" "f")] UNSPEC_MSA_MADD_Q))] "ISA_HAS_MSA" "madd_q.\t%w0,%w2,%w3" @@ -2224,10 +2225,10 @@ (set_attr "mode" "")]) (define_insn "msa_maddr_q_" - [(set (match_operand:IMSA_WH 0 "register_operand" "=f") - (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") - (match_operand:IMSA_WH 2 "register_operand" "f") - (match_operand:IMSA_WH 3 "register_operand" "f")] + [(set (match_operand:IMSA_WH 0 "msa_reg_operand" "=f") + (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "msa_reg_operand" "0") + (match_operand:IMSA_WH 2 "msa_reg_operand" "f") + (match_operand:IMSA_WH 3 "msa_reg_operand" "f")] UNSPEC_MSA_MADDR_Q))] "ISA_HAS_MSA" "maddr_q.\t%w0,%w2,%w3" @@ -2235,10 +2236,10 @@ (set_attr "mode" "")]) (define_insn "msa_max_a_" - [(set (match_operand:IMSA 0 "register_operand" "=f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") (if_then_else:IMSA - (gt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) - (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))) + (gt (abs:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f")) + (abs:IMSA (match_operand:IMSA 2 "msa_reg_operand" "f"))) (match_dup 1) (match_dup 2)))] "ISA_HAS_MSA" @@ -2247,8 +2248,8 @@ (set_attr "mode" "")]) (define_insn "smax3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") - (smax:IMSA (match_operand:IMSA 1 "register_operand" "f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") + (smax:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))] "ISA_HAS_MSA" "@ @@ -2258,8 +2259,8 @@ (set_attr "mode" "")]) (define_insn "umax3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") - (umax:IMSA (match_operand:IMSA 1 "register_operand" "f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") + (umax:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))] "ISA_HAS_MSA" "@ @@ -2269,10 +2270,10 @@ (set_attr "mode" "")]) (define_insn "msa_min_a_" - [(set (match_operand:IMSA 0 "register_operand" "=f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") (if_then_else:IMSA - (lt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) - (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))) + (lt (abs:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f")) + (abs:IMSA (match_operand:IMSA 2 "msa_reg_operand" "f"))) (match_dup 1) (match_dup 2)))] "ISA_HAS_MSA" @@ -2281,8 +2282,8 @@ (set_attr "mode" "")]) (define_insn "smin3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") - (smin:IMSA (match_operand:IMSA 1 "register_operand" "f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") + (smin:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))] "ISA_HAS_MSA" "@ @@ -2292,8 +2293,8 @@ (set_attr "mode" "")]) (define_insn "umin3" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") - (umin:IMSA (match_operand:IMSA 1 "register_operand" "f,f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") + (umin:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))] "ISA_HAS_MSA" "@ @@ -2303,10 +2304,10 @@ (set_attr "mode" "")]) (define_insn "msa_msub_q_" - [(set (match_operand:IMSA_WH 0 "register_operand" "=f") - (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") - (match_operand:IMSA_WH 2 "register_operand" "f") - (match_operand:IMSA_WH 3 "register_operand" "f")] + [(set (match_operand:IMSA_WH 0 "msa_reg_operand" "=f") + (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "msa_reg_operand" "0") + (match_operand:IMSA_WH 2 "msa_reg_operand" "f") + (match_operand:IMSA_WH 3 "msa_reg_operand" "f")] UNSPEC_MSA_MSUB_Q))] "ISA_HAS_MSA" "msub_q.\t%w0,%w2,%w3" @@ -2314,10 +2315,10 @@ (set_attr "mode" "")]) (define_insn "msa_msubr_q_" - [(set (match_operand:IMSA_WH 0 "register_operand" "=f") - (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") - (match_operand:IMSA_WH 2 "register_operand" "f") - (match_operand:IMSA_WH 3 "register_operand" "f")] + [(set (match_operand:IMSA_WH 0 "msa_reg_operand" "=f") + (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "msa_reg_operand" "0") + (match_operand:IMSA_WH 2 "msa_reg_operand" "f") + (match_operand:IMSA_WH 3 "msa_reg_operand" "f")] UNSPEC_MSA_MSUBR_Q))] "ISA_HAS_MSA" "msubr_q.\t%w0,%w2,%w3" @@ -2325,9 +2326,9 @@ (set_attr "mode" "")]) (define_insn "msa_mul_q_" - [(set (match_operand:IMSA_WH 0 "register_operand" "=f") - (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f") - (match_operand:IMSA_WH 2 "register_operand" "f")] + [(set (match_operand:IMSA_WH 0 "msa_reg_operand" "=f") + (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "msa_reg_operand" "f") + (match_operand:IMSA_WH 2 "msa_reg_operand" "f")] UNSPEC_MSA_MUL_Q))] "ISA_HAS_MSA" "mul_q.\t%w0,%w1,%w2" @@ -2335,9 +2336,9 @@ (set_attr "mode" "")]) (define_insn "msa_mulr_q_" - [(set (match_operand:IMSA_WH 0 "register_operand" "=f") - (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f") - (match_operand:IMSA_WH 2 "register_operand" "f")] + [(set (match_operand:IMSA_WH 0 "msa_reg_operand" "=f") + (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "msa_reg_operand" "f") + (match_operand:IMSA_WH 2 "msa_reg_operand" "f")] UNSPEC_MSA_MULR_Q))] "ISA_HAS_MSA" "mulr_q.\t%w0,%w1,%w2" @@ -2345,8 +2346,8 @@ (set_attr "mode" "")]) (define_insn "msa_nloc_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_NLOC))] "ISA_HAS_MSA" "nloc.\t%w0,%w1" @@ -2354,16 +2355,16 @@ (set_attr "mode" "")]) (define_insn "clz2" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (clz:IMSA (match_operand:IMSA 1 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (clz:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "nlzc.\t%w0,%w1" [(set_attr "type" "simd_bit") (set_attr "mode" "")]) (define_insn "msa_nor_" - [(set (match_operand:IMSA 0 "register_operand" "=f,f") - (and:IMSA (not:IMSA (match_operand:IMSA 1 "register_operand" "f,f")) + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f,f") + (and:IMSA (not:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f,f")) (not:IMSA (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,Urv8"))))] "ISA_HAS_MSA" "@ @@ -2373,11 +2374,11 @@ (set_attr "mode" "")]) (define_insn "msa_pckev_b" -[(set (match_operand:V16QI 0 "register_operand" "=f") +[(set (match_operand:V16QI 0 "msa_reg_operand" "=f") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "register_operand" "f") - (match_operand:V16QI 2 "register_operand" "f")) + (match_operand:V16QI 1 "msa_reg_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -2392,11 +2393,11 @@ (set_attr "mode" "V16QI")]) (define_insn "msa_pckev_h" -[(set (match_operand:V8HI 0 "register_operand" "=f") +[(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "register_operand" "f") - (match_operand:V8HI 2 "register_operand" "f")) + (match_operand:V8HI 1 "msa_reg_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -2407,11 +2408,11 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_pckev_w" -[(set (match_operand:V4SI 0 "register_operand" "=f") +[(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "f") - (match_operand:V4SI 2 "register_operand" "f")) + (match_operand:V4SI 1 "msa_reg_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))] "ISA_HAS_MSA" @@ -2420,11 +2421,11 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_pckev_w_f" -[(set (match_operand:V4SF 0 "register_operand" "=f") +[(set (match_operand:V4SF 0 "msa_reg_operand" "=f") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")) + (match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")) (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))] "ISA_HAS_MSA" @@ -2433,11 +2434,11 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_pckod_b" -[(set (match_operand:V16QI 0 "register_operand" "=f") +[(set (match_operand:V16QI 0 "msa_reg_operand" "=f") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "register_operand" "f") - (match_operand:V16QI 2 "register_operand" "f")) + (match_operand:V16QI 1 "msa_reg_operand" "f") + (match_operand:V16QI 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7) (const_int 9) (const_int 11) @@ -2452,11 +2453,11 @@ (set_attr "mode" "V16QI")]) (define_insn "msa_pckod_h" -[(set (match_operand:V8HI 0 "register_operand" "=f") +[(set (match_operand:V8HI 0 "msa_reg_operand" "=f") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "register_operand" "f") - (match_operand:V8HI 2 "register_operand" "f")) + (match_operand:V8HI 1 "msa_reg_operand" "f") + (match_operand:V8HI 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7) (const_int 9) (const_int 11) @@ -2467,11 +2468,11 @@ (set_attr "mode" "V8HI")]) (define_insn "msa_pckod_w" -[(set (match_operand:V4SI 0 "register_operand" "=f") +[(set (match_operand:V4SI 0 "msa_reg_operand" "=f") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "f") - (match_operand:V4SI 2 "register_operand" "f")) + (match_operand:V4SI 1 "msa_reg_operand" "f") + (match_operand:V4SI 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)])))] "ISA_HAS_MSA" @@ -2480,11 +2481,11 @@ (set_attr "mode" "V4SI")]) (define_insn "msa_pckod_w_f" -[(set (match_operand:V4SF 0 "register_operand" "=f") +[(set (match_operand:V4SF 0 "msa_reg_operand" "=f") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")) + (match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")) (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)])))] "ISA_HAS_MSA" @@ -2493,16 +2494,16 @@ (set_attr "mode" "V4SF")]) (define_insn "popcount2" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (popcount:IMSA (match_operand:IMSA 1 "register_operand" "f")))] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (popcount:IMSA (match_operand:IMSA 1 "msa_reg_operand" "f")))] "ISA_HAS_MSA" "pcnt.\t%w0,%w1" [(set_attr "type" "simd_pcnt") (set_attr "mode" "")]) (define_insn "msa_sat_s_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") (match_operand 2 "const__operand" "")] UNSPEC_MSA_SAT_S))] "ISA_HAS_MSA" @@ -2511,8 +2512,8 @@ (set_attr "mode" "")]) (define_insn "msa_sat_u_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") (match_operand 2 "const__operand" "")] UNSPEC_MSA_SAT_U))] "ISA_HAS_MSA" @@ -2521,9 +2522,9 @@ (set_attr "mode" "")]) (define_insn "msa_shf_" - [(set (match_operand:MSA 0 "register_operand" "=f") + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") (vec_select:MSA - (match_operand:MSA 1 "register_operand" "f") + (match_operand:MSA 1 "msa_reg_operand" "f") (match_operand 2 "par_const_vector_shf_set_operand" "")))] "ISA_HAS_MSA" { @@ -2549,9 +2550,9 @@ (set_attr "mode" "")]) (define_insn "msa_srar_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_SRAR))] "ISA_HAS_MSA" "srar.\t%w0,%w1,%w2" @@ -2559,8 +2560,8 @@ (set_attr "mode" "")]) (define_insn "msa_srari_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") (match_operand 2 "const__operand" "")] UNSPEC_MSA_SRARI))] "ISA_HAS_MSA" @@ -2569,9 +2570,9 @@ (set_attr "mode" "")]) (define_insn "msa_srlr_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_SRLR))] "ISA_HAS_MSA" "srlr.\t%w0,%w1,%w2" @@ -2579,8 +2580,8 @@ (set_attr "mode" "")]) (define_insn "msa_srlri_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") (match_operand 2 "const__operand" "")] UNSPEC_MSA_SRLRI))] "ISA_HAS_MSA" @@ -2589,9 +2590,9 @@ (set_attr "mode" "")]) (define_insn "msa_subs_s_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_SUBS_S))] "ISA_HAS_MSA" "subs_s.\t%w0,%w1,%w2" @@ -2599,9 +2600,9 @@ (set_attr "mode" "")]) (define_insn "msa_subs_u_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_SUBS_U))] "ISA_HAS_MSA" "subs_u.\t%w0,%w1,%w2" @@ -2609,9 +2610,9 @@ (set_attr "mode" "")]) (define_insn "msa_subsuu_s_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_SUBSUU_S))] "ISA_HAS_MSA" "subsuu_s.\t%w0,%w1,%w2" @@ -2619,9 +2620,9 @@ (set_attr "mode" "")]) (define_insn "msa_subsus_u_" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] + [(set (match_operand:IMSA 0 "msa_reg_operand" "=f") + (unspec:IMSA [(match_operand:IMSA 1 "msa_reg_operand" "f") + (match_operand:IMSA 2 "msa_reg_operand" "f")] UNSPEC_MSA_SUBSUS_U))] "ISA_HAS_MSA" "subsus_u.\t%w0,%w1,%w2" @@ -2629,9 +2630,9 @@ (set_attr "mode" "")]) (define_insn "msa_sld_" - [(set (match_operand:MSA 0 "register_operand" "=f") - (unspec:MSA [(match_operand:MSA 1 "register_operand" "0") - (match_operand:MSA 2 "register_operand" "f") + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") + (unspec:MSA [(match_operand:MSA 1 "msa_reg_operand" "0") + (match_operand:MSA 2 "msa_reg_operand" "f") (match_operand:SI 3 "reg_or_0_operand" "dJ")] UNSPEC_MSA_SLD))] "ISA_HAS_MSA" @@ -2640,9 +2641,9 @@ (set_attr "mode" "")]) (define_insn "msa_sldi_" - [(set (match_operand:MSA 0 "register_operand" "=f") - (unspec:MSA [(match_operand:MSA 1 "register_operand" "0") - (match_operand:MSA 2 "register_operand" "f") + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") + (unspec:MSA [(match_operand:MSA 1 "msa_reg_operand" "0") + (match_operand:MSA 2 "msa_reg_operand" "f") (match_operand 3 "const__operand" "")] UNSPEC_MSA_SLDI))] "ISA_HAS_MSA" @@ -2651,9 +2652,9 @@ (set_attr "mode" "")]) (define_insn "msa_splat_" - [(set (match_operand:MSA 0 "register_operand" "=f") - (unspec:MSA [(match_operand:MSA 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "d")] + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") + (unspec:MSA [(match_operand:MSA 1 "msa_reg_operand" "f") + (match_operand:SI 2 "msa_reg_operand" "d")] UNSPEC_MSA_SPLAT))] "ISA_HAS_MSA" "splat.\t%w0,%w1[%z2]" @@ -2661,10 +2662,10 @@ (set_attr "mode" "")]) (define_insn "msa_splati_" - [(set (match_operand:MSA 0 "register_operand" "=f") + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") (vec_duplicate:MSA (vec_select: - (match_operand:MSA 1 "register_operand" "f") + (match_operand:MSA 1 "msa_reg_operand" "f") (parallel [(match_operand 2 "const__operand" "")]))))] "ISA_HAS_MSA" "splati.\t%w0,%w1[%2]" @@ -2672,8 +2673,8 @@ (set_attr "mode" "")]) (define_insn "msa_splati__scalar" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand: 1 "register_operand" "f")] + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (unspec:FMSA [(match_operand: 1 "msa_reg_operand" "f")] UNSPEC_MSA_SPLATI))] "ISA_HAS_MSA" "splati.\t%w0,%w1[0]" @@ -2681,7 +2682,7 @@ (set_attr "mode" "")]) (define_insn "msa_cfcmsa" - [(set (match_operand:SI 0 "register_operand" "=d") + [(set (match_operand:SI 0 "msa_reg_operand" "=d") (unspec_volatile:SI [(match_operand 1 "const_uimm5_operand" "")] UNSPEC_MSA_CFCMSA))] "ISA_HAS_MSA" @@ -2691,7 +2692,7 @@ (define_insn "msa_ctcmsa" [(unspec_volatile [(match_operand 0 "const_uimm5_operand" "") - (match_operand:SI 1 "register_operand" "d")] + (match_operand:SI 1 "msa_reg_operand" "d")] UNSPEC_MSA_CTCMSA)] "ISA_HAS_MSA" "ctcmsa\t$%0,%1" @@ -2699,9 +2700,9 @@ (set_attr "mode" "SI")]) (define_insn "msa_fexdo_h" - [(set (match_operand:V8HI 0 "register_operand" "=f") - (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f") - (match_operand:V4SF 2 "register_operand" "f")] + [(set (match_operand:V8HI 0 "msa_reg_operand" "=f") + (unspec:V8HI [(match_operand:V4SF 1 "msa_reg_operand" "f") + (match_operand:V4SF 2 "msa_reg_operand" "f")] UNSPEC_MSA_FEXDO))] "ISA_HAS_MSA" "fexdo.h\t%w0,%w1,%w2" @@ -2709,18 +2710,18 @@ (set_attr "mode" "V8HI")]) (define_insn "vec_pack_trunc_v2df" - [(set (match_operand:V4SF 0 "register_operand" "=f") + [(set (match_operand:V4SF 0 "msa_reg_operand" "=f") (vec_concat:V4SF - (float_truncate:V2SF (match_operand:V2DF 1 "register_operand" "f")) - (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "f"))))] + (float_truncate:V2SF (match_operand:V2DF 1 "msa_reg_operand" "f")) + (float_truncate:V2SF (match_operand:V2DF 2 "msa_reg_operand" "f"))))] "ISA_HAS_MSA" "fexdo.w\t%w0,%w2,%w1" [(set_attr "type" "simd_fcvt") (set_attr "mode" "V4SF")]) (define_insn "msa_fexupl_w" - [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")] + [(set (match_operand:V4SF 0 "msa_reg_operand" "=f") + (unspec:V4SF [(match_operand:V8HI 1 "msa_reg_operand" "f")] UNSPEC_MSA_FEXUPL))] "ISA_HAS_MSA" "fexupl.w\t%w0,%w1" @@ -2728,10 +2729,10 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_fexupl_d" - [(set (match_operand:V2DF 0 "register_operand" "=f") + [(set (match_operand:V2DF 0 "msa_reg_operand" "=f") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "f") + (match_operand:V4SF 1 "msa_reg_operand" "f") (parallel [(const_int 2) (const_int 3)]))))] "ISA_HAS_MSA" "fexupl.d\t%w0,%w1" @@ -2739,8 +2740,8 @@ (set_attr "mode" "V2DF")]) (define_insn "msa_fexupr_w" - [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")] + [(set (match_operand:V4SF 0 "msa_reg_operand" "=f") + (unspec:V4SF [(match_operand:V8HI 1 "msa_reg_operand" "f")] UNSPEC_MSA_FEXUPR))] "ISA_HAS_MSA" "fexupr.w\t%w0,%w1" @@ -2748,10 +2749,10 @@ (set_attr "mode" "V4SF")]) (define_insn "msa_fexupr_d" - [(set (match_operand:V2DF 0 "register_operand" "=f") + [(set (match_operand:V2DF 0 "msa_reg_operand" "=f") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "f") + (match_operand:V4SF 1 "msa_reg_operand" "f") (parallel [(const_int 0) (const_int 1)]))))] "ISA_HAS_MSA" "fexupr.d\t%w0,%w1" @@ -2769,7 +2770,7 @@ (define_insn "msa__" [(set (pc) (if_then_else (equality_op - (unspec:SI [(match_operand:MSA 1 "register_operand" "f")] + (unspec:SI [(match_operand:MSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_BRANCH) (match_operand:SI 2 "const_0_operand")) (label_ref (match_operand 0)) @@ -2790,7 +2791,7 @@ (define_insn "msa__v_" [(set (pc) (if_then_else (equality_op - (unspec:SI [(match_operand:MSA 1 "register_operand" "f")] + (unspec:SI [(match_operand:MSA 1 "msa_reg_operand" "f")] UNSPEC_MSA_BRANCH_V) (match_operand:SI 2 "const_0_operand")) (label_ref (match_operand 0)) @@ -2810,8 +2811,8 @@ ;; Vector reduction operation (define_expand "reduc_smin_scal_" - [(match_operand: 0 "register_operand") - (match_operand:MSA 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:MSA 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp = gen_reg_rtx (mode); @@ -2822,8 +2823,8 @@ }) (define_expand "reduc_smax_scal_" - [(match_operand: 0 "register_operand") - (match_operand:MSA 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:MSA 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp = gen_reg_rtx (mode); @@ -2834,8 +2835,8 @@ }) (define_expand "reduc_umin_scal_" - [(match_operand: 0 "register_operand") - (match_operand:IMSA 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:IMSA 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp = gen_reg_rtx (mode); @@ -2846,8 +2847,8 @@ }) (define_expand "reduc_umax_scal_" - [(match_operand: 0 "register_operand") - (match_operand:IMSA 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:IMSA 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp = gen_reg_rtx (mode); @@ -2858,8 +2859,8 @@ }) (define_expand "reduc_plus_scal_" - [(match_operand: 0 "register_operand") - (match_operand:MSA_NO_HADD 1 "register_operand")] + [(match_operand: 0 "msa_reg_operand") + (match_operand:MSA_NO_HADD 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp = gen_reg_rtx (mode); @@ -2870,8 +2871,8 @@ }) (define_expand "reduc_plus_scal_v4si" - [(match_operand:SI 0 "register_operand") - (match_operand:V4SI 1 "register_operand")] + [(match_operand:SI 0 "msa_reg_operand") + (match_operand:V4SI 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp = gen_reg_rtx (SImode); @@ -2886,8 +2887,8 @@ }) (define_expand "reduc_plus_scal_v8hi" - [(match_operand:HI 0 "register_operand") - (match_operand:V8HI 1 "register_operand")] + [(match_operand:HI 0 "msa_reg_operand") + (match_operand:V8HI 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp1 = gen_reg_rtx (V4SImode); @@ -2902,8 +2903,8 @@ }) (define_expand "reduc_plus_scal_v16qi" - [(match_operand:QI 0 "register_operand") - (match_operand:V16QI 1 "register_operand")] + [(match_operand:QI 0 "msa_reg_operand") + (match_operand:V16QI 1 "msa_reg_operand")] "ISA_HAS_MSA" { rtx tmp1 = gen_reg_rtx (V8HImode); @@ -2921,8 +2922,8 @@ (define_expand "reduc__scal_" [(any_bitwise: - (match_operand: 0 "register_operand") - (match_operand:IMSA 1 "register_operand"))] + (match_operand: 0 "msa_reg_operand") + (match_operand:IMSA 1 "msa_reg_operand"))] "ISA_HAS_MSA" { rtx tmp = gen_reg_rtx (mode); @@ -2933,10 +2934,12 @@ }) ;; On big-endian targets we cannot use subregs to refer to MSA register -;; in different mode. See mips_can_change_mode_class. +;; in different mode. See mips_can_change_mode_class. This is used +;; specifically during expansion of vec_unpack operations, which requires +;; MSA register mode changes. (define_expand "msa_change_mode" - [(match_operand 0 "register_operand") - (match_operand 1 "register_operand")] + [(match_operand 0 "msa_reg_operand") + (match_operand 1 "msa_reg_operand")] "ISA_HAS_MSA" { gcc_assert (MSA_SUPPORTED_MODE_P (GET_MODE (operands[0])) @@ -2954,8 +2957,8 @@ }) (define_insn_and_split "msa_change_mode_" - [(set (match_operand:MSA 0 "register_operand" "=f") - (unspec:MSA [(match_operand 1 "register_operand" "f")] + [(set (match_operand:MSA 0 "msa_reg_operand" "=f") + (unspec:MSA [(match_operand 1 "msa_reg_operand" "f")] UNSPEC_MSA_CHANGE_MODE))] "ISA_HAS_MSA && TARGET_BIG_ENDIAN && MSA_SUPPORTED_MODE_P (GET_MODE (operands[1]))" @@ -2967,3 +2970,18 @@ } [(set_attr "move_type" "fmove") (set_attr "mode" "")]) + +;; A pattern for optimizing SUBREGs which have a reinterpreting effect +;; on big-endian targets. +(define_insn_and_split "*msa_mov_subreg_be" + [(set (match_operand:MSA 0 "nonimmediate_operand" "=f") + (unspec:MSA [(match_operand 1 "move_operand" "f")] + UNSPEC_MSA_SUBREG_BE))] + "ISA_HAS_MSA && TARGET_BIG_ENDIAN" + "#" + "&& reload_completed" + [(const_int 0)] +{ + mips_split_msa_subreg_move (operands[0], operands[1]); + DONE; +}) diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 2de7195f2b8..435b2e7e179 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -397,6 +397,8 @@ extern bool mips_bit_clear_p (enum machine_mode, unsigned HOST_WIDE_INT); extern void mips_bit_clear_info (enum machine_mode, unsigned HOST_WIDE_INT, int *, int *); +extern void mips_split_msa_subreg_move (rtx, rtx); + extern const char *mips_output_compare (const char *fpcmp, const char *fcond, const char *fmt, const char *fpcc_mode, bool swap); #endif /* ! GCC_MIPS_PROTOS_H */ diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 0b155c107c2..fa2039175ff 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -4716,6 +4716,116 @@ mips_legitimize_const_move (machine_mode mode, rtx dest, rtx src) mips_emit_move (dest, src); } +/* Called only on big-endian targets. See whether an MSA vector move from + SRC to DEST is effectively a (pair of) SHF instruction(s), because at least + one operand is a SUBREG of an MSA vector that has wider or narrower + elements. Return true and emit the instruction if so. + + VIEW_CONVERT (bitconvert) between the two vectors should change only the + compiler's interpretation of the data, not the data itself, which is what + happens on big-endian targets. Therefore, we insert one or two shuffle + instructions to keep the data in registers in a valid state. + + Without this modification, we would spill the SUBREG operand to stack in + one mode and reload it in the other, which is also valid, but obviously + a lot slower. */ + +static bool +mips_maybe_expand_msa_subreg_move (rtx dest, rtx src) +{ + gcc_assert (TARGET_BIG_ENDIAN); + + if (GET_CODE (dest) == SUBREG) + dest = SUBREG_REG (dest); + if (GET_CODE (src) == SUBREG) + src = SUBREG_REG (src); + + /* The optimization handles two MSA REGs with different element size. */ + if (!REG_P (dest) + || !REG_P (src) + || (GET_MODE_UNIT_SIZE (GET_MODE (dest)) + == GET_MODE_UNIT_SIZE (GET_MODE (src)))) + return false; + + /* Generate *msa_mov_subreg_be. */ + rtx unspec = gen_rtx_UNSPEC (GET_MODE (dest), + gen_rtvec (1, src), + UNSPEC_MSA_SUBREG_BE); + emit_insn (gen_rtx_SET (dest, unspec)); + return true; +} + +/* Return a copy of X with mode MODE, without changing its other + attributes. */ +static rtx +mips_replace_reg_mode (rtx x, machine_mode mode) +{ + if (GET_MODE (x) == mode) + return x; + + x = shallow_copy_rtx (x); + set_mode_and_regno (x, mode, REGNO (x)); + return x; +} + +/* Split a *msa_mov_subreg_be pattern with the given operands. */ +void +mips_split_msa_subreg_move (rtx dest, rtx src) +{ + /* Decide how many and which SHF operations we need. The size ratio of + machine modes defines the number of operations, while the mode with the + narrower elements determines the mode of the operands. */ + int shf_value_1, shf_value_2 = 0xb1; + machine_mode mode_with_wider_elts = GET_MODE (dest); + machine_mode mode_with_narrower_elts = GET_MODE (src); + unsigned char wider_mode_size, narrower_mode_size; + rtx x; + + wider_mode_size = GET_MODE_UNIT_SIZE (mode_with_wider_elts); + narrower_mode_size = GET_MODE_UNIT_SIZE (mode_with_narrower_elts); + + if (wider_mode_size < narrower_mode_size) + { + std::swap (mode_with_wider_elts, mode_with_narrower_elts); + std::swap (wider_mode_size, narrower_mode_size); + } + + int size_ratio = wider_mode_size / narrower_mode_size; + switch (size_ratio) + { + case 8: + case 4: + shf_value_1 = 0x1b; + break; + case 2: + shf_value_1 = 0xb1; + break; + default: + gcc_unreachable (); + } + + /* Emit the first SHF instruction with appropriate modes. */ + dest = mips_replace_reg_mode (dest, mode_with_narrower_elts); + src = mips_replace_reg_mode (src, mode_with_narrower_elts); + x = mips_gen_const_int_vector_shuffle (mode_with_narrower_elts, + shf_value_1); + x = gen_rtx_VEC_SELECT (mode_with_narrower_elts, src, x); + x = gen_rtx_SET (dest, x); + emit_insn (x); + + /* Emit the second SHF instruction (if needed) with appropriate modes. */ + if (size_ratio == 8) + { + dest = mips_replace_reg_mode (dest, V4SImode); + src = mips_replace_reg_mode (dest, V4SImode); + x = mips_gen_const_int_vector_shuffle (V4SImode, + shf_value_2); + x = gen_rtx_VEC_SELECT (V4SImode, src, x); + x = gen_rtx_SET (dest, x); + emit_insn (x); + } +} + /* If (set DEST SRC) is not a valid move instruction, emit an equivalent sequence that is valid. */ @@ -4743,6 +4853,33 @@ mips_legitimize_move (machine_mode mode, rtx dest, rtx src) set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); return true; } + + if (TARGET_BIG_ENDIAN + && MSA_SUPPORTED_MODE_P (GET_MODE (dest)) + && MSA_SUPPORTED_MODE_P (GET_MODE (src))) + { + /* SRC or DEST with an MSA mode have an allocated hard register only if + they are function call arguments or return values. In that case, + force their machine modes to V2DImode or V4SImode, depending on the + target size. This will produce shuffle instruction(s) which will + reorder the elements within a vector, so that they conform to the + calling convention. This fixes the discrepancy between calling + conventions of MSA and non-MSA builds. */ + if (REG_P (dest) + && HARD_REGISTER_P (dest) + && GP_REG_P (REGNO (dest))) + dest = mips_replace_reg_mode (dest, TARGET_64BIT ? V2DImode : V4SImode); + + if (REG_P (src) + && HARD_REGISTER_P (src) + && GP_REG_P (REGNO (src))) + src = mips_replace_reg_mode (src, TARGET_64BIT ? V2DImode : V4SImode); + + /* See whether MSA SUBREG move can be replaced with shuffle(s). */ + if (mips_maybe_expand_msa_subreg_move (dest, src)) + return true; + } + return false; } @@ -6005,12 +6142,12 @@ mips_split_128bit_move (rtx dest, rtx src) if (!TARGET_64BIT) { if (GET_MODE (dest) != V4SImode) - new_dest = gen_rtx_REG (V4SImode, REGNO (dest)); + new_dest = mips_replace_reg_mode (dest, V4SImode); } else { if (GET_MODE (dest) != V2DImode) - new_dest = gen_rtx_REG (V2DImode, REGNO (dest)); + new_dest = mips_replace_reg_mode (dest, V2DImode); } for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode); @@ -6033,12 +6170,12 @@ mips_split_128bit_move (rtx dest, rtx src) if (!TARGET_64BIT) { if (GET_MODE (src) != V4SImode) - new_src = gen_rtx_REG (V4SImode, REGNO (src)); + new_src = mips_replace_reg_mode (src, V4SImode); } else { if (GET_MODE (src) != V2DImode) - new_src = gen_rtx_REG (V2DImode, REGNO (src)); + new_src = mips_replace_reg_mode (src, V2DImode); } for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode); @@ -6095,7 +6232,7 @@ mips_split_msa_copy_d (rtx dest, rtx src, rtx index, rtx low = mips_subword (dest, false); rtx high = mips_subword (dest, true); - rtx new_src = gen_rtx_REG (V4SImode, REGNO (src)); + rtx new_src = mips_replace_reg_mode (src, V4SImode); emit_insn (gen_fn (low, new_src, GEN_INT (INTVAL (index) * 2))); emit_insn (gen_fn (high, new_src, GEN_INT (INTVAL (index) * 2 + 1))); @@ -6116,8 +6253,8 @@ mips_split_msa_insert_d (rtx dest, rtx src1, rtx index, rtx src2) from the higher index. */ rtx low = mips_subword (src2, false); rtx high = mips_subword (src2, true); - rtx new_dest = gen_rtx_REG (V4SImode, REGNO (dest)); - rtx new_src1 = gen_rtx_REG (V4SImode, REGNO (src1)); + rtx new_dest = mips_replace_reg_mode (dest, V4SImode); + rtx new_src1 = mips_replace_reg_mode (src1, V4SImode); i = exact_log2 (INTVAL (index)); gcc_assert (i != -1); @@ -6149,7 +6286,7 @@ mips_split_msa_fill_d (rtx dest, rtx src) low = mips_subword (src, false); high = mips_subword (src, true); } - rtx new_dest = gen_rtx_REG (V4SImode, REGNO (dest)); + rtx new_dest = mips_replace_reg_mode (dest, V4SImode); emit_insn (gen_msa_fill_w (new_dest, low)); emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 1))); emit_insn (gen_msa_insert_w (new_dest, high, new_dest, GEN_INT (1 << 3))); diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index 604b1676f2b..6af54d07fc3 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -656,3 +656,8 @@ (define_predicate "reg_or_vector_same_uimm6_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "const_vector_same_uimm6_operand"))) + +(define_predicate "msa_reg_operand" + (if_then_else (match_test "TARGET_BIG_ENDIAN") + (match_code "reg") + (match_operand 0 "register_operand"))) diff --git a/gcc/testsuite/gcc.target/mips/inter/msa-inter.exp b/gcc/testsuite/gcc.target/mips/inter/msa-inter.exp new file mode 100644 index 00000000000..a4d3145fd92 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inter/msa-inter.exp @@ -0,0 +1,67 @@ +# Copyright (C) 2025 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# Run calling convention compatibility tests for vector types in which the "alt" +# compiler uses -mmsa. + +load_lib gcc-dg.exp + +# Check whether we can execute MSA code. +if { ![check_mips_msa_hw_available] } { + return +} + +# Save the old value of CFLAGS_FOR_TARGET, if any. +global saved_CFLAGS_FOR_TARGET +if { [info exists CFLAGS_FOR_TARGET] } { + set saved_CFLAGS_FOR_TARGET $CFLAGS_FOR_TARGET +} else { + unset -nocomplain saved_CFLAGS_FOR_TARGET +} + +# The "alt" compiler is the normal compiler with an extra "-mmsa" argument. +proc compat-use-alt-compiler { } { + global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET + + if { [info exists saved_CFLAGS_FOR_TARGET] } { + set CFLAGS_FOR_TARGET [concat $saved_CFLAGS_FOR_TARGET "-mmsa"] + } else { + set CFLAGS_FOR_TARGET "-mmsa" + } +} + +# Make the compiler under test the default. +proc compat-use-tst-compiler { } { + global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET + + if { [info exists saved_CFLAGS_FOR_TARGET] } { + set CFLAGS_FOR_TARGET $saved_CFLAGS_FOR_TARGET + } else { + unset -nocomplain CFLAGS_FOR_TARGET + } +} + +load_lib compat.exp + +gcc_init +foreach src [lsort [find $srcdir/$subdir msa_*_main.c]] { + if { [runtest_file_p $runtests $src] } { + compat-execute $src "msa_inter" 1 + } +} +compat-use-tst-compiler diff --git a/gcc/testsuite/gcc.target/mips/inter/msa_1.h b/gcc/testsuite/gcc.target/mips/inter/msa_1.h new file mode 100644 index 00000000000..12114a94f3e --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inter/msa_1.h @@ -0,0 +1,23 @@ +typedef signed char v16i8 __attribute__ ((vector_size(16))); +typedef short v8i16 __attribute__ ((vector_size(16))); +typedef int v4i32 __attribute__ ((vector_size(16))); +typedef long long v2i64 __attribute__ ((vector_size(16))); +typedef unsigned char v16u8 __attribute__ ((vector_size(16))); +typedef unsigned short v8u16 __attribute__ ((vector_size(16))); +typedef unsigned int v4u32 __attribute__ ((vector_size(16))); +typedef unsigned long long v2u64 __attribute__ ((vector_size(16))); +typedef float v4f32 __attribute__ ((vector_size(16))); +typedef double v2f64 __attribute__ ((vector_size(16))); + + +#define ITERATE_FOR_ALL_TYPES(FUNC) \ + FUNC (v16i8, 16) \ + FUNC (v8i16, 8) \ + FUNC (v4i32, 4) \ + FUNC (v2i64, 2) \ + FUNC (v16u8, 16) \ + FUNC (v8u16, 8) \ + FUNC (v4u32, 4) \ + FUNC (v2u64, 2) \ + FUNC (v4f32, 4) \ + FUNC (v2f64, 2) diff --git a/gcc/testsuite/gcc.target/mips/inter/msa_1_main.c b/gcc/testsuite/gcc.target/mips/inter/msa_1_main.c new file mode 100644 index 00000000000..0d17c8381a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inter/msa_1_main.c @@ -0,0 +1,8 @@ +extern void test (void); + +int +main (void) +{ + test (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/mips/inter/msa_1_x.c b/gcc/testsuite/gcc.target/mips/inter/msa_1_x.c new file mode 100644 index 00000000000..f3d43ca5c16 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inter/msa_1_x.c @@ -0,0 +1,35 @@ +#include "msa_1.h" + +#define INIT_2 {1, 2} +#define INIT_4 {1, 2, 3, 4} +#define INIT_8 {1, 2, 3, 4, 5, 6, 7, 8} +#define INIT_16 {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 ,14 ,15 ,16} + +#define TEST(TYPE, NUM) \ +__attribute__ ((noinline)) static void \ +test_ ## TYPE ##_caller (void) \ +{ \ + extern TYPE test_ ## TYPE ##_callee (TYPE, const TYPE*); \ + TYPE vect = (TYPE) INIT_ ## NUM; \ + TYPE res = test_ ## TYPE ## _callee (vect, &vect); \ + if (__builtin_memcmp (&vect, &res, sizeof vect)) \ + __builtin_abort(); \ +} + +ITERATE_FOR_ALL_TYPES(TEST) + +#undef TEST +#undef INIT_2 +#undef INIT_4 +#undef INIT_8 +#undef INIT_16 + +#define RUN_TEST(TYPE, NUM) test_ ## TYPE ##_caller (); + +void +test (void) +{ + ITERATE_FOR_ALL_TYPES(RUN_TEST) +} + +#undef RUN_TEST diff --git a/gcc/testsuite/gcc.target/mips/inter/msa_1_y.c b/gcc/testsuite/gcc.target/mips/inter/msa_1_y.c new file mode 100644 index 00000000000..250df27d703 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inter/msa_1_y.c @@ -0,0 +1,14 @@ +#include "msa_1.h" + +#define TEST(TYPE, NUM) \ +TYPE \ +test_ ## TYPE ##_callee (TYPE vect, const TYPE* pvect) \ +{ \ + if (__builtin_memcmp (&vect, pvect, sizeof vect)) \ + __builtin_abort(); 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Fri, 31 Jan 2025 17:14:13 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Mihailo Stojanovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 51/61] Test solution on dspmac builtins Thread-Topic: [PATCH 51/61] Test solution on dspmac builtins Thread-Index: AQHbdAN8wOYwpU3fJ0erxq3Nhib1bQ== Date: Fri, 31 Jan 2025 17:13:45 +0000 Message-ID: <20250131171232.1018281-53-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: 2c968653-9364-45cd-73c8-08dd421aaf95 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Cherry-picked 110ec7a3e56737bb8ed2ae653298aa55ad014377 and 712169a3630d45284ddd6ea6d0dedcb2b60e0ba4 from https://github.com/MIPS/gcc Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 24 ++++++++++++++ .../gcc.target/mips/mac_zero_reload.c | 32 +++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/mac_zero_reload.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index fa2039175ff..20128c7f537 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -19215,6 +19215,30 @@ mips_expand_builtin_insn (enum insn_code icode, unsigned int nops, case CODE_FOR_msa_dpsub_u_w: case CODE_FOR_msa_dpsub_u_h: case CODE_FOR_msa_dpsub_u_d: + + case CODE_FOR_mips_dpau_h_qbl: + case CODE_FOR_mips_dpau_h_qbr: + case CODE_FOR_mips_dpsu_h_qbl: + case CODE_FOR_mips_dpsu_h_qbr: + case CODE_FOR_mips_dpaq_s_w_ph: + case CODE_FOR_mips_dpsq_s_w_ph: + case CODE_FOR_mips_mulsaq_s_w_ph: + case CODE_FOR_mips_dpaq_sa_l_w: + case CODE_FOR_mips_dpsq_sa_l_w: + case CODE_FOR_mips_maq_s_w_phl: + case CODE_FOR_mips_maq_s_w_phr: + case CODE_FOR_mips_maq_sa_w_phl: + case CODE_FOR_mips_maq_sa_w_phr: + + case CODE_FOR_mips_dpa_w_ph: + case CODE_FOR_mips_dps_w_ph: + case CODE_FOR_mips_mulsa_w_ph: + case CODE_FOR_mips_dpax_w_ph: + case CODE_FOR_mips_dpsx_w_ph: + case CODE_FOR_mips_dpaqx_s_w_ph: + case CODE_FOR_mips_dpaqx_sa_w_ph: + case CODE_FOR_mips_dpsqx_s_w_ph: + case CODE_FOR_mips_dpsqx_sa_w_ph: /* Force the operands which correspond to the same in-out register to have the same pseudo assigned to them. If the input operand is not REG, create one for it. */ diff --git a/gcc/testsuite/gcc.target/mips/mac_zero_reload.c b/gcc/testsuite/gcc.target/mips/mac_zero_reload.c new file mode 100644 index 00000000000..63261bc1493 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mac_zero_reload.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-fno-unroll-loops -mgp32 -mdspr2" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ +/* { dg-final { scan-assembler-not "\tmflo\t" } } */ +/* { dg-final { scan-assembler-not "\tmfhi\t" } } */ +/* { dg-final { scan-assembler-not "\tmtlo\t" } } */ +/* { dg-final { scan-assembler-not "\tmthi\t" } } */ + +typedef short v2i16 __attribute__ ((vector_size(4))); + +extern v2i16 ps32Ptrl[4096]; + +extern int sink[4096]; + +int main(void) +{ + v2i16 v2i16_h0; + long long s64Acc; + + for (int i = 0; i < 4; ++i) + { + v2i16_h0 = ps32Ptrl[i]; + + s64Acc = 0; + + s64Acc = __builtin_mips_dpa_w_ph(s64Acc, v2i16_h0, v2i16_h0); + + sink[i] = __builtin_mips_extr_rs_w(s64Acc, 0); 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Cherry-picked fa3b6a1347154973324d264e6ad2dbd66d3f0028 from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.target/mips/tls-1.c | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/tls-1.c diff --git a/gcc/testsuite/gcc.target/mips/tls-1.c b/gcc/testsuite/gcc.target/mips/tls-1.c new file mode 100644 index 00000000000..38f6a5e1176 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/tls-1.c @@ -0,0 +1,10 @@ +/* { dg-options "-mgp32" } */ + +extern __thread int x __attribute__ ((tls_model ("initial-exec"))); + +long long +foo (long long y) +{ + x = 0; + return y; +} From patchwork Fri Jan 31 17:13:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105815 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C79453857704 for ; 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Cherry-picked 092a39db956a418e7e020107b062c170ed976841 from https://github.com/MIPS/gcc Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 20128c7f537..4894e07f72c 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -25749,6 +25749,22 @@ mips_set_up_by_prologue (hard_reg_set_container *regs) CLEAR_HARD_REG_BIT (regs->set, GLOBAL_POINTER_REGNUM); } +/* Implemet TARGET_LEGITIMATE_COMBINED_INSN hook. */ + +static bool +mips_legitimate_combined_insn (rtx_insn *insn) +{ + rtx p = PATTERN (insn); + if (GET_CODE (p) == SET + && GET_CODE (XEXP (p, 1)) == VEC_DUPLICATE + && GET_CODE (XEXP (XEXP (p, 1), 0)) == REG + && (GET_MODE_UNIT_SIZE (GET_MODE (XEXP (XEXP (p, 1), 0))) + > UNITS_PER_WORD)) + return false; + + return true; +} + void mips_bit_clear_info (enum machine_mode mode, unsigned HOST_WIDE_INT m, int *start_pos, int *size) @@ -26130,6 +26146,9 @@ mips_noce_conversion_profitable_p (rtx_insn *seq, struct noce_if_info *if_info) #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class +#undef TARGET_LEGITIMATE_COMBINED_INSN +#define TARGET_LEGITIMATE_COMBINED_INSN mips_legitimate_combined_insn + #undef TARGET_HARD_REGNO_SCRATCH_OK #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok From patchwork Fri Jan 31 17:13:47 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:14:15 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , dragan.mladjenovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 54/61] fmadd.w should be restricted to mipsr6 Thread-Topic: [PATCH 54/61] fmadd.w should be restricted to mipsr6 Thread-Index: AQHbdAN9Y0yWfMYv6EGXUfA1X5R/Jg== Date: Fri, 31 Jan 2025 17:13:47 +0000 Message-ID: <20250131171232.1018281-56-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|GVXPR09MB7727:EE_ x-ms-office365-filtering-correlation-id: fbebb61e-d518-4d63-9206-08dd421ab09d x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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There might be Loongson targets that support MSA while having scalar multiply-add that is fused (contrary to ISA spec). This patch doesn't handle those cases. gcc/ * config/mips/mips-msa.md (fma4, fnma4): Transform into empty expander. Conditionalize on ISA_HAS_FUSED_MADDF. Move the body into ... (msa_fmadd_, msa_fmsub_): New insn patterns. * config/mips/mips.cc (CODE_FOR_msa_fmadd_*): Remove. (CODE_FOR_msa_fmsub_*): Ditto. gcc/testsuite/ * gcc.target/mips/msa-fuse-madd-double.c: New test. * gcc.target/mips/msa-fuse-madd-single.c: New test. * gcc.target/mips/msa.c: Do not match fmadd/fmsub on !mipsisar6 targets. * lib/target-supports.exp: Define mipsisar6 target. Cherry-picked 7a48948f245a5e46f55d59c6ac0982a815665ccf from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips-msa.md | 26 +++++++--- gcc/config/mips/mips.cc | 4 -- .../gcc.target/mips/msa-fuse-madd-double.c | 52 +++++++++++++++++++ .../gcc.target/mips/msa-fuse-madd-single.c | 51 ++++++++++++++++++ gcc/testsuite/gcc.target/mips/msa.c | 14 +++-- gcc/testsuite/lib/target-supports.exp | 10 ++++ 6 files changed, 143 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/msa-fuse-madd-double.c create mode 100644 gcc/testsuite/gcc.target/mips/msa-fuse-madd-single.c diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index e2fdf8e191e..34f140e159c 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -973,21 +973,35 @@ [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) -(define_insn "fma4" +(define_expand "fma4" [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") (fma:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") (match_operand:FMSA 2 "msa_reg_operand" "f") (match_operand:FMSA 3 "msa_reg_operand" "0")))] - "ISA_HAS_MSA" - "fmadd.\t%w0,%w1,%w2" - [(set_attr "type" "simd_fmadd") - (set_attr "mode" "")]) + "ISA_HAS_MSA && ISA_HAS_FUSED_MADDF") -(define_insn "fnma4" +(define_expand "fnma4" [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f")) (match_operand:FMSA 2 "msa_reg_operand" "f") (match_operand:FMSA 3 "msa_reg_operand" "0")))] + "ISA_HAS_MSA && ISA_HAS_FUSED_MADDF") + +(define_insn "msa_fmadd_" + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (fma:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f") + (match_operand:FMSA 2 "msa_reg_operand" "f") + (match_operand:FMSA 3 "msa_reg_operand" "0")))] + "ISA_HAS_MSA" + "fmadd.\t%w0,%w1,%w2" + [(set_attr "type" "simd_fmadd") + (set_attr "mode" "")]) + +(define_insn "msa_fmsub_" + [(set (match_operand:FMSA 0 "msa_reg_operand" "=f") + (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "msa_reg_operand" "f")) + (match_operand:FMSA 2 "msa_reg_operand" "f") + (match_operand:FMSA 3 "msa_reg_operand" "0")))] "ISA_HAS_MSA" "fmsub.\t%w0,%w1,%w2" [(set_attr "type" "simd_fmadd") diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 4894e07f72c..4521cac15c7 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -17752,10 +17752,6 @@ AVAIL_NON_MIPS16 (msa, TARGET_MSA) #define CODE_FOR_msa_ffint_u_d CODE_FOR_floatunsv2div2df2 #define CODE_FOR_msa_fsub_w CODE_FOR_subv4sf3 #define CODE_FOR_msa_fsub_d CODE_FOR_subv2df3 -#define CODE_FOR_msa_fmadd_w CODE_FOR_fmav4sf4 -#define CODE_FOR_msa_fmadd_d CODE_FOR_fmav2df4 -#define CODE_FOR_msa_fmsub_w CODE_FOR_fnmav4sf4 -#define CODE_FOR_msa_fmsub_d CODE_FOR_fnmav2df4 #define CODE_FOR_msa_fmul_w CODE_FOR_mulv4sf3 #define CODE_FOR_msa_fmul_d CODE_FOR_mulv2df3 #define CODE_FOR_msa_fdiv_w CODE_FOR_divv4sf3 diff --git a/gcc/testsuite/gcc.target/mips/msa-fuse-madd-double.c b/gcc/testsuite/gcc.target/mips/msa-fuse-madd-double.c new file mode 100644 index 00000000000..e98bf017a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-fuse-madd-double.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-mhard-float -mmsa" } */ +/* { dg-additional-options "-ffp-contract=fast" } */ + +#define VSIZE 8 + +typedef union +{ double d; long long unsigned i; } double_ull_u; + +struct test_vec { + double_ull_u a; + double_ull_u b; + double_ull_u c; +} test_bench[VSIZE] = { + {{.i=0x2c27173b4c9b0904ull}, {.i=0x6aa7b75c1df029d3ull}, {.i=0x5675ff363dd15094ull}}, + {{.i=0x3a6f0e78379a5b56ull}, {.i=0x53b735d529784870ull}, {.i=0x4cdced4c10a30d9cull}}, + {{.i=0x12d2eee56cc2b66aull}, {.i=0x60cd438558be66cdull}, {.i=0x335e9e8d425c189bull}}, + {{.i=0x680d29830daea0c2ull}, {.i=0x4c5977b52c0d49efull}, {.i=0x7305e21c2165c647ull}}, + {{.i=0x4e4add4115ecbebull}, {.i=0x401d6aed0c821feeull}, {.i=0x300832736663b62ull}}, + {{.i=0x1f6f475265504cc9ull}, {.i=0x4e5785aa042408acull}, {.i=0x2ab32c6b25521f4aull}}, + {{.i=0xd09c440443b602dull}, {.i=0x5f618fbb1fe650a2ull}, {.i=0x295aa9221841d645ull}}, + {{.i=0x732612c95a91b01full}, {.i=0x268678105b8f78b5ull}, {.i=0x5973c32a350e1c23ull}}, +}; + +int main (void) +{ + int i; + double __attribute__((aligned(16))) av [VSIZE]; + double __attribute__((aligned(16))) bv[VSIZE]; + double __attribute__((aligned(16))) cv[VSIZE]; + double __attribute__((aligned(16))) res1[VSIZE]; + double __attribute__((aligned(16))) res2[VSIZE - 1]; + + for (i = 0; i < VSIZE; i++) + { + av[i] = test_bench[i].a.d; + bv[i] = test_bench[i].b.d; + cv[i] = test_bench[i].c.d; + } + + for (i = 0; i < VSIZE; i++) + res1[i] = av[i] * bv[i] + cv[i]; + + for (i = 0; i < VSIZE - 1; i++) + res2[i] = av[i] * bv[i] + cv[i]; + + for (i = 0; i < VSIZE - 1; i++) + if (res2[i] != res1[i]) + return 1; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/mips/msa-fuse-madd-single.c b/gcc/testsuite/gcc.target/mips/msa-fuse-madd-single.c new file mode 100644 index 00000000000..03828a8ffb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-fuse-madd-single.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-mhard-float -mmsa" } */ +/* { dg-additional-options "-ffp-contract=fast" } */ + +#define VSIZE 8 + +typedef union { float f; unsigned long i; } float_ul_u; + +struct test_vec { + float_ul_u a; + float_ul_u b; + float_ul_u c; +} test_bench[VSIZE] = { + {{.i=0x42963e5aul}, {.i=0xa0382c5ul}, {.i=0x8f2b15eul}}, + {{.i=0x1c695decul}, {.i=0x3fcfaed9ul}, {.i=0xf856867ul}}, + {{.i=0x116ae494ul}, {.i=0x3494b2fbul}, {.i=0xb13a31ul}}, + {{.i=0x683caad3ul}, {.i=0x313c7c99ul}, {.i=0x519eb94cul}}, + {{.i=0x4a9554feul}, {.i=0x392edbe4ul}, {.i=0x3d1a2dd9ul}}, + {{.i=0x4c4fff5bul}, {.i=0x51b76675ul}, {.i=0x59a4ba71ul}}, + {{.i=0x17cfc87dul}, {.i=0x5d66dc65ul}, {.i=0x30bb2b99ul}}, + {{.i=0x61c66e3ul}, {.i=0x69321f16ul}, {.i=0x2d96b714ul}}, +}; + +int main (void) +{ + int i; + float __attribute__((aligned(16))) av [VSIZE]; + float __attribute__((aligned(16))) bv[VSIZE]; + float __attribute__((aligned(16))) cv[VSIZE]; + float __attribute__((aligned(16))) res1[VSIZE]; + float __attribute__((aligned(16))) res2[VSIZE - 1]; + + for (i = 0; i < VSIZE; i++) + { + av[i] = test_bench[i].a.f; + bv[i] = test_bench[i].b.f; + cv[i] = test_bench[i].c.f; + } + + for (i = 0; i < VSIZE; i++) + res1[i] = av[i] * bv[i] + cv[i]; + + for (i = 0; i < VSIZE - 1; i++) + res2[i] = av[i] * bv[i] + cv[i]; + + for (i = 0; i < VSIZE - 1; i++) + if (res2[i] != res1[i]) + return 1; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/mips/msa.c b/gcc/testsuite/gcc.target/mips/msa.c index 8647b6d9530..b6aaa5e9921 100644 --- a/gcc/testsuite/gcc.target/mips/msa.c +++ b/gcc/testsuite/gcc.target/mips/msa.c @@ -362,8 +362,11 @@ /* { dg-final { scan-assembler-times "test37_v8u16:.*maddv.h.*test37_v8u16" 1 } } */ /* { dg-final { scan-assembler-times "test37_v4u32:.*maddv.w.*test37_v4u32" 1 } } */ /* { dg-final { scan-assembler-times "test37_v2u64:.*maddv.d.*test37_v2u64" 1 } } */ -/* { dg-final { scan-assembler-times "test37_v4f32:.*fmadd.w.*test37_v4f32" 1 } } */ -/* { dg-final { scan-assembler-times "test37_v2f64:.*fmadd.d.*test37_v2f64" 1 } } */ +/* Note: We chose not to emit fmadd.* on pre-r6 targets that lack scalar fma. */ +/* { dg-final { scan-assembler-times "test37_v4f32:.*fmadd.w.*test37_v4f32" 1 { target mipsisar6 } } } */ +/* { dg-final { scan-assembler-times "test37_v2f64:.*fmadd.d.*test37_v2f64" 1 { target mipsisar6 } } } */ +/* { dg-final { scan-assembler-times "test37_v4f32:.*fmul.w.*fadd.w.*test37_v4f32" 1 { target {! mipsisar6 } } } } */ +/* { dg-final { scan-assembler-times "test37_v2f64:.*fmul.d.*fadd.d.*test37_v2f64" 1 { target {! mipsisar6 } } } } */ /* { dg-final { scan-assembler-times "test38_v16i8:.*msubv.b.*test38_v16i8" 1 } } */ /* { dg-final { scan-assembler-times "test38_v8i16:.*msubv.h.*test38_v8i16" 1 } } */ /* { dg-final { scan-assembler-times "test38_v4i32:.*msubv.w.*test38_v4i32" 1 } } */ @@ -372,8 +375,11 @@ /* { dg-final { scan-assembler-times "test38_v8u16:.*msubv.h.*test38_v8u16" 1 } } */ /* { dg-final { scan-assembler-times "test38_v4u32:.*msubv.w.*test38_v4u32" 1 } } */ /* { dg-final { scan-assembler-times "test38_v2u64:.*msubv.d.*test38_v2u64" 1 } } */ -/* { dg-final { scan-assembler-times "test38_v4f32:.*fmsub.w.*test38_v4f32" 1 } } */ -/* { dg-final { scan-assembler-times "test38_v2f64:.*fmsub.d.*test38_v2f64" 1 } } */ +/* Note: We chose not to emit fmsub.* on pre-r6 targets that lack scalar fma. */ +/* { dg-final { scan-assembler-times "test38_v4f32:.*fmsub.w.*test38_v4f32" 1 { target mipsisar6 } } } */ +/* { dg-final { scan-assembler-times "test38_v2f64:.*fmsub.d.*test38_v2f64" 1 { target mipsisar6 } } } */ +/* { dg-final { scan-assembler-times "test38_v4f32:.*fmul.w.*fsub.w.*test38_v4f32" 1 { target {! mipsisar6 } } } } */ +/* { dg-final { scan-assembler-times "test38_v2f64:.*fmul.d.*fsub.d.*test38_v2f64" 1 { target {! mipsisar6 } } } } */ /* { dg-final { scan-assembler-times "test39_v16i8:.*ld.b.*test39_v16i8" 1 } } */ /* { dg-final { scan-assembler-times "test39_v8i16:.*ld.h.*test39_v8i16" 1 } } */ /* { dg-final { scan-assembler-times "test39_v4i32:.*ld.w.*test39_v4i32" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 4f005c5a7d2..72c2fa195b4 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1514,6 +1514,16 @@ proc check_effective_target_mips64 { } { }] } +# Return true if the target is a MIPS rev 6 target. + +proc check_effective_target_mipsisar6 { } { + return [check_no_compiler_messages mipsisar6 assembly { + #if __mips_isa_rev < 6 + #error !__mips_isa_rev + #endif + }] +} + # Return true if the target is using a compressed MIPS ISA. proc check_effective_target_mips_compressed { } { From patchwork Fri Jan 31 17:13:48 2025 Content-Type: text/plain; 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Fri, 31 Jan 2025 17:14:16 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , Mihailo Stojanovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 55/61] Performance drop in mips-img-linux-gnu-gcc 7.x Thread-Topic: [PATCH 55/61] Performance drop in mips-img-linux-gnu-gcc 7.x Thread-Index: AQHbdAN9Z+uQmTp+LkOBtAGRD8kUhg== Date: Fri, 31 Jan 2025 17:13:48 +0000 Message-ID: <20250131171232.1018281-57-aleksandar.rakic@htecgroup.com> References: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> In-Reply-To: <20250131171232.1018281-1-aleksandar.rakic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|VI1PR09MB3838:EE_ x-ms-office365-filtering-correlation-id: 58678627-cb69-4166-7ae0-08dd421ab0d4 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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(mips_prune_insertions_deletions): Target hook which checks whether a basic block is possibly if-convertible. Adjusts the insertion and deletion maps accordingly. (check_bb): Check whether a basic block is a THEN or ELSE block of IF-THEN-ELSE construct and whether it consists only of a single set instruction. This is a condition for marking the block as possibly if-convertible. (bb_valid_for_noce): Helper function. (last_active_insn): Same. (first_active_insn): Same. (insn_valid_noce_process_p): Same. (noce_operand_ok): Same. * config/mips/mips.opt: Add an option which disables the mips_prune_insertions_deletions hook. * doc/tm.texi.in: Add a macro definition for the new target hook. * gcse.c (compute_pre_data): Add the target hook call, which will modify the insertion and deletion bitmaps. * target.def: Define the target hook. * targhooks.h: Add default target hook prototype. * targhooks.c: Define the default target hook prototype. * doc/tm.texi: Regenerated. Cherry-picked 64e5b4b4ff53872482454908a29c94665e40d25c from https://github.com/MIPS/gcc Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 238 +++++++++++++++++++++++++++++++++++++++ gcc/config/mips/mips.opt | 3 + gcc/doc/tm.texi | 5 + gcc/doc/tm.texi.in | 2 + gcc/gcse.cc | 3 + gcc/target.def | 8 ++ gcc/targhooks.cc | 9 ++ gcc/targhooks.h | 5 + 8 files changed, 273 insertions(+) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 4521cac15c7..d23c30a43be 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -5754,6 +5754,8 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code, default: break; } + if (GET_CODE (SET_DEST (x)) != PC) + *total = 0; return false; case IF_THEN_ELSE: @@ -25872,6 +25874,239 @@ mips_noce_conversion_profitable_p (rtx_insn *seq, struct noce_if_info *if_info) return speed && cost <= if_info->max_seq_cost; } + +/* Return true if OP is ok for if-then-else processing. */ + +static int +noce_operand_ok (const_rtx op) +{ + if (side_effects_p (op)) + return FALSE; + + /* We special-case memories, so handle any of them with + no address side effects. */ + if (MEM_P (op)) + return ! side_effects_p (XEXP (op, 0)); + + return ! may_trap_p (op); +} + + +/* Helper for bb_valid_for_noce_process_p. Validate that + the rtx insn INSN is a single set that does not set + the conditional register CC and is in general valid for + if-conversion. */ + +static bool +insn_valid_noce_process_p (rtx_insn *insn) +{ + if (!insn + || !NONJUMP_INSN_P (insn)) + return false; + + rtx sset = single_set (insn); + + /* Currently support only simple single sets in test_bb. */ + if (!sset + || !noce_operand_ok (SET_DEST (sset)) + || !noce_operand_ok (SET_SRC (sset))) + return false; + + return true; +} + +/* Return the first non-jump active insn in the basic block. */ + +static rtx_insn * +first_active_insn (basic_block bb) +{ + rtx_insn *insn = BB_HEAD (bb); + + if (LABEL_P (insn)) + { + if (insn == BB_END (bb)) + return NULL; + insn = NEXT_INSN (insn); + } + + while (NOTE_P (insn) || DEBUG_INSN_P (insn)) + { + if (insn == BB_END (bb)) + return NULL; + insn = NEXT_INSN (insn); + } + + if (JUMP_P (insn)) + return NULL; + + return insn; +} + +static rtx_insn * +last_active_insn (basic_block bb, int skip_use_p) +{ + rtx_insn *insn = BB_END (bb); + rtx_insn *head = BB_HEAD (bb); + + while (NOTE_P (insn) + || JUMP_P (insn) + || DEBUG_INSN_P (insn) + || (skip_use_p + && NONJUMP_INSN_P (insn) + && GET_CODE (PATTERN (insn)) == USE)) + { + if (insn == head) + return NULL; + insn = PREV_INSN (insn); + } + + if (LABEL_P (insn)) + return NULL; + + return insn; +} + +static bool +bb_valid_for_noce (basic_block test_bb, bool *simple) +{ + if (!test_bb) + return false; + + rtx_insn *last_insn = last_active_insn (test_bb, FALSE); + + if (!insn_valid_noce_process_p (last_insn)) + return false; + + rtx_insn *first_insn = first_active_insn (test_bb); + rtx first_set = single_set (first_insn); + + if (!first_set) + return false; + + *simple = first_insn == last_insn; + return true; +} + +#define NULL_BLOCK ((basic_block) NULL) + +static bool +check_bb (basic_block test_bb, sbitmap *ifcv_blocks) +{ + /* The kind of block we're looking for has exactly two successors. */ + if (EDGE_COUNT (test_bb->succs) != 2) + return false; + + edge then_edge = EDGE_SUCC (test_bb, 0); + edge else_edge = EDGE_SUCC (test_bb, 1); + + /* The THEN edge is canonically the one that falls through. */ + if (then_edge->flags & EDGE_FALLTHRU) + ; + else if (else_edge->flags & EDGE_FALLTHRU) + std::swap (then_edge, else_edge); + else + /* Otherwise this must be a multiway branch of some sort. */ + return false; + + basic_block then_bb, else_bb; + + /* Recognize an IF-THEN-ELSE-JOIN block. */ + if (single_pred_p (then_edge->dest) + && single_succ_p (then_edge->dest) + && single_pred_p (else_edge->dest) + && single_succ_p (else_edge->dest) + && single_succ (then_edge->dest) == single_succ (else_edge->dest)) + { + then_bb = then_edge->dest; + else_bb = else_edge->dest; + } + /* Recognize an IF-THEN-JOIN block. */ + else if (single_pred_p (then_edge->dest) + && single_succ_p (then_edge->dest) + && single_succ (then_edge->dest) == else_edge->dest) + { + then_bb = then_edge->dest; + else_bb = NULL_BLOCK; + } + /* Recognize an IF-ELSE-JOIN block. We can have those because the order + of basic blocks in cfglayout mode does not matter, so the fallthrough + edge can go to any basic block (and not just to bb->next_bb, like in + cfgrtl mode). */ + else if (single_pred_p (else_edge->dest) + && single_succ_p (else_edge->dest) + && single_succ (else_edge->dest) == then_edge->dest) + { + /* The noce transformations do not apply to IF-ELSE-JOIN blocks. + To make this work, we have to invert the THEN and ELSE blocks + and reverse the jump condition. */ + then_bb = else_edge->dest; + else_bb = NULL_BLOCK; + } + else + /* Not a form we can handle. */ + return FALSE; + + bool then_simple = false; + bool else_simple = false; + + if (bb_valid_for_noce (then_bb, &then_simple) && then_simple) + bitmap_set_bit (*ifcv_blocks, then_bb->index); + if (bb_valid_for_noce (else_bb, &else_simple) && else_simple) + bitmap_set_bit (*ifcv_blocks, else_bb->index); + + return false; +} + +void +mips_prune_insertions_deletions (struct edge_list* edge_list, + unsigned int n_elems, + sbitmap *pre_insert_map, + sbitmap *pre_delete_map) +{ + basic_block bb; + unsigned int i, j; + sbitmap_iterator sbi; + unsigned int bb_num = (unsigned) last_basic_block_for_fn (cfun); + sbitmap ifcv_blocks = sbitmap_alloc (bb_num); + sbitmap insertions = sbitmap_alloc (n_elems); + bitmap_clear (ifcv_blocks); + bitmap_clear (insertions); + + if (TARGET_PRUNE_INSERT_DELETE) + return; + + FOR_EACH_BB_FN (bb, cfun) + check_bb (bb, &ifcv_blocks); + + int num_edges = NUM_EDGES (edge_list); + int e; + for (e = 0; e < num_edges; e++) + { + basic_block pred = INDEX_EDGE_PRED_BB (edge_list, e); + basic_block succ = INDEX_EDGE_SUCC_BB (edge_list, e); + + if (bitmap_bit_p (ifcv_blocks, pred->index) + || bitmap_bit_p (ifcv_blocks, succ->index)) + { + EXECUTE_IF_SET_IN_BITMAP (pre_insert_map[e], 0, i, sbi) + bitmap_set_bit (insertions, i); + + bitmap_clear (pre_insert_map[e]); + } + } + + for (i = 0; i < bb_num; i++) + { + EXECUTE_IF_SET_IN_BITMAP (pre_delete_map[i], 0, j, sbi) + { + if (bitmap_bit_p (insertions, j)) + bitmap_clear_bit (pre_delete_map[i], j); + } + } + + sbitmap_free (ifcv_blocks); + sbitmap_free (insertions); +} /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP @@ -26217,6 +26452,9 @@ mips_noce_conversion_profitable_p (rtx_insn *seq, struct noce_if_info *if_info) #undef TARGET_NOCE_CONVERSION_PROFITABLE_P #define TARGET_NOCE_CONVERSION_PROFITABLE_P mips_noce_conversion_profitable_p +#undef TARGET_PRUNE_INSERTIONS_DELETIONS +#define TARGET_PRUNE_INSERTIONS_DELETIONS mips_prune_insertions_deletions + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-mips.h" diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index be347155286..804f4fecbc9 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -570,6 +570,9 @@ Target Undocumented Var(TARGET_USE_SAVE_RESTORE) Init(-1) muse-copyw-ucopyw Target Undocumented Var(TARGET_USE_COPYW_UCOPYW) Init(-1) +mno-prune-insert-delete +Target Undocumented Var(TARGET_PRUNE_INSERT_DELETE) + minline-intermix Target Var(TARGET_INLINE_INTERMIX) Allow inlining even if the compression flags differ between caller and callee. diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 109e40384b6..aac034524e7 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -7323,6 +7323,11 @@ The default implementation of this hook uses the and uses a multiple of @code{BRANCH_COST} otherwise. @end deftypefn +@deftypefn {Target Hook} void TARGET_PRUNE_INSERTIONS_DELETIONS (struct edge_list *@var{edge_list}, unsigned int @var{n_elems}, sbitmap *@var{pre_insert_map}, sbitmap *@var{pre_delete_map}) +This hook gives the target a possibility to stop the code motion during + GCSE pass for basic blocks which have a potential to be if-converted. +@end deftypefn + @deftypefn {Target Hook} bool TARGET_NOCE_CONVERSION_PROFITABLE_P (rtx_insn *@var{seq}, struct noce_if_info *@var{if_info}) This hook returns true if the instruction sequence @code{seq} is a good candidate as a replacement for the if-convertible sequence described in diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 93bcd747e37..4d81a1729de 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -4744,6 +4744,8 @@ Define this macro if a non-short-circuit operation produced by @hook TARGET_MAX_NOCE_IFCVT_SEQ_COST +@hook TARGET_PRUNE_INSERTIONS_DELETIONS + @hook TARGET_NOCE_CONVERSION_PROFITABLE_P @hook TARGET_NEW_ADDRESS_PROFITABLE_P diff --git a/gcc/gcse.cc b/gcc/gcse.cc index 31b92f30fa1..12e252d826d 100644 --- a/gcc/gcse.cc +++ b/gcc/gcse.cc @@ -1893,6 +1893,9 @@ compute_pre_data (void) prune_insertions_deletions (expr_hash_table.n_elems); + targetm.prune_insertions_deletions (edge_list, expr_hash_table.n_elems, + pre_insert_map, pre_delete_map); + return edge_list; } diff --git a/gcc/target.def b/gcc/target.def index 523ae7ec9aa..80f0f1ef53b 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -7056,6 +7056,14 @@ You need not define this hook if @code{WORD_REGISTER_OPERATIONS} is not\n\ defined to 1.", unsigned int, (void), default_min_arithmetic_precision) +/* Function to update PRE deletion and insertion bitmaps. */ +DEFHOOK +(prune_insertions_deletions, + "This hook gives the target a possibility to stop the code motion during\n\ + GCSE pass for basic blocks which have a potential to be if-converted.", + void, (struct edge_list *edge_list, unsigned int n_elems, sbitmap *pre_insert_map, sbitmap *pre_delete_map), + default_prune_insertions_deletions) + DEFHOOKPOD (atomic_test_and_set_trueval, "This value should be set if the result written by\n\ diff --git a/gcc/targhooks.cc b/gcc/targhooks.cc index 304b35ed772..f1e0a157c9e 100644 --- a/gcc/targhooks.cc +++ b/gcc/targhooks.cc @@ -2843,4 +2843,13 @@ default_memtag_untagged_pointer (rtx tagged_pointer, rtx target) return untagged_base; } +void +default_prune_insertions_deletions (struct edge_list * + edge_list ATTRIBUTE_UNUSED, + unsigned int n_elems ATTRIBUTE_UNUSED, + sbitmap *pre_insert_map ATTRIBUTE_UNUSED, + sbitmap *pre_delete_map ATTRIBUTE_UNUSED) +{ +} + #include "gt-targhooks.h" diff --git a/gcc/targhooks.h b/gcc/targhooks.h index 2704d6008f1..2e3d05a1e92 100644 --- a/gcc/targhooks.h +++ b/gcc/targhooks.h @@ -309,4 +309,9 @@ extern rtx default_memtag_set_tag (rtx, rtx, rtx); extern rtx default_memtag_extract_tag (rtx, rtx); extern rtx default_memtag_untagged_pointer (rtx, rtx); +extern void default_prune_insertions_deletions (struct edge_list *edge_list, + unsigned int n_elems, + sbitmap *pre_insert_map, + sbitmap *pre_delete_map); + #endif /* GCC_TARGHOOKS_H */ From patchwork Fri Jan 31 17:13:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105776 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DCE44385782C for ; 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Modify the cost modulo by power of two. (mips_expand_mod_pow2): New expander for modulo by power of two of 64-bit values on 32-bit targets. * config/mips/mips.md (define_expand "mod3"): Separate define_expand for "mod3" from the define_insn and call the new expander for 64-bit values on 32-bit targets. (define_insn "*mod3"): Add * to the pattern name to avoid clash with the define_expand pattern. gcc/testsuite/ * gcc.target/mips/mod-pow2.c: New test. Cherry-picked e683ed1717b3f689c959c738a764174fdcdc7998 from https://github.com/MIPS/gcc Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips-protos.h | 2 + gcc/config/mips/mips.cc | 144 ++++++++++++++++++- gcc/config/mips/mips.md | 31 +++- gcc/testsuite/gcc.target/mips/mod-pow2.c | 176 +++++++++++++++++++++++ 4 files changed, 350 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mod-pow2.c diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 435b2e7e179..5782cd5d1b7 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -401,4 +401,6 @@ extern void mips_split_msa_subreg_move (rtx, rtx); extern const char *mips_output_compare (const char *fpcmp, const char *fcond, const char *fmt, const char *fpcc_mode, bool swap); +extern bool mips_expand_mod_pow2 (rtx, rtx, rtx); + #endif /* ! GCC_MIPS_PROTOS_H */ diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index d23c30a43be..19d428e6ed6 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -5292,6 +5292,19 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code, return true; } + /* Don't force the constant into register during modulo by power of two. + This is needed so that the MIPS-specific modulo pattern will be + selected during the expand phase. */ + if (!TARGET_64BIT + && !TARGET_MIPS16 + && outer_code == MOD + && mode == DImode + && (exact_log2 (INTVAL (x)) > 0)) + { + *total = 0; + return true; + } + if (TARGET_MIPS16) { cost = mips16_constant_cost (outer_code, INTVAL (x)); @@ -5615,8 +5628,20 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code, } /* Fall through. */ - case SQRT: case MOD: + /* Modulo by power of two produces (at most) nine instructions. */ + if (CONST_INT_P (XEXP (x, 1)) + && exact_log2 (INTVAL (XEXP (x, 1))) > 0 + && !TARGET_64BIT + && !TARGET_MIPS16 + && mode == DImode) + { + *total = COSTS_N_INSNS (9); + return true; + } + /* Fall through. */ + + case SQRT: if (float_mode_p) { *total = mips_fp_div_cost (mode); @@ -26107,6 +26132,123 @@ mips_prune_insertions_deletions (struct edge_list* edge_list, sbitmap_free (ifcv_blocks); sbitmap_free (insertions); } + +/* Expand modulo by power of two of DImode values on 32-bit targets. */ + +bool +mips_expand_mod_pow2 (rtx target, rtx op1, rtx op2) +{ + HOST_WIDE_INT val, reg_width; + rtx out_low, out_high; + rtx in_low, in_high; + rtx at, temp; + rtx comp, cond_operands[4]; + + gcc_assert (GET_CODE (op2) == CONST_INT); + + val = INTVAL (op2); + + int logd = exact_log2 (val); + + if (logd <= 0) + return false; + + /* Extract lower and upper words of DImode source and destination. */ + out_low = mips_subword (target, 0); + out_high = mips_subword (target, 1); + + in_low = mips_subword (op1, 0); + in_high = mips_subword (op1, 1); + + at = gen_reg_rtx (SImode); + temp = gen_reg_rtx (SImode); + + reg_width = GET_MODE_BITSIZE (SImode); + + /* Divisor equals 2. */ + if (logd == 1) + { + mips_emit_binary (AND, at, in_low, const1_rtx); + mips_emit_binary (ASHIFT, temp, in_low, + gen_int_mode (reg_width - 1, SImode)); + mips_emit_binary (AND, temp, in_high, temp); + mips_emit_binary (ASHIFTRT, out_high, temp, + gen_int_mode (reg_width - 1, SImode)); + mips_emit_binary (IOR, out_low, out_high, at); + + return true; + } + /* Divisor fits into 32 bits. */ + else if (logd <= reg_width) + { + mips_emit_binary (ASHIFTRT, at, in_high, + gen_int_mode (reg_width - 1, SImode)); + + if (logd == reg_width) + mips_emit_move (out_low, in_low); + else if (ISA_HAS_EXT_INS || logd <= 16) + mips_emit_binary (AND, out_low, in_low, + gen_int_mode ((1 << logd) - 1, SImode)); + else + { + mips_emit_binary (ASHIFT, out_low, in_low, + gen_int_mode (reg_width - logd, SImode)); + mips_emit_binary (LSHIFTRT, out_low, out_low, + gen_int_mode (reg_width - logd, SImode)); + } + + comp = gen_rtx_EQ (VOIDmode, out_low, const0_rtx); + cond_operands[0] = at; + cond_operands[1] = comp; + cond_operands[2] = const0_rtx; + cond_operands[3] = at; + + mips_expand_conditional_move (cond_operands); + mips_emit_move (out_high, at); + if (logd < reg_width) + { + mips_emit_binary (ASHIFT, at, at, gen_int_mode (logd, SImode)); + mips_emit_binary (IOR, out_low, out_low, at); + } + + return true; + } + /* Divisor is wider than 32 bits. */ + else if (logd <= 2 * reg_width - 1) + { + mips_emit_binary (ASHIFTRT, at, in_high, + gen_int_mode (reg_width - 1, SImode)); + mips_emit_move (temp, in_low); + + if (ISA_HAS_EXT_INS || logd <= 16) + mips_emit_binary (AND, out_high, in_high, + gen_int_mode ((1 << (logd - reg_width)) - 1, SImode)); + else + { + mips_emit_binary (ASHIFT, out_high, in_high, + gen_int_mode (2 * reg_width - logd, SImode)); + mips_emit_binary (LSHIFTRT, out_high, out_high, + gen_int_mode (2 * reg_width - logd, SImode)); + } + mips_emit_move (out_low, temp); + mips_emit_binary (IOR, temp, temp, out_high); + + comp = gen_rtx_EQ (VOIDmode, temp, const0_rtx); + cond_operands[0] = at; + cond_operands[1] = comp; + cond_operands[2] = const0_rtx; + cond_operands[3] = at; + + mips_expand_conditional_move (cond_operands); + mips_emit_binary (ASHIFT, at, at, + gen_int_mode (logd - reg_width, SImode)); + mips_emit_binary (IOR, out_high, out_high, at); + + return true; + } + + return false; +} /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1243f20f344..0c93ce17ae4 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -821,6 +821,10 @@ ;; modes. (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) +;; This mode iterator is used in the same way as GPR, except that it allows +;; 64-bit patterns on 32-bit targets. +(define_mode_iterator GPR3 [SI DI]) + (define_mode_iterator MOVEP1 [SI SF]) (define_mode_iterator MOVEP2 [SI SF]) (define_mode_iterator JOIN_MODE [HI @@ -3098,7 +3102,31 @@ [(set_attr "type" "idiv3") (set_attr "mode" "")]) -(define_insn "mod3" +(define_expand "mod3" + [(set (match_operand:GPR3 0 "register_operand") + (any_mod:GPR3 (match_operand:GPR3 1 "register_operand") + (match_operand:GPR3 2 "nonmemory_operand")))] + "(TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6DIV) + || (!TARGET_64BIT && !TARGET_MIPS16 && mode == DImode)" +{ + /* In case of DImode signed modulo with power of 2 on 32-bit targets, call + the custom expander. */ + if ( == MOD + && !TARGET_64BIT + && !TARGET_MIPS16 + && GET_CODE (operands[2]) == CONST_INT) + { + if (mips_expand_mod_pow2 (operands[0], operands[1], operands[2])) + DONE; + FAIL; + } + /* Else, forbid the expand of DImode modulo on 32-bit targets. */ + else if ((!TARGET_64BIT && mode == DImode) + || GET_CODE (operands[2]) == CONST_INT) + FAIL; +}) + +(define_insn "*mod3" [(set (match_operand:GPR 0 "register_operand" "=&d") (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] @@ -3113,7 +3141,6 @@ } [(set_attr "type" "idiv3") (set_attr "mode" "")]) - ;; ;; .................... ;; diff --git a/gcc/testsuite/gcc.target/mips/mod-pow2.c b/gcc/testsuite/gcc.target/mips/mod-pow2.c new file mode 100644 index 00000000000..4fee299a777 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mod-pow2.c @@ -0,0 +1,176 @@ +/* { dg-do run } */ +/* { dg-options "-mabi=32 (REQUIRES_STDLIB)" } */ + +/* Test modulo by power of two expansion. */ +#include + +#define ARGPASTE(X, Y) X ## Y +#define ARGPASTE2(X) ARGPASTE (mod_, X) + +/* Create 64 distinct functions which calculate the modulo by power of two */ +#define MOD(LOG) \ + __attribute__((noinline)) long long ARGPASTE2 (__COUNTER__) (long long x) \ + { return x % (1LL << (LOG)); } +#define MOD_1(x) \ + MOD (x) \ + MOD (x + 1) +#define MOD_2(x) \ + MOD_1 (x) \ + MOD_1 (x + 2) +#define MOD_4(x) \ + MOD_2 (x) \ + MOD_2 (x + 4) +#define MOD_8(x) \ + MOD_4 (x) \ + MOD_4 (x + 8) +#define MOD_16(x) \ + MOD_8 (x) \ + MOD_8 (x + 16) +#define MOD_32(x) \ + MOD_16 (x) \ + MOD_16 (x + 32) + +MOD_32 (0) + +#define TEST_NUM_POS 0x7fffffffffffffff +#define TEST_NUM_NEG 0xffffffffffffffff + +/* Test the modulo by power of two with a positive number. */ +#define TEST_MOD_POS(LOG) \ + ARGPASTE2 (LOG) (TEST_NUM_POS) == (TEST_NUM_POS & ((1LL << (LOG)) - 1)) \ + ? (void) 0 : abort () + +/* Test the modulo by power of two with a negative number. */ +#define TEST_MOD_NEG(LOG) \ + ARGPASTE2 (LOG) (TEST_NUM_NEG) == -1LL ? (void) 0 : abort() + +int main() { + TEST_MOD_POS(1); + TEST_MOD_POS(2); + TEST_MOD_POS(3); + TEST_MOD_POS(4); + TEST_MOD_POS(5); + TEST_MOD_POS(6); + TEST_MOD_POS(7); + TEST_MOD_POS(8); + TEST_MOD_POS(9); + TEST_MOD_POS(10); + TEST_MOD_POS(11); + TEST_MOD_POS(12); + TEST_MOD_POS(13); + TEST_MOD_POS(14); + TEST_MOD_POS(15); + TEST_MOD_POS(16); + TEST_MOD_POS(17); + TEST_MOD_POS(18); + TEST_MOD_POS(19); + TEST_MOD_POS(20); + TEST_MOD_POS(21); + TEST_MOD_POS(22); + TEST_MOD_POS(23); + TEST_MOD_POS(24); + TEST_MOD_POS(25); + TEST_MOD_POS(26); + TEST_MOD_POS(27); + TEST_MOD_POS(28); + TEST_MOD_POS(29); + TEST_MOD_POS(30); + TEST_MOD_POS(31); + TEST_MOD_POS(32); + TEST_MOD_POS(33); + TEST_MOD_POS(34); + TEST_MOD_POS(35); + TEST_MOD_POS(36); + TEST_MOD_POS(37); + TEST_MOD_POS(38); + TEST_MOD_POS(39); + TEST_MOD_POS(40); + TEST_MOD_POS(41); + TEST_MOD_POS(42); + TEST_MOD_POS(43); + TEST_MOD_POS(44); + TEST_MOD_POS(45); + TEST_MOD_POS(46); + TEST_MOD_POS(47); + TEST_MOD_POS(48); + TEST_MOD_POS(49); + TEST_MOD_POS(50); + TEST_MOD_POS(51); + TEST_MOD_POS(52); + TEST_MOD_POS(53); + TEST_MOD_POS(54); + TEST_MOD_POS(55); + TEST_MOD_POS(56); + TEST_MOD_POS(57); + TEST_MOD_POS(58); + TEST_MOD_POS(59); + TEST_MOD_POS(60); + TEST_MOD_POS(61); + TEST_MOD_POS(62); + + TEST_MOD_NEG(1); + TEST_MOD_NEG(2); + TEST_MOD_NEG(3); + TEST_MOD_NEG(4); + TEST_MOD_NEG(5); + TEST_MOD_NEG(6); + TEST_MOD_NEG(7); + TEST_MOD_NEG(8); + TEST_MOD_NEG(9); + TEST_MOD_NEG(10); + TEST_MOD_NEG(11); + TEST_MOD_NEG(12); + TEST_MOD_NEG(13); + TEST_MOD_NEG(14); + TEST_MOD_NEG(15); + TEST_MOD_NEG(16); + TEST_MOD_NEG(17); + TEST_MOD_NEG(18); + TEST_MOD_NEG(19); + TEST_MOD_NEG(20); + TEST_MOD_NEG(21); + TEST_MOD_NEG(22); + TEST_MOD_NEG(23); + TEST_MOD_NEG(24); + TEST_MOD_NEG(25); + TEST_MOD_NEG(26); + TEST_MOD_NEG(27); + TEST_MOD_NEG(28); + TEST_MOD_NEG(29); + TEST_MOD_NEG(30); + TEST_MOD_NEG(31); + TEST_MOD_NEG(32); + TEST_MOD_NEG(33); + TEST_MOD_NEG(34); + TEST_MOD_NEG(35); + TEST_MOD_NEG(36); + TEST_MOD_NEG(37); + TEST_MOD_NEG(38); + TEST_MOD_NEG(39); + TEST_MOD_NEG(40); + TEST_MOD_NEG(41); + TEST_MOD_NEG(42); + TEST_MOD_NEG(43); + TEST_MOD_NEG(44); + TEST_MOD_NEG(45); + TEST_MOD_NEG(46); + TEST_MOD_NEG(47); + TEST_MOD_NEG(48); + TEST_MOD_NEG(49); + TEST_MOD_NEG(50); + TEST_MOD_NEG(51); + TEST_MOD_NEG(52); + TEST_MOD_NEG(53); + TEST_MOD_NEG(54); + TEST_MOD_NEG(55); + TEST_MOD_NEG(56); + TEST_MOD_NEG(57); + TEST_MOD_NEG(58); + TEST_MOD_NEG(59); + TEST_MOD_NEG(60); + TEST_MOD_NEG(61); + TEST_MOD_NEG(62); + TEST_MOD_NEG(63); + + exit (0); +} From patchwork Fri Jan 31 17:13:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105797 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 10B0D3858405 for ; Fri, 31 Jan 2025 18:14:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 10B0D3858405 Authentication-Results: sourceware.org; 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if (test) a = C; x ^= a; This reduces the number of necessary conditional moves on some targets (most notably MIPS). gcc/ * config/mips/mips.cc (mips_rtx_costs): Increase the cost of conditional moves which allow both operands to be registers on mips64r6. * ifcvt.cc (noce_try_synthesized_xor_ok): New function. Do not try the XOR/IOR conversion if the target has a conditional move which accepts two registers. (noce_try_synthesized_xor): New function. Discover the sequence of instructions which fit the description and expand them accordingly. gcc/testsuite/ * gcc.target/mips/cond_xor.c: New test. * gcc.target/mips/cond_xor1.c: New test. * gcc.target/mips/cond_xor2.c: New test. Skip -Os. Cherry-picked 5409eee7c24688cd73df92d83a6844a041545c2f, 31d6d46912ad3cbb56c6fc251418c2624b4bb07f and ff607fa78b23b8e1d753a6e836419e3fe46e3045 from https://github.com/MIPS/gcc Signed-off-by: Mihailo Stojanovic Signed-off-by: Faraz Shahbazker Signed-off-by: Chao-ying Fu Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 18 ++- gcc/ifcvt.cc | 135 ++++++++++++++++++++++ gcc/testsuite/gcc.target/mips/cond_xor.c | 15 +++ gcc/testsuite/gcc.target/mips/cond_xor1.c | 15 +++ gcc/testsuite/gcc.target/mips/cond_xor2.c | 15 +++ 5 files changed, 194 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/cond_xor.c create mode 100644 gcc/testsuite/gcc.target/mips/cond_xor1.c create mode 100644 gcc/testsuite/gcc.target/mips/cond_xor2.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 19d428e6ed6..63b7bdd255c 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -5784,10 +5784,20 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code, return false; case IF_THEN_ELSE: - if (reg_or_0_operand (XEXP (x, 1), VOIDmode) - || reg_or_0_operand (XEXP (x, 2), VOIDmode)) - *total = 0; - return false; + if (reg_or_0_operand (XEXP (x, 1), VOIDmode) + || reg_or_0_operand (XEXP (x, 2), VOIDmode)) + *total = 0; + if (outer_code == SET) + { + /* Conditional moves on r6 only allow one parameter to be a register + (the other parameter is zero). Increase the cost of conditional + moves which allow both parameters to be registers. */ + if (mips_isa_rev == 6 + && register_operand (XEXP (x, 1), VOIDmode) + && register_operand (XEXP (x, 2), VOIDmode)) + *total = 1; + } + return false; default: return false; diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 74f13a637b2..297ccd470dc 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -1962,6 +1962,137 @@ noce_try_cmove (struct noce_if_info *if_info) return false; } +/* If the target has a conditional move which accepts two registers, do not + try synthesized conditional XOR/IOR, as it will not yield any benefits. */ + +static bool +noce_try_synthesized_xor_ok (struct noce_if_info *if_info) +{ + rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); + + rtx if_then_else = gen_rtx_IF_THEN_ELSE (word_mode, + if_info->cond, + const0_rtx, if_info->x); + + rtx if_then_else_2 = gen_rtx_IF_THEN_ELSE (word_mode, + if_info->cond, + testreg, if_info->x); + + return rtx_cost (if_then_else_2, word_mode, SET, 1, true) + > rtx_cost (if_then_else, word_mode, SET, 1, true); +} + +/* Expand "if (test) x ^= C;" as + + a = 0; + if (test) a = C; + x ^= a; + + This lowers the number of necessary conditional moves on some targets. + + We allow for maximum of three instructions in the then block. + First one loads the constant into a register. Second one is an actual + XOR/IOR instruction. Third one is a zero or sign extend. */ + +static bool +noce_try_synthesized_xor (struct noce_if_info *if_info) +{ + enum rtx_code code = GET_CODE (if_info->cond); + + if (code != NE && code != EQ) + return FALSE; + + /* Fail if there is an else block. */ + if (if_info->else_bb) + return FALSE; + + /* We allow for the final instruction in the basic block to be sign or + zero extend. */ + rtx a = if_info->a; + rtx_insn *insn_a = if_info->insn_a; + if ((GET_CODE (a) == ZERO_EXTEND + || GET_CODE (a) == SIGN_EXTEND) + && single_set (prev_nonnote_nondebug_insn (insn_a))) + { + a = SET_SRC (single_set (prev_nonnote_nondebug_insn (insn_a))); + insn_a = prev_nonnote_nondebug_insn (insn_a); + } + + /* Check that the operation is indeed XOR or IOR. Also check that we don't + have any more instructions in the then block. */ + enum rtx_code opcode = GET_CODE (a); + if (opcode != XOR + && opcode != IOR) + return FALSE; + + rtx xor_src = XEXP (a, 0); + rtx xor_const = XEXP (a, 1); + xor_src = GET_CODE (xor_src) == SUBREG ? SUBREG_REG (xor_src) : xor_src; + + /* Check if the instruction prior to XOR or IOR loads the constant into + the register. */ + rtx_insn *prev = prev_nonnote_nondebug_insn (insn_a); + if (BLOCK_FOR_INSN (insn_a) == BLOCK_FOR_INSN (prev)) + { + if (GET_CODE (xor_const) != REG) + return FALSE; + + a = single_set (prev); + if (a != NULL_RTX + && rtx_equal_p (SET_DEST (a), xor_const) + && GET_CODE (SET_SRC (a)) == CONST_INT) + xor_const = SET_SRC (a); + else + return FALSE; + + /* This must be the first instruction of the basic block. */ + if (BLOCK_FOR_INSN (prev) + == BLOCK_FOR_INSN (prev_nonnote_nondebug_insn (prev))) + return FALSE; + } + else if (GET_CODE (xor_const) != CONST_INT) + return FALSE; + + if (!rtx_equal_p (xor_src, if_info->x)) + return FALSE; + + start_sequence (); + + machine_mode mode = GET_MODE (if_info->x); + rtx const_reg = gen_reg_rtx (mode); + rtx target = gen_reg_rtx (mode); + + noce_emit_move_insn (const_reg, xor_const); + target = noce_emit_cmove (if_info, target, code, + XEXP (if_info->cond, 0), + XEXP (if_info->cond, 1), + const_reg, const0_rtx); + if (!target) + { + end_sequence (); + return FALSE; + } + + target = expand_simple_binop (GET_MODE (if_info->x), opcode, + if_info->x, target, if_info->x, + 0, OPTAB_WIDEN); + if (!target) + { + end_sequence (); + return FALSE; + } + + rtx_insn* seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return FALSE; + + emit_insn_before_setloc (seq, if_info->jump, + INSN_LOCATION (if_info->insn_a)); + if_info->transform_name = "noce_try_synthesized_xor"; + + return TRUE; +} + /* Return true if X contains a conditional code mode rtx. */ static bool @@ -4246,6 +4377,10 @@ noce_process_if_block (struct noce_if_info *if_info) if (HAVE_conditional_move && noce_try_cond_zero_arith (if_info)) goto success; + if (HAVE_conditional_move + && noce_try_synthesized_xor_ok (if_info) + && noce_try_synthesized_xor (if_info)) + goto success; if (HAVE_conditional_move && noce_try_cmove_arith (if_info)) goto success; diff --git a/gcc/testsuite/gcc.target/mips/cond_xor.c b/gcc/testsuite/gcc.target/mips/cond_xor.c new file mode 100644 index 00000000000..c0635c9dc53 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/cond_xor.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=64 -march=mips64r6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } } */ + +NOMIPS16 unsigned int +foo (unsigned int x, unsigned int y) +{ + if (x == 1) + y ^= 0xabcd; + + return y; +} + +/* { dg-final { scan-assembler-times "seleqz" 1 } } */ +/* { dg-final { scan-assembler-not "selnez" } } */ diff --git a/gcc/testsuite/gcc.target/mips/cond_xor1.c b/gcc/testsuite/gcc.target/mips/cond_xor1.c new file mode 100644 index 00000000000..6a09465cecd --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/cond_xor1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=64 -march=mips64r6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } } */ + +NOMIPS16 unsigned int +foo (unsigned int x, unsigned int y, unsigned z) +{ + if (x == z) + y ^= 0xabcd; + + return y; +} + +/* { dg-final { scan-assembler-times "seleqz" 1 } } */ +/* { dg-final { scan-assembler-not "selnez" } } */ diff --git a/gcc/testsuite/gcc.target/mips/cond_xor2.c b/gcc/testsuite/gcc.target/mips/cond_xor2.c new file mode 100644 index 00000000000..a64cc189116 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/cond_xor2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=64 -march=mips64r6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os" } } */ + +NOMIPS16 unsigned int +foo (unsigned int x, unsigned int y, unsigned int z) +{ + if (x == 1) + y ^= z; + + return y; +} + +/* { dg-final { scan-assembler-times "seleqz" 1 } } */ +/* { dg-final { scan-assembler-times "selnez" 1 } } */ From patchwork Fri Jan 31 17:13:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105782 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6F71A385772E for ; Fri, 31 Jan 2025 18:01:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6F71A385772E Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=kGbLdbrS X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR02-VI1-obe.outbound.protection.outlook.com (mail-vi1eur02on20701.outbound.protection.outlook.com [IPv6:2a01:111:f403:2607::701]) by sourceware.org (Postfix) with ESMTPS id 9274B3857C78 for ; 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Fri, 31 Jan 2025 17:14:17 +0000 From: Aleksandar Rakic To: "gcc-patches@gcc.gnu.org" CC: Djordje Todorovic , "cfu@mips.com" , dragan.mladjenovic , Faraz Shahbazker , Aleksandar Rakic Subject: [PATCH 58/61] Add EHB after last load if branch within 16 inst. Thread-Topic: [PATCH 58/61] Add EHB after last load if branch within 16 inst. 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If any of those two options are active, it will add an EHB after the last load instruction in sequence if there is a branch within 16 instructions following it. Options have no effect on pre-R6 or compressed ISA targets. Inline assembly is treated as safe. It is up to user to insert required EHB instruction after the loads and before the branches/jumps. gcc/ * config/mips/mips.cc (MIPS_JR): Define as JR.HB for TARGET_FIX_I6500. (mips_idiv_insns): Account for extra ehb instruction for TARGET_FIX_I6500. (mips_adjust_insn_length): Likewise for long pic jumps. (mips_output_conditional_branch): Output ehb in long pic jumps for TARGET_FIX_I6500. (mips_process_sync_loop): Output ehb before the first branch in sequence for TARGET_FIX_I6500. (mips_output_division): Likewise for -mdivide-breaks. (mips_msa_output_division): Likewise. (mips_avoid_hazard): Add new state to track loads and handle ehb insertion. (mips_reorg_process_insns): Setup new state for calling mips_avoid_hazard. (mips_set_compression_mode): Disable the TARGET_FIX_I6500 for compressed ISA. (mips_option_override): Allow TARGET_FIX_i6400 and TARGET_FIX_I6500 only for R6 ISA. (mips_trampoline_init): Do not use compact branches with TARGET_FIX_I6500. * config/mips/mips.md (can_delay): Set to "no" for load instruction when TARGET_FIX_I6500 is enabled. (jump_pic) : Output ehb for TARGET_FIX_I6500. * config/mips/mips.opt (-mfix-i6400): New option. (-mfix-i6500): Likewise. * doc/invoke.texi (-mfix-i6400): Document. (-mfix-i6500): Likewise. gcc/testsuite/ * gcc.target/mips/fix-i6500.c: New file. Cherry-picked 784408360ef462711181e5cb59f1b0ff575f92ca from https://github.com/MIPS/gcc Signed-off-by: Dragan Mladjenovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.cc | 81 ++++++++++++++++++++--- gcc/config/mips/mips.md | 8 ++- gcc/config/mips/mips.opt | 8 +++ gcc/doc/invoke.texi | 8 +++ gcc/testsuite/gcc.target/mips/fix-i6500.c | 18 +++++ 5 files changed, 112 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/fix-i6500.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 63b7bdd255c..b09794eab15 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -179,10 +179,13 @@ static int *consumer_luid = NULL; ((0xf << 26) | ((DEST) << 16) | (VALUE)) /* Return the opcode to jump to register DEST. When the JR opcode is not - available use JALR $0, DEST. */ + available use JALR $0, DEST. + Use hazard barrier for TARGET_FIX_I6500. */ #define MIPS_JR(DEST) \ - (TARGET_CB_ALWAYS ? ((0x1b << 27) | ((DEST) << 16)) \ - : (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9))) + (TARGET_CB_ALWAYS && !TARGET_FIX_I6500 \ + ? ((0x1b << 27) | ((DEST) << 16)) \ + : (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9) \ + | (TARGET_FIX_I6500 ? (0x1 << 10) : 0x0))) /* Return the opcode for: @@ -3993,7 +3996,7 @@ mips_idiv_insns (machine_mode mode) if (GENERATE_DIVIDE_TRAPS && !MSA_SUPPORTED_MODE_P (mode)) count++; else - count += 2; + count += !TARGET_FIX_I6500 ? 2 : 3; } if (TARGET_FIX_R4000 || TARGET_FIX_R4400) @@ -15601,6 +15604,9 @@ mips_adjust_insn_length (rtx_insn *insn, int length) /* Add the length of an indirect jump, ignoring the delay slot. */ length += TARGET_COMPRESSION ? 2 : 4; + + if (TARGET_FIX_I6500 && !TARGET_ABSOLUTE_JUMPS) + length += 4; } /* A unconditional jump has an unfilled delay slot if it is not part @@ -15769,6 +15775,10 @@ mips_output_conditional_branch (rtx_insn *insn, rtx *operands, else { mips_output_load_label (taken); + + if (TARGET_FIX_I6500) + output_asm_insn ("ehb", 0); + if (TARGET_CB_MAYBE) output_asm_insn ("jrc\t%@%]", 0); else @@ -16149,6 +16159,10 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands) at, oldval, inclusive_mask, NULL); tmp1 = at; } + + if (TARGET_FIX_I6500) + mips_multi_add_insn ("ehb", NULL); + if (TARGET_CB_NEVER) mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL); @@ -16413,6 +16427,9 @@ mips_output_division (const char *division, rtx *operands) } else { + if (TARGET_FIX_I6500) + output_asm_insn ("ehb", NULL); + if (flag_delayed_branch) { output_asm_insn ("%(bne\t%2,%.,1f", operands); @@ -16441,6 +16458,9 @@ mips_msa_output_division (const char *division, rtx *operands) s = division; if (TARGET_CHECK_ZERO_DIV) { + if (TARGET_FIX_I6500) + output_asm_insn ("ehb", NULL); + output_asm_insn ("%(bnz.%v0\t%w2,1f", operands); output_asm_insn (s, operands); s = "break\t7%)\n1:"; @@ -21095,7 +21115,8 @@ mips_classify_branch_p6600 (rtx_insn *insn) static void mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, - rtx *delayed_reg, rtx lo_reg, bool *fs_delay) + rtx *delayed_reg, rtx lo_reg, bool *fs_delay, + rtx_insn **last_load, int *load_delay) { rtx pattern, set; int nops, ninsns; @@ -21113,6 +21134,15 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, if (get_attr_length (insn) == 0) return; + if (TARGET_FIX_I6500 + && (CALL_P (insn) || JUMP_P (insn)) + && (*last_load != 0 && *load_delay > 0)) + { + emit_insn_after (gen_mips_ehb (), *last_load); + *last_load = 0; + *load_delay = 0; + } + /* Work out how many nops are needed. Note that we only care about registers that are explicitly mentioned in the instruction's pattern. It doesn't matter that calls use the argument registers or that they @@ -21170,6 +21200,10 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, *hilo_delay += ninsns; *delayed_reg = 0; *fs_delay = false; + + if (*last_load && *load_delay > 0) + *load_delay -= ninsns; + if (INSN_CODE (insn) >= 0) switch (get_attr_hazard (insn)) { @@ -21200,6 +21234,21 @@ mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, *delayed_reg = SET_DEST (set); break; } + + if (TARGET_FIX_I6500 && INSN_CODE (insn) >= 0) + switch (get_attr_type (insn)) + { + case TYPE_LOAD: + case TYPE_FPLOAD: + case TYPE_FPIDXLOAD: + case TYPE_SIMD_LOAD: + gcc_assert (!insn->deleted ()); + *last_load = insn; + *load_delay = 16; + break; + default: + break; + } } /* Emit a speculation barrier. @@ -21246,9 +21295,9 @@ mips_break_sequence (rtx_insn *insn) static void mips_reorg_process_insns (void) { - rtx_insn *insn, *last_insn, *subinsn, *next_insn; + rtx_insn *insn, *last_insn, *subinsn, *next_insn, *last_load; rtx lo_reg, delayed_reg; - int hilo_delay; + int hilo_delay, load_delay; bool fs_delay; /* Force all instructions to be split into their final form. */ @@ -21315,7 +21364,9 @@ mips_reorg_process_insns (void) } last_insn = 0; + last_load = 0; hilo_delay = 2; + load_delay = 0; delayed_reg = 0; lo_reg = gen_rtx_REG (SImode, LO_REGNUM); fs_delay = false; @@ -21404,7 +21455,8 @@ mips_reorg_process_insns (void) INSN_CODE (subinsn) = CODE_FOR_nop; } mips_avoid_hazard (last_insn, subinsn, &hilo_delay, - &delayed_reg, lo_reg, &fs_delay); + &delayed_reg, lo_reg, &fs_delay, + &last_load, &load_delay); } last_insn = insn; } @@ -21425,7 +21477,8 @@ mips_reorg_process_insns (void) else { mips_avoid_hazard (last_insn, insn, &hilo_delay, - &delayed_reg, lo_reg, &fs_delay); + &delayed_reg, lo_reg, &fs_delay, + &last_load, &load_delay); /* When a compact branch introduces a forbidden slot hazard and the next useful instruction is a SEQUENCE of a jump and a non-nop instruction in the delay slot, remove the @@ -21919,6 +21972,10 @@ mips_set_compression_mode (unsigned int compression_mode) target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS); target_flags |= compression_mode; + if (compression_mode && (TARGET_FIX_I6500 || TARGET_FIX_I6400)) + error ("-mfix-i6500 (-mfix-i6400) not compatible with " + "-mmips16 or -mmicromips"); + if (compression_mode & MASK_MIPS16) { /* Switch to MIPS16 mode. */ @@ -22526,6 +22583,10 @@ mips_option_override (void) SUBTARGET_OVERRIDE_OPTIONS; #endif + if (mips_isa_rev < 6 && (TARGET_FIX_I6500 || TARGET_FIX_I6400)) + error ("-mfix-i6500 (-mfix-i6400) not compatible with " + "pre-R6 target: %qs", mips_arch_info->name); + /* MIPS16 and microMIPS cannot coexist. */ if (TARGET_MICROMIPS && TARGET_MIPS16) error ("unsupported combination: %s", "-mips16 -mmicromips"); @@ -24180,7 +24241,7 @@ mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) place the instruction that was in the delay slot before the JRC instruction. */ - if (TARGET_CB_ALWAYS) + if (TARGET_CB_ALWAYS && !TARGET_FIX_I6500) { rtx temp; temp = trampoline[i-2]; diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 0c93ce17ae4..52abb9c1119 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -784,7 +784,9 @@ (define_attr "can_delay" "no,yes" (if_then_else (and (eq_attr "type" "!branch,call,jump,simd_branch") (eq_attr "hazard" "none") - (match_test "get_attr_insn_count (insn) == 1")) + (match_test "get_attr_insn_count (insn) == 1") + (ior (match_test "!TARGET_FIX_I6500") + (eq_attr "type" "!load,fpload,fpidxload,simd_load"))) (const_string "yes") (const_string "no"))) @@ -6716,6 +6718,10 @@ else { mips_output_load_label (operands[0]); + + if (TARGET_FIX_I6500) + output_asm_insn ("ehb", 0); + if (TARGET_CB_MAYBE) return "%*jr%:\t%@%]"; else diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 804f4fecbc9..36c9d567a24 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -218,6 +218,14 @@ mfix4300 Target Var(TARGET_4300_MUL_FIX) Work around an early 4300 hardware bug. +mfix-i6400 +Target Var(TARGET_FIX_I6400) Init(0) +Work around certain I6400 errata. + +mfix-i6500 +Target Var(TARGET_FIX_I6500) Init(0) +Work around certain I6500 errata. + mfp-exceptions Target Var(TARGET_FP_EXCEPTIONS) Init(1) FP exceptions are enabled. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b2e11a7fd0d..63d97c73efb 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -29177,6 +29177,14 @@ Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 ``F1'' and ``F2'' floating-point errata.) +@opindex mfix-i6500 +@item -mfix-i6500 +@itemx -mno-fix-i6500 +@itemx -mfix-i6400 +@itemx -mno-fix-i6400 +Work around certain I6500/I6400 core errata. +(These flags currently work around the ``E75'' errata for I6500.) + @opindex mr10k-cache-barrier @item -mr10k-cache-barrier=@var{setting} Specify whether GCC should insert cache barriers to avoid the diff --git a/gcc/testsuite/gcc.target/mips/fix-i6500.c b/gcc/testsuite/gcc.target/mips/fix-i6500.c new file mode 100644 index 00000000000..07488a6a83e --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/fix-i6500.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-micromips -mno-mips16 (HAS_LSA)" } */ +/* { dg-additional-options "-mfix-i6500" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int +foo (int ***p) +{ + return ***p; +} + +float +bar (float *p) +{ + return *p; +} + +/* { dg-final { scan-assembler-times "ehb" 2 } } */ From patchwork Fri Jan 31 17:13:50 2025 Content-Type: text/plain; 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Fix "ASan runtime does not come first in initial library list; you should either link runtime to your application or manually preload it with LD_PRELOAD." Disable SANITIZER_INTERCEPT_GLOB. Resolve libsanitizer build issues for uclibc. Cherry-picked 94e7806991cf3af0dbaf6147d0010480a7760cc8, 52849bd97f29b6ad17d493ad383d8833473ee6a7, 0dcb2d0c3cc4d7118bd211a24e01d9a991dd72d2, 127b4d28d9bfba10e7006decdcd0f24665e5d5af, 5cd320103ba1248c6925b9843f1139e60d283bed and af4425414cef0155d6f00ad118417f4908eae756 from https://github.com/MIPS/gcc Signed-off-by: Jean Lee Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- libsanitizer/asan/asan_descriptions.cpp | 5 ++ libsanitizer/asan/asan_linux.cpp | 2 +- .../interception/interception_linux.cpp | 6 ++- .../interception/interception_linux.h | 6 ++- .../sanitizer_common/sanitizer_common.cpp | 10 +++- .../sanitizer_common/sanitizer_linux.cpp | 6 ++- .../sanitizer_common/sanitizer_platform.h | 9 ++++ .../sanitizer_platform_interceptors.h | 14 ++++-- .../sanitizer_platform_limits_posix.cpp | 46 +++++++++++++++---- .../sanitizer_platform_limits_posix.h | 9 +++- .../sanitizer_unwind_linux_libcdep.cpp | 2 + 11 files changed, 93 insertions(+), 22 deletions(-) diff --git a/libsanitizer/asan/asan_descriptions.cpp b/libsanitizer/asan/asan_descriptions.cpp index caec79313e2..0b8180bbf0f 100644 --- a/libsanitizer/asan/asan_descriptions.cpp +++ b/libsanitizer/asan/asan_descriptions.cpp @@ -175,10 +175,15 @@ bool GetHeapAddressInformation(uptr addr, uptr access_size, } static StackTrace GetStackTraceFromId(u32 id) { +#if !(defined(__mips__) && SANITIZER_UCLIBC) CHECK(id); StackTrace res = StackDepotGet(id); CHECK(res.trace); return res; +#else + StackTrace res; + return res; +#endif } bool DescribeAddressIfHeap(uptr addr, uptr access_size) { diff --git a/libsanitizer/asan/asan_linux.cpp b/libsanitizer/asan/asan_linux.cpp index 4cabca388ca..abcfb2467c9 100644 --- a/libsanitizer/asan/asan_linux.cpp +++ b/libsanitizer/asan/asan_linux.cpp @@ -107,7 +107,7 @@ void FlushUnneededASanShadowMemory(uptr p, uptr size) { ReleaseMemoryPagesToOS(MemToShadow(p), MemToShadow(p + size)); } -# if SANITIZER_ANDROID +# if SANITIZER_ANDROID || SANITIZER_UCLIBC // FIXME: should we do anything for Android? void AsanCheckDynamicRTPrereqs() {} void AsanCheckIncompatibleRT() {} diff --git a/libsanitizer/interception/interception_linux.cpp b/libsanitizer/interception/interception_linux.cpp index ef8136eb4fc..ed8bd3a80b9 100644 --- a/libsanitizer/interception/interception_linux.cpp +++ b/libsanitizer/interception/interception_linux.cpp @@ -64,7 +64,8 @@ bool InterceptFunction(const char *name, uptr *ptr_to_real, uptr func, } // dlvsym is a GNU extension supported by some other platforms. -#if SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD +#if (SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD) && \ + !SANITIZER_UCLIBC static void *GetFuncAddr(const char *name, const char *ver) { return dlvsym(RTLD_NEXT, name, ver); } @@ -75,7 +76,8 @@ bool InterceptFunction(const char *name, const char *ver, uptr *ptr_to_real, *ptr_to_real = (uptr)addr; return addr && (func == trampoline); } -# endif // SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD +# endif // (SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD) && + // !SANITIZER_UCLIBC } // namespace __interception diff --git a/libsanitizer/interception/interception_linux.h b/libsanitizer/interception/interception_linux.h index 2e01ff44578..897ec677350 100644 --- a/libsanitizer/interception/interception_linux.h +++ b/libsanitizer/interception/interception_linux.h @@ -38,7 +38,8 @@ bool InterceptFunction(const char *name, const char *ver, uptr *ptr_to_real, (::__interception::uptr) &TRAMPOLINE(func)) // dlvsym is a GNU extension supported by some other platforms. -#if SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD +#if (SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD) && \ + !SANITIZER_UCLIBC #define INTERCEPT_FUNCTION_VER_LINUX_OR_FREEBSD(func, symver) \ ::__interception::InterceptFunction( \ #func, symver, \ @@ -48,7 +49,8 @@ bool InterceptFunction(const char *name, const char *ver, uptr *ptr_to_real, #else #define INTERCEPT_FUNCTION_VER_LINUX_OR_FREEBSD(func, symver) \ INTERCEPT_FUNCTION_LINUX_OR_FREEBSD(func) -#endif // SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD +#endif // (SANITIZER_GLIBC || SANITIZER_FREEBSD || SANITIZER_NETBSD) && + // !SANITIZER_UCLIBC #endif // INTERCEPTION_LINUX_H #endif // SANITIZER_LINUX || SANITIZER_FREEBSD || SANITIZER_NETBSD || diff --git a/libsanitizer/sanitizer_common/sanitizer_common.cpp b/libsanitizer/sanitizer_common/sanitizer_common.cpp index 6cd69a53093..812102028ad 100644 --- a/libsanitizer/sanitizer_common/sanitizer_common.cpp +++ b/libsanitizer/sanitizer_common/sanitizer_common.cpp @@ -384,7 +384,15 @@ void internal_sleep(unsigned seconds) { void SleepForSeconds(unsigned seconds) { internal_usleep((u64)seconds * 1000 * 1000); } -void SleepForMillis(unsigned millis) { internal_usleep((u64)millis * 1000); } +void SleepForMillis (unsigned millis) +{ + #if SANITIZER_UCLIBC + struct timespec tv = {0, millis * 1000000}; + nanosleep (&tv, NULL); + #else + internal_usleep ((u64)millis * 1000); + #endif +} void WaitForDebugger(unsigned seconds, const char *label) { if (seconds) { diff --git a/libsanitizer/sanitizer_common/sanitizer_linux.cpp b/libsanitizer/sanitizer_common/sanitizer_linux.cpp index 8b1850f8501..5b326cd4e53 100644 --- a/libsanitizer/sanitizer_common/sanitizer_linux.cpp +++ b/libsanitizer/sanitizer_common/sanitizer_linux.cpp @@ -71,7 +71,9 @@ # include # include # include -# include +# if !SANITIZER_UCLIBC +# include +# endif # include # if SANITIZER_LINUX @@ -1215,6 +1217,8 @@ uptr GetPageSize() { return (uptr)pz; # elif SANITIZER_USE_GETAUXVAL return getauxval(AT_PAGESZ); +# elif defined(__mips__) && SANITIZER_UCLIBC + return 4096; # else return sysconf(_SC_PAGESIZE); // EXEC_PAGESIZE may not be trustworthy. # endif diff --git a/libsanitizer/sanitizer_common/sanitizer_platform.h b/libsanitizer/sanitizer_common/sanitizer_platform.h index 57966403c92..fd3e8543f91 100644 --- a/libsanitizer/sanitizer_common/sanitizer_platform.h +++ b/libsanitizer/sanitizer_common/sanitizer_platform.h @@ -140,6 +140,15 @@ (SANITIZER_FREEBSD || SANITIZER_LINUX || SANITIZER_APPLE || \ SANITIZER_NETBSD || SANITIZER_SOLARIS) +#include //for uclibc + +#if defined(__UCLIBC__) +# define SANITIZER_UCLIBC 1 +#else +# define SANITIZER_UCLIBC 0 +#endif + + #if __LP64__ || defined(_WIN64) # define SANITIZER_WORDSIZE 64 #else diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_interceptors.h b/libsanitizer/sanitizer_common/sanitizer_platform_interceptors.h index 3fd6b595ef1..48f28729498 100644 --- a/libsanitizer/sanitizer_common/sanitizer_platform_interceptors.h +++ b/libsanitizer/sanitizer_common/sanitizer_platform_interceptors.h @@ -58,6 +58,12 @@ #define SI_ANDROID 0 #endif +#if SANITIZER_LINUX && !SANITIZER_UCLIBC +# define SI_LINUX_NOT_UCLIBC 1 +#else +# define SI_LINUX_NOT_UCLIBC 0 +#endif + #if SANITIZER_FREEBSD #define SI_FREEBSD 1 #else @@ -258,8 +264,9 @@ SANITIZER_WEAK_IMPORT void *aligned_alloc(__sanitizer::usize __alignment, (SI_LINUX || SI_FREEBSD || SI_NETBSD) #define SANITIZER_INTERCEPT_GETITIMER SI_POSIX #define SANITIZER_INTERCEPT_TIME SI_POSIX -#define SANITIZER_INTERCEPT_GLOB (SI_GLIBC || SI_SOLARIS) -#define SANITIZER_INTERCEPT_GLOB64 SI_GLIBC +#define SANITIZER_INTERCEPT_GLOB \ + ((SI_GLIBC && SI_LINUX_NOT_UCLIBC) || SI_SOLARIS) +#define SANITIZER_INTERCEPT_GLOB64 (SI_GLIBC && SI_LINUX_NOT_UCLIBC) #define SANITIZER_INTERCEPT___B64_TO SI_LINUX_NOT_ANDROID #define SANITIZER_INTERCEPT_DN_COMP_EXPAND SI_LINUX_NOT_ANDROID #define SANITIZER_INTERCEPT_POSIX_SPAWN SI_POSIX @@ -439,7 +446,8 @@ SANITIZER_WEAK_IMPORT void *aligned_alloc(__sanitizer::usize __alignment, #define SANITIZER_INTERCEPT_GETXATTR SI_LINUX #define SANITIZER_INTERCEPT_GETRESID SI_LINUX #define SANITIZER_INTERCEPT_GETIFADDRS \ - (SI_FREEBSD || SI_NETBSD || SI_LINUX_NOT_ANDROID || SI_MAC || SI_SOLARIS) + (SI_FREEBSD || SI_NETBSD || (SI_LINUX_NOT_ANDROID && SI_LINUX_NOT_UCLIBC) \ + || SI_MAC || SI_SOLARIS) #define SANITIZER_INTERCEPT_IF_INDEXTONAME \ (SI_FREEBSD || SI_NETBSD || SI_LINUX_NOT_ANDROID || SI_MAC || SI_SOLARIS) #define SANITIZER_INTERCEPT_CAPGET SI_LINUX_NOT_ANDROID diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp index c87d5ef42c9..2744172cb82 100644 --- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp +++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp @@ -35,7 +35,9 @@ #include #include #include +#if !SANITIZER_UCLIBC #include +#endif #include #include #include @@ -62,15 +64,19 @@ #if !SANITIZER_ANDROID #include +#if !SANITIZER_UCLIBC #include #include #endif +#endif #if SANITIZER_LINUX #include #include #include +#if !SANITIZER_UCLIBC //for redefine #include +#endif #include #include #include @@ -92,7 +98,9 @@ #endif #if SANITIZER_LINUX -# include +# if !SANITIZER_UCLIBC +# include +# endif # include # if defined(__mips64) || defined(__aarch64__) || defined(__arm__) || \ defined(__hexagon__) || defined(__loongarch__) || SANITIZER_RISCV64 || \ @@ -109,7 +117,7 @@ typedef struct user_fpregs elf_fpregset_t; # include #endif -#if !SANITIZER_ANDROID +#if !SANITIZER_ANDROID && !SANITIZER_UCLIBC #include #include #include @@ -122,7 +130,9 @@ typedef struct user_fpregs elf_fpregset_t; # include # include # include -# include +# if !SANITIZER_UCLIBC +# include +# endif # include # if HAVE_RPC_XDR_H # include @@ -200,12 +210,16 @@ namespace __sanitizer { unsigned timeval_sz = sizeof(timeval); unsigned uid_t_sz = sizeof(uid_t); unsigned gid_t_sz = sizeof(gid_t); + #if !SANITIZER_UCLIBC unsigned mbstate_t_sz = sizeof(mbstate_t); + #endif unsigned sigset_t_sz = sizeof(sigset_t); unsigned struct_timezone_sz = sizeof(struct timezone); unsigned struct_tms_sz = sizeof(struct tms); unsigned struct_sigevent_sz = sizeof(struct sigevent); + #if !SANITIZER_UCLIBC unsigned struct_sched_param_sz = sizeof(struct sched_param); + #endif unsigned struct_regex_sz = sizeof(regex_t); unsigned struct_regmatch_sz = sizeof(regmatch_t); @@ -271,7 +285,9 @@ namespace __sanitizer { #if SANITIZER_LINUX unsigned struct_rlimit_sz = sizeof(struct rlimit); unsigned struct_timespec_sz = sizeof(struct timespec); + #if !SANITIZER_UCLIBC unsigned struct_utimbuf_sz = sizeof(struct utimbuf); + #endif unsigned struct_itimerspec_sz = sizeof(struct itimerspec); #endif // SANITIZER_LINUX @@ -327,7 +343,7 @@ namespace __sanitizer { #if !SANITIZER_APPLE && !SANITIZER_FREEBSD unsigned struct_utmp_sz = sizeof(struct utmp); #endif -#if !SANITIZER_ANDROID +#if !SANITIZER_ANDROID && !SANITIZER_UCLIBC unsigned struct_utmpx_sz = sizeof(struct utmpx); #endif @@ -351,7 +367,7 @@ unsigned struct_ElfW_Phdr_sz = sizeof(ElfW(Phdr)); unsigned struct_ElfW_Phdr_sz = sizeof(Elf_Phdr); #endif -#if SANITIZER_GLIBC +#if SANITIZER_GLIBC && !SANITIZER_UCLIBC int glob_nomatch = GLOB_NOMATCH; int glob_altdirfunc = GLOB_ALTDIRFUNC; #endif @@ -525,7 +541,9 @@ unsigned struct_ElfW_Phdr_sz = sizeof(Elf_Phdr); unsigned struct_kbkeycode_sz = sizeof(struct kbkeycode); unsigned struct_kbsentry_sz = sizeof(struct kbsentry); unsigned struct_mtconfiginfo_sz = sizeof(struct mtconfiginfo); +#if !SANITIZER_UCLIBC unsigned struct_nr_parms_struct_sz = sizeof(struct nr_parms_struct); +#endif unsigned struct_scc_modem_sz = sizeof(struct scc_modem); unsigned struct_scc_stat_sz = sizeof(struct scc_stat); unsigned struct_serial_multiport_struct_sz @@ -894,7 +912,11 @@ unsigned struct_ElfW_Phdr_sz = sizeof(Elf_Phdr); unsigned IOCTL_EQL_SETSLAVECFG = EQL_SETSLAVECFG; #if EV_VERSION > (0x010000) unsigned IOCTL_EVIOCGKEYCODE_V2 = EVIOCGKEYCODE_V2; +#if !SANITIZER_UCLIBC unsigned IOCTL_EVIOCGPROP = EVIOCGPROP(0); +#else + unsigned IOCTL_EVIOCGPROP = IOCTL_NOT_PRESENT; +#endif unsigned IOCTL_EVIOCSKEYCODE_V2 = EVIOCSKEYCODE_V2; #else unsigned IOCTL_EVIOCGKEYCODE_V2 = IOCTL_NOT_PRESENT; @@ -958,10 +980,12 @@ unsigned struct_ElfW_Phdr_sz = sizeof(Elf_Phdr); unsigned IOCTL_SIOCAX25SETPARMS = SIOCAX25SETPARMS; unsigned IOCTL_SIOCDEVPLIP = SIOCDEVPLIP; unsigned IOCTL_SIOCIPXCFGDATA = SIOCIPXCFGDATA; +#if !SANITIZER_UCLIBC unsigned IOCTL_SIOCNRDECOBS = SIOCNRDECOBS; unsigned IOCTL_SIOCNRGETPARMS = SIOCNRGETPARMS; unsigned IOCTL_SIOCNRRTCTL = SIOCNRRTCTL; unsigned IOCTL_SIOCNRSETPARMS = SIOCNRSETPARMS; +#endif #endif unsigned IOCTL_TIOCGSERIAL = TIOCGSERIAL; unsigned IOCTL_TIOCSERGETMULTI = TIOCSERGETMULTI; @@ -1033,7 +1057,7 @@ CHECK_SIZE_AND_OFFSET(dl_phdr_info, dlpi_phdr); CHECK_SIZE_AND_OFFSET(dl_phdr_info, dlpi_phnum); #endif // SANITIZER_LINUX || SANITIZER_FREEBSD -#if SANITIZER_GLIBC || SANITIZER_FREEBSD +#if (SANITIZER_GLIBC || SANITIZER_FREEBSD) && !SANITIZER_UCLIBC CHECK_TYPE_SIZE(glob_t); CHECK_SIZE_AND_OFFSET(glob_t, gl_pathc); CHECK_SIZE_AND_OFFSET(glob_t, gl_pathv); @@ -1172,7 +1196,7 @@ CHECK_TYPE_SIZE(__kernel_loff_t); CHECK_TYPE_SIZE(__kernel_fd_set); #endif -#if !SANITIZER_ANDROID +#if !SANITIZER_ANDROID && !SANITIZER_UCLIBC CHECK_TYPE_SIZE(wordexp_t); CHECK_SIZE_AND_OFFSET(wordexp_t, we_wordc); CHECK_SIZE_AND_OFFSET(wordexp_t, we_wordv); @@ -1240,7 +1264,7 @@ CHECK_TYPE_SIZE(clock_t); CHECK_TYPE_SIZE(clockid_t); #endif -#if !SANITIZER_ANDROID +#if !SANITIZER_ANDROID && !SANITIZER_UCLIBC CHECK_TYPE_SIZE(ifaddrs); CHECK_SIZE_AND_OFFSET(ifaddrs, ifa_next); CHECK_SIZE_AND_OFFSET(ifaddrs, ifa_name); @@ -1270,7 +1294,7 @@ CHECK_SIZE_AND_OFFSET(ifaddrs, ifa_data); COMPILER_CHECK(sizeof(__sanitizer_struct_mallinfo) == sizeof(struct mallinfo)); #endif -#if !SANITIZER_ANDROID +#if !SANITIZER_ANDROID && !SANITIZER_UCLIBC CHECK_TYPE_SIZE(timeb); CHECK_SIZE_AND_OFFSET(timeb, time); CHECK_SIZE_AND_OFFSET(timeb, millitm); @@ -1316,7 +1340,7 @@ COMPILER_CHECK(__sanitizer_XDR_DECODE == XDR_DECODE); COMPILER_CHECK(__sanitizer_XDR_FREE == XDR_FREE); #endif -#if SANITIZER_GLIBC +#if SANITIZER_GLIBC && !SANITIZER_UCLIBC COMPILER_CHECK(sizeof(__sanitizer_FILE) <= sizeof(FILE)); CHECK_SIZE_AND_OFFSET(FILE, _flags); CHECK_SIZE_AND_OFFSET(FILE, _IO_read_ptr); @@ -1334,6 +1358,7 @@ CHECK_SIZE_AND_OFFSET(FILE, _markers); CHECK_SIZE_AND_OFFSET(FILE, _chain); CHECK_SIZE_AND_OFFSET(FILE, _fileno); +#if !SANITIZER_UCLIBC COMPILER_CHECK(sizeof(__sanitizer__obstack_chunk) <= sizeof(_obstack_chunk)); CHECK_SIZE_AND_OFFSET(_obstack_chunk, limit); CHECK_SIZE_AND_OFFSET(_obstack_chunk, prev); @@ -1348,6 +1373,7 @@ CHECK_SIZE_AND_OFFSET(cookie_io_functions_t, read); CHECK_SIZE_AND_OFFSET(cookie_io_functions_t, write); CHECK_SIZE_AND_OFFSET(cookie_io_functions_t, seek); CHECK_SIZE_AND_OFFSET(cookie_io_functions_t, close); +#endif #endif // SANITIZER_GLIBC #if SANITIZER_LINUX || SANITIZER_FREEBSD diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h index e8c81aa8e28..e2ac31a5fb3 100644 --- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h +++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h @@ -316,7 +316,7 @@ struct __sanitizer_iovec { uptr iov_len; }; -#if !SANITIZER_ANDROID +#if !SANITIZER_ANDROID && !SANITIZER_UCLIBC struct __sanitizer_ifaddrs { struct __sanitizer_ifaddrs *ifa_next; char *ifa_name; @@ -570,6 +570,11 @@ typedef unsigned long __sanitizer_sigset_t; # endif #elif SANITIZER_APPLE typedef unsigned __sanitizer_sigset_t; +#elif SANITIZER_UCLIBC + struct __sanitizer_sigset_t { + // The size is determined by looking at sizeof of real sigset_t on linux. + uptr val[128 / (sizeof (unsigned long) * 8)]; + }; #elif SANITIZER_LINUX struct __sanitizer_sigset_t { // The size is determined by looking at sizeof of real sigset_t on linux. @@ -681,7 +686,7 @@ struct __sanitizer_sigaction { #if SANITIZER_LINUX void (*sa_restorer)(); #endif -#if defined(__mips__) && (SANITIZER_WORDSIZE == 32) +#if defined(__mips__) && (SANITIZER_WORDSIZE == 32) && !SANITIZER_UCLIBC int sa_resv[1]; #endif #if defined(__s390x__) diff --git a/libsanitizer/sanitizer_common/sanitizer_unwind_linux_libcdep.cpp b/libsanitizer/sanitizer_common/sanitizer_unwind_linux_libcdep.cpp index 6a8e82e2e21..d678ebacb2a 100644 --- a/libsanitizer/sanitizer_common/sanitizer_unwind_linux_libcdep.cpp +++ b/libsanitizer/sanitizer_common/sanitizer_unwind_linux_libcdep.cpp @@ -126,6 +126,7 @@ void SanitizerInitializeUnwinder() { void BufferedStackTrace::UnwindSlow(uptr pc, u32 max_depth) { CHECK_GE(max_depth, 2); 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Assert other two operands do not overlap after they are reordered. (*join2_loadhi): Same. Cherry-picked 63175687761e51dfe2f75dfab7b4de7f44bb4abe from https://github.com/MIPS/gcc Signed-off-by: Chao-ying Fu Signed-off-by: Aleksandar Rakic --- gcc/config/mips/mips.md | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 52abb9c1119..c5603c1aa9e 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -8130,7 +8130,7 @@ /* Reg-renaming pass reuses base register if it is dead after bonded loads. Hardware does not bond those loads, even when they are consecutive. However, order of the loads need to be checked for correctness. */ - if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1])) + if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[3])) { output_asm_insn (mips_output_move (insn, operands[0], operands[1]), operands); @@ -8139,6 +8139,8 @@ } else { + /* Check the other two registers. */ + gcc_assert (!reg_overlap_mentioned_p (operands[2], operands[1])); output_asm_insn (mips_output_move (insn, operands[2], operands[3]), &operands[2]); output_asm_insn (mips_output_move (insn, operands[0], operands[1]), @@ -8193,13 +8195,15 @@ /* Reg-renaming pass reuses base register if it is dead after bonded loads. Hardware does not bond those loads, even when they are consecutive. However, order of the loads need to be checked for correctness. */ - if (!reg_overlap_mentioned_p (operands[0], operands[1])) + if (!reg_overlap_mentioned_p (operands[0], operands[3])) { output_asm_insn ("lh\t%0,%1", operands); output_asm_insn ("lh\t%2,%3", operands); } else { + /* Check the other two registers. */ + gcc_assert (!reg_overlap_mentioned_p (operands[2], operands[1])); output_asm_insn ("lh\t%2,%3", operands); output_asm_insn ("lh\t%0,%1", operands); } From patchwork Fri Jan 31 17:13:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 105801 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E1C03385801B for ; Fri, 31 Jan 2025 18:17:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E1C03385801B Authentication-Results: sourceware.org; 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Cherry-picked 02dd052d4822ca187af075f1fb5301c954844144 from https://github.com/MIPS/gcc Signed-off-by: Chao-ying Fu Signed-off-by: Aleksandar Rakic --- gcc/testsuite/gcc.target/mips/pr54240.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/mips/pr54240.c b/gcc/testsuite/gcc.target/mips/pr54240.c index d3976f6cfef..31b793bb8c6 100644 --- a/gcc/testsuite/gcc.target/mips/pr54240.c +++ b/gcc/testsuite/gcc.target/mips/pr54240.c @@ -27,4 +27,4 @@ NOMIPS16 int foo(S *s) return next->v; } -/* { dg-final { scan-tree-dump "Hoisting adjacent loads" "phiopt1" } } */ +/* { dg-final { scan-tree-dump "Hoisting adjacent loads" "phiopt2" } } */