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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31afaf8sm53229495e9.21.2025.01.22.23.58.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Jan 2025 23:58:58 -0800 (PST) Message-ID: <8c45b1de-0e47-49d1-af19-abc047df4b6a@suse.com> Date: Thu, 23 Jan 2025 08:58:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 1/3] x86-64: omit "default" segment prefixes from string insn disassembly From: Jan Beulich To: Binutils Cc: "Kalvakuntla, Umesh" , "H.J. Lu" References: <862169bd-fa49-42a7-9081-7ac68e54f6f0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <862169bd-fa49-42a7-9081-7ac68e54f6f0@suse.com> X-Spam-Status: No, score=-3021.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Printing implicit %ds: and %es: prefixes is pretty meaningless in 64-bit mode. The SDM explicitly omits them for the 64-bit forms, and it obviously has them for the other ones only to cover non-64-bit modes (oddly enough the AMD PM has them present). --- In fact even outside of 64-bit mode I wonder about the need to print the default %ds: (making things indistinguishable from the case where a redundant explicit DS override is present). Maybe having the segment explicit is kind of reasonable for the two-memory-operand insns (where the other uses %es:, i.e. CMPS and MOVS), albeit said ambiguity then remains. But it's pretty obviously inconsistent with other memory operands we print when there's only one (LODS and OUTS). Yet further: Why are we printing operands at all when address size is the default one and there's no segment override? The (suffixed) short form (without operands) is certainly helping readbility of the output. Similarly I question the printing of the other operand for those insns with just a single memory operand: That's a GNU extension afaict; SDM and PM don't name such forms except for INS and OUTS (and even for these two that 2nd operand is pretty pointless to print, mainly adding clutter; IN and OUT are different in this regard because they also have immediate forms, which need to be distinguishable). --- a/gas/testsuite/gas/i386/ilp32/x86-64.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64.d @@ -37,9 +37,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 41 0f 20 c0 mov %cr0,%r8 [ ]*[a-f0-9]+: 44 0f 20 c0 mov %cr8,%rax [ ]*[a-f0-9]+: 44 0f 22 c0 mov %rax,%cr8 -[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\) -[ ]*[a-f0-9]+: 66 f3 a5 rep movsw %ds:\(%rsi\),%es:\(%rdi\) -[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\) +[ ]*[a-f0-9]+: f3 48 a5 rep movsq \(%rsi\),\(%rdi\) +[ ]*[a-f0-9]+: 66 f3 a5 rep movsw \(%rsi\),\(%rdi\) +[ ]*[a-f0-9]+: f3 48 a5 rep movsq \(%rsi\),\(%rdi\) [ ]*[a-f0-9]+: b0 11 mov \$0x11,%al [ ]*[a-f0-9]+: b4 11 mov \$0x11,%ah [ ]*[a-f0-9]+: 40 b4 11 mov \$0x11,%spl --- a/gas/testsuite/gas/i386/ilp32/x86-64-io.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-io.d @@ -1,24 +1,4 @@ #source: ../x86-64-io.s #objdump: -dw #name: x86-64 (ILP32) rex.W in/out - -.*: +file format .* - -Disassembly of section .text: - -0+000 <_in>: - 0: 48 ed rex.W in \(%dx\),%eax - 2: 66 48 ed data16 rex.W in \(%dx\),%eax - -0+005 <_out>: - 5: 48 ef rex.W out %eax,\(%dx\) - 7: 66 48 ef data16 rex.W out %eax,\(%dx\) - -0+00a <_ins>: - a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) - c: 66 48 6d data16 rex.W insl \(%dx\),%es:\(%rdi\) - -0+00f <_outs>: - f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) - 11: 66 48 6f data16 rex.W outsl %ds:\(%rsi\),\(%dx\) -#pass +#dump: ../x86-64-io.d --- a/gas/testsuite/gas/i386/ilp32/x86-64-io-intel.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-io-intel.d @@ -1,24 +1,4 @@ #source: ../x86-64-io.s #objdump: -dwMintel #name: x86-64 (ILP32) rex.W in/out (Intel disassembly) - -.*: +file format .* - -Disassembly of section .text: - -0+000 <_in>: - 0: 48 ed rex.W in eax,dx - 2: 66 48 ed data16 rex.W in eax,dx - -0+005 <_out>: - 5: 48 ef rex.W out dx,eax - 7: 66 48 ef data16 rex.W out dx,eax - -0+00a <_ins>: - a: 48 6d rex.W ins DWORD PTR es:\[rdi\],dx - c: 66 48 6d data16 rex.W ins DWORD PTR es:\[rdi\],dx - -0+00f <_outs>: - f: 48 6f rex.W outs dx,DWORD PTR ds:\[rsi\] - 11: 66 48 6f data16 rex.W outs dx,DWORD PTR ds:\[rsi\] -#pass +#dump: ../x86-64-io-intel.d --- a/gas/testsuite/gas/i386/ilp32/x86-64-io-suffix.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-io-suffix.d @@ -1,6 +1,7 @@ #source: ../x86-64-io.s #objdump: -dwMsuffix #name: x86-64 (ILP32) rex.W in/out w/ suffix +#dump: ../x86-64-io-suffix.d .*: +file format .* --- a/gas/testsuite/gas/i386/ilp32/x86-64-rep.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-rep.d @@ -1,62 +1,4 @@ #source: ../x86-64-rep.s #objdump: -dw #name: x86-64 (ILP32) rep prefix - -.*: +file format .* - -Disassembly of section .text: - -0+ <_start>: - 0: f3 6c[ ]+rep insb \(%dx\),%es:\(%rdi\) - 2: f3 6e[ ]+rep outsb %ds:\(%rsi\),\(%dx\) - 4: f3 a4[ ]+rep movsb %ds:\(%rsi\),%es:\(%rdi\) - 6: f3 ac[ ]+rep lods %ds:\(%rsi\),%al - 8: f3 aa[ ]+rep stos %al,%es:\(%rdi\) - a: f3 a6[ ]+repz cmpsb %es:\(%rdi\),%ds:\(%rsi\) - c: f3 ae[ ]+repz scas %es:\(%rdi\),%al - e: 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%rdi\) - 11: 66 f3 6f[ ]+rep outsw %ds:\(%rsi\),\(%dx\) - 14: 66 f3 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\) - 17: 66 f3 ad[ ]+rep lods %ds:\(%rsi\),%ax - 1a: 66 f3 ab[ ]+rep stos %ax,%es:\(%rdi\) - 1d: 66 f3 a7[ ]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\) - 20: 66 f3 af[ ]+repz scas %es:\(%rdi\),%ax - 23: f3 6d[ ]+rep insl \(%dx\),%es:\(%rdi\) - 25: f3 6f[ ]+rep outsl %ds:\(%rsi\),\(%dx\) - 27: f3 a5[ ]+rep movsl %ds:\(%rsi\),%es:\(%rdi\) - 29: f3 ad[ ]+rep lods %ds:\(%rsi\),%eax - 2b: f3 ab[ ]+rep stos %eax,%es:\(%rdi\) - 2d: f3 a7[ ]+repz cmpsl %es:\(%rdi\),%ds:\(%rsi\) - 2f: f3 af[ ]+repz scas %es:\(%rdi\),%eax - 31: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\) - 34: f3 48 ad[ ]+rep lods %ds:\(%rsi\),%rax - 37: f3 48 ab[ ]+rep stos %rax,%es:\(%rdi\) - 3a: f3 48 a7[ ]+repz cmpsq %es:\(%rdi\),%ds:\(%rsi\) - 3d: f3 48 af[ ]+repz scas %es:\(%rdi\),%rax - 40: 67 f3 6c[ ]+rep insb \(%dx\),%es:\(%edi\) - 43: 67 f3 6e[ ]+rep outsb %ds:\(%esi\),\(%dx\) - 46: 67 f3 a4[ ]+rep movsb %ds:\(%esi\),%es:\(%edi\) - 49: 67 f3 ac[ ]+rep lods %ds:\(%esi\),%al - 4c: 67 f3 aa[ ]+rep stos %al,%es:\(%edi\) - 4f: 67 f3 a6[ ]+repz cmpsb %es:\(%edi\),%ds:\(%esi\) - 52: 67 f3 ae[ ]+repz scas %es:\(%edi\),%al - 55: 67 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%edi\) - 59: 67 66 f3 6f[ ]+rep outsw %ds:\(%esi\),\(%dx\) - 5d: 67 66 f3 a5[ ]+rep movsw %ds:\(%esi\),%es:\(%edi\) - 61: 67 66 f3 ad[ ]+rep lods %ds:\(%esi\),%ax - 65: 67 66 f3 ab[ ]+rep stos %ax,%es:\(%edi\) - 69: 67 66 f3 a7[ ]+repz cmpsw %es:\(%edi\),%ds:\(%esi\) - 6d: 67 66 f3 af[ ]+repz scas %es:\(%edi\),%ax - 71: 67 f3 6d[ ]+rep insl \(%dx\),%es:\(%edi\) - 74: 67 f3 6f[ ]+rep outsl %ds:\(%esi\),\(%dx\) - 77: 67 f3 a5[ ]+rep movsl %ds:\(%esi\),%es:\(%edi\) - 7a: 67 f3 ad[ ]+rep lods %ds:\(%esi\),%eax - 7d: 67 f3 ab[ ]+rep stos %eax,%es:\(%edi\) - 80: 67 f3 a7[ ]+repz cmpsl %es:\(%edi\),%ds:\(%esi\) - 83: 67 f3 af[ ]+repz scas %es:\(%edi\),%eax - 86: 67 f3 48 a5[ ]+rep movsq %ds:\(%esi\),%es:\(%edi\) - 8a: 67 f3 48 ad[ ]+rep lods %ds:\(%esi\),%rax - 8e: 67 f3 48 ab[ ]+rep stos %rax,%es:\(%edi\) - 92: 67 f3 48 a7[ ]+repz cmpsq %es:\(%edi\),%ds:\(%esi\) - 96: 67 f3 48 af[ ]+repz scas %es:\(%edi\),%rax -#pass +#dump: ../x86-64-rep.d --- a/gas/testsuite/gas/i386/intel-cmps64.d +++ b/gas/testsuite/gas/i386/intel-cmps64.d @@ -7,80 +7,80 @@ Disassembly of section .text: 0+ : -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 64 67 a6 * cmps +BYTE PTR fs:\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR (ds:)?\[esi\],(BYTE PTR )?es:\[edi\] -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 64 a6 * cmps +BYTE PTR fs:\[rsi\],(BYTE PTR )?es:\[rdi\] -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR (ds:)?\[rsi\],(BYTE PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 64 67 66 a7 * cmps +WORD PTR fs:\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR (ds:)?\[esi\],(WORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 64 66 a7 * cmps +WORD PTR fs:\[rsi\],(WORD PTR )?es:\[rdi\] -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR (ds:)?\[rsi\],(WORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 64 67 a7 * cmps +DWORD PTR fs:\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR (ds:)?\[esi\],(DWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 64 a7 * cmps +DWORD PTR fs:\[rsi\],(DWORD PTR )?es:\[rdi\] -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR (ds:)?\[rsi\],(DWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 64 48 a7 * cmps +QWORD PTR fs:?\[rsi\],(QWORD PTR )?es:\[rdi\] -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR (ds:)?\[rsi\],(QWORD PTR )?es:\[rdi\]) -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 64 67 48 a7 * cmps +QWORD PTR fs:?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] -[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR (ds:)?\[esi\],(QWORD PTR )?es:\[edi\] +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 64 67 a6 * cmps +BYTE PTR fs:\[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a6 * cmps +BYTE PTR \[esi\],(BYTE PTR )?\[edi\] +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 64 a6 * cmps +BYTE PTR fs:\[rsi\],(BYTE PTR )?\[rdi\] +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a6 * cmps(b *| +BYTE PTR \[rsi\],(BYTE PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 64 67 66 a7 * cmps +WORD PTR fs:\[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 66 a7 * cmps +WORD PTR \[esi\],(WORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 64 66 a7 * cmps +WORD PTR fs:\[rsi\],(WORD PTR )?\[rdi\] +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 66 a7 * cmps(w *| +WORD PTR \[rsi\],(WORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 64 67 a7 * cmps +DWORD PTR fs:\[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 a7 * cmps +DWORD PTR \[esi\],(DWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 64 a7 * cmps +DWORD PTR fs:\[rsi\],(DWORD PTR )?\[rdi\] +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: a7 * cmps(d *| +DWORD PTR \[rsi\],(DWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 64 48 a7 * cmps +QWORD PTR fs:?\[rsi\],(QWORD PTR )?\[rdi\] +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 48 a7 * cmps(q *| +QWORD PTR \[rsi\],(QWORD PTR )?\[rdi\]) +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 64 67 48 a7 * cmps +QWORD PTR fs:?\[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] +[ ]*[a-f0-9]+: 67 48 a7 * cmps +QWORD PTR \[esi\],(QWORD PTR )?\[edi\] #pass --- a/gas/testsuite/gas/i386/intel-movs64.d +++ b/gas/testsuite/gas/i386/intel-movs64.d @@ -7,80 +7,80 @@ Disassembly of section .text: 0+ : -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 64 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?fs:\[esi\] -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR es:\[edi\],(BYTE PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 64 a4 * movs +BYTE PTR es:\[rdi\],(BYTE PTR )?fs:\[rsi\] -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR es:\[rdi\],(BYTE PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 64 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?fs:\[esi\] -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR es:\[edi\],(WORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 64 66 a5 * movs +WORD PTR es:\[rdi\],(WORD PTR )?fs:\[rsi\] -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR es:\[rdi\],(WORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 64 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?fs:\[esi\] -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR es:\[edi\],(DWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 64 a5 * movs +DWORD PTR es:\[rdi\],(DWORD PTR )?fs:\[rsi\] -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR es:\[rdi\],(DWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 64 48 a5 * movs +QWORD PTR es:\[rdi\],(QWORD PTR )?fs:?\[rsi\] -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR es:\[rdi\],(QWORD PTR )?(ds:)?\[rsi\]) -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 64 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?fs:?\[esi\] -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] -[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR es:\[edi\],(QWORD PTR )?(ds:)?\[esi\] +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: 64 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?fs:\[esi\] +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a4 * movs +BYTE PTR \[edi\],(BYTE PTR )?\[esi\] +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 64 a4 * movs +BYTE PTR \[rdi\],(BYTE PTR )?fs:\[rsi\] +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a4 * movs(b *| +BYTE PTR \[rdi\],(BYTE PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 64 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?fs:\[esi\] +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 66 a5 * movs +WORD PTR \[edi\],(WORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 64 66 a5 * movs +WORD PTR \[rdi\],(WORD PTR )?fs:\[rsi\] +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 66 a5 * movs(w *| +WORD PTR \[rdi\],(WORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 64 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?fs:\[esi\] +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 a5 * movs +DWORD PTR \[edi\],(DWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 64 a5 * movs +DWORD PTR \[rdi\],(DWORD PTR )?fs:\[rsi\] +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: a5 * movs(d *| +DWORD PTR \[rdi\],(DWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 64 48 a5 * movs +QWORD PTR \[rdi\],(QWORD PTR )?fs:?\[rsi\] +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 48 a5 * movs(q *| +QWORD PTR \[rdi\],(QWORD PTR )?\[rsi\]) +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 64 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?fs:?\[esi\] +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] +[ ]*[a-f0-9]+: 67 48 a5 * movs +QWORD PTR \[edi\],(QWORD PTR )?\[esi\] #pass --- a/gas/testsuite/gas/i386/noreg64.d +++ b/gas/testsuite/gas/i386/noreg64.d @@ -32,8 +32,8 @@ Disassembly of section .text: *[a-f0-9]+: 81 38 89 00 00 00 cmpl \$0x89,\(%rax\) *[a-f0-9]+: 81 38 34 12 00 00 cmpl \$0x1234,\(%rax\) *[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%rax\) - *[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\) - *[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\) + *[a-f0-9]+: a7 cmpsl \(%rdi\),\(%rsi\) + *[a-f0-9]+: a7 cmpsl \(%rdi\),\(%rsi\) *[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%rax\),%eax *[a-f0-9]+: f2 48 0f 38 f1 00 crc32q \(%rax\),%rax *[a-f0-9]+: 62 f4 04 07 f7 00 89 00 00 00 ctestal \{dfv=\} \$0x89,\(%rax\) @@ -69,8 +69,8 @@ Disassembly of section .text: *[a-f0-9]+: e5 00 in \$0x0,%eax *[a-f0-9]+: ed in \(%dx\),%eax *[a-f0-9]+: ff 00 incl \(%rax\) - *[a-f0-9]+: 6d insl \(%dx\),%es:\(%rdi\) - *[a-f0-9]+: 6d insl \(%dx\),%es:\(%rdi\) + *[a-f0-9]+: 6d insl \(%dx\),\(%rdi\) + *[a-f0-9]+: 6d insl \(%dx\),\(%rdi\) *[a-f0-9]+: cf iret *[a-f0-9]+: ff 20 jmp \*\(%rax\) *[a-f0-9]+: ff 18 lcall \*\(%rax\) @@ -79,8 +79,8 @@ Disassembly of section .text: *[a-f0-9]+: ff 28 ljmp \*\(%rax\) *[a-f0-9]+: 0f 00 10 lldt \(%rax\) *[a-f0-9]+: 0f 01 30 lmsw \(%rax\) - *[a-f0-9]+: ad lods %ds:\(%rsi\),%eax - *[a-f0-9]+: ad lods %ds:\(%rsi\),%eax + *[a-f0-9]+: ad lods \(%rsi\),%eax + *[a-f0-9]+: ad lods \(%rsi\),%eax *[a-f0-9]+: cb lret *[a-f0-9]+: ca 04 00 lret \$0x4 *[a-f0-9]+: 0f 00 18 ltr \(%rax\) @@ -89,8 +89,8 @@ Disassembly of section .text: *[a-f0-9]+: c7 00 78 56 34 12 movl \$0x12345678,\(%rax\) *[a-f0-9]+: 8c 00 mov %es,\(%rax\) *[a-f0-9]+: 8e 00 mov \(%rax\),%es - *[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\) - *[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\) + *[a-f0-9]+: a5 movsl \(%rsi\),\(%rdi\) + *[a-f0-9]+: a5 movsl \(%rsi\),\(%rdi\) *[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax *[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax *[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax @@ -107,8 +107,8 @@ Disassembly of section .text: *[a-f0-9]+: 81 08 78 56 34 12 orl \$0x12345678,\(%rax\) *[a-f0-9]+: e7 00 out %eax,\$0x0 *[a-f0-9]+: ef out %eax,\(%dx\) - *[a-f0-9]+: 6f outsl %ds:\(%rsi\),\(%dx\) - *[a-f0-9]+: 6f outsl %ds:\(%rsi\),\(%dx\) + *[a-f0-9]+: 6f outsl \(%rsi\),\(%dx\) + *[a-f0-9]+: 6f outsl \(%rsi\),\(%dx\) *[a-f0-9]+: 8f 00 pop \(%rax\) *[a-f0-9]+: 0f a1 pop %fs *[a-f0-9]+: f3 0f ae 20 ptwritel \(%rax\) @@ -134,8 +134,8 @@ Disassembly of section .text: *[a-f0-9]+: 81 18 89 00 00 00 sbbl \$0x89,\(%rax\) *[a-f0-9]+: 81 18 34 12 00 00 sbbl \$0x1234,\(%rax\) *[a-f0-9]+: 81 18 78 56 34 12 sbbl \$0x12345678,\(%rax\) - *[a-f0-9]+: af scas %es:\(%rdi\),%eax - *[a-f0-9]+: af scas %es:\(%rdi\),%eax + *[a-f0-9]+: af scas \(%rdi\),%eax + *[a-f0-9]+: af scas \(%rdi\),%eax *[a-f0-9]+: d1 20 shll \$1,\(%rax\) *[a-f0-9]+: c1 20 02 shll \$0x2,\(%rax\) *[a-f0-9]+: d3 20 shll %cl,\(%rax\) @@ -152,8 +152,8 @@ Disassembly of section .text: *[a-f0-9]+: c1 28 02 shrl \$0x2,\(%rax\) *[a-f0-9]+: d3 28 shrl %cl,\(%rax\) *[a-f0-9]+: d1 28 shrl \$1,\(%rax\) - *[a-f0-9]+: ab stos %eax,%es:\(%rdi\) - *[a-f0-9]+: ab stos %eax,%es:\(%rdi\) + *[a-f0-9]+: ab stos %eax,\(%rdi\) + *[a-f0-9]+: ab stos %eax,\(%rdi\) *[a-f0-9]+: 83 28 01 subl \$0x1,\(%rax\) *[a-f0-9]+: 81 28 89 00 00 00 subl \$0x89,\(%rax\) *[a-f0-9]+: 81 28 34 12 00 00 subl \$0x1234,\(%rax\) --- a/gas/testsuite/gas/i386/noreg64-data16.d +++ b/gas/testsuite/gas/i386/noreg64-data16.d @@ -34,8 +34,8 @@ Disassembly of section .text: *[a-f0-9]+: 66 81 38 89 00 cmpw \$0x89,\(%rax\) *[a-f0-9]+: 66 81 38 34 12 cmpw \$0x1234,\(%rax\) *[a-f0-9]+: 66 81 38 78 56 cmpw \$0x5678,\(%rax\) - *[a-f0-9]+: 66 a7 cmpsw %es:\(%rdi\),%ds:\(%rsi\) - *[a-f0-9]+: 66 a7 cmpsw %es:\(%rdi\),%ds:\(%rsi\) + *[a-f0-9]+: 66 a7 cmpsw \(%rdi\),\(%rsi\) + *[a-f0-9]+: 66 a7 cmpsw \(%rdi\),\(%rsi\) *[a-f0-9]+: 66 f2 0f 38 f1 00 crc32w \(%rax\),%eax *[a-f0-9]+: 66 f2 48 0f 38 f1 00 data16 crc32q \(%rax\),%rax *[a-f0-9]+: 62 f4 05 07 f7 00 89 00[ ]+ctestaw \{dfv=\} \$0x89,\(%rax\) @@ -71,8 +71,8 @@ Disassembly of section .text: *[a-f0-9]+: 66 e5 00 in \$0x0,%ax *[a-f0-9]+: 66 ed in \(%dx\),%ax *[a-f0-9]+: 66 ff 00 incw \(%rax\) - *[a-f0-9]+: 66 6d insw \(%dx\),%es:\(%rdi\) - *[a-f0-9]+: 66 6d insw \(%dx\),%es:\(%rdi\) + *[a-f0-9]+: 66 6d insw \(%dx\),\(%rdi\) + *[a-f0-9]+: 66 6d insw \(%dx\),\(%rdi\) *[a-f0-9]+: 66 cf iretw *[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\) *[a-f0-9]+: 66 ff 18 lcallw \*\(%rax\) @@ -81,8 +81,8 @@ Disassembly of section .text: *[a-f0-9]+: 66 ff 28 ljmpw \*\(%rax\) *[a-f0-9]+: 66 0f 00 10 data16 lldt \(%rax\) *[a-f0-9]+: 66 0f 01 30 data16 lmsw \(%rax\) - *[a-f0-9]+: 66 ad lods %ds:\(%rsi\),%ax - *[a-f0-9]+: 66 ad lods %ds:\(%rsi\),%ax + *[a-f0-9]+: 66 ad lods \(%rsi\),%ax + *[a-f0-9]+: 66 ad lods \(%rsi\),%ax *[a-f0-9]+: 66 cb lretw *[a-f0-9]+: 66 ca 04 00 lretw \$0x4 *[a-f0-9]+: 66 0f 00 18 data16 ltr \(%rax\) @@ -91,8 +91,8 @@ Disassembly of section .text: *[a-f0-9]+: 66 c7 00 78 56 movw \$0x5678,\(%rax\) *[a-f0-9]+: 66 8c 00 data16 mov %es,\(%rax\) *[a-f0-9]+: 66 8e 00 data16 mov \(%rax\),%es - *[a-f0-9]+: 66 a5 movsw %ds:\(%rsi\),%es:\(%rdi\) - *[a-f0-9]+: 66 a5 movsw %ds:\(%rsi\),%es:\(%rdi\) + *[a-f0-9]+: 66 a5 movsw \(%rsi\),\(%rdi\) + *[a-f0-9]+: 66 a5 movsw \(%rsi\),\(%rdi\) *[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax *[a-f0-9]+: 66 48 0f be 00 data16 movsbq \(%rax\),%rax *[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax @@ -107,8 +107,8 @@ Disassembly of section .text: *[a-f0-9]+: 66 81 08 78 56 orw \$0x5678,\(%rax\) *[a-f0-9]+: 66 e7 00 out %ax,\$0x0 *[a-f0-9]+: 66 ef out %ax,\(%dx\) - *[a-f0-9]+: 66 6f outsw %ds:\(%rsi\),\(%dx\) - *[a-f0-9]+: 66 6f outsw %ds:\(%rsi\),\(%dx\) + *[a-f0-9]+: 66 6f outsw \(%rsi\),\(%dx\) + *[a-f0-9]+: 66 6f outsw \(%rsi\),\(%dx\) *[a-f0-9]+: 66 8f 00 popw \(%rax\) *[a-f0-9]+: 66 0f a1 popw %fs *[a-f0-9]+: 66 ff 30 pushw \(%rax\) @@ -133,8 +133,8 @@ Disassembly of section .text: *[a-f0-9]+: 66 81 18 89 00 sbbw \$0x89,\(%rax\) *[a-f0-9]+: 66 81 18 34 12 sbbw \$0x1234,\(%rax\) *[a-f0-9]+: 66 81 18 78 56 sbbw \$0x5678,\(%rax\) - *[a-f0-9]+: 66 af scas %es:\(%rdi\),%ax - *[a-f0-9]+: 66 af scas %es:\(%rdi\),%ax + *[a-f0-9]+: 66 af scas \(%rdi\),%ax + *[a-f0-9]+: 66 af scas \(%rdi\),%ax *[a-f0-9]+: 66 d1 20 shlw \$1,\(%rax\) *[a-f0-9]+: 66 c1 20 02 shlw \$0x2,\(%rax\) *[a-f0-9]+: 66 d3 20 shlw %cl,\(%rax\) @@ -151,8 +151,8 @@ Disassembly of section .text: *[a-f0-9]+: 66 c1 28 02 shrw \$0x2,\(%rax\) *[a-f0-9]+: 66 d3 28 shrw %cl,\(%rax\) *[a-f0-9]+: 66 d1 28 shrw \$1,\(%rax\) - *[a-f0-9]+: 66 ab stos %ax,%es:\(%rdi\) - *[a-f0-9]+: 66 ab stos %ax,%es:\(%rdi\) + *[a-f0-9]+: 66 ab stos %ax,\(%rdi\) + *[a-f0-9]+: 66 ab stos %ax,\(%rdi\) *[a-f0-9]+: 66 83 28 01 subw \$0x1,\(%rax\) *[a-f0-9]+: 66 81 28 89 00 subw \$0x89,\(%rax\) *[a-f0-9]+: 66 81 28 34 12 subw \$0x1234,\(%rax\) --- a/gas/testsuite/gas/i386/noreg64-rex64.d +++ b/gas/testsuite/gas/i386/noreg64-rex64.d @@ -33,8 +33,8 @@ Disassembly of section .text: *[a-f0-9]+: 48 81 38 89 00 00 00 cmpq \$0x89,\(%rax\) *[a-f0-9]+: 48 81 38 34 12 00 00 cmpq \$0x1234,\(%rax\) *[a-f0-9]+: 48 81 38 78 56 34 12 cmpq \$0x12345678,\(%rax\) - *[a-f0-9]+: 48 a7 cmpsq %es:\(%rdi\),%ds:\(%rsi\) - *[a-f0-9]+: 48 a7 cmpsq %es:\(%rdi\),%ds:\(%rsi\) + *[a-f0-9]+: 48 a7 cmpsq \(%rdi\),\(%rsi\) + *[a-f0-9]+: 48 a7 cmpsq \(%rdi\),\(%rsi\) *[a-f0-9]+: f2 48 0f 38 f1 00 crc32q \(%rax\),%rax *[a-f0-9]+: 62 f4 84 07 f7 00 89 00 00 00[ ]+ctestaq \{dfv=\} \$0x89,\(%rax\) *[a-f0-9]+: 62 f4 84 07 f7 00 34 12 00 00[ ]+ctestaq \{dfv=\} \$0x1234,\(%rax\) @@ -69,8 +69,8 @@ Disassembly of section .text: *[a-f0-9]+: 48 e5 00 rex\.W in \$0x0,%eax *[a-f0-9]+: 48 ed rex\.W in \(%dx\),%eax *[a-f0-9]+: 48 ff 00 incq \(%rax\) - *[a-f0-9]+: 48 6d rex\.W insl \(%dx\),%es:\(%rdi\) - *[a-f0-9]+: 48 6d rex\.W insl \(%dx\),%es:\(%rdi\) + *[a-f0-9]+: 48 6d rex\.W insl \(%dx\),\(%rdi\) + *[a-f0-9]+: 48 6d rex\.W insl \(%dx\),\(%rdi\) *[a-f0-9]+: 48 cf iretq *[a-f0-9]+: 48 ff 20 rex\.W jmp \*\(%rax\) *[a-f0-9]+: 48 ff 18 rex\.W lcall \*\(%rax\) @@ -79,8 +79,8 @@ Disassembly of section .text: *[a-f0-9]+: 48 ff 28 rex\.W ljmp \*\(%rax\) *[a-f0-9]+: 48 0f 00 10 rex\.W lldt \(%rax\) *[a-f0-9]+: 48 0f 01 30 rex\.W lmsw \(%rax\) - *[a-f0-9]+: 48 ad lods %ds:\(%rsi\),%rax - *[a-f0-9]+: 48 ad lods %ds:\(%rsi\),%rax + *[a-f0-9]+: 48 ad lods \(%rsi\),%rax + *[a-f0-9]+: 48 ad lods \(%rsi\),%rax *[a-f0-9]+: 48 cb lretq *[a-f0-9]+: 48 ca 04 00 lretq \$0x4 *[a-f0-9]+: 48 0f 00 18 rex\.W ltr \(%rax\) @@ -89,8 +89,8 @@ Disassembly of section .text: *[a-f0-9]+: 48 c7 00 78 56 34 12 movq \$0x12345678,\(%rax\) *[a-f0-9]+: 48 8c 00 rex\.W mov %es,\(%rax\) *[a-f0-9]+: 48 8e 00 rex\.W mov \(%rax\),%es - *[a-f0-9]+: 48 a5 movsq %ds:\(%rsi\),%es:\(%rdi\) - *[a-f0-9]+: 48 a5 movsq %ds:\(%rsi\),%es:\(%rdi\) + *[a-f0-9]+: 48 a5 movsq \(%rsi\),\(%rdi\) + *[a-f0-9]+: 48 a5 movsq \(%rsi\),\(%rdi\) *[a-f0-9]+: 66 48 0f be 00 data16 movsbq \(%rax\),%rax *[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax *[a-f0-9]+: 66 48 0f b6 00 data16 movzbq \(%rax\),%rax @@ -105,8 +105,8 @@ Disassembly of section .text: *[a-f0-9]+: 48 81 08 78 56 34 12 orq \$0x12345678,\(%rax\) *[a-f0-9]+: 48 e7 00 rex\.W out %eax,\$0x0 *[a-f0-9]+: 48 ef rex\.W out %eax,\(%dx\) - *[a-f0-9]+: 48 6f rex\.W outsl %ds:\(%rsi\),\(%dx\) - *[a-f0-9]+: 48 6f rex\.W outsl %ds:\(%rsi\),\(%dx\) + *[a-f0-9]+: 48 6f rex\.W outsl \(%rsi\),\(%dx\) + *[a-f0-9]+: 48 6f rex\.W outsl \(%rsi\),\(%dx\) *[a-f0-9]+: 48 8f 00 rex\.W pop \(%rax\) *[a-f0-9]+: 48 0f a1 rex\.W pop %fs *[a-f0-9]+: f3 48 0f ae 20 ptwriteq \(%rax\) @@ -132,8 +132,8 @@ Disassembly of section .text: *[a-f0-9]+: 48 81 18 89 00 00 00 sbbq \$0x89,\(%rax\) *[a-f0-9]+: 48 81 18 34 12 00 00 sbbq \$0x1234,\(%rax\) *[a-f0-9]+: 48 81 18 78 56 34 12 sbbq \$0x12345678,\(%rax\) - *[a-f0-9]+: 48 af scas %es:\(%rdi\),%rax - *[a-f0-9]+: 48 af scas %es:\(%rdi\),%rax + *[a-f0-9]+: 48 af scas \(%rdi\),%rax + *[a-f0-9]+: 48 af scas \(%rdi\),%rax *[a-f0-9]+: 48 d1 20 shlq \$1,\(%rax\) *[a-f0-9]+: 48 c1 20 02 shlq \$0x2,\(%rax\) *[a-f0-9]+: 48 d3 20 shlq %cl,\(%rax\) @@ -150,8 +150,8 @@ Disassembly of section .text: *[a-f0-9]+: 48 c1 28 02 shrq \$0x2,\(%rax\) *[a-f0-9]+: 48 d3 28 shrq %cl,\(%rax\) *[a-f0-9]+: 48 d1 28 shrq \$1,\(%rax\) - *[a-f0-9]+: 48 ab stos %rax,%es:\(%rdi\) - *[a-f0-9]+: 48 ab stos %rax,%es:\(%rdi\) + *[a-f0-9]+: 48 ab stos %rax,\(%rdi\) + *[a-f0-9]+: 48 ab stos %rax,\(%rdi\) *[a-f0-9]+: 48 83 28 01 subq \$0x1,\(%rax\) *[a-f0-9]+: 48 81 28 89 00 00 00 subq \$0x89,\(%rax\) *[a-f0-9]+: 48 81 28 34 12 00 00 subq \$0x1234,\(%rax\) --- a/gas/testsuite/gas/i386/x86-64-align-branch-5.d +++ b/gas/testsuite/gas/i386/x86-64-align-branch-5.d @@ -20,7 +20,7 @@ Disassembly of section .text: 19: c1 e9 02 shr \$0x2,%ecx 1c: c1 e9 02 shr \$0x2,%ecx 1f: f6 c2 02 test \$0x2,%dl - 22: f3 ab rep stos %eax,%es:\(%rdi\) + 22: f3 ab rep stos %eax,\(%rdi\) 24: 75 dd jne (0x)?3( .*)? 26: 31 c0 xor %eax,%eax 28: c1 e9 02 shr \$0x2,%ecx --- a/gas/testsuite/gas/i386/x86-64-disassem.d +++ b/gas/testsuite/gas/i386/x86-64-disassem.d @@ -15,235 +15,235 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ec 4a[ ]+kaddw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ed 4a[ ]+kaddb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ec 4a[ ]+kaddq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ed 4a[ ]+kaddd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ec 41[ ]+kandw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ed 41[ ]+kandb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ec 41[ ]+kandq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ed 41[ ]+kandd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ec 42[ ]+kandnw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ed 42[ ]+kandnb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ec 42[ ]+kandnq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ed 42[ ]+kandnd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ec 4b[ ]+kunpckwd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ed 4b[ ]+kunpckbw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ec 4b[ ]+kunpckdq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f8 44[ ]+knotw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f9 44[ ]+knotb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f8 44[ ]+knotq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f9 44[ ]+knotd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ec 45[ ]+korw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ed 45[ ]+korb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ec 45[ ]+korq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ed 45[ ]+kord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f8 98[ ]+kortestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f9 98[ ]+kortestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f8 98[ ]+kortestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f9 98[ ]+kortestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ec 46[ ]+kxnorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ed 46[ ]+kxnorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ec 46[ ]+kxnorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ed 46[ ]+kxnord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ec 47[ ]+kxorw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 ed 47[ ]+kxorb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ec 47[ ]+kxorq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 ed 47[ ]+kxord[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f8 99[ ]+ktestw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f9 99[ ]+ktestb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f8 99[ ]+ktestq[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f9 99[ ]+ktestd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e3 f9 30 8f[ ]+kshiftrw[ ]*\$0x[0-9a-f]*,\(bad\),.* @@ -297,49 +297,49 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f8 92[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f9 92[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 fb 92[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 92[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f9 92[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f9 92[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f8 93[ ]+kmovw[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 f9 93[ ]+kmovb[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c5 fb 93[ ]+kmovd[ ]*\(bad\),.* [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*9b[ ]*fwait [ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\) -[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\) +[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl .* [ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\) [ ]*[a-f0-9]+:[ ]*c4 62 01 1c[ ]*\(bad\) --- a/gas/testsuite/gas/i386/x86-64-io.d +++ b/gas/testsuite/gas/i386/x86-64-io.d @@ -14,10 +14,10 @@ Disassembly of section .text: 7: 66 48 ef data16 rex.W out %eax,\(%dx\) 0+00a <_ins>: - a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) - c: 66 48 6d data16 rex.W insl \(%dx\),%es:\(%rdi\) + a: 48 6d rex.W insl \(%dx\),\(%rdi\) + c: 66 48 6d data16 rex.W insl \(%dx\),\(%rdi\) 0+00f <_outs>: - f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) - 11: 66 48 6f data16 rex.W outsl %ds:\(%rsi\),\(%dx\) + f: 48 6f rex.W outsl \(%rsi\),\(%dx\) + 11: 66 48 6f data16 rex.W outsl \(%rsi\),\(%dx\) #pass --- a/gas/testsuite/gas/i386/x86-64-io-intel.d +++ b/gas/testsuite/gas/i386/x86-64-io-intel.d @@ -15,10 +15,10 @@ Disassembly of section .text: 7: 66 48 ef data16 rex.W out dx,eax 0+00a <_ins>: - a: 48 6d rex.W ins DWORD PTR es:\[rdi\],dx - c: 66 48 6d data16 rex.W ins DWORD PTR es:\[rdi\],dx + a: 48 6d rex.W ins DWORD PTR \[rdi\],dx + c: 66 48 6d data16 rex.W ins DWORD PTR \[rdi\],dx 0+00f <_outs>: - f: 48 6f rex.W outs dx,DWORD PTR ds:\[rsi\] - 11: 66 48 6f data16 rex.W outs dx,DWORD PTR ds:\[rsi\] + f: 48 6f rex.W outs dx,DWORD PTR \[rsi\] + 11: 66 48 6f data16 rex.W outs dx,DWORD PTR \[rsi\] #pass --- a/gas/testsuite/gas/i386/x86-64-io-suffix.d +++ b/gas/testsuite/gas/i386/x86-64-io-suffix.d @@ -15,10 +15,10 @@ Disassembly of section .text: 7: 66 48 ef data16 rex.W outl %eax,\(%dx\) 0+00a <_ins>: - a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) - c: 66 48 6d data16 rex.W insl \(%dx\),%es:\(%rdi\) + a: 48 6d rex.W insl \(%dx\),\(%rdi\) + c: 66 48 6d data16 rex.W insl \(%dx\),\(%rdi\) 0+00f <_outs>: - f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) - 11: 66 48 6f data16 rex.W outsl %ds:\(%rsi\),\(%dx\) + f: 48 6f rex.W outsl \(%rsi\),\(%dx\) + 11: 66 48 6f data16 rex.W outsl \(%rsi\),\(%dx\) #pass --- a/gas/testsuite/gas/i386/x86-64-lfence-byte.d +++ b/gas/testsuite/gas/i386/x86-64-lfence-byte.d @@ -9,7 +9,7 @@ Disassembly of section .text: 0+ <_start>: - +[a-f0-9]+: f3 aa rep stos %al,%es:\(%rdi\) + +[a-f0-9]+: f3 aa rep stos %al,\(%rdi\) +[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\) +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: f3 c3 repz ret --- a/gas/testsuite/gas/i386/x86-64-lfence-load.d +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d @@ -40,7 +40,7 @@ Disassembly of section .text: +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: 9d popf +[a-f0-9]+: 0f ae e8 lfence - +[a-f0-9]+: d7 xlat %ds:\(%rbx\) + +[a-f0-9]+: d7 xlat \(%rbx\) +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: d9 55 00 fsts 0x0\(%rbp\) +[a-f0-9]+: d9 45 00 flds 0x0\(%rbp\) @@ -109,17 +109,17 @@ Disassembly of section .text: +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: 48 8d 04 40 lea \(%rax,%rax,2\),%rax +[a-f0-9]+: c9 leave - +[a-f0-9]+: 6e outsb %ds:\(%rsi\),\(%dx\) + +[a-f0-9]+: 6e outsb \(%rsi\),\(%dx\) +[a-f0-9]+: 0f ae e8 lfence - +[a-f0-9]+: ac lods %ds:\(%rsi\),%al + +[a-f0-9]+: ac lods \(%rsi\),%al +[a-f0-9]+: 0f ae e8 lfence - +[a-f0-9]+: f3 a5 rep movsl %ds:\(%rsi\),%es:\(%rdi\) + +[a-f0-9]+: f3 a5 rep movsl \(%rsi\),\(%rdi\) +[a-f0-9]+: 0f ae e8 lfence - +[a-f0-9]+: f3 af repz scas %es:\(%rdi\),%eax + +[a-f0-9]+: f3 af repz scas \(%rdi\),%eax +[a-f0-9]+: 0f ae e8 lfence - +[a-f0-9]+: f3 a7 repz cmpsl %es:\(%rdi\),%ds:\(%rsi\) + +[a-f0-9]+: f3 a7 repz cmpsl \(%rdi\),\(%rsi\) +[a-f0-9]+: 0f ae e8 lfence - +[a-f0-9]+: f3 ad rep lods %ds:\(%rsi\),%eax + +[a-f0-9]+: f3 ad rep lods \(%rsi\),%eax +[a-f0-9]+: 0f ae e8 lfence +[a-f0-9]+: 41 83 03 01 addl \$0x1,\(%r11\) +[a-f0-9]+: 0f ae e8 lfence --- a/gas/testsuite/gas/i386/x86-64-rep.d +++ b/gas/testsuite/gas/i386/x86-64-rep.d @@ -6,56 +6,56 @@ Disassembly of section .text: 0+ <_start>: - 0: f3 6c[ ]+rep insb \(%dx\),%es:\(%rdi\) - 2: f3 6e[ ]+rep outsb %ds:\(%rsi\),\(%dx\) - 4: f3 a4[ ]+rep movsb %ds:\(%rsi\),%es:\(%rdi\) - 6: f3 ac[ ]+rep lods %ds:\(%rsi\),%al - 8: f3 aa[ ]+rep stos %al,%es:\(%rdi\) - a: f3 a6[ ]+repz cmpsb %es:\(%rdi\),%ds:\(%rsi\) - c: f3 ae[ ]+repz scas %es:\(%rdi\),%al - e: 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%rdi\) - 11: 66 f3 6f[ ]+rep outsw %ds:\(%rsi\),\(%dx\) - 14: 66 f3 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\) - 17: 66 f3 ad[ ]+rep lods %ds:\(%rsi\),%ax - 1a: 66 f3 ab[ ]+rep stos %ax,%es:\(%rdi\) - 1d: 66 f3 a7[ ]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\) - 20: 66 f3 af[ ]+repz scas %es:\(%rdi\),%ax - 23: f3 6d[ ]+rep insl \(%dx\),%es:\(%rdi\) - 25: f3 6f[ ]+rep outsl %ds:\(%rsi\),\(%dx\) - 27: f3 a5[ ]+rep movsl %ds:\(%rsi\),%es:\(%rdi\) - 29: f3 ad[ ]+rep lods %ds:\(%rsi\),%eax - 2b: f3 ab[ ]+rep stos %eax,%es:\(%rdi\) - 2d: f3 a7[ ]+repz cmpsl %es:\(%rdi\),%ds:\(%rsi\) - 2f: f3 af[ ]+repz scas %es:\(%rdi\),%eax - 31: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\) - 34: f3 48 ad[ ]+rep lods %ds:\(%rsi\),%rax - 37: f3 48 ab[ ]+rep stos %rax,%es:\(%rdi\) - 3a: f3 48 a7[ ]+repz cmpsq %es:\(%rdi\),%ds:\(%rsi\) - 3d: f3 48 af[ ]+repz scas %es:\(%rdi\),%rax - 40: 67 f3 6c[ ]+rep insb \(%dx\),%es:\(%edi\) - 43: 67 f3 6e[ ]+rep outsb %ds:\(%esi\),\(%dx\) - 46: 67 f3 a4[ ]+rep movsb %ds:\(%esi\),%es:\(%edi\) - 49: 67 f3 ac[ ]+rep lods %ds:\(%esi\),%al - 4c: 67 f3 aa[ ]+rep stos %al,%es:\(%edi\) - 4f: 67 f3 a6[ ]+repz cmpsb %es:\(%edi\),%ds:\(%esi\) - 52: 67 f3 ae[ ]+repz scas %es:\(%edi\),%al - 55: 67 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%edi\) - 59: 67 66 f3 6f[ ]+rep outsw %ds:\(%esi\),\(%dx\) - 5d: 67 66 f3 a5[ ]+rep movsw %ds:\(%esi\),%es:\(%edi\) - 61: 67 66 f3 ad[ ]+rep lods %ds:\(%esi\),%ax - 65: 67 66 f3 ab[ ]+rep stos %ax,%es:\(%edi\) - 69: 67 66 f3 a7[ ]+repz cmpsw %es:\(%edi\),%ds:\(%esi\) - 6d: 67 66 f3 af[ ]+repz scas %es:\(%edi\),%ax - 71: 67 f3 6d[ ]+rep insl \(%dx\),%es:\(%edi\) - 74: 67 f3 6f[ ]+rep outsl %ds:\(%esi\),\(%dx\) - 77: 67 f3 a5[ ]+rep movsl %ds:\(%esi\),%es:\(%edi\) - 7a: 67 f3 ad[ ]+rep lods %ds:\(%esi\),%eax - 7d: 67 f3 ab[ ]+rep stos %eax,%es:\(%edi\) - 80: 67 f3 a7[ ]+repz cmpsl %es:\(%edi\),%ds:\(%esi\) - 83: 67 f3 af[ ]+repz scas %es:\(%edi\),%eax - 86: 67 f3 48 a5[ ]+rep movsq %ds:\(%esi\),%es:\(%edi\) - 8a: 67 f3 48 ad[ ]+rep lods %ds:\(%esi\),%rax - 8e: 67 f3 48 ab[ ]+rep stos %rax,%es:\(%edi\) - 92: 67 f3 48 a7[ ]+repz cmpsq %es:\(%edi\),%ds:\(%esi\) - 96: 67 f3 48 af[ ]+repz scas %es:\(%edi\),%rax + 0: f3 6c[ ]+rep insb \(%dx\),\(%rdi\) + 2: f3 6e[ ]+rep outsb \(%rsi\),\(%dx\) + 4: f3 a4[ ]+rep movsb \(%rsi\),\(%rdi\) + 6: f3 ac[ ]+rep lods \(%rsi\),%al + 8: f3 aa[ ]+rep stos %al,\(%rdi\) + a: f3 a6[ ]+repz cmpsb \(%rdi\),\(%rsi\) + c: f3 ae[ ]+repz scas \(%rdi\),%al + e: 66 f3 6d[ ]+rep insw \(%dx\),\(%rdi\) + 11: 66 f3 6f[ ]+rep outsw \(%rsi\),\(%dx\) + 14: 66 f3 a5[ ]+rep movsw \(%rsi\),\(%rdi\) + 17: 66 f3 ad[ ]+rep lods \(%rsi\),%ax + 1a: 66 f3 ab[ ]+rep stos %ax,\(%rdi\) + 1d: 66 f3 a7[ ]+repz cmpsw \(%rdi\),\(%rsi\) + 20: 66 f3 af[ ]+repz scas \(%rdi\),%ax + 23: f3 6d[ ]+rep insl \(%dx\),\(%rdi\) + 25: f3 6f[ ]+rep outsl \(%rsi\),\(%dx\) + 27: f3 a5[ ]+rep movsl \(%rsi\),\(%rdi\) + 29: f3 ad[ ]+rep lods \(%rsi\),%eax + 2b: f3 ab[ ]+rep stos %eax,\(%rdi\) + 2d: f3 a7[ ]+repz cmpsl \(%rdi\),\(%rsi\) + 2f: f3 af[ ]+repz scas \(%rdi\),%eax + 31: f3 48 a5[ ]+rep movsq \(%rsi\),\(%rdi\) + 34: f3 48 ad[ ]+rep lods \(%rsi\),%rax + 37: f3 48 ab[ ]+rep stos %rax,\(%rdi\) + 3a: f3 48 a7[ ]+repz cmpsq \(%rdi\),\(%rsi\) + 3d: f3 48 af[ ]+repz scas \(%rdi\),%rax + 40: 67 f3 6c[ ]+rep insb \(%dx\),\(%edi\) + 43: 67 f3 6e[ ]+rep outsb \(%esi\),\(%dx\) + 46: 67 f3 a4[ ]+rep movsb \(%esi\),\(%edi\) + 49: 67 f3 ac[ ]+rep lods \(%esi\),%al + 4c: 67 f3 aa[ ]+rep stos %al,\(%edi\) + 4f: 67 f3 a6[ ]+repz cmpsb \(%edi\),\(%esi\) + 52: 67 f3 ae[ ]+repz scas \(%edi\),%al + 55: 67 66 f3 6d[ ]+rep insw \(%dx\),\(%edi\) + 59: 67 66 f3 6f[ ]+rep outsw \(%esi\),\(%dx\) + 5d: 67 66 f3 a5[ ]+rep movsw \(%esi\),\(%edi\) + 61: 67 66 f3 ad[ ]+rep lods \(%esi\),%ax + 65: 67 66 f3 ab[ ]+rep stos %ax,\(%edi\) + 69: 67 66 f3 a7[ ]+repz cmpsw \(%edi\),\(%esi\) + 6d: 67 66 f3 af[ ]+repz scas \(%edi\),%ax + 71: 67 f3 6d[ ]+rep insl \(%dx\),\(%edi\) + 74: 67 f3 6f[ ]+rep outsl \(%esi\),\(%dx\) + 77: 67 f3 a5[ ]+rep movsl \(%esi\),\(%edi\) + 7a: 67 f3 ad[ ]+rep lods \(%esi\),%eax + 7d: 67 f3 ab[ ]+rep stos %eax,\(%edi\) + 80: 67 f3 a7[ ]+repz cmpsl \(%edi\),\(%esi\) + 83: 67 f3 af[ ]+repz scas \(%edi\),%eax + 86: 67 f3 48 a5[ ]+rep movsq \(%esi\),\(%edi\) + 8a: 67 f3 48 ad[ ]+rep lods \(%esi\),%rax + 8e: 67 f3 48 ab[ ]+rep stos %rax,\(%edi\) + 92: 67 f3 48 a7[ ]+repz cmpsq \(%edi\),\(%esi\) + 96: 67 f3 48 af[ ]+repz scas \(%edi\),%rax #pass --- a/gas/testsuite/gas/i386/x86-64-rep-suffix.d +++ b/gas/testsuite/gas/i386/x86-64-rep-suffix.d @@ -6,14 +6,14 @@ Disassembly of section .text: 0+000 <_start>: - 0: f3 ac[ ]+rep lodsb %ds:\(%rsi\),%al - 2: f3 aa[ ]+rep stosb %al,%es:\(%rdi\) - 4: 66 f3 ad[ ]+rep lodsw %ds:\(%rsi\),%ax - 7: 66 f3 ab[ ]+rep stosw %ax,%es:\(%rdi\) - a: f3 ad[ ]+rep lodsl %ds:\(%rsi\),%eax - c: f3 ab[ ]+rep stosl %eax,%es:\(%rdi\) - e: f3 48 ad[ ]+rep lodsq %ds:\(%rsi\),%rax - 11: f3 48 ab[ ]+rep stosq %rax,%es:\(%rdi\) + 0: f3 ac[ ]+rep lodsb \(%rsi\),%al + 2: f3 aa[ ]+rep stosb %al,\(%rdi\) + 4: 66 f3 ad[ ]+rep lodsw \(%rsi\),%ax + 7: 66 f3 ab[ ]+rep stosw %ax,\(%rdi\) + a: f3 ad[ ]+rep lodsl \(%rsi\),%eax + c: f3 ab[ ]+rep stosl %eax,\(%rdi\) + e: f3 48 ad[ ]+rep lodsq \(%rsi\),%rax + 11: f3 48 ab[ ]+rep stosq %rax,\(%rdi\) 14: f3 0f bc c1[ ]+tzcntl %ecx,%eax 18: f3 0f bd c1[ ]+lzcntl %ecx,%eax 1c: f3 c3[ ]+repz retq\s* --- a/gas/testsuite/gas/i386/x86_64.d +++ b/gas/testsuite/gas/i386/x86_64.d @@ -38,9 +38,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 41 0f 20 c0 mov %cr0,%r8 [ ]*[a-f0-9]+: 44 0f 20 c0 mov %cr8,%rax [ ]*[a-f0-9]+: 44 0f 22 c0 mov %rax,%cr8 -[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\) -[ ]*[a-f0-9]+: 66 f3 a5 rep movsw %ds:\(%rsi\),%es:\(%rdi\) -[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\) +[ ]*[a-f0-9]+: f3 48 a5 rep movsq \(%rsi\),\(%rdi\) +[ ]*[a-f0-9]+: 66 f3 a5 rep movsw \(%rsi\),\(%rdi\) +[ ]*[a-f0-9]+: f3 48 a5 rep movsq \(%rsi\),\(%rdi\) [ ]*[a-f0-9]+: b0 11 mov \$0x11,%al [ ]*[a-f0-9]+: b4 11 mov \$0x11,%ah [ ]*[a-f0-9]+: 40 b4 11 mov \$0x11,%spl --- a/gas/testsuite/gas/i386/x86_64-intel.d +++ b/gas/testsuite/gas/i386/x86_64-intel.d @@ -38,9 +38,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 41 0f 20 c0 mov r8,cr0 [ ]*[a-f0-9]+: 44 0f 20 c0 mov rax,cr8 [ ]*[a-f0-9]+: 44 0f 22 c0 mov cr8,rax -[ ]*[a-f0-9]+: f3 48 a5 rep movs QWORD PTR es:\[rdi\],QWORD PTR ds:\[rsi\] -[ ]*[a-f0-9]+: 66 f3 a5 rep movs WORD PTR es:\[rdi\],WORD PTR ds:\[rsi\] -[ ]*[a-f0-9]+: f3 48 a5 rep movs QWORD PTR es:\[rdi\],QWORD PTR ds:\[rsi\] +[ ]*[a-f0-9]+: f3 48 a5 rep movs QWORD PTR \[rdi\],QWORD PTR \[rsi\] +[ ]*[a-f0-9]+: 66 f3 a5 rep movs WORD PTR \[rdi\],WORD PTR \[rsi\] +[ ]*[a-f0-9]+: f3 48 a5 rep movs QWORD PTR \[rdi\],QWORD PTR \[rsi\] [ ]*[a-f0-9]+: b0 11 mov al,0x11 [ ]*[a-f0-9]+: b4 11 mov ah,0x11 [ ]*[a-f0-9]+: 40 b4 11 mov spl,0x11 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -13126,8 +13126,11 @@ OP_ESreg (instr_info *ins, int code, int intel_operand_size (ins, b_mode, sizeflag); } } - oappend_register (ins, att_names_seg[0]); - oappend_char (ins, ':'); + if (ins->address_mode != mode_64bit) + { + oappend_register (ins, att_names_seg[0]); + oappend_char (ins, ':'); + } ptr_reg (ins, code, sizeflag); return true; } @@ -13151,9 +13154,9 @@ OP_DSreg (instr_info *ins, int code, int intel_operand_size (ins, b_mode, sizeflag); } } - /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the - default segment register DS is printed. */ - if (!ins->active_seg_prefix) + /* Outside of 64-bit mode set ins->active_seg_prefix to PREFIX_DS if it + is unset, so that the default segment register DS is printed. */ + if (ins->address_mode != mode_64bit && !ins->active_seg_prefix) ins->active_seg_prefix = PREFIX_DS; append_seg (ins); ptr_reg (ins, code, sizeflag); From patchwork Thu Jan 23 07:59:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 105281 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 83E71385840C for ; Thu, 23 Jan 2025 08:02:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 83E71385840C Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=suse.com header.i=@suse.com header.a=rsa-sha256 header.s=google header.b=HYktSXrJ X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-wm1-x32e.google.com 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm55615515e9.7.2025.01.22.23.59.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Jan 2025 23:59:40 -0800 (PST) Message-ID: <367987fe-c0b8-412a-a5ad-84ff6ab7c059@suse.com> Date: Thu, 23 Jan 2025 08:59:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/3] x86: RMPUPDATE wants operands in different form From: Jan Beulich To: Binutils Cc: "Kalvakuntla, Umesh" , "H.J. Lu" References: <862169bd-fa49-42a7-9081-7ac68e54f6f0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <862169bd-fa49-42a7-9081-7ac68e54f6f0@suse.com> X-Spam-Status: No, score=-3022.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org AMD are about to update their doc, to help clarify that what we currently do isn't quite right: In particular it is not %rax but %rcx which is affected by address size. In fact, that's a normal memory operand, just not expressed via ModR/M byte, but fixed to (%rcx) (or (%ecx) with 32-bit addressing). To support this in the assembler, generalize memory operand handling so far specific to XLAT (which isn't really a string insn, but requires its memory operand to be (%bx) / (%ebx) / (%rbx)). In the disassembler mimic handling after XLAT's, too. --- As said above, having the rAX operand affect address size is wrong. I'm uncertain though whether in the two affected templates we should actually correct this, as people may in principle already be using either of those forms to control the address size prefix (short of a correct way for doing so). Then again it seems pretty unlikely that address size overrides might be used in practice with this insn, for other than testcase purposes. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -6999,10 +6999,10 @@ i386_assemble (char *line) /* All Intel opcodes have reversed operands except for "bound", "enter", "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", - "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse - intersegment "jmp" and "call" instructions with 2 immediate operands so - that the immediate segment precedes the offset consistently in Intel and - AT&T modes. */ + "rmpadjust", "rmpquery", and deprecated forms of "rmpupdate". + We also don't reverse intersegment "jmp" and "call" instructions with + 2 immediate operands so that the immediate segment precedes the offset + consistently in Intel and AT&T modes. */ if (intel_syntax && i.operands > 1 && (t->mnem_off != MN_bound) @@ -7010,7 +7010,7 @@ i386_assemble (char *line) && !startswith (mnemonic, "monitor") && !startswith (mnemonic, "mwait") && (t->mnem_off != MN_pvalidate) - && !startswith (mnemonic, "rmp") + && (!startswith (mnemonic, "rmp") || i.mem_operands) && (t->mnem_off != MN_tpause) && (t->mnem_off != MN_umwait) && !(i.operands == 2 @@ -14878,7 +14878,7 @@ i386_index_check (const char *operand_st if (t->opcode_modifier.isstring) { /* Memory operands of string insns are special in that they only allow - a single register (rDI, rSI, or rBX) as their memory address. */ + a single register (rDI or rSI) as their memory address. */ const reg_entry *expected_reg; static const char di_si[][2][4] = { @@ -14886,7 +14886,14 @@ i386_index_check (const char *operand_st { "si", "di" }, { "rsi", "rdi" } }; - static const char bx[][4] = { "ebx", "bx", "rbx" }; + /* For a few other insns with fixed register addressing we (ab)use the + IsString attribute as well. */ + static const char loregs[][4][4] = + { + { "eax", "ecx", "edx", "ebx" }, + { "ax", "cx", "dx", "bx" }, + { "rax", "rcx", "rdx", "rbx" } + }; kind = "string address"; @@ -14904,8 +14911,16 @@ i386_index_check (const char *operand_st di_si[addr_mode][op == es_op]); } else - expected_reg - = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); + { + unsigned int op = t->operand_types[0].bitfield.baseindex ? 0 : 1; + + if (!t->operand_types[op].bitfield.instance) + return 1; /* Operand mismatch will be detected elsewhere. */ + expected_reg + = str_hash_find (reg_hash, + loregs[addr_mode][t->operand_types[op] + .bitfield.instance - 1]); + } if (i.base_reg != expected_reg || i.index_reg --- a/gas/testsuite/gas/i386/snp.s +++ b/gas/testsuite/gas/i386/snp.s @@ -11,7 +11,8 @@ att: psmash %eax rmpupdate rmpupdate %rax, %rcx - rmpupdate %eax, %rcx + rmpupdate (%rcx), %rax + rmpupdate (%ecx), %rax rmpadjust rmpadjust %rax, %rcx, %rdx rmpadjust %eax, %rcx, %rdx @@ -30,7 +31,8 @@ intel: psmash eax rmpupdate rmpupdate rax, rcx - rmpupdate eax, rcx + rmpupdate rax, [rcx] + rmpupdate rax, [ecx] rmpadjust rmpadjust rax, rcx, rdx rmpadjust eax, rcx, rdx --- a/gas/testsuite/gas/i386/snp64.d +++ b/gas/testsuite/gas/i386/snp64.d @@ -14,9 +14,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash [ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash [ ]*[a-f0-9]+:[ ]+67 f3 0f 01 ff[ ]+addr32 psmash -[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate -[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate -[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+addr32 rmpupdate +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate \(%rcx\),%rax +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate \(%rcx\),%rax +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate \(%rcx\),%rax +[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+rmpupdate \(%ecx\),%rax [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+67 f3 0f 01 fe[ ]+addr32 rmpadjust @@ -28,9 +29,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash [ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash [ ]*[a-f0-9]+:[ ]+67 f3 0f 01 ff[ ]+addr32 psmash -[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate -[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate -[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+addr32 rmpupdate +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate \(%rcx\),%rax +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate \(%rcx\),%rax +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate \(%rcx\),%rax +[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+rmpupdate \(%ecx\),%rax [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+67 f3 0f 01 fe[ ]+addr32 rmpadjust --- a/gas/testsuite/gas/i386/x86-64-arch-4.d +++ b/gas/testsuite/gas/i386/x86-64-arch-4.d @@ -25,7 +25,7 @@ Disassembly of section .text: [ ]*[a-f0-9]+: c4 e2 4d df 39[ ]+vaesdeclast \(%rcx\),%ymm6,%ymm7 [ ]*[a-f0-9]+: f3 0f 01 ff[ ]+psmash [ ]*[a-f0-9]+: f2 0f 01 ff[ ]+pvalidate -[ ]*[a-f0-9]+: f2 0f 01 fe[ ]+rmpupdate +[ ]*[a-f0-9]+: f2 0f 01 fe[ ]+rmpupdate \(%rcx\),%rax [ ]*[a-f0-9]+: f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+: 66 0f 38 82 10[ ]+invpcid \(%rax\),%rdx [ ]*[a-f0-9]+: 0f 01 ee[ ]+rdpkru --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -524,6 +524,7 @@ fetch_error (const instr_info *ins) #define Xz { OP_DSreg, eSI_reg } #define Yb { OP_ESreg, eDI_reg } #define Yv { OP_ESreg, eDI_reg } +#define DSCX { OP_DSreg, eCX_reg } #define DSBX { OP_DSreg, eBX_reg } #define es { OP_REG, es_reg } @@ -4640,7 +4641,7 @@ static const struct dis386 x86_64_table[ /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ { { Bad_Opcode }, - { "rmpupdate", { Skip_MODRM }, 0 }, + { "rmpupdate", { RMrAX, DSCX, Skip_MODRM }, 0 }, }, /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */ @@ -13142,6 +13143,8 @@ OP_DSreg (instr_info *ins, int code, int { switch (ins->codep[-1]) { + case 0x01: /* rmpupdate */ + break; case 0x6f: /* outsw/outsl */ intel_operand_size (ins, z_mode, sizeflag); break; --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -596,7 +596,7 @@ ssto, 0xaa, 0, W|No_sSuf|RepPrefixOk, {} ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IntelSuffix, {} -xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString|IntelSuffix, { Byte|Unspecified|BaseIndex } +xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString|IntelSuffix, { RegB|Byte|Unspecified|BaseIndex } // Bit manipulation. bsf, 0xfbc, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } @@ -3159,6 +3159,7 @@ psmash, 0xf30f01ff, SNP&x64, NoSuf, {} psmash, 0xf30f01ff, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } pvalidate, 0xf20f01ff, SNP, NoSuf, {} pvalidate, 0xf20f01ff, SNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +// These two forms exist only for compatibility with older gas. rmpupdate, 0xf20f01fe, SNP&x64, NoSuf, {} rmpupdate, 0xf20f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } rmpadjust, 0xf30f01fe, SNP&x64, NoSuf, {} @@ -3168,6 +3169,9 @@ pvalidate, 0xf20f01ff, SNP, AddrPrefixOp rmpupdate, 0xf20f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } rmpadjust, 0xf30f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +// This must come last, for its IsString attribute to take effect. +rmpupdate, 0xf20f01fe, SNP&x64, IsString|NoSuf|NoRex64, { RegC|Unspecified|BaseIndex, Acc|Qword } + // SNP instructions end // RMPQUERY instruction From patchwork Thu Jan 23 08:01:42 2025 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31a21adsm52437655e9.12.2025.01.23.00.01.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Jan 2025 00:01:42 -0800 (PST) Message-ID: <1fedd7b9-19f2-4f6f-aa77-e103830913b6@suse.com> Date: Thu, 23 Jan 2025 09:01:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 3/3] x86: support RMPREAD insn From: Jan Beulich To: Binutils Cc: "Kalvakuntla, Umesh" , "H.J. Lu" References: <862169bd-fa49-42a7-9081-7ac68e54f6f0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <862169bd-fa49-42a7-9081-7ac68e54f6f0@suse.com> X-Spam-Status: No, score=-3022.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Like for RMPUPDATE documentation is about to change as far as operands are concerned. They're merely the other way around here. While adjustind gas documentation, also add the missing RMPQUERY counterparts there. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1214,6 +1214,7 @@ static const arch_entry cpu_arch[] = VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset), SUBARCH (rao_int, RAO_INT, RAO_INT, false), SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), + SUBARCH (rmpread, RMPREAD, ANY_RMPREAD, false), SUBARCH (fred, FRED, ANY_FRED, false), SUBARCH (lkgs, LKGS, ANY_LKGS, false), VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset), --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -281,6 +281,8 @@ accept various extension mnemonics. For @code{snp}, @code{invlpgb}, @code{tlbsync}, +@code{rmpquery}, +@code{rmpread}, @code{svme}, @code{gmism2}, @code{gmiccs}, @@ -1719,8 +1721,8 @@ supported on the CPU specified. The cho @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} -@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmism2} @tab @samp{.gmiccs} -@item @samp{.padlockrng2} @tab @samp{.padlockphe2} +@item @samp{.tlbsync} @tab @samp{.rmpquery} @tab @samp{.rmpread} @tab @samp{.apx_f} +@item @samp{.gmism2} @tab @samp{.gmiccs} @tab @samp{.padlockrng2} @tab @samp{.padlockphe2} @end multitable --- a/gas/testsuite/gas/i386/snp.s +++ b/gas/testsuite/gas/i386/snp.s @@ -16,6 +16,8 @@ att: rmpadjust rmpadjust %rax, %rcx, %rdx rmpadjust %eax, %rcx, %rdx + rmpread %rax, (%rcx) + rmpread %rax, (%ecx) .else pvalidate %ax, %ecx, %edx .endif @@ -36,6 +38,8 @@ intel: rmpadjust rmpadjust rax, rcx, rdx rmpadjust eax, rcx, rdx + rmpread [rcx], rax + rmpread [ecx], rax .else pvalidate ax, ecx, edx .endif --- a/gas/testsuite/gas/i386/snp64.d +++ b/gas/testsuite/gas/i386/snp64.d @@ -21,6 +21,8 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+67 f3 0f 01 fe[ ]+addr32 rmpadjust +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fd[ ]+rmpread %rax,\(%rcx\) +[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fd[ ]+rmpread %rax,\(%ecx\) [0-9a-f]+ : [ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate @@ -36,4 +38,6 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust [ ]*[a-f0-9]+:[ ]+67 f3 0f 01 fe[ ]+addr32 rmpadjust +[ ]*[a-f0-9]+:[ ]+f2 0f 01 fd[ ]+rmpread %rax,\(%rcx\) +[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fd[ ]+rmpread %rax,\(%ecx\) #pass --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1347,6 +1347,7 @@ enum X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1, + X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3, X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, @@ -3253,6 +3254,8 @@ static const struct dis386 prefix_table[ { { "rdpru", { Skip_MODRM }, 0 }, { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3) }, }, /* PREFIX_0F01_REG_7_MOD_3_RM_6 */ @@ -4632,6 +4635,12 @@ static const struct dis386 x86_64_table[ { "rmpquery", { Skip_MODRM }, 0 }, }, + /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ + { + { Bad_Opcode }, + { "rmpread", { DSCX, RMrAX, Skip_MODRM }, 0 }, + }, + /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */ { { Bad_Opcode }, @@ -13143,7 +13152,7 @@ OP_DSreg (instr_info *ins, int code, int { switch (ins->codep[-1]) { - case 0x01: /* rmpupdate */ + case 0x01: /* rmpupdate/rmpread */ break; case 0x6f: /* outsw/outsl */ intel_operand_size (ins, z_mode, sizeflag); --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -251,6 +251,8 @@ static const dependency isa_dependencies "SEV_ES" }, { "RMPQUERY", "SNP|64" }, + { "RMPREAD", + "SNP|64" }, { "TSX", "RTM|HLE" }, { "TSXLDTRK", @@ -470,6 +472,7 @@ static bitfield cpu_flags[] = BITFIELD (TLBSYNC), BITFIELD (SNP), BITFIELD (RMPQUERY), + BITFIELD (RMPREAD), BITFIELD (64), BITFIELD (No64), #ifdef CpuUnused --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -316,6 +316,8 @@ enum i386_cpu CpuSNP, /* RMPQUERY instruction required */ CpuRMPQUERY, + /* RMPREAD instruction required */ + CpuRMPREAD, /* NOTE: These items, which can be combined with other ISA flags above, need to remain second to last and in sync with CPU_FLAGS_COMMON. */ @@ -549,6 +551,7 @@ typedef union i386_cpu_flags unsigned int cputlbsync:1; unsigned int cpusnp:1; unsigned int cpurmpquery:1; + unsigned int cpurmpread:1; CPU_FLAGS_COMMON; #ifdef CpuUnused unsigned int unused:(CpuNumOfBits - CpuUnused); --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3181,6 +3181,12 @@ rmpquery, 0xf30f01fd, RMPQUERY, AddrPref // RMPQUERY instruction end +// RMPREAD instruction + +rmpread, 0xf20f01fd, RMPREAD&x64, IsString|NoSuf|NoRex64, { Acc|Qword, RegC|Unspecified|BaseIndex } + +// RMPREAD instruction end + // RDPRU instruction rdpru, 0x0f01fd, RDPRU, NoSuf, {}