From patchwork Wed Dec 4 18:02:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 102416 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D1EE83858404 for ; Wed, 4 Dec 2024 18:04:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D1EE83858404 X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B85043858C52 for ; Wed, 4 Dec 2024 18:03:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B85043858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B85043858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733335398; cv=none; b=k7DcgtU76E+VmZqlTDXehE3Sa9Zzz+cvSh4mmCOQEgcw+niQHn5f9u3WY3lnSrHfOsmIjh8PRxd+WeFbu3nuv1MtmkOTOIAoDSVoiDDMXjavVFF4GuGZoG0dc0judS0+ZbbD2858eBAMn8DXotkWmT5KbEXjq6PGXhOfJzC8A6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733335398; c=relaxed/simple; bh=vUxk1SMd9NLajCfEIIJP9jD3sgBgCggDYfuqRTxP+Lc=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=VNyzAxsI02hJ7VTNkyr1W9lrowHuXlAOWGQnUyekQlloWfQ3tIB8UCZ6ZkNHbED/qQ/yJj6iUKtwJCwlcgzYsO6JSisvFJqlMktpclqAxq01r3drVbzZfv3iegCxa+MuTWu34EnsLUUoSZZU0iKt+6wj7g8oFRxIdHQaiMIripQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B85043858C52 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 61BCA1063; Wed, 4 Dec 2024 10:03:46 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7BB213F5A1; Wed, 4 Dec 2024 10:03:17 -0800 (PST) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@nvidia.com, pinskia@gmail.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 1/4] aarch64: Rename FLAG_AUTO_FP to FLAG_QUIET Date: Wed, 4 Dec 2024 18:02:41 +0000 Message-Id: <20241204180244.4077058-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241204180244.4077058-1-richard.sandiford@arm.com> References: <20241204180244.4077058-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-18.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org I'd suggested the name "FLAG_AUTO_FP" to mean "automatically derive FLAG_FP from the mode", i.e. automatically decide whether the function might read the FPCR or might raise FP exceptions. However, the flag currently suppresses that behaviour instead. This patch renames FLAG_AUTO_FP to FLAG_QUIET. That's probably not a great name, but it's also what the SVE code means by "quiet", and is borrowed from "quiet NaNs". gcc/ * config/aarch64/aarch64-builtins.cc (FLAG_AUTO_FP): Rename to... (FLAG_QUIET): ...this and update all references. * config/aarch64/aarch64-simd-builtins.def: Update all references here too. --- gcc/config/aarch64/aarch64-builtins.cc | 10 +++--- gcc/config/aarch64/aarch64-simd-builtins.def | 36 ++++++++++---------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 22f8216a45b..4f735e8e58b 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -202,13 +202,13 @@ const unsigned int FLAG_WRITE_MEMORY = 1U << 4; /* Not all FP intrinsics raise FP exceptions or read FPCR register, use this flag to suppress it. */ -const unsigned int FLAG_AUTO_FP = 1U << 5; +const unsigned int FLAG_QUIET = 1U << 5; const unsigned int FLAG_FP = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS; const unsigned int FLAG_ALL = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS | FLAG_READ_MEMORY | FLAG_PREFETCH_MEMORY | FLAG_WRITE_MEMORY; -const unsigned int FLAG_STORE = FLAG_WRITE_MEMORY | FLAG_AUTO_FP; -const unsigned int FLAG_LOAD = FLAG_READ_MEMORY | FLAG_AUTO_FP; +const unsigned int FLAG_STORE = FLAG_WRITE_MEMORY | FLAG_QUIET; +const unsigned int FLAG_LOAD = FLAG_READ_MEMORY | FLAG_QUIET; typedef struct { @@ -1322,7 +1322,7 @@ aarch64_init_simd_builtin_scalar_types (void) static unsigned int aarch64_call_properties (unsigned int flags, machine_mode mode) { - if (!(flags & FLAG_AUTO_FP) && FLOAT_MODE_P (mode)) + if (!(flags & FLAG_QUIET) && FLOAT_MODE_P (mode)) flags |= FLAG_FP; /* -fno-trapping-math means that we can assume any FP exceptions @@ -4061,7 +4061,7 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt)); break; - BUILTIN_VDC (BINOP, combine, 0, AUTO_FP) + BUILTIN_VDC (BINOP, combine, 0, QUIET) BUILTIN_VD_I (BINOPU, combine, 0, NONE) BUILTIN_VDC_P (BINOPP, combine, 0, NONE) { diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 0814f8ba14f..3df2773380e 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -50,7 +50,7 @@ BUILTIN_V12DI (STORESTRUCT_LANE_U, vec_stl1_lane, 0, ALL) BUILTIN_V12DI (STORESTRUCT_LANE_P, vec_stl1_lane, 0, ALL) - BUILTIN_VDC (BINOP, combine, 0, AUTO_FP) + BUILTIN_VDC (BINOP, combine, 0, QUIET) BUILTIN_VD_I (BINOPU, combine, 0, NONE) BUILTIN_VDC_P (BINOPP, combine, 0, NONE) BUILTIN_VB (BINOPP, pmul, 0, NONE) @@ -657,12 +657,12 @@ /* Implemented by aarch64_. */ - BUILTIN_VALL (BINOP, zip1, 0, AUTO_FP) - BUILTIN_VALL (BINOP, zip2, 0, AUTO_FP) - BUILTIN_VALL (BINOP, uzp1, 0, AUTO_FP) - BUILTIN_VALL (BINOP, uzp2, 0, AUTO_FP) - BUILTIN_VALL (BINOP, trn1, 0, AUTO_FP) - BUILTIN_VALL (BINOP, trn2, 0, AUTO_FP) + BUILTIN_VALL (BINOP, zip1, 0, QUIET) + BUILTIN_VALL (BINOP, zip2, 0, QUIET) + BUILTIN_VALL (BINOP, uzp1, 0, QUIET) + BUILTIN_VALL (BINOP, uzp2, 0, QUIET) + BUILTIN_VALL (BINOP, trn1, 0, QUIET) + BUILTIN_VALL (BINOP, trn2, 0, QUIET) BUILTIN_GPF_F16 (UNOP, frecpe, 0, FP) BUILTIN_GPF_F16 (UNOP, frecpx, 0, FP) @@ -674,9 +674,9 @@ /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is only ever used for the int64x1_t intrinsic, there is no scalar version. */ - BUILTIN_VSDQ_I_DI (UNOP, abs, 0, AUTO_FP) - BUILTIN_VHSDF (UNOP, abs, 2, AUTO_FP) - VAR1 (UNOP, abs, 2, AUTO_FP, hf) + BUILTIN_VSDQ_I_DI (UNOP, abs, 0, QUIET) + BUILTIN_VHSDF (UNOP, abs, 2, QUIET) + VAR1 (UNOP, abs, 2, QUIET, hf) BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10, FP) VAR1 (BINOP, float_truncate_hi_, 0, FP, v4sf) @@ -720,7 +720,7 @@ BUILTIN_VDQQH (BSL_P, simd_bsl, 0, NONE) VAR2 (BSL_P, simd_bsl,0, NONE, di, v2di) BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0, NONE) - BUILTIN_VALLDIF (BSL_S, simd_bsl, 0, AUTO_FP) + BUILTIN_VALLDIF (BSL_S, simd_bsl, 0, QUIET) /* Implemented by aarch64_crypto_aes. */ VAR1 (BINOPU, crypto_aese, 0, NONE, v16qi) @@ -940,12 +940,12 @@ BUILTIN_VSFDF (UNOP, frint64x, 0, FP) /* Implemented by aarch64_bfdot{_lane}{q}. */ - VAR2 (TERNOP, bfdot, 0, AUTO_FP, v2sf, v4sf) - VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, AUTO_FP, v2sf, v4sf) - VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, AUTO_FP, v2sf, v4sf) + VAR2 (TERNOP, bfdot, 0, QUIET, v2sf, v4sf) + VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, QUIET, v2sf, v4sf) + VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, QUIET, v2sf, v4sf) /* Implemented by aarch64_bfmmlaqv4sf */ - VAR1 (TERNOP, bfmmlaq, 0, AUTO_FP, v4sf) + VAR1 (TERNOP, bfmmlaq, 0, QUIET, v4sf) /* Implemented by aarch64_bfmlal{_lane{q}}v4sf */ VAR1 (TERNOP, bfmlalb, 0, FP, v4sf) @@ -967,6 +967,6 @@ VAR1 (UNOP, bfcvt, 0, FP, bf) /* Implemented by aarch64_{v}bfcvt{_high}. */ - VAR2 (UNOP, vbfcvt, 0, AUTO_FP, v4bf, v8bf) - VAR1 (UNOP, vbfcvt_high, 0, AUTO_FP, v8bf) - VAR1 (UNOP, bfcvt, 0, AUTO_FP, sf) + VAR2 (UNOP, vbfcvt, 0, QUIET, v4bf, v8bf) + VAR1 (UNOP, vbfcvt_high, 0, QUIET, v8bf) + VAR1 (UNOP, bfcvt, 0, QUIET, sf) From patchwork Wed Dec 4 18:02:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 102417 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AF1F33858402 for ; Wed, 4 Dec 2024 18:04:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AF1F33858402 X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id D42863858C66 for ; Wed, 4 Dec 2024 18:03:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D42863858C66 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D42863858C66 Authentication-Results: server2.sourceware.org; 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Wed, 4 Dec 2024 10:03:28 -0800 (PST) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@nvidia.com, pinskia@gmail.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 2/4] aarch64: Rename FLAG_NONE to FLAG_DEFAULT Date: Wed, 4 Dec 2024 18:02:42 +0000 Message-Id: <20241204180244.4077058-3-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241204180244.4077058-1-richard.sandiford@arm.com> References: <20241204180244.4077058-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-18.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, UPPERCASE_50_75, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org This patch renames to FLAG_NONE to FLAG_DEFAULT. "NONE" suggests that the function has no side-effects, whereas it actually means that floating-point operations are assumed to read FPCR and to raise FP exceptions. gcc/ * config/aarch64/aarch64-builtins.cc (FLAG_NONE): Rename to... (FLAG_DEFAULT): ...this and update all references. * config/aarch64/aarch64-simd-builtins.def: Update all references here too. * config/aarch64/aarch64-simd-pragma-builtins.def: Likewise. --- gcc/config/aarch64/aarch64-builtins.cc | 32 +- gcc/config/aarch64/aarch64-simd-builtins.def | 726 +++++++++--------- .../aarch64/aarch64-simd-pragma-builtins.def | 24 +- 3 files changed, 391 insertions(+), 391 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 4f735e8e58b..eb44580bd9c 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -193,7 +193,7 @@ using namespace aarch64; #define SIMD_MAX_BUILTIN_ARGS 5 /* Flags that describe what a function might do. */ -const unsigned int FLAG_NONE = 0U; +const unsigned int FLAG_DEFAULT = 0U; const unsigned int FLAG_READ_FPCR = 1U << 0; const unsigned int FLAG_RAISE_FP_EXCEPTIONS = 1U << 1; const unsigned int FLAG_READ_MEMORY = 1U << 2; @@ -913,7 +913,7 @@ static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = { 2, \ { SIMD_INTR_MODE(A, L), SIMD_INTR_MODE(B, L) }, \ { SIMD_INTR_QUAL(A), SIMD_INTR_QUAL(B) }, \ - FLAG_NONE, \ + FLAG_DEFAULT, \ SIMD_INTR_MODE(A, L) == SIMD_INTR_MODE(B, L) \ && SIMD_INTR_QUAL(A) == SIMD_INTR_QUAL(B) \ }, @@ -925,7 +925,7 @@ static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = { 2, \ { SIMD_INTR_MODE(A, d), SIMD_INTR_MODE(A, q) }, \ { SIMD_INTR_QUAL(A), SIMD_INTR_QUAL(A) }, \ - FLAG_NONE, \ + FLAG_DEFAULT, \ false \ }, @@ -936,7 +936,7 @@ static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = { 2, \ { SIMD_INTR_MODE(A, d), SIMD_INTR_MODE(A, q) }, \ { SIMD_INTR_QUAL(A), SIMD_INTR_QUAL(A) }, \ - FLAG_NONE, \ + FLAG_DEFAULT, \ false \ }, @@ -1857,7 +1857,7 @@ aarch64_init_crc32_builtins () aarch64_crc_builtin_datum* d = &aarch64_crc_builtin_data[i]; tree argtype = aarch64_simd_builtin_type (d->mode, qualifier_unsigned); tree ftype = build_function_type_list (usi_type, usi_type, argtype, NULL_TREE); - tree attrs = aarch64_get_attributes (FLAG_NONE, d->mode); + tree attrs = aarch64_get_attributes (FLAG_DEFAULT, d->mode); tree fndecl = aarch64_general_add_builtin (d->name, ftype, d->fcode, attrs); @@ -2232,7 +2232,7 @@ static void aarch64_init_data_intrinsics (void) { /* These intrinsics are not fp nor they read/write memory. */ - tree attrs = aarch64_get_attributes (FLAG_NONE, SImode); + tree attrs = aarch64_get_attributes (FLAG_DEFAULT, SImode); tree uint32_fntype = build_function_type_list (uint32_type_node, uint32_type_node, NULL_TREE); tree ulong_fntype = build_function_type_list (long_unsigned_type_node, @@ -4048,7 +4048,7 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, switch (fcode) { BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, ALL) - BUILTIN_VDQ_I (UNOPU, reduc_plus_scal_, 10, NONE) + BUILTIN_VDQ_I (UNOPU, reduc_plus_scal_, 10, DEFAULT) new_stmt = gimple_build_call_internal (IFN_REDUC_PLUS, 1, args[0]); gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt)); @@ -4062,8 +4062,8 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, break; BUILTIN_VDC (BINOP, combine, 0, QUIET) - BUILTIN_VD_I (BINOPU, combine, 0, NONE) - BUILTIN_VDC_P (BINOPP, combine, 0, NONE) + BUILTIN_VD_I (BINOPU, combine, 0, DEFAULT) + BUILTIN_VDC_P (BINOPP, combine, 0, DEFAULT) { tree first_part, second_part; if (BYTES_BIG_ENDIAN) @@ -4152,14 +4152,14 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, 1, args[0]); gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt)); break; - BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, NONE) + BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, DEFAULT) if (TREE_CODE (args[1]) == INTEGER_CST && wi::ltu_p (wi::to_wide (args[1]), element_precision (args[0]))) new_stmt = gimple_build_assign (gimple_call_lhs (stmt), LSHIFT_EXPR, args[0], args[1]); break; - BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, NONE) - BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, NONE) + BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, DEFAULT) { tree cst = args[1]; tree ctype = TREE_TYPE (cst); @@ -4191,10 +4191,10 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, } } break; - BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, NONE) - VAR1 (SHIFTIMM, ashr_simd, 0, NONE, di) - BUILTIN_VDQ_I (USHIFTIMM, lshr, 3, NONE) - VAR1 (USHIFTIMM, lshr_simd, 0, NONE, di) + BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, DEFAULT) + VAR1 (SHIFTIMM, ashr_simd, 0, DEFAULT, di) + BUILTIN_VDQ_I (USHIFTIMM, lshr, 3, DEFAULT) + VAR1 (USHIFTIMM, lshr_simd, 0, DEFAULT, di) if (TREE_CODE (args[1]) == INTEGER_CST && wi::ltu_p (wi::to_wide (args[1]), element_precision (args[0]))) new_stmt = gimple_build_assign (gimple_call_lhs (stmt), diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 3df2773380e..b20dff956b8 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -51,33 +51,33 @@ BUILTIN_V12DI (STORESTRUCT_LANE_P, vec_stl1_lane, 0, ALL) BUILTIN_VDC (BINOP, combine, 0, QUIET) - BUILTIN_VD_I (BINOPU, combine, 0, NONE) - BUILTIN_VDC_P (BINOPP, combine, 0, NONE) - BUILTIN_VB (BINOPP, pmul, 0, NONE) - VAR1 (BINOPP, pmull, 0, NONE, v8qi) - VAR1 (BINOPP, pmull_hi, 0, NONE, v16qi) + BUILTIN_VD_I (BINOPU, combine, 0, DEFAULT) + BUILTIN_VDC_P (BINOPP, combine, 0, DEFAULT) + BUILTIN_VB (BINOPP, pmul, 0, DEFAULT) + VAR1 (BINOPP, pmull, 0, DEFAULT, v8qi) + VAR1 (BINOPP, pmull_hi, 0, DEFAULT, v16qi) BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0, FP) BUILTIN_VHSDF_DF (UNOP, sqrt, 2, FP) - BUILTIN_VDQ_I (BINOP, addp, 0, NONE) - BUILTIN_VDQ_I (BINOPU, addp, 0, NONE) - BUILTIN_VDQ_BHSI (UNOP, clrsb, 2, NONE) - BUILTIN_VDQ_BHSI (UNOP, clz, 2, NONE) - BUILTIN_VS (UNOP, ctz, 2, NONE) - BUILTIN_VB (UNOP, popcount, 2, NONE) + BUILTIN_VDQ_I (BINOP, addp, 0, DEFAULT) + BUILTIN_VDQ_I (BINOPU, addp, 0, DEFAULT) + BUILTIN_VDQ_BHSI (UNOP, clrsb, 2, DEFAULT) + BUILTIN_VDQ_BHSI (UNOP, clz, 2, DEFAULT) + BUILTIN_VS (UNOP, ctz, 2, DEFAULT) + BUILTIN_VB (UNOP, popcount, 2, DEFAULT) /* Implemented by aarch64_qshl. */ - BUILTIN_VSDQ_I (BINOP, sqshl, 0, NONE) - BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0, NONE) - BUILTIN_VSDQ_I (BINOP, sqrshl, 0, NONE) - BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0, NONE) + BUILTIN_VSDQ_I (BINOP, sqshl, 0, DEFAULT) + BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0, DEFAULT) + BUILTIN_VSDQ_I (BINOP, sqrshl, 0, DEFAULT) + BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0, DEFAULT) /* Implemented by aarch64_. */ - BUILTIN_VSDQ_I (BINOP, sqadd, 0, NONE) - BUILTIN_VSDQ_I (BINOPU, uqadd, 0, NONE) - BUILTIN_VSDQ_I (BINOP, sqsub, 0, NONE) - BUILTIN_VSDQ_I (BINOPU, uqsub, 0, NONE) + BUILTIN_VSDQ_I (BINOP, sqadd, 0, DEFAULT) + BUILTIN_VSDQ_I (BINOPU, uqadd, 0, DEFAULT) + BUILTIN_VSDQ_I (BINOP, sqsub, 0, DEFAULT) + BUILTIN_VSDQ_I (BINOPU, uqsub, 0, DEFAULT) /* Implemented by aarch64_qadd. */ - BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0, NONE) - BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0, NONE) + BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0, DEFAULT) + BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0, DEFAULT) /* Implemented by aarch64_ld1x2. */ BUILTIN_VALLDIF (LOADSTRUCT, ld1x2, 0, LOAD) @@ -160,276 +160,276 @@ BUILTIN_VSDQ_I_DI (STORESTRUCT_LANE_U, st4_lane, 0, ALL) BUILTIN_VALLP (STORESTRUCT_LANE_P, st4_lane, 0, ALL) - BUILTIN_VQW (BINOP, saddl2, 0, NONE) - BUILTIN_VQW (BINOPU, uaddl2, 0, NONE) - BUILTIN_VQW (BINOP, ssubl2, 0, NONE) - BUILTIN_VQW (BINOPU, usubl2, 0, NONE) - BUILTIN_VQW (BINOP, saddw2, 0, NONE) - BUILTIN_VQW (BINOPU, uaddw2, 0, NONE) - BUILTIN_VQW (BINOP, ssubw2, 0, NONE) - BUILTIN_VQW (BINOPU, usubw2, 0, NONE) + BUILTIN_VQW (BINOP, saddl2, 0, DEFAULT) + BUILTIN_VQW (BINOPU, uaddl2, 0, DEFAULT) + BUILTIN_VQW (BINOP, ssubl2, 0, DEFAULT) + BUILTIN_VQW (BINOPU, usubl2, 0, DEFAULT) + BUILTIN_VQW (BINOP, saddw2, 0, DEFAULT) + BUILTIN_VQW (BINOPU, uaddw2, 0, DEFAULT) + BUILTIN_VQW (BINOP, ssubw2, 0, DEFAULT) + BUILTIN_VQW (BINOPU, usubw2, 0, DEFAULT) /* Implemented by aarch64_l. */ - BUILTIN_VD_BHSI (BINOP, saddl, 0, NONE) - BUILTIN_VD_BHSI (BINOPU, uaddl, 0, NONE) - BUILTIN_VD_BHSI (BINOP, ssubl, 0, NONE) - BUILTIN_VD_BHSI (BINOPU, usubl, 0, NONE) + BUILTIN_VD_BHSI (BINOP, saddl, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOPU, uaddl, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOP, ssubl, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOPU, usubl, 0, DEFAULT) /* Implemented by aarch64_w. */ - BUILTIN_VD_BHSI (BINOP, saddw, 0, NONE) - BUILTIN_VD_BHSI (BINOPU, uaddw, 0, NONE) - BUILTIN_VD_BHSI (BINOP, ssubw, 0, NONE) - BUILTIN_VD_BHSI (BINOPU, usubw, 0, NONE) + BUILTIN_VD_BHSI (BINOP, saddw, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOPU, uaddw, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOP, ssubw, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOPU, usubw, 0, DEFAULT) /* Implemented by aarch64_h. */ - BUILTIN_VDQ_BHSI (BINOP, shadd, 0, NONE) - BUILTIN_VDQ_BHSI (BINOP, shsub, 0, NONE) - BUILTIN_VDQ_BHSI (BINOPU, uhadd, 0, NONE) - BUILTIN_VDQ_BHSI (BINOPU, uhsub, 0, NONE) - BUILTIN_VDQ_BHSI (BINOP, srhadd, 0, NONE) - BUILTIN_VDQ_BHSI (BINOPU, urhadd, 0, NONE) + BUILTIN_VDQ_BHSI (BINOP, shadd, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, shsub, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOPU, uhadd, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOPU, uhsub, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, srhadd, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOPU, urhadd, 0, DEFAULT) /* Implemented by aarch64_addlp. */ - BUILTIN_VDQV_L (UNOP, saddlp, 0, NONE) - BUILTIN_VDQV_L (UNOPU, uaddlp, 0, NONE) + BUILTIN_VDQV_L (UNOP, saddlp, 0, DEFAULT) + BUILTIN_VDQV_L (UNOPU, uaddlp, 0, DEFAULT) /* Implemented by aarch64_addlv. */ - BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE) - BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE) + BUILTIN_VDQV_L (UNOP, saddlv, 0, DEFAULT) + BUILTIN_VDQV_L (UNOPU, uaddlv, 0, DEFAULT) /* Implemented by aarch64_abd. */ - BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE) - BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE) + BUILTIN_VDQ_BHSI (BINOP, sabd, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, DEFAULT) /* Implemented by aarch64_aba. */ - BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE) - BUILTIN_VDQ_BHSI (TERNOPU, uaba, 0, NONE) + BUILTIN_VDQ_BHSI (TERNOP, saba, 0, DEFAULT) + BUILTIN_VDQ_BHSI (TERNOPU, uaba, 0, DEFAULT) - BUILTIN_VDQV_L (BINOP, sadalp, 0, NONE) - BUILTIN_VDQV_L (BINOPU, uadalp, 0, NONE) + BUILTIN_VDQV_L (BINOP, sadalp, 0, DEFAULT) + BUILTIN_VDQV_L (BINOPU, uadalp, 0, DEFAULT) /* Implemented by aarch64_abal. */ - BUILTIN_VD_BHSI (TERNOP, sabal, 0, NONE) - BUILTIN_VD_BHSI (TERNOPU, uabal, 0, NONE) + BUILTIN_VD_BHSI (TERNOP, sabal, 0, DEFAULT) + BUILTIN_VD_BHSI (TERNOPU, uabal, 0, DEFAULT) /* Implemented by aarch64_abal2. */ - BUILTIN_VQW (TERNOP, sabal2, 0, NONE) - BUILTIN_VQW (TERNOPU, uabal2, 0, NONE) + BUILTIN_VQW (TERNOP, sabal2, 0, DEFAULT) + BUILTIN_VQW (TERNOPU, uabal2, 0, DEFAULT) /* Implemented by aarch64_abdl. */ - BUILTIN_VD_BHSI (BINOP, sabdl, 0, NONE) - BUILTIN_VD_BHSI (BINOPU, uabdl, 0, NONE) + BUILTIN_VD_BHSI (BINOP, sabdl, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOPU, uabdl, 0, DEFAULT) /* Implemented by aarch64_abdl2. */ - BUILTIN_VQW (BINOP, sabdl2, 0, NONE) - BUILTIN_VQW (BINOPU, uabdl2, 0, NONE) + BUILTIN_VQW (BINOP, sabdl2, 0, DEFAULT) + BUILTIN_VQW (BINOPU, uabdl2, 0, DEFAULT) /* Implemented by aarch64_hn. */ - BUILTIN_VQN (BINOP, addhn, 0, NONE) - BUILTIN_VQN (BINOPU, addhn, 0, NONE) - BUILTIN_VQN (BINOP, subhn, 0, NONE) - BUILTIN_VQN (BINOPU, subhn, 0, NONE) - BUILTIN_VQN (BINOP, raddhn, 0, NONE) - BUILTIN_VQN (BINOPU, raddhn, 0, NONE) - BUILTIN_VQN (BINOP, rsubhn, 0, NONE) - BUILTIN_VQN (BINOPU, rsubhn, 0, NONE) + BUILTIN_VQN (BINOP, addhn, 0, DEFAULT) + BUILTIN_VQN (BINOPU, addhn, 0, DEFAULT) + BUILTIN_VQN (BINOP, subhn, 0, DEFAULT) + BUILTIN_VQN (BINOPU, subhn, 0, DEFAULT) + BUILTIN_VQN (BINOP, raddhn, 0, DEFAULT) + BUILTIN_VQN (BINOPU, raddhn, 0, DEFAULT) + BUILTIN_VQN (BINOP, rsubhn, 0, DEFAULT) + BUILTIN_VQN (BINOPU, rsubhn, 0, DEFAULT) /* Implemented by aarch64_hn2. */ - BUILTIN_VQN (TERNOP, addhn2, 0, NONE) - BUILTIN_VQN (TERNOPU, addhn2, 0, NONE) - BUILTIN_VQN (TERNOP, subhn2, 0, NONE) - BUILTIN_VQN (TERNOPU, subhn2, 0, NONE) - BUILTIN_VQN (TERNOP, raddhn2, 0, NONE) - BUILTIN_VQN (TERNOPU, raddhn2, 0, NONE) - BUILTIN_VQN (TERNOP, rsubhn2, 0, NONE) - BUILTIN_VQN (TERNOPU, rsubhn2, 0, NONE) + BUILTIN_VQN (TERNOP, addhn2, 0, DEFAULT) + BUILTIN_VQN (TERNOPU, addhn2, 0, DEFAULT) + BUILTIN_VQN (TERNOP, subhn2, 0, DEFAULT) + BUILTIN_VQN (TERNOPU, subhn2, 0, DEFAULT) + BUILTIN_VQN (TERNOP, raddhn2, 0, DEFAULT) + BUILTIN_VQN (TERNOPU, raddhn2, 0, DEFAULT) + BUILTIN_VQN (TERNOP, rsubhn2, 0, DEFAULT) + BUILTIN_VQN (TERNOPU, rsubhn2, 0, DEFAULT) /* Implemented by aarch64_xtl. */ - BUILTIN_VQN (UNOP, sxtl, 0, NONE) - BUILTIN_VQN (UNOPU, uxtl, 0, NONE) + BUILTIN_VQN (UNOP, sxtl, 0, DEFAULT) + BUILTIN_VQN (UNOPU, uxtl, 0, DEFAULT) /* Implemented by aarch64_xtn. */ - BUILTIN_VQN (UNOP, xtn, 0, NONE) - BUILTIN_VQN (UNOPU, xtn, 0, NONE) + BUILTIN_VQN (UNOP, xtn, 0, DEFAULT) + BUILTIN_VQN (UNOPU, xtn, 0, DEFAULT) /* Implemented by aarch64_mla. */ - BUILTIN_VDQ_BHSI (TERNOP, mla, 0, NONE) - BUILTIN_VDQ_BHSI (TERNOPU, mla, 0, NONE) + BUILTIN_VDQ_BHSI (TERNOP, mla, 0, DEFAULT) + BUILTIN_VDQ_BHSI (TERNOPU, mla, 0, DEFAULT) /* Implemented by aarch64_mla_n. */ - BUILTIN_VDQHS (TERNOP, mla_n, 0, NONE) - BUILTIN_VDQHS (TERNOPU, mla_n, 0, NONE) + BUILTIN_VDQHS (TERNOP, mla_n, 0, DEFAULT) + BUILTIN_VDQHS (TERNOPU, mla_n, 0, DEFAULT) /* Implemented by aarch64_mls. */ - BUILTIN_VDQ_BHSI (TERNOP, mls, 0, NONE) - BUILTIN_VDQ_BHSI (TERNOPU, mls, 0, NONE) + BUILTIN_VDQ_BHSI (TERNOP, mls, 0, DEFAULT) + BUILTIN_VDQ_BHSI (TERNOPU, mls, 0, DEFAULT) /* Implemented by aarch64_mls_n. */ - BUILTIN_VDQHS (TERNOP, mls_n, 0, NONE) - BUILTIN_VDQHS (TERNOPU, mls_n, 0, NONE) + BUILTIN_VDQHS (TERNOP, mls_n, 0, DEFAULT) + BUILTIN_VDQHS (TERNOPU, mls_n, 0, DEFAULT) - BUILTIN_VQN (SHIFTIMM, shrn_n, 0, NONE) - BUILTIN_VQN (USHIFTIMM, shrn_n, 0, NONE) + BUILTIN_VQN (SHIFTIMM, shrn_n, 0, DEFAULT) + BUILTIN_VQN (USHIFTIMM, shrn_n, 0, DEFAULT) - BUILTIN_VQN (SHIFT2IMM, ushrn2_n, 0, NONE) - BUILTIN_VQN (USHIFT2IMM, ushrn2_n, 0, NONE) + BUILTIN_VQN (SHIFT2IMM, ushrn2_n, 0, DEFAULT) + BUILTIN_VQN (USHIFT2IMM, ushrn2_n, 0, DEFAULT) - BUILTIN_VQN (SHIFTIMM, rshrn_n, 0, NONE) - BUILTIN_VQN (USHIFTIMM, rshrn_n, 0, NONE) + BUILTIN_VQN (SHIFTIMM, rshrn_n, 0, DEFAULT) + BUILTIN_VQN (USHIFTIMM, rshrn_n, 0, DEFAULT) - BUILTIN_VQN (SHIFT2IMM, rshrn2_n, 0, NONE) - BUILTIN_VQN (USHIFT2IMM, rshrn2_n, 0, NONE) + BUILTIN_VQN (SHIFT2IMM, rshrn2_n, 0, DEFAULT) + BUILTIN_VQN (USHIFT2IMM, rshrn2_n, 0, DEFAULT) /* Implemented by aarch64_mlsl. */ - BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE) - BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, NONE) + BUILTIN_VD_BHSI (TERNOP, smlsl, 0, DEFAULT) + BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, DEFAULT) /* Implemented by aarch64_mlsl_n. */ - BUILTIN_VD_HSI (TERNOP, smlsl_n, 0, NONE) - BUILTIN_VD_HSI (TERNOPU, umlsl_n, 0, NONE) + BUILTIN_VD_HSI (TERNOP, smlsl_n, 0, DEFAULT) + BUILTIN_VD_HSI (TERNOPU, umlsl_n, 0, DEFAULT) /* Implemented by aarch64_mlal. */ - BUILTIN_VD_BHSI (TERNOP, smlal, 0, NONE) - BUILTIN_VD_BHSI (TERNOPU, umlal, 0, NONE) + BUILTIN_VD_BHSI (TERNOP, smlal, 0, DEFAULT) + BUILTIN_VD_BHSI (TERNOPU, umlal, 0, DEFAULT) /* Implemented by aarch64_mlal_n. */ - BUILTIN_VD_HSI (TERNOP, smlal_n, 0, NONE) - BUILTIN_VD_HSI (TERNOPU, umlal_n, 0, NONE) + BUILTIN_VD_HSI (TERNOP, smlal_n, 0, DEFAULT) + BUILTIN_VD_HSI (TERNOPU, umlal_n, 0, DEFAULT) /* Implemented by aarch64_mlsl_hi. */ - BUILTIN_VQW (TERNOP, smlsl_hi, 0, NONE) - BUILTIN_VQW (TERNOPU, umlsl_hi, 0, NONE) + BUILTIN_VQW (TERNOP, smlsl_hi, 0, DEFAULT) + BUILTIN_VQW (TERNOPU, umlsl_hi, 0, DEFAULT) /* Implemented by aarch64_mlsl_hi_n. */ - BUILTIN_VQ_HSI (TERNOP, smlsl_hi_n, 0, NONE) - BUILTIN_VQ_HSI (TERNOPU, umlsl_hi_n, 0, NONE) + BUILTIN_VQ_HSI (TERNOP, smlsl_hi_n, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOPU, umlsl_hi_n, 0, DEFAULT) /* Implemented by aarch64_mlal_hi. */ - BUILTIN_VQW (TERNOP, smlal_hi, 0, NONE) - BUILTIN_VQW (TERNOPU, umlal_hi, 0, NONE) + BUILTIN_VQW (TERNOP, smlal_hi, 0, DEFAULT) + BUILTIN_VQW (TERNOPU, umlal_hi, 0, DEFAULT) /* Implemented by aarch64_mlal_hi_n. */ - BUILTIN_VQ_HSI (TERNOP, smlal_hi_n, 0, NONE) - BUILTIN_VQ_HSI (TERNOPU, umlal_hi_n, 0, NONE) + BUILTIN_VQ_HSI (TERNOP, smlal_hi_n, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOPU, umlal_hi_n, 0, DEFAULT) /* Implemented by aarch64_sqmovun. */ - BUILTIN_VQN (UNOPUS, sqmovun, 0, NONE) - BUILTIN_SD_HSDI (UNOPUS, sqmovun, 0, NONE) + BUILTIN_VQN (UNOPUS, sqmovun, 0, DEFAULT) + BUILTIN_SD_HSDI (UNOPUS, sqmovun, 0, DEFAULT) /* Implemented by aarch64_sqxtun2. */ - BUILTIN_VQN (BINOP_UUS, sqxtun2, 0, NONE) + BUILTIN_VQN (BINOP_UUS, sqxtun2, 0, DEFAULT) /* Implemented by aarch64_qmovn. */ - BUILTIN_VQN (UNOP, sqmovn, 0, NONE) - BUILTIN_SD_HSDI (UNOP, sqmovn, 0, NONE) - BUILTIN_VQN (UNOP, uqmovn, 0, NONE) - BUILTIN_SD_HSDI (UNOP, uqmovn, 0, NONE) + BUILTIN_VQN (UNOP, sqmovn, 0, DEFAULT) + BUILTIN_SD_HSDI (UNOP, sqmovn, 0, DEFAULT) + BUILTIN_VQN (UNOP, uqmovn, 0, DEFAULT) + BUILTIN_SD_HSDI (UNOP, uqmovn, 0, DEFAULT) /* Implemented by aarch64_qxtn2. */ - BUILTIN_VQN (BINOP, sqxtn2, 0, NONE) - BUILTIN_VQN (BINOPU, uqxtn2, 0, NONE) + BUILTIN_VQN (BINOP, sqxtn2, 0, DEFAULT) + BUILTIN_VQN (BINOPU, uqxtn2, 0, DEFAULT) /* Implemented by aarch64_s. */ - BUILTIN_VSDQ_I (UNOP, sqabs, 0, NONE) - BUILTIN_VSDQ_I (UNOP, sqneg, 0, NONE) + BUILTIN_VSDQ_I (UNOP, sqabs, 0, DEFAULT) + BUILTIN_VSDQ_I (UNOP, sqneg, 0, DEFAULT) /* Implemented by aarch64_sqdmll. */ - BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0, NONE) - BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0, NONE) + BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0, DEFAULT) + BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0, DEFAULT) /* Implemented by aarch64_sqdmll_lane. */ - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0, NONE) - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0, NONE) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0, DEFAULT) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0, DEFAULT) /* Implemented by aarch64_sqdmll_laneq. */ - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0, NONE) - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0, NONE) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0, DEFAULT) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0, DEFAULT) /* Implemented by aarch64_sqdmll_n. */ - BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0, NONE) - BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0, NONE) - - BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0, NONE) - BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0, NONE) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0, NONE) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0, NONE) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0, NONE) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0, NONE) - BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0, NONE) - BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0, NONE) - - BUILTIN_VD_BHSI (BINOP, intrinsic_vec_smult_lo_, 0, NONE) - BUILTIN_VD_BHSI (BINOPU, intrinsic_vec_umult_lo_, 0, NONE) - - BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10, NONE) - BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10, NONE) - - BUILTIN_VD_HSI (BINOP, smull_n, 0, NONE) - BUILTIN_VD_HSI (BINOPU, umull_n, 0, NONE) - - BUILTIN_VQ_HSI (BINOP, smull_hi_n, 0, NONE) - BUILTIN_VQ_HSI (BINOPU, umull_hi_n, 0, NONE) - - BUILTIN_VQ_HSI (TERNOP_LANE, smull_hi_lane, 0, NONE) - BUILTIN_VQ_HSI (TERNOP_LANE, smull_hi_laneq, 0, NONE) - BUILTIN_VQ_HSI (TERNOPU_LANE, umull_hi_lane, 0, NONE) - BUILTIN_VQ_HSI (TERNOPU_LANE, umull_hi_laneq, 0, NONE) - - BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, NONE) - BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, NONE) - BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, NONE) - BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0, NONE) - BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0, NONE) - BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0, NONE) - BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0, NONE) - BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0, NONE) - - BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_lane_, 0, NONE) - BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_laneq_, 0, NONE) - BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_lane_, 0, NONE) - BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_laneq_, 0, NONE) - - BUILTIN_VQ_HSI (QUADOP_LANE, smlal_hi_lane, 0, NONE) - BUILTIN_VQ_HSI (QUADOP_LANE, smlal_hi_laneq, 0, NONE) - BUILTIN_VQ_HSI (QUADOPU_LANE, umlal_hi_lane, 0, NONE) - BUILTIN_VQ_HSI (QUADOPU_LANE, umlal_hi_laneq, 0, NONE) - - BUILTIN_VQ_HSI (QUADOP_LANE, smlsl_hi_lane, 0, NONE) - BUILTIN_VQ_HSI (QUADOP_LANE, smlsl_hi_laneq, 0, NONE) - BUILTIN_VQ_HSI (QUADOPU_LANE, umlsl_hi_lane, 0, NONE) - BUILTIN_VQ_HSI (QUADOPU_LANE, umlsl_hi_laneq, 0, NONE) - - BUILTIN_VSD_HSI (BINOP, sqdmull, 0, NONE) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0, NONE) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0, NONE) - BUILTIN_VD_HSI (BINOP, sqdmull_n, 0, NONE) - BUILTIN_VQ_HSI (BINOP, sqdmull2, 0, NONE) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0, NONE) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0, NONE) - BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0, NONE) + BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0, DEFAULT) + BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0, DEFAULT) + + BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0, DEFAULT) + + BUILTIN_VD_BHSI (BINOP, intrinsic_vec_smult_lo_, 0, DEFAULT) + BUILTIN_VD_BHSI (BINOPU, intrinsic_vec_umult_lo_, 0, DEFAULT) + + BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10, DEFAULT) + BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10, DEFAULT) + + BUILTIN_VD_HSI (BINOP, smull_n, 0, DEFAULT) + BUILTIN_VD_HSI (BINOPU, umull_n, 0, DEFAULT) + + BUILTIN_VQ_HSI (BINOP, smull_hi_n, 0, DEFAULT) + BUILTIN_VQ_HSI (BINOPU, umull_hi_n, 0, DEFAULT) + + BUILTIN_VQ_HSI (TERNOP_LANE, smull_hi_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOP_LANE, smull_hi_laneq, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOPU_LANE, umull_hi_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOPU_LANE, umull_hi_laneq, 0, DEFAULT) + + BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, DEFAULT) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, DEFAULT) + BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, DEFAULT) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0, DEFAULT) + BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0, DEFAULT) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0, DEFAULT) + BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0, DEFAULT) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0, DEFAULT) + + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_lane_, 0, DEFAULT) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_laneq_, 0, DEFAULT) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_lane_, 0, DEFAULT) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_laneq_, 0, DEFAULT) + + BUILTIN_VQ_HSI (QUADOP_LANE, smlal_hi_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOP_LANE, smlal_hi_laneq, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlal_hi_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlal_hi_laneq, 0, DEFAULT) + + BUILTIN_VQ_HSI (QUADOP_LANE, smlsl_hi_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOP_LANE, smlsl_hi_laneq, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlsl_hi_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (QUADOPU_LANE, umlsl_hi_laneq, 0, DEFAULT) + + BUILTIN_VSD_HSI (BINOP, sqdmull, 0, DEFAULT) + BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0, DEFAULT) + BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0, DEFAULT) + BUILTIN_VD_HSI (BINOP, sqdmull_n, 0, DEFAULT) + BUILTIN_VQ_HSI (BINOP, sqdmull2, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0, DEFAULT) + BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0, DEFAULT) + BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0, DEFAULT) /* Implemented by aarch64_sqdmulh. */ - BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0, NONE) - BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0, NONE) + BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0, DEFAULT) + BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0, DEFAULT) /* Implemented by aarch64_sqdmulh_n. */ - BUILTIN_VDQHS (BINOP, sqdmulh_n, 0, NONE) - BUILTIN_VDQHS (BINOP, sqrdmulh_n, 0, NONE) + BUILTIN_VDQHS (BINOP, sqdmulh_n, 0, DEFAULT) + BUILTIN_VDQHS (BINOP, sqrdmulh_n, 0, DEFAULT) /* Implemented by aarch64_sqdmulh_lane. */ - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0, NONE) - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0, NONE) - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0, NONE) - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0, NONE) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0, DEFAULT) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0, DEFAULT) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0, DEFAULT) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0, DEFAULT) - BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, NONE) + BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, DEFAULT) /* Implemented by aarch64_shl. */ - BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, NONE) - BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, NONE) - BUILTIN_VSDQ_I_DI (BINOP, srshl, 0, NONE) - BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0, NONE) + BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (BINOP, srshl, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0, DEFAULT) /* Implemented by _prod. */ - BUILTIN_VB (TERNOP, sdot_prod, 0, NONE) - BUILTIN_VB (TERNOPU, udot_prod, 0, NONE) - BUILTIN_VB (TERNOP_SUSS, usdot_prod, 0, NONE) + BUILTIN_VB (TERNOP, sdot_prod, 0, DEFAULT) + BUILTIN_VB (TERNOPU, udot_prod, 0, DEFAULT) + BUILTIN_VB (TERNOP_SUSS, usdot_prod, 0, DEFAULT) /* Implemented by aarch64__lane{q}. */ - BUILTIN_VB (QUADOP_LANE, sdot_lane, 0, NONE) - BUILTIN_VB (QUADOPU_LANE, udot_lane, 0, NONE) - BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0, NONE) - BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0, NONE) - BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0, NONE) - BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0, NONE) - BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0, NONE) - BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0, NONE) + BUILTIN_VB (QUADOP_LANE, sdot_lane, 0, DEFAULT) + BUILTIN_VB (QUADOPU_LANE, udot_lane, 0, DEFAULT) + BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0, DEFAULT) + BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0, DEFAULT) + BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0, DEFAULT) + BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0, DEFAULT) + BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0, DEFAULT) + BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0, DEFAULT) /* Implemented by aarch64_fcadd. */ BUILTIN_VHSDF (BINOP, fcadd90, 0, FP) @@ -450,79 +450,79 @@ BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0, FP) BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0, FP) - BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, NONE) - VAR1 (SHIFTIMM, ashr_simd, 0, NONE, di) - BUILTIN_VDQ_I (USHIFTIMM, lshr, 3, NONE) - VAR1 (USHIFTIMM, lshr_simd, 0, NONE, di) + BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, DEFAULT) + VAR1 (SHIFTIMM, ashr_simd, 0, DEFAULT, di) + BUILTIN_VDQ_I (USHIFTIMM, lshr, 3, DEFAULT) + VAR1 (USHIFTIMM, lshr_simd, 0, DEFAULT, di) /* Implemented by aarch64_shr_n. */ - BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0, NONE) - BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0, NONE) + BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0, DEFAULT) /* Implemented by aarch64_sra_n. */ - BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0, NONE) - BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0, NONE) - BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0, NONE) - BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0, NONE) + BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0, DEFAULT) /* Implemented by aarch64_shll_n. */ - BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0, NONE) - BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0, NONE) + BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0, DEFAULT) + BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0, DEFAULT) /* Implemented by aarch64_shll2_n. */ - BUILTIN_VQW (SHIFTIMM, sshll2_n, 0, NONE) - BUILTIN_VQW (SHIFTIMM, ushll2_n, 0, NONE) - BUILTIN_VQN (SHIFTIMM, sqshrun_n, 0, NONE) - BUILTIN_VQN (SHIFTIMM, sqrshrun_n, 0, NONE) - BUILTIN_VQN (SHIFTIMM, sqshrn_n, 0, NONE) - BUILTIN_VQN (USHIFTIMM, uqshrn_n, 0, NONE) - BUILTIN_VQN (SHIFTIMM, sqrshrn_n, 0, NONE) - BUILTIN_VQN (USHIFTIMM, uqrshrn_n, 0, NONE) - BUILTIN_SD_HSDI (SHIFTIMM, sqshrun_n, 0, NONE) - BUILTIN_SD_HSDI (SHIFTIMM, sqrshrun_n, 0, NONE) - BUILTIN_SD_HSDI (SHIFTIMM, sqshrn_n, 0, NONE) - BUILTIN_SD_HSDI (USHIFTIMM, uqshrn_n, 0, NONE) - BUILTIN_SD_HSDI (SHIFTIMM, sqrshrn_n, 0, NONE) - BUILTIN_SD_HSDI (USHIFTIMM, uqrshrn_n, 0, NONE) - BUILTIN_VQN (SHIFT2IMM_UUSS, sqshrun2_n, 0, NONE) - BUILTIN_VQN (SHIFT2IMM_UUSS, sqrshrun2_n, 0, NONE) - BUILTIN_VQN (SHIFT2IMM, sqsshrn2_n, 0, NONE) - BUILTIN_VQN (USHIFT2IMM, uqushrn2_n, 0, NONE) - BUILTIN_VQN (SHIFT2IMM, sqrshrn2_n, 0, NONE) - BUILTIN_VQN (USHIFT2IMM, uqrshrn2_n, 0, NONE) + BUILTIN_VQW (SHIFTIMM, sshll2_n, 0, DEFAULT) + BUILTIN_VQW (SHIFTIMM, ushll2_n, 0, DEFAULT) + BUILTIN_VQN (SHIFTIMM, sqshrun_n, 0, DEFAULT) + BUILTIN_VQN (SHIFTIMM, sqrshrun_n, 0, DEFAULT) + BUILTIN_VQN (SHIFTIMM, sqshrn_n, 0, DEFAULT) + BUILTIN_VQN (USHIFTIMM, uqshrn_n, 0, DEFAULT) + BUILTIN_VQN (SHIFTIMM, sqrshrn_n, 0, DEFAULT) + BUILTIN_VQN (USHIFTIMM, uqrshrn_n, 0, DEFAULT) + BUILTIN_SD_HSDI (SHIFTIMM, sqshrun_n, 0, DEFAULT) + BUILTIN_SD_HSDI (SHIFTIMM, sqrshrun_n, 0, DEFAULT) + BUILTIN_SD_HSDI (SHIFTIMM, sqshrn_n, 0, DEFAULT) + BUILTIN_SD_HSDI (USHIFTIMM, uqshrn_n, 0, DEFAULT) + BUILTIN_SD_HSDI (SHIFTIMM, sqrshrn_n, 0, DEFAULT) + BUILTIN_SD_HSDI (USHIFTIMM, uqrshrn_n, 0, DEFAULT) + BUILTIN_VQN (SHIFT2IMM_UUSS, sqshrun2_n, 0, DEFAULT) + BUILTIN_VQN (SHIFT2IMM_UUSS, sqrshrun2_n, 0, DEFAULT) + BUILTIN_VQN (SHIFT2IMM, sqsshrn2_n, 0, DEFAULT) + BUILTIN_VQN (USHIFT2IMM, uqushrn2_n, 0, DEFAULT) + BUILTIN_VQN (SHIFT2IMM, sqrshrn2_n, 0, DEFAULT) + BUILTIN_VQN (USHIFT2IMM, uqrshrn2_n, 0, DEFAULT) /* Implemented by aarch64_si_n. */ - BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0, NONE) - BUILTIN_VALLP (SHIFTINSERTP, ssri_n, 0, NONE) - BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0, NONE) - BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0, NONE) - BUILTIN_VALLP (SHIFTINSERTP, ssli_n, 0, NONE) - BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0, NONE) + BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0, DEFAULT) + BUILTIN_VALLP (SHIFTINSERTP, ssri_n, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0, DEFAULT) + BUILTIN_VALLP (SHIFTINSERTP, ssli_n, 0, DEFAULT) + BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0, DEFAULT) /* Implemented by aarch64_qshl_n. */ - BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0, NONE) - BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0, NONE) - BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0, NONE) + BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0, DEFAULT) + BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0, DEFAULT) + BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0, DEFAULT) /* Implemented by aarch64_xtn2. */ - BUILTIN_VQN (BINOP, xtn2, 0, NONE) - BUILTIN_VQN (BINOPU, xtn2, 0, NONE) + BUILTIN_VQN (BINOP, xtn2, 0, DEFAULT) + BUILTIN_VQN (BINOPU, xtn2, 0, DEFAULT) /* Implemented by vec_unpack_hi_. */ - BUILTIN_VQW (UNOP, vec_unpacks_hi_, 10, NONE) - BUILTIN_VQW (UNOPU, vec_unpacku_hi_, 10, NONE) + BUILTIN_VQW (UNOP, vec_unpacks_hi_, 10, DEFAULT) + BUILTIN_VQW (UNOPU, vec_unpacku_hi_, 10, DEFAULT) /* Implemented by aarch64_reduc_plus_. */ - BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, NONE) - BUILTIN_VDQ_I (UNOPU, reduc_plus_scal_, 10, NONE) + BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, DEFAULT) + BUILTIN_VDQ_I (UNOPU, reduc_plus_scal_, 10, DEFAULT) /* Implemented by reduc__scal_ (producing scalar). */ - BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10, NONE) - BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10, NONE) - BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10, NONE) - BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10, NONE) - BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10, NONE) - BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10, NONE) + BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10, DEFAULT) + BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10, DEFAULT) + BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10, DEFAULT) + BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10, DEFAULT) + BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10, DEFAULT) + BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10, DEFAULT) /* Implemented by 3. */ - BUILTIN_VDQ_BHSI (BINOP, smax, 3, NONE) - BUILTIN_VDQ_BHSI (BINOP, smin, 3, NONE) - BUILTIN_VDQ_BHSI (BINOP, umax, 3, NONE) - BUILTIN_VDQ_BHSI (BINOP, umin, 3, NONE) + BUILTIN_VDQ_BHSI (BINOP, smax, 3, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, smin, 3, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, umax, 3, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, umin, 3, DEFAULT) /* Implemented by 3. */ BUILTIN_VHSDF_HSDF (BINOP, fmax, 3, FP) @@ -531,14 +531,14 @@ BUILTIN_VHSDF_DF (BINOP, fmin_nan, 3, FP) /* Implemented by aarch64_p. */ - BUILTIN_VDQ_BHSI (BINOP, smaxp, 0, NONE) - BUILTIN_VDQ_BHSI (BINOP, sminp, 0, NONE) - BUILTIN_VDQ_BHSI (BINOP, umaxp, 0, NONE) - BUILTIN_VDQ_BHSI (BINOP, uminp, 0, NONE) - BUILTIN_VHSDF (BINOP, smaxp, 0, NONE) - BUILTIN_VHSDF (BINOP, sminp, 0, NONE) - BUILTIN_VHSDF (BINOP, smax_nanp, 0, NONE) - BUILTIN_VHSDF (BINOP, smin_nanp, 0, NONE) + BUILTIN_VDQ_BHSI (BINOP, smaxp, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, sminp, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, umaxp, 0, DEFAULT) + BUILTIN_VDQ_BHSI (BINOP, uminp, 0, DEFAULT) + BUILTIN_VHSDF (BINOP, smaxp, 0, DEFAULT) + BUILTIN_VHSDF (BINOP, sminp, 0, DEFAULT) + BUILTIN_VHSDF (BINOP, smax_nanp, 0, DEFAULT) + BUILTIN_VHSDF (BINOP, smin_nanp, 0, DEFAULT) /* Implemented by 2. */ BUILTIN_VHSDF (UNOP, btrunc, 2, FP) @@ -651,9 +651,9 @@ VAR1 (UNOP, floatunsv4si, 2, FP, v4sf) VAR1 (UNOP, floatunsv2di, 2, FP, v2df) - VAR5 (UNOPU, bswap, 2, NONE, v4hi, v8hi, v2si, v4si, v2di) + VAR5 (UNOPU, bswap, 2, DEFAULT, v4hi, v8hi, v2si, v4si, v2di) - BUILTIN_VB (UNOP, rbit, 0, NONE) + BUILTIN_VB (UNOP, rbit, 0, DEFAULT) /* Implemented by aarch64_. */ @@ -667,7 +667,7 @@ BUILTIN_GPF_F16 (UNOP, frecpe, 0, FP) BUILTIN_GPF_F16 (UNOP, frecpx, 0, FP) - BUILTIN_VDQ_SI (UNOP, urecpe, 0, NONE) + BUILTIN_VDQ_SI (UNOP, urecpe, 0, DEFAULT) BUILTIN_VHSDF (UNOP, frecpe, 0, FP) BUILTIN_VHSDF_HSDF (BINOP, frecps, 0, FP) @@ -717,96 +717,96 @@ BUILTIN_VDQSF (QUADOP_LANE, float_mls_laneq, 0, FP) /* Implemented by aarch64_simd_bsl. */ - BUILTIN_VDQQH (BSL_P, simd_bsl, 0, NONE) - VAR2 (BSL_P, simd_bsl,0, NONE, di, v2di) - BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0, NONE) + BUILTIN_VDQQH (BSL_P, simd_bsl, 0, DEFAULT) + VAR2 (BSL_P, simd_bsl,0, DEFAULT, di, v2di) + BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0, DEFAULT) BUILTIN_VALLDIF (BSL_S, simd_bsl, 0, QUIET) /* Implemented by aarch64_crypto_aes. */ - VAR1 (BINOPU, crypto_aese, 0, NONE, v16qi) - VAR1 (BINOPU, crypto_aesd, 0, NONE, v16qi) - VAR1 (UNOPU, crypto_aesmc, 0, NONE, v16qi) - VAR1 (UNOPU, crypto_aesimc, 0, NONE, v16qi) + VAR1 (BINOPU, crypto_aese, 0, DEFAULT, v16qi) + VAR1 (BINOPU, crypto_aesd, 0, DEFAULT, v16qi) + VAR1 (UNOPU, crypto_aesmc, 0, DEFAULT, v16qi) + VAR1 (UNOPU, crypto_aesimc, 0, DEFAULT, v16qi) /* Implemented by aarch64_crypto_sha1. */ - VAR1 (UNOPU, crypto_sha1h, 0, NONE, si) - VAR1 (BINOPU, crypto_sha1su1, 0, NONE, v4si) - VAR1 (TERNOPU, crypto_sha1c, 0, NONE, v4si) - VAR1 (TERNOPU, crypto_sha1m, 0, NONE, v4si) - VAR1 (TERNOPU, crypto_sha1p, 0, NONE, v4si) - VAR1 (TERNOPU, crypto_sha1su0, 0, NONE, v4si) + VAR1 (UNOPU, crypto_sha1h, 0, DEFAULT, si) + VAR1 (BINOPU, crypto_sha1su1, 0, DEFAULT, v4si) + VAR1 (TERNOPU, crypto_sha1c, 0, DEFAULT, v4si) + VAR1 (TERNOPU, crypto_sha1m, 0, DEFAULT, v4si) + VAR1 (TERNOPU, crypto_sha1p, 0, DEFAULT, v4si) + VAR1 (TERNOPU, crypto_sha1su0, 0, DEFAULT, v4si) /* Implemented by aarch64_crypto_sha256. */ - VAR1 (TERNOPU, crypto_sha256h, 0, NONE, v4si) - VAR1 (TERNOPU, crypto_sha256h2, 0, NONE, v4si) - VAR1 (BINOPU, crypto_sha256su0, 0, NONE, v4si) - VAR1 (TERNOPU, crypto_sha256su1, 0, NONE, v4si) + VAR1 (TERNOPU, crypto_sha256h, 0, DEFAULT, v4si) + VAR1 (TERNOPU, crypto_sha256h2, 0, DEFAULT, v4si) + VAR1 (BINOPU, crypto_sha256su0, 0, DEFAULT, v4si) + VAR1 (TERNOPU, crypto_sha256su1, 0, DEFAULT, v4si) /* Implemented by aarch64_crypto_pmull. */ - VAR1 (BINOPP, crypto_pmull, 0, NONE, di) - VAR1 (BINOPP, crypto_pmull, 0, NONE, v2di) + VAR1 (BINOPP, crypto_pmull, 0, DEFAULT, di) + VAR1 (BINOPP, crypto_pmull, 0, DEFAULT, v2di) /* Implemented by aarch64_qtbl1. */ - VAR2 (BINOP, qtbl1, 0, NONE, v8qi, v16qi) - VAR2 (BINOPU, qtbl1, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_PPU, qtbl1, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_SSU, qtbl1, 0, NONE, v8qi, v16qi) + VAR2 (BINOP, qtbl1, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOPU, qtbl1, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_PPU, qtbl1, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_SSU, qtbl1, 0, DEFAULT, v8qi, v16qi) /* Implemented by aarch64_qtbl2. */ - VAR2 (BINOP, qtbl2, 0, NONE, v8qi, v16qi) - VAR2 (BINOPU, qtbl2, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_PPU, qtbl2, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_SSU, qtbl2, 0, NONE, v8qi, v16qi) + VAR2 (BINOP, qtbl2, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOPU, qtbl2, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_PPU, qtbl2, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_SSU, qtbl2, 0, DEFAULT, v8qi, v16qi) /* Implemented by aarch64_qtbl3. */ - VAR2 (BINOP, qtbl3, 0, NONE, v8qi, v16qi) - VAR2 (BINOPU, qtbl3, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_PPU, qtbl3, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_SSU, qtbl3, 0, NONE, v8qi, v16qi) + VAR2 (BINOP, qtbl3, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOPU, qtbl3, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_PPU, qtbl3, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_SSU, qtbl3, 0, DEFAULT, v8qi, v16qi) /* Implemented by aarch64_qtbl4. */ - VAR2 (BINOP, qtbl4, 0, NONE, v8qi, v16qi) - VAR2 (BINOPU, qtbl4, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_PPU, qtbl4, 0, NONE, v8qi, v16qi) - VAR2 (BINOP_SSU, qtbl4, 0, NONE, v8qi, v16qi) + VAR2 (BINOP, qtbl4, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOPU, qtbl4, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_PPU, qtbl4, 0, DEFAULT, v8qi, v16qi) + VAR2 (BINOP_SSU, qtbl4, 0, DEFAULT, v8qi, v16qi) /* Implemented by aarch64_qtbx1. */ - VAR2 (TERNOP, qtbx1, 0, NONE, v8qi, v16qi) - VAR2 (TERNOPU, qtbx1, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_PPPU, qtbx1, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_SSSU, qtbx1, 0, NONE, v8qi, v16qi) + VAR2 (TERNOP, qtbx1, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOPU, qtbx1, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_PPPU, qtbx1, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_SSSU, qtbx1, 0, DEFAULT, v8qi, v16qi) /* Implemented by aarch64_qtbx2. */ - VAR2 (TERNOP, qtbx2, 0, NONE, v8qi, v16qi) - VAR2 (TERNOPU, qtbx2, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_PPPU, qtbx2, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_SSSU, qtbx2, 0, NONE, v8qi, v16qi) + VAR2 (TERNOP, qtbx2, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOPU, qtbx2, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_PPPU, qtbx2, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_SSSU, qtbx2, 0, DEFAULT, v8qi, v16qi) /* Implemented by aarch64_qtbx3. */ - VAR2 (TERNOP, qtbx3, 0, NONE, v8qi, v16qi) - VAR2 (TERNOPU, qtbx3, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_PPPU, qtbx3, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_SSSU, qtbx3, 0, NONE, v8qi, v16qi) + VAR2 (TERNOP, qtbx3, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOPU, qtbx3, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_PPPU, qtbx3, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_SSSU, qtbx3, 0, DEFAULT, v8qi, v16qi) /* Implemented by aarch64_qtbx4. */ - VAR2 (TERNOP, qtbx4, 0, NONE, v8qi, v16qi) - VAR2 (TERNOPU, qtbx4, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_PPPU, qtbx4, 0, NONE, v8qi, v16qi) - VAR2 (TERNOP_SSSU, qtbx4, 0, NONE, v8qi, v16qi) + VAR2 (TERNOP, qtbx4, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOPU, qtbx4, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_PPPU, qtbx4, 0, DEFAULT, v8qi, v16qi) + VAR2 (TERNOP_SSSU, qtbx4, 0, DEFAULT, v8qi, v16qi) /* Builtins for ARMv8.1-A Adv.SIMD instructions. */ /* Implemented by aarch64_sqrdmlh. */ - BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0, NONE) - BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0, NONE) + BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0, DEFAULT) + BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0, DEFAULT) /* Implemented by aarch64_sqrdmlh_lane. */ - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0, NONE) - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0, NONE) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0, DEFAULT) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0, DEFAULT) /* Implemented by aarch64_sqrdmlh_laneq. */ - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0, NONE) - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0, NONE) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0, DEFAULT) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0, DEFAULT) /* Implemented by <*><*>3. */ BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3, FP) @@ -827,7 +827,7 @@ BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0, FP) /* Implemented by aarch64_ursqrte. */ - BUILTIN_VDQ_SI (UNOPU, ursqrte, 0, NONE) + BUILTIN_VDQ_SI (UNOPU, ursqrte, 0, DEFAULT) /* Implemented by fabd3. */ BUILTIN_VHSDF_HSDF (BINOP, fabd, 3, FP) @@ -866,37 +866,37 @@ BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2, FP) /* Implemented by aarch64_sm3ss1qv4si. */ - VAR1 (TERNOPU, sm3ss1q, 0, NONE, v4si) + VAR1 (TERNOPU, sm3ss1q, 0, DEFAULT, v4si) /* Implemented by aarch64_sm3ttqv4si. */ - VAR1 (QUADOPUI, sm3tt1aq, 0, NONE, v4si) - VAR1 (QUADOPUI, sm3tt1bq, 0, NONE, v4si) - VAR1 (QUADOPUI, sm3tt2aq, 0, NONE, v4si) - VAR1 (QUADOPUI, sm3tt2bq, 0, NONE, v4si) + VAR1 (QUADOPUI, sm3tt1aq, 0, DEFAULT, v4si) + VAR1 (QUADOPUI, sm3tt1bq, 0, DEFAULT, v4si) + VAR1 (QUADOPUI, sm3tt2aq, 0, DEFAULT, v4si) + VAR1 (QUADOPUI, sm3tt2bq, 0, DEFAULT, v4si) /* Implemented by aarch64_sm3partwqv4si. */ - VAR1 (TERNOPU, sm3partw1q, 0, NONE, v4si) - VAR1 (TERNOPU, sm3partw2q, 0, NONE, v4si) + VAR1 (TERNOPU, sm3partw1q, 0, DEFAULT, v4si) + VAR1 (TERNOPU, sm3partw2q, 0, DEFAULT, v4si) /* Implemented by aarch64_sm4eqv4si. */ - VAR1 (BINOPU, sm4eq, 0, NONE, v4si) + VAR1 (BINOPU, sm4eq, 0, DEFAULT, v4si) /* Implemented by aarch64_sm4ekeyqv4si. */ - VAR1 (BINOPU, sm4ekeyq, 0, NONE, v4si) + VAR1 (BINOPU, sm4ekeyq, 0, DEFAULT, v4si) /* Implemented by aarch64_crypto_sha512hqv2di. */ - VAR1 (TERNOPU, crypto_sha512hq, 0, NONE, v2di) + VAR1 (TERNOPU, crypto_sha512hq, 0, DEFAULT, v2di) /* Implemented by aarch64_sha512h2qv2di. */ - VAR1 (TERNOPU, crypto_sha512h2q, 0, NONE, v2di) + VAR1 (TERNOPU, crypto_sha512h2q, 0, DEFAULT, v2di) /* Implemented by aarch64_crypto_sha512su0qv2di. */ - VAR1 (BINOPU, crypto_sha512su0q, 0, NONE, v2di) + VAR1 (BINOPU, crypto_sha512su0q, 0, DEFAULT, v2di) /* Implemented by aarch64_crypto_sha512su1qv2di. */ - VAR1 (TERNOPU, crypto_sha512su1q, 0, NONE, v2di) + VAR1 (TERNOPU, crypto_sha512su1q, 0, DEFAULT, v2di) /* Implemented by eor3q4. */ - BUILTIN_VQ_I (TERNOPU, eor3q, 4, NONE) - BUILTIN_VQ_I (TERNOP, eor3q, 4, NONE) + BUILTIN_VQ_I (TERNOPU, eor3q, 4, DEFAULT) + BUILTIN_VQ_I (TERNOP, eor3q, 4, DEFAULT) /* Implemented by aarch64_rax1qv2di. */ - VAR1 (BINOPU, rax1q, 0, NONE, v2di) + VAR1 (BINOPU, rax1q, 0, DEFAULT, v2di) /* Implemented by aarch64_xarqv2di. */ - VAR1 (TERNOPUI, xarq, 0, NONE, v2di) + VAR1 (TERNOPUI, xarq, 0, DEFAULT, v2di) /* Implemented by bcaxq4. */ - BUILTIN_VQ_I (TERNOPU, bcaxq, 4, NONE) - BUILTIN_VQ_I (TERNOP, bcaxq, 4, NONE) + BUILTIN_VQ_I (TERNOPU, bcaxq, 4, DEFAULT) + BUILTIN_VQ_I (TERNOP, bcaxq, 4, DEFAULT) /* Implemented by aarch64_fmll_low. */ VAR1 (TERNOP, fmlal_low, 0, FP, v2sf) @@ -956,9 +956,9 @@ VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, FP, v4sf) /* Implemented by aarch64_simd_mmlav16qi. */ - VAR1 (TERNOP, simd_smmla, 0, NONE, v16qi) - VAR1 (TERNOPU, simd_ummla, 0, NONE, v16qi) - VAR1 (TERNOP_SSUS, simd_usmmla, 0, NONE, v16qi) + VAR1 (TERNOP, simd_smmla, 0, DEFAULT, v16qi) + VAR1 (TERNOPU, simd_ummla, 0, DEFAULT, v16qi) + VAR1 (TERNOP_SSUS, simd_usmmla, 0, DEFAULT, v16qi) /* Implemented by aarch64_bfcvtn{q}{2} */ VAR1 (UNOP, bfcvtn, 0, FP, v4bf) diff --git a/gcc/config/aarch64/aarch64-simd-pragma-builtins.def b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def index ae8732bdb31..dfcfa8a0ac0 100644 --- a/gcc/config/aarch64/aarch64-simd-pragma-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def @@ -37,32 +37,32 @@ #undef ENTRY_TERNARY_VLUT8 #define ENTRY_TERNARY_VLUT8(T) \ ENTRY_BINARY_LANE (vluti2_lane_##T##8, T##8q, T##8, u8, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti2_laneq_##T##8, T##8q, T##8, u8q, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti2q_lane_##T##8, T##8q, T##8q, u8, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti2q_laneq_##T##8, T##8q, T##8q, u8q, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti4q_lane_##T##8, T##8q, T##8q, u8, \ - UNSPEC_LUTI4, NONE) \ + UNSPEC_LUTI4, DEFAULT) \ ENTRY_BINARY_LANE (vluti4q_laneq_##T##8, T##8q, T##8q, u8q, \ - UNSPEC_LUTI4, NONE) + UNSPEC_LUTI4, DEFAULT) #undef ENTRY_TERNARY_VLUT16 #define ENTRY_TERNARY_VLUT16(T) \ ENTRY_BINARY_LANE (vluti2_lane_##T##16, T##16q, T##16, u8, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti2_laneq_##T##16, T##16q, T##16, u8q, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti2q_lane_##T##16, T##16q, T##16q, u8, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti2q_laneq_##T##16, T##16q, T##16q, u8q, \ - UNSPEC_LUTI2, NONE) \ + UNSPEC_LUTI2, DEFAULT) \ ENTRY_BINARY_LANE (vluti4q_lane_##T##16_x2, T##16q, T##16qx2, u8, \ - UNSPEC_LUTI4, NONE) \ + UNSPEC_LUTI4, DEFAULT) \ ENTRY_BINARY_LANE (vluti4q_laneq_##T##16_x2, T##16q, T##16qx2, u8q, \ - UNSPEC_LUTI4, NONE) + UNSPEC_LUTI4, DEFAULT) // faminmax #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_FAMINMAX) From patchwork Wed Dec 4 18:02:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 102419 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E09113858C51 for ; Wed, 4 Dec 2024 18:06:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E09113858C51 X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id D32723858C62 for ; Wed, 4 Dec 2024 18:03:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D32723858C62 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D32723858C62 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733335420; cv=none; b=TYe9yzulbNB8ZduD6uaeJZz3dShFPj4oPCHEVQ5bWpJQeziJX6NMqTT8C8/6KHNWHbB7bDJmeWb+qT60Dedpfn2gATWx2ZcZ+8L9wsPa3fISko3XXVxH5z0K7PrGjNjwPHIlRkOxFaFQuGryOXJASFgsvDRlpmijSxKHlMnvGQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733335420; c=relaxed/simple; bh=YIZ2UfdtMyerfidI3a2aWjxdWLfSKI7pROSmY6f3iuU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ZnDa9W2RuPY4fvRsSu56Xlghr2eLtAu38TeQy+QsyqXtDCPlBPMdCi8p/svpCoEOUl743yxdLzeV39kC62if8H4M43etCoRxEZtlNzxmenrkvsCvPO5BgyTrGvXsjZoeSxUM7sayBP8ENMro8JQn51f7KwoF0JKM3zWAsnn4QpQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D32723858C62 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 904D91063; Wed, 4 Dec 2024 10:04:08 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AA17C3F5A1; Wed, 4 Dec 2024 10:03:39 -0800 (PST) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@nvidia.com, pinskia@gmail.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 3/4] aarch64: Reintroduce FLAG_AUTO_FP Date: Wed, 4 Dec 2024 18:02:43 +0000 Message-Id: <20241204180244.4077058-4-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241204180244.4077058-1-richard.sandiford@arm.com> References: <20241204180244.4077058-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-18.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org The flag now known as FLAG_QUIET is an odd-one-out in that it removes side-effects rather than adding them. This patch inverts it and gives it the old name FLAG_AUTO_FP. FLAG_QUIET now means "no flags" instead. gcc/ * config/aarch64/aarch64-builtins.cc (FLAG_QUIET): Redefine to 0, replacing the old flag with... (FLAG_AUTO_FP): ...this. (FLAG_DEFAULT): Redefine to FLAG_AUTO_FP. (aarch64_call_properties): Update accordingly. --- gcc/config/aarch64/aarch64-builtins.cc | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index eb44580bd9c..f528592a17d 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -193,22 +193,23 @@ using namespace aarch64; #define SIMD_MAX_BUILTIN_ARGS 5 /* Flags that describe what a function might do. */ -const unsigned int FLAG_DEFAULT = 0U; const unsigned int FLAG_READ_FPCR = 1U << 0; const unsigned int FLAG_RAISE_FP_EXCEPTIONS = 1U << 1; const unsigned int FLAG_READ_MEMORY = 1U << 2; const unsigned int FLAG_PREFETCH_MEMORY = 1U << 3; const unsigned int FLAG_WRITE_MEMORY = 1U << 4; -/* Not all FP intrinsics raise FP exceptions or read FPCR register, - use this flag to suppress it. */ -const unsigned int FLAG_QUIET = 1U << 5; +/* Indicates that READ_FPCR and RAISE_FP_EXCEPTIONS should be set for + floating-point modes but not for integer modes. */ +const unsigned int FLAG_AUTO_FP = 1U << 5; +const unsigned int FLAG_QUIET = 0; +const unsigned int FLAG_DEFAULT = FLAG_AUTO_FP; const unsigned int FLAG_FP = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS; const unsigned int FLAG_ALL = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS | FLAG_READ_MEMORY | FLAG_PREFETCH_MEMORY | FLAG_WRITE_MEMORY; -const unsigned int FLAG_STORE = FLAG_WRITE_MEMORY | FLAG_QUIET; -const unsigned int FLAG_LOAD = FLAG_READ_MEMORY | FLAG_QUIET; +const unsigned int FLAG_STORE = FLAG_WRITE_MEMORY; +const unsigned int FLAG_LOAD = FLAG_READ_MEMORY; typedef struct { @@ -1322,7 +1323,7 @@ aarch64_init_simd_builtin_scalar_types (void) static unsigned int aarch64_call_properties (unsigned int flags, machine_mode mode) { - if (!(flags & FLAG_QUIET) && FLOAT_MODE_P (mode)) + if ((flags & FLAG_AUTO_FP) && FLOAT_MODE_P (mode)) flags |= FLAG_FP; /* -fno-trapping-math means that we can assume any FP exceptions From patchwork Wed Dec 4 18:02:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 102418 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 79F0A3858D3C for ; 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d=sourceware.org; s=key; t=1733335432; c=relaxed/simple; bh=WZZSx+WuS1tYdQeAKByaNOVNQOJ1Ov7IdCEAI9P8AXU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=q1EIbTZbAYXSId2Yj8Ites/FPy3ESfUzrB7PUfujTAw3tGTB3qD3PTggoiGK4I7hGlZ0st42szrczdDYgc33e+nBTrMlAKJzypf+N5XGR1gelDKXObGQlG89CTnvO/SeSYuDOJXL0pygd38MoPnT2GUUWLJw8WaPYcverDRnTcc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 06A633858406 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C0C051063; Wed, 4 Dec 2024 10:04:19 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA8733F5A1; Wed, 4 Dec 2024 10:03:50 -0800 (PST) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@nvidia.com, pinskia@gmail.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 4/4] aarch64: Mark vluti* intrinsics as QUIET Date: Wed, 4 Dec 2024 18:02:44 +0000 Message-Id: <20241204180244.4077058-5-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241204180244.4077058-1-richard.sandiford@arm.com> References: <20241204180244.4077058-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-18.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org This patch fixes the vluti* definitions to say that they don't raise FP exceptions even for floating-point modes. gcc/ * config/aarch64/aarch64-simd-pragma-builtins.def (ENTRY_TERNARY_VLUT8): Use FLAG_QUIET rather than FLAG_DEFAULT. (ENTRY_TERNARY_VLUT16): Likewise. --- .../aarch64/aarch64-simd-pragma-builtins.def | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd-pragma-builtins.def b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def index dfcfa8a0ac0..bc9a63b968a 100644 --- a/gcc/config/aarch64/aarch64-simd-pragma-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def @@ -37,32 +37,32 @@ #undef ENTRY_TERNARY_VLUT8 #define ENTRY_TERNARY_VLUT8(T) \ ENTRY_BINARY_LANE (vluti2_lane_##T##8, T##8q, T##8, u8, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti2_laneq_##T##8, T##8q, T##8, u8q, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti2q_lane_##T##8, T##8q, T##8q, u8, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti2q_laneq_##T##8, T##8q, T##8q, u8q, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti4q_lane_##T##8, T##8q, T##8q, u8, \ - UNSPEC_LUTI4, DEFAULT) \ + UNSPEC_LUTI4, QUIET) \ ENTRY_BINARY_LANE (vluti4q_laneq_##T##8, T##8q, T##8q, u8q, \ - UNSPEC_LUTI4, DEFAULT) + UNSPEC_LUTI4, QUIET) #undef ENTRY_TERNARY_VLUT16 #define ENTRY_TERNARY_VLUT16(T) \ ENTRY_BINARY_LANE (vluti2_lane_##T##16, T##16q, T##16, u8, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti2_laneq_##T##16, T##16q, T##16, u8q, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti2q_lane_##T##16, T##16q, T##16q, u8, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti2q_laneq_##T##16, T##16q, T##16q, u8q, \ - UNSPEC_LUTI2, DEFAULT) \ + UNSPEC_LUTI2, QUIET) \ ENTRY_BINARY_LANE (vluti4q_lane_##T##16_x2, T##16q, T##16qx2, u8, \ - UNSPEC_LUTI4, DEFAULT) \ + UNSPEC_LUTI4, QUIET) \ ENTRY_BINARY_LANE (vluti4q_laneq_##T##16_x2, T##16q, T##16qx2, u8q, \ - UNSPEC_LUTI4, DEFAULT) + UNSPEC_LUTI4, QUIET) // faminmax #define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_FAMINMAX)