From patchwork Wed Dec 4 02:08:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 102343 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 251673858D33 for ; Wed, 4 Dec 2024 02:11:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 251673858D33 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=IbQZprLY X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id D0D1F3858D26 for ; Wed, 4 Dec 2024 02:10:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D0D1F3858D26 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D0D1F3858D26 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733278247; cv=none; b=JL1JQbs9zXVnAzmj467NUYau3nCt7kQrAb2VHh1VmYiJaIVCD+3wHAwaQnUmtMPVUDx1D1GWMxMerNbNopFmnYJd53MignP9XkZ7xetJS0xapZ2z6apOKcJA2GZQPL7tM2ZagTWFwdvDmv0da9hUMD4l9BQMb+hr6C3+5BTswHQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733278247; c=relaxed/simple; bh=jK1sLKiby4Bs4//CzqIzpTR9WVsF2RjRCRpijtUe8w0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=NZU9iSljkAE5ukjVcDDUGq37liDYXA5FkW6lPGna/chjOkSXEjC3muvCsh2cMmY9x/peCgkqpj/vPEy5W2EY4XqJ+A8lboLxuvVTCs4rrODwDae4byiTl0ggDpsrRFF6l88muVtnPk1oEJNb9MJ3j/ily34m4MHvQL/vPYTPTiQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D0D1F3858D26 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733278247; x=1764814247; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=jK1sLKiby4Bs4//CzqIzpTR9WVsF2RjRCRpijtUe8w0=; b=IbQZprLYXpsWIJ8I+vcTStpSsIJnhFaSobExCAWeTDGPzaugCnQSv8Yn ulPrAEV0zbkWcJchK8VcGlNECaEoo0McY/q/BLt9oIWiesfUKl21ygGUC Ne5iaQljhyDXdnFC4f5Fr7RGs9hDh2V1GRJIebuFsBoMN8iAVi5TaSNYe VaZb+gvEQz3XhBbLt6X6ToniXY7niSkDdMbwzkOTA1x1Dym1BM9odmmc6 CvK1pyKjYO6itDjMoupmfz2KlROTQecf0QdeyclY7FIYHEbzQu0hkZx/8 ABhe+RZIr5oElQRcTlL/5nzWeNJOckWWUx59+SCcahpXmSfRJfWjcTxyh w==; X-CSE-ConnectionGUID: xEjubynXQr2uOT/oFdahgA== X-CSE-MsgGUID: p6WrMFu0SMiRP4U/4zsF3A== X-IronPort-AV: E=McAfee;i="6700,10204,11275"; a="58930783" X-IronPort-AV: E=Sophos;i="6.12,206,1728975600"; d="scan'208";a="58930783" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2024 18:10:45 -0800 X-CSE-ConnectionGUID: aew73sJeRyWQyo63Gt5DoA== X-CSE-MsgGUID: VmClMBnQRpSuZ+MxerLKHQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,206,1728975600"; d="scan'208";a="131071840" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 03 Dec 2024 18:10:43 -0800 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 1/2] RISC-V: Fix incorrect optimization options passing to convert and unop Date: Wed, 4 Dec 2024 10:08:11 +0800 Message-ID: <20241204020812.3604240-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Like the strided load/store, the testcases of vector convert and unop are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of the gcc.log. This patch would like to make it correct almost the same as how we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 65a57aa7913..aee297752f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -67,9 +67,9 @@ foreach op $AUTOVEC_TEST_OPTS { dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/cmp/*.\[cS\]]] \ "" "$op" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/conversions/*.\[cS\]]] \ - "" "$op" + "$op" "" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/unop/*.\[cS\]]] \ - "" "$op" + "$op" "" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/ternop/*.\[cS\]]] \ "$op" "" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/reduc/*.\[cS\]]] \ From patchwork Wed Dec 4 02:08:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 102344 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BC36C3858D3C for ; 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X-CSE-ConnectionGUID: JX1nKE1uT0eSBHeGwvU+/w== X-CSE-MsgGUID: 8aozXoHwSxWdT4YSzmr9Vg== X-IronPort-AV: E=McAfee;i="6700,10204,11275"; a="58930791" X-IronPort-AV: E=Sophos;i="6.12,206,1728975600"; d="scan'208";a="58930791" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2024 18:10:47 -0800 X-CSE-ConnectionGUID: omPpIGNOTBen0b7HqPYa6Q== X-CSE-MsgGUID: rnwWADcDSX2EZD/o5XSiRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,206,1728975600"; d="scan'208";a="131071846" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa001.jf.intel.com with ESMTP; 03 Dec 2024 18:10:45 -0800 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 2/2] RISC-V: Refactor the testcases for bswap16-0 Date: Wed, 4 Dec 2024 10:08:12 +0800 Message-ID: <20241204020812.3604240-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241204020812.3604240-1-pan2.li@intel.com> References: <20241204020812.3604240-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li This patch would like to refactor the testcases of bswap16-0 after sorts of optimization option passing to testcase. To fits the big lmul like m8 for asm dump check. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/bswap16-0.c: Update the vector register RE to cover v10 - v31. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c index 605b3565b6b..4b55c001a31 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c @@ -10,7 +10,7 @@ ** ... ** vsrl\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ ** vsll\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ -** vor\.vv\s+v[0-9]+,\s*v[0-9],\s*v[0-9]+ +** vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ ** ... */ TEST_UNARY_CALL (uint16_t, __builtin_bswap16)