From patchwork Mon Dec 2 02:27:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Chu X-Patchwork-Id: 102203 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AC84C3858C98 for ; Mon, 2 Dec 2024 02:28:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AC84C3858C98 X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from NelsondeMBP.localdomain (36-230-178-162.dynamic-ip.hinet.net [36.230.178.162]) by sourceware.org (Postfix) with ESMTP id 0D4CB3858D33 for ; Mon, 2 Dec 2024 02:27:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D4CB3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=NelsondeMBP.localdomain ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0D4CB3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=36.230.178.162 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733106442; cv=none; b=TsZpS5IiqW0XfYCiO5kN2vhi82vlHg+85P/tg1P3qTrdEBLpuJO0IvodnFAyafBHrUnldos00b399cRKb6TVw1SnXerQD79JTZt3AvjUM6qQgOPtKtpS1CtHGCoCzQxSdVbP0mGMXwV5FA/gmad1JnKYSpLAFHH9+sRF3l3WIO8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733106442; c=relaxed/simple; bh=71MlHTWq/m2DW+HYSrTPwkNBo9lYmw4dNKXS50xm9q4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=q/JDSRmHpYZELxIkgq0+Zf4ZA5wlCuHdzVnk3d2NSDTWJseIVFEzlmoGNDd5tGVm6tbfpzpzRx66TZOjluMU5Uu0qxydbhBactKrQBWDWM44sM2WLVkYKU19SkJkIdu8HEWrv+LtRWlljoAzhmOTyB6p43Tgb0wY9cB4IC3Wnds= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0D4CB3858D33 Received: by NelsondeMBP.localdomain (Postfix, from userid 501) id 9F44B2538F78; Mon, 2 Dec 2024 10:27:17 +0800 (CST) From: Nelson Chu To: binutils@sourceware.org Cc: chendongyan@isrc.iscas.ac.cn Subject: [committed v3] RISC-V: Add support for ssdbltrp and smdbltrp extension. Date: Mon, 2 Dec 2024 10:27:16 +0800 Message-Id: <20241202022716.46238-1-nelson@rivosinc.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, NO_DNS_FOR_FROM, RCVD_IN_PBL, RDNS_DYNAMIC, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: Dongyan Chen This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp extensions, version1.0[2]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc [2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc bfd/ChangeLog: * elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn standard extensions. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/imply.d: Ditto. * testsuite/gas/riscv/imply.s: Ditto. * testsuite/gas/riscv/march-help.l: Ditto. --- bfd/elfxx-riscv.c | 4 ++++ gas/NEWS | 4 ++-- gas/testsuite/gas/riscv/imply.d | 2 ++ gas/testsuite/gas/riscv/imply.s | 3 +++ gas/testsuite/gas/riscv/march-help.l | 2 ++ 5 files changed, 13 insertions(+), 2 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 45da83e6926..a6511f6558d 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1262,6 +1262,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"smcntrpmf", "+zicsr", check_implicit_always}, {"smstateen", "+ssstateen", check_implicit_always}, {"smepmp", "+zicsr", check_implicit_always}, + {"smdbltrp", "+zicsr", check_implicit_always}, {"ssaia", "+zicsr", check_implicit_always}, {"sscsrind", "+zicsr", check_implicit_always}, @@ -1272,6 +1273,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"sstvala", "+zicsr", check_implicit_always}, {"sstvecd", "+zicsr", check_implicit_always}, {"ssu64xl", "+zicsr", check_implicit_always}, + {"ssdbltrp", "+zicsr", check_implicit_always}, {"svade", "+zicsr", check_implicit_always}, {"svadu", "+zicsr", check_implicit_always}, @@ -1448,6 +1450,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smrnmi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1458,6 +1461,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/NEWS b/gas/NEWS index 23eda334ec6..269b63e2056 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -9,8 +9,8 @@ * On x86 emulation support (for secondary targets) was dropped. -* Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi, CORE-V - (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive +* Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi, S[sm]dbltrp, + CORE-V (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive extensions (xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf). Changes in 2.43: diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d index 26eff8c650a..474694d9071 100644 --- a/gas/testsuite/gas/riscv/imply.d +++ b/gas/testsuite/gas/riscv/imply.d @@ -80,6 +80,7 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smdbltrp1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0 @@ -89,6 +90,7 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvala1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvecd1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssu64xl1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssdbltrp1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svade1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svadu1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svbare1p0 diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s index dabb08d8c8b..790c6f335ee 100644 --- a/gas/testsuite/gas/riscv/imply.s +++ b/gas/testsuite/gas/riscv/imply.s @@ -90,6 +90,8 @@ imply smcsrind imply smcntrpmf imply smstateen imply smepmp +imply smdbltrp + imply ssaia imply sscsrind imply sscofpmf @@ -99,6 +101,7 @@ imply sstc imply sstvala imply sstvecd imply ssu64xl +imply ssdbltrp imply svade imply svadu diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 71cccb77102..fd1174059e5 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -117,6 +117,7 @@ All available -march extensions for RISC-V: smepmp 1.0 smrnmi 1.0 smstateen 1.0 + smdbltrp 1.0 ssaia 1.0 ssccptr 1.0 sscsrind 1.0 @@ -127,6 +128,7 @@ All available -march extensions for RISC-V: sstvala 1.0 sstvecd 1.0 ssu64xl 1.0 + ssdbltrp 1.0 svade 1.0 svadu 1.0 svbare 1.0