From patchwork Fri Nov 22 05:13:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chendongyan X-Patchwork-Id: 101717 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CAEA9385802C for ; Fri, 22 Nov 2024 05:15:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CAEA9385802C X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTPS id DD434385802C for ; Fri, 22 Nov 2024 05:14:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DD434385802C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DD434385802C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1732252480; cv=none; b=guiAKORWW+IpMtWju6Rc/Qec7iyKXgrYMZh/NfjVoXWtt4PT3+bq6STRKoViiRvFXAyfiGvzt2SailB0OoHmmj59SdTAL0uxb+ae8yVel76Ga0Al2J+/ED5fLo4JqWfOc3+oYIXNyPXmVKci7Dto9EG0BAgH0AQFwvCulnDHZ7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1732252480; c=relaxed/simple; bh=nbarWB+Ao8iWJETTzhR9fBvVPf2YEg5j33gVkIe8N9E=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=OLmgKYCBYyB2tRj5SA0cKWw20bB+Xd0LpGzYV/QUaBp6ejmJFi5nS/LCSlB7GYcyb46dHOcl/EQzS2NU9IfLX85bmHcJfzIGn7Nk8jE4iZL22t5CtXzUQp4LgSKgWnDNEqPHnLPDKLhGQTpcJNbJs5NxTb4Nsv0n+jzlVIXSH+0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DD434385802C Received: from GNU.. (unknown [47.252.79.111]) by APP-01 (Coremail) with SMTP id qwCowABXKMQzE0Bnqsz5BA--.14913S2; Fri, 22 Nov 2024 13:14:32 +0800 (CST) From: Dongyan Chen To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, jlaw@ventanamicro.com, chenyixuan@iscas.ac.cn, Dongyan Chen Subject: [PATCH v3] RISC-V: Minimal support for svvptc extension. Date: Fri, 22 Nov 2024 13:13:46 +0800 Message-ID: <20241122051346.11171-1-chendongyan@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CM-TRANSID: qwCowABXKMQzE0Bnqsz5BA--.14913S2 X-Coremail-Antispam: 1UD129KBjvJXoWxurWxAF4fKryUWryrury7trb_yoW5Aw4kpF 48Gw4rA3yFq3Z7Ww4xtFWUWFW5Jwn3Wrn5Zw4kur1UArWDJrWDAF1v934xGw4kXF4jqrn3 Ca1F9FWYyw4UC37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkl14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWUGVWUWwAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWU tVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14 v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkG c2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4U MIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbGQ6JUUUU U== X-Originating-IP: [47.252.79.111] X-CM-SenderInfo: hfkh0v5rqj5tnq6l223fol2u1dvotugofq/ X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org This patch support svvptc extension[1]. To enable GCC to recognize and process svvptc extension correctly at compile time. [1] https://github.com/riscv/riscv-svvptc gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto. * config/riscv/riscv.opt: New mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-44.c: New test. add svvptc testsuite --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/common/config/riscv/riscv-ext-bitmask.def | 1 + gcc/config/riscv/riscv.opt | 2 ++ gcc/testsuite/gcc.target/riscv/arch-44.c | 5 +++++ 4 files changed, 10 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index b0e49eb82c0..199b449a22f 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -405,6 +405,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svvptc", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1720,6 +1721,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), + RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC), RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def index ca5df1740f3..a733533df98 100644 --- a/gcc/common/config/riscv/riscv-ext-bitmask.def +++ b/gcc/common/config/riscv/riscv-ext-bitmask.def @@ -79,5 +79,6 @@ RISCV_EXT_BITMASK ("zcd", 1, 4) RISCV_EXT_BITMASK ("zcf", 1, 5) RISCV_EXT_BITMASK ("zcmop", 1, 6) RISCV_EXT_BITMASK ("zawrs", 1, 7) +RISCV_EXT_BITMASK ("svvptc", 1, 8) #undef RISCV_EXT_BITMASK diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ab9d6e82723..b9e980e30f5 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -466,6 +466,8 @@ Mask(SVINVAL) Var(riscv_sv_subext) Mask(SVNAPOT) Var(riscv_sv_subext) +Mask(SVVPTC) Var(riscv_sv_subext) + TargetVariable int riscv_ztso_subext diff --git a/gcc/testsuite/gcc.target/riscv/arch-44.c b/gcc/testsuite/gcc.target/riscv/arch-44.c new file mode 100644 index 00000000000..80dc19a7083 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-44.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svvptc -mabi=lp64" } */ +int foo() +{ +}