From patchwork Thu Oct 21 01:42:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 46470 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 50C523857C52 for ; Thu, 21 Oct 2021 01:43:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 50C523857C52 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1634780585; bh=wGWVoGFQr9sD9SDRB8bDnkCCiUsVaR37cyL36PqVOrM=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=p7Olek6Nr7jQ2P1+BaRstw9cC+Jko6OL9LYGpssnIKFvyswzNSWI3ZHsahPmi7n9O TzgDVUmbk0JFRaTS6VzrQAxmojtvNbPkxlZIrbZyFRMLYxkS277ij74eFGIPIhbker i+DDmdg3+NcFD+c8EfmxFXTkOgl/Vb+6W3SenMhM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 2E4723857C78 for ; Thu, 21 Oct 2021 01:42:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2E4723857C78 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19L1MReo007058; Wed, 20 Oct 2021 21:42:17 -0400 Received: from ppma01dal.us.ibm.com (83.d6.3fa9.ip4.static.sl-reverse.com [169.63.214.131]) by mx0a-001b2d01.pphosted.com with ESMTP id 3btxg30akj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Oct 2021 21:42:17 -0400 Received: from pps.filterd (ppma01dal.us.ibm.com [127.0.0.1]) by ppma01dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 19L1gEuE017471; Thu, 21 Oct 2021 01:42:16 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma01dal.us.ibm.com with ESMTP id 3bqpcd7fh5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Oct 2021 01:42:16 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 19L1gFge34210278 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Oct 2021 01:42:15 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E9C3CAC05E; Thu, 21 Oct 2021 01:42:14 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B629CAC064; Thu, 21 Oct 2021 01:42:14 +0000 (GMT) Received: from localhost (unknown [9.160.109.161]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Thu, 21 Oct 2021 01:42:14 +0000 (GMT) To: segher@kernel.crashing.org Subject: [PATCH] rs6000: Add Power10 optimization for _mm_blendv* Date: Wed, 20 Oct 2021 20:42:07 -0500 Message-Id: <20211021014207.342435-1-pc@us.ibm.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4cxIRgQXwwWa3LUh6hTfVdhp6g0N8HUU X-Proofpoint-ORIG-GUID: 4cxIRgQXwwWa3LUh6hTfVdhp6g0N8HUU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-20_06,2021-10-20_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 bulkscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110210007 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Paul A. Clarke via Gcc-patches" From: "Paul A. Clarke" Reply-To: "Paul A. Clarke" Cc: wschmidt@linux.ibm.com, gcc-patches@gcc.gnu.org Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Power10 ISA added `xxblendv*` instructions which are realized in the `vec_blendv` instrinsic. Use `vec_blendv` for `_mm_blendv_epi8`, `_mm_blendv_ps`, and `_mm_blendv_pd` compatibility intrinsics, when `_ARCH_PWR10`. Also, copy a test from i386 for testing `_mm_blendv_ps`. This should have come with commit ed04cf6d73e233c74c4e55c27f1cbd89ae4710e8, but was inadvertently omitted. 2021-10-20 Paul A. Clarke gcc * config/rs6000/smmintrin.h (_mm_blendv_epi8): Use vec_blendv when _ARCH_PWR10. (_mm_blendv_ps): Likewise. (_mm_blendv_pd): Likewise. gcc/testsuite * gcc.target/powerpc/sse4_1-blendvps.c: Copy from gcc.target/i386, adjust dg directives to suit. --- Tested on Power10 powerpc64le-linux (compiled with and without `-mcpu=power10`). OK for trunk? gcc/config/rs6000/smmintrin.h | 12 ++++ .../gcc.target/powerpc/sse4_1-blendvps.c | 65 +++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h index b732fbca7b09..5d87fd7b6f61 100644 --- a/gcc/config/rs6000/smmintrin.h +++ b/gcc/config/rs6000/smmintrin.h @@ -113,9 +113,13 @@ _mm_blend_epi16 (__m128i __A, __m128i __B, const int __imm8) extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_blendv_epi8 (__m128i __A, __m128i __B, __m128i __mask) { +#ifdef _ARCH_PWR10 + return (__m128i) vec_blendv ((__v16qu) __A, (__v16qu) __B, (__v16qu) __mask); +#else const __v16qu __seven = vec_splats ((unsigned char) 0x07); __v16qu __lmask = vec_sra ((__v16qu) __mask, __seven); return (__m128i) vec_sel ((__v16qu) __A, (__v16qu) __B, __lmask); +#endif } __inline __m128 @@ -149,9 +153,13 @@ __inline __m128 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_blendv_ps (__m128 __A, __m128 __B, __m128 __mask) { +#ifdef _ARCH_PWR10 + return (__m128) vec_blendv ((__v4sf) __A, (__v4sf) __B, (__v4su) __mask); +#else const __v4si __zero = {0}; const __vector __bool int __boolmask = vec_cmplt ((__v4si) __mask, __zero); return (__m128) vec_sel ((__v4su) __A, (__v4su) __B, (__v4su) __boolmask); +#endif } __inline __m128d @@ -174,9 +182,13 @@ __inline __m128d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_blendv_pd (__m128d __A, __m128d __B, __m128d __mask) { +#ifdef _ARCH_PWR10 + return (__m128d) vec_blendv ((__v2df) __A, (__v2df) __B, (__v2du) __mask); +#else const __v2di __zero = {0}; const __vector __bool long long __boolmask = vec_cmplt ((__v2di) __mask, __zero); return (__m128d) vec_sel ((__v2du) __A, (__v2du) __B, (__v2du) __boolmask); +#endif } #endif diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c new file mode 100644 index 000000000000..8fcb55383047 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c @@ -0,0 +1,65 @@ +/* { dg-do run } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ + +#include "sse4_1-check.h" + +#include +#include + +#define NUM 20 + +static void +init_blendvps (float *src1, float *src2, float *mask) +{ + int i, msk, sign = 1; + + msk = -1; + for (i = 0; i < NUM * 4; i++) + { + if((i % 4) == 0) + msk++; + src1[i] = i* (i + 1) * sign; + src2[i] = (i + 20) * sign; + mask[i] = (i + 120) * i; + if( (msk & (1 << (i % 4)))) + mask[i] = -mask[i]; + sign = -sign; + } +} + +static int +check_blendvps (__m128 *dst, float *src1, float *src2, + float *mask) +{ + float tmp[4]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 4; j++) + if (mask [j] < 0.0) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +sse4_1_test (void) +{ + union + { + __m128 x[NUM]; + float f[NUM * 4]; + } dst, src1, src2, mask; + int i; + + init_blendvps (src1.f, src2.f, mask.f); + + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blendv_ps (src1.x[i], src2.x[i], mask.x[i]); + if (check_blendvps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], + &mask.f[i * 4])) + abort (); + } +}