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Sat, 2 Nov 2024 08:58:41 +0000 (GMT) X-AuditID: cbfec7f2-b11c470000005155-8f-6725e9c2e8f6 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id C7.F3.19654.1C9E5276; Sat, 2 Nov 2024 08:58:41 +0000 (GMT) Received: from [106.109.129.19] (unknown [106.109.129.19]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20241102085841eusmtip1425e4a4d8c3bb53b9a1be9fc57449716~EGxIgR1Uz0818308183eusmtip1e; Sat, 2 Nov 2024 08:58:41 +0000 (GMT) Message-ID: <3ebcb202-d6e5-4368-9217-033345fa308a@samsung.com> Date: Sat, 2 Nov 2024 11:58:40 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: alexey.merzlyakov@samsung.com Content-Language: en-US From: Alexey Merzlyakov Subject: [PATCH] RISC-V: zero_extend(not) -> xor optimization [PR112398] To: gcc-patches@gcc.gnu.org X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOIsWRmVeSWpSXmKPExsWy7djPc7qHX6qmG+ydwmixqmcbk8Wn/+kO TB5H729k8ujbsooxgCmKyyYlNSezLLVI3y6BK+P7pj1sBSdkK/73b2BsYLwi0cXIySEhYCKx fvFVli5GLg4hgRWMEuvn3WOGcL4wSuyePJ0RwvnMKPH5y1ImmJaD3VdZIRLLGSVubW6H6n/P KHG7dydYFa+AncThx21gNouAisSPd4ug4oISJ2c+YQGxRQXkJe7fmsEOYjMLKEps+fSCCcIW l7j1ZD6YzSZgLnHi5FSwemEBD4nDR3aygtgiAtISN25MZoSol5do3job7G4JgUYOicedy1gg TnWROHVqAZQtLPHq+BZ2CFtG4vTkHhaIhnZGib57e5kgnAmMEp3ft7FBVNlLdN1vAOrgAFqh KbF+lz5E2FFixr1DYGEJAT6JG28FIY7gk5i0bTozRJhXoqNNCKJaW2L3wQ1QAxUl9n6/B3WO h8TeC+2MExgVZyEFyywk789C8toshBsWMLKsYhRPLS3OTU8tNsxLLdcrTswtLs1L10vOz93E CEwbp/8d/7SDce6rj3qHGJk4GA8xSnAwK4nwfihQThfiTUmsrEotyo8vKs1JLT7EKM3BoiTO q5oinyokkJ5YkpqdmlqQWgSTZeLglGpgknQ0ujFnyuz48ssRDytVl9Wt2Z6rc2ph4M/HP66s m/Fylnjv41nisQtqLltpzJWR5BIy/Wca1xjSUe/49LHb2p3Hztxz3l+Yk1X8NFQsaf4aR9VT 2/KeHVs1q621ie2rf4g3979PNaYNpUavFl/Wd1Y7lW+srvVzJ/f5dv8Uzkliy/7I/j/6ZqHG n7kvpkRWtPUwi/xb4/dS3nU+j8scHk6ruapf7d9Piym5V3HqwTb3A30LMyW3VXo66+yMNexS rVwY4W+Q39ktsGrFpYDEdCed6HB2iX0P/gXH99tmv/xZ98u2O/Hm3MapyXe0xJ+IH9TLtDng XpOXKtbfdaDzxPW79195zZwdcL18Zo2NEktxRqKhFnNRcSIAeUutWIoDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrALMWRmVeSWpSXmKPExsVy+t/xu7oHX6qmG/z/q2Oxqmcbk8Wn/+kO TB5H729k8ujbsooxgClKz6Yov7QkVSEjv7jEVina0MJIz9DSQs/IxFLP0Ng81srIVEnfziYl NSezLLVI3y5BL+P7pj1sBSdkK/73b2BsYLwi0cXIySEhYCJxsPsqaxcjF4eQwFJGifUt65gh EooSc/e/Z4WwhSX+XOtigyh6yyjx68khFpAEr4CdxOHHbUwgNouAisSPd4uYIOKCEidnPgGr ERWQl7h/awY7iM0MNHTLpxdMELa4xK0n88FsNgFziRMnp4LVCwt4SBw+shNssYiAtMSNG5MZ IerNJLq2dkHZ8hLNW2czT2AUmIVk3SwkY2chaZmFpGUBI8sqRpHU0uLc9NxiI73ixNzi0rx0 veT83E2MwKDfduznlh2MK1991DvEyMTBeIhRgoNZSYT3Q4FyuhBvSmJlVWpRfnxRaU5q8SFG U6CfJzJLiSbnA+MuryTe0MzA1NDEzNLA1NLMWEmcl+3K+TQhgfTEktTs1NSC1CKYPiYOTqkG puIcUZOGRx+eigYrzE3V4Ih3js1452su8bXo9UoL/8LjjArBetay8ze9CdL09fmxNl7oUL3R rcMKE8VYsqKWFB/prGQ48+nczOYVPc5zbh2I/cc0QWfivx69Y7XOLzo1L0U85RN8ryH/8m9Z 3vcjMh132n63GbolvjIWUH02xeSrl3awbs3maMbc1CPrzcysHtjYMhbUdT4+xrmjkdOtkd3m xPxD7654iRfPKGNiKGKTjLpfUyusuvCnq9LEPWp6zqvueIu+LshacbY18k1umq/72bpovquv 9/I5fu19d3PJxMIvLRcLZTZLqfAfs7D1Km/bUM2W4XGte6Jef4jkEwc3t4rT+XluCv9slyix FGckGmoxFxUnAgBxcNUxAwMAAA== X-CMS-MailID: 20241102085841eucas1p18073a29ca676e921a1ccb49dfa28d520 X-Msg-Generator: CA X-RootMTR: 20241102085841eucas1p18073a29ca676e921a1ccb49dfa28d520 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241102085841eucas1p18073a29ca676e921a1ccb49dfa28d520 References: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, BODY_8BITS, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org This patch adds optimization of the following patterns:   (zero_extend:M (subreg:N (not:O==M (X:Q==M)))) ->   (xor:M (zero_extend:M (subreg:N (X:M)), 0xffff))     ... where mask takes 0xffff bits of N mode bitsize For the cases when X:M doesn't have any non-zero bits outside of mode N, (zero_extend:M (subreg:N (X:M)) could be simplified to just (X:M) and whole optimization will be:   (zero_extend:M (subreg:N (not:M (X:M)))) ->   (xor:M (X:M, 0xffff)) Patch targets to handle code patterns like:   not   a0,a0   andi  a0,a0,0xff to be optimized to:   xori    a0,a0,255 Change was locally tested for x86_64 and AArch64 (as most common) and for RV-64 and MIPS-32 targets (as having an effect from this optimization): no regressions for all cases. gcc/ChangeLog:     * simplify-rtx.cc (simplify_context::simplify_unary_operation_1):     Simplify ZERO_EXTEND (SUBREG (NOT X)) to XOR (X, 0xff...f) when X     doesn't have any non-zero bits outside of SUBREG mode. gcc/testsuite/ChangeLog:     * gcc.target/riscv/pr112398.c: New test. Signed-off-by: Alexey Merzlyakov ---  gcc/simplify-rtx.cc                       | 23 +++++++++++++++++++++++  gcc/testsuite/gcc.target/riscv/pr112398.c | 14 ++++++++++++++  2 files changed, 37 insertions(+)  create mode 100644 gcc/testsuite/gcc.target/riscv/pr112398.c diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index 2c04ce960ee..608ecedbcb8 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -1842,6 +1842,29 @@ simplify_context::simplify_unary_operation_1 (rtx_code code, machine_mode mode,            & ~GET_MODE_MASK (op_mode)) == 0)      return SUBREG_REG (op); +      /* Trying to optimize: +     (zero_extend:M (subreg:N (not:M (X:M)))) -> +     (xor:M (zero_extend:M (subreg:N (X:M)), 0xffff)) +     where mask takes 0xffff bits of N mode bitsize. +     For the cases when X:M doesn't have any non-zero bits +     outside of mode N, (zero_extend:M (subreg:N (X:M)) +     will be simplified to just (X:M) +     and whole optimization will be -> (xor:M (X:M), 0xffff). */ +      if (GET_CODE (op) == SUBREG +      && GET_CODE (XEXP (op, 0)) == NOT +      && GET_MODE (XEXP (op, 0)) == mode +      && GET_MODE (XEXP (XEXP (op, 0), 0)) == mode +      && subreg_lowpart_p (op) +      && (nonzero_bits (XEXP (XEXP (op, 0), 0), mode) +          & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (op, 0), 0)))) == 0) +      { +    const uint64_t mask +      = ~((uint64_t)~0 << GET_MODE_BITSIZE (GET_MODE (op)).coeffs[0]); +    return simplify_gen_binary (XOR, mode, +                    XEXP (XEXP (op, 0), 0), +                    gen_int_mode (mask, mode)); +      } +  #if defined(POINTERS_EXTEND_UNSIGNED)        /* As we do not know which address space the pointer is referring to,       we can do this only if the target does not support different pointer diff --git a/gcc/testsuite/gcc.target/riscv/pr112398.c b/gcc/testsuite/gcc.target/riscv/pr112398.c new file mode 100644 index 00000000000..624a665b76c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr112398.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +#include + +uint8_t neg_u8 (const uint8_t src) +{ +  return ~src; +} + +/* { dg-final { scan-assembler-times "xori\t" 1 } } */ +/* { dg-final { scan-assembler-not "not\t" } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */