From patchwork Wed Oct 30 17:14:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 99834 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 730B13857C6E for ; Wed, 30 Oct 2024 17:14:46 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 71B21385841E for ; Wed, 30 Oct 2024 17:14:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 71B21385841E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 71B21385841E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730308456; cv=none; b=phiODCyYxH9FQyEpKWu+nW6UybT5mpzZFv2JlFZwPHb4LRNoyHjWmUZ4qNKEGwN2Pp5NO1Qhbc914g64vro6BOKM01DFMsWawu+5OMp1wTv3ihJsmRvJx2mpdliP1LCS0FwIOgISNhI+BUDY+LDsTF2DstOQ+oeTWdDEPYXgcaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730308456; c=relaxed/simple; bh=cVTCkDOjOR30I30Wg3/U4TqXuzJNR5npM5k1oHUtfGs=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=qZtRnYOQdMax2/OiTEuihAGUs6vxxBF+FloWQy+4rPWhQs8rrO/jwPql+ua0KPuC5PTWBuilV7KCmPzu0bvm0D8NE6zfEVMXVPJDdB5WFjm1xjQokaWxCAE17KunKGbSnGZxnrSSM9O1sbwshNZfoh8fBcNzG3RtUCTiB5BaDpw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CAC1911FB; Wed, 30 Oct 2024 10:14:42 -0700 (PDT) Received: from [10.57.24.83] (unknown [10.57.24.83]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 900973F66E; Wed, 30 Oct 2024 10:14:10 -0700 (PDT) Message-ID: Date: Wed, 30 Oct 2024 17:14:06 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 1/2] arm, objdump: Make objdump use bfd's machine detection to drive disassembly To: binutils@sourceware.org References: <37e1e3d7-ada9-47a7-9830-9f8f9aaa145b@arm.com> Content-Language: en-US Cc: "richard.earnshaw@arm.com" From: "Andre Vieira (lists)" In-Reply-To: <37e1e3d7-ada9-47a7-9830-9f8f9aaa145b@arm.com> X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch disables, for any elf target, an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. This patch teaches the disassembler to detect such situations by looking for the combination of the bx encoding bits and a relocation, and if both are present it will disassemble it as a bx instead. This patch removes the unused and wrongfully defined ARM_ARCH_V8A_CRC, and defines and uses a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. This also patches up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested. diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index 6f642dbe97f0121d664016ea85d14f2c96be24aa..3fda9465193398695a37ffa146487ab6db7f6e71 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -95,22 +95,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teq r0, #10 @ -0+15c <[^>]*> e132f004 ? teq r2, r4 @ -0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ -0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ -0+168 <[^>]*> e370f00a ? cmn r0, #10 @ -0+16c <[^>]*> e172f004 ? cmn r2, r4 @ -0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ -0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ -0+178 <[^>]*> e350f00a ? cmp r0, #10 @ -0+17c <[^>]*> e152f004 ? cmp r2, r4 @ -0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ -0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ -0+188 <[^>]*> e310f00a ? tst r0, #10 @ -0+18c <[^>]*> e112f004 ? tst r2, r4 @ -0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ -0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ +0+158 <[^>]*> e330f00a ? teqp r0, #10 +0+15c <[^>]*> e132f004 ? teqp r2, r4 +0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 +0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 +0+168 <[^>]*> e370f00a ? cmnp r0, #10 +0+16c <[^>]*> e172f004 ? cmnp r2, r4 +0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 +0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 +0+178 <[^>]*> e350f00a ? cmpp r0, #10 +0+17c <[^>]*> e152f004 ? cmpp r2, r4 +0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 +0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 +0+188 <[^>]*> e310f00a ? tstp r0, #10 +0+18c <[^>]*> e112f004 ? tstp r2, r4 +0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 +0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/gas/testsuite/gas/arm/nops.d b/gas/testsuite/gas/arm/nops.d index bda0c307dceb022f63b0457434c7ee3992d452b1..0f5de019bbef4256a7a454753f4c6ce60ba1f786 100644 --- a/gas/testsuite/gas/arm/nops.d +++ b/gas/testsuite/gas/arm/nops.d @@ -1,4 +1,5 @@ # name: NOP instructions +# as: -march=armv7-a # objdump: -dr --prefix-addresses --show-raw-insn # skip: *-*-pe *-*-wince diff --git a/gas/testsuite/gas/arm/unpredictable.d b/gas/testsuite/gas/arm/unpredictable.d index 0781c18377ca21833145cf9111ad79d9b2f342fb..0d3c14b623406a795bac81c8ee4739b99bd3108b 100644 --- a/gas/testsuite/gas/arm/unpredictable.d +++ b/gas/testsuite/gas/arm/unpredictable.d @@ -1,4 +1,5 @@ # name: Upredictable Instructions +# as: -march=armv6 # objdump: -D --prefix-addresses --show-raw-insn .*: +file format .*arm.* diff --git a/include/opcode/arm.h b/include/opcode/arm.h index a89c215faff8660b8fbd276a08738a1fce3cb169..de1fcd49adb83111d6926e8eea9b1f0e80c2f74a 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -354,8 +354,6 @@ #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) -#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, \ - ARM_AEXT2_V8A | ARM_EXT2_CRC) #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A \ | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA) #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A \ @@ -381,6 +379,8 @@ #define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \ ARM_AEXT2_V8M_MAIN_DSP) #define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) +#define ARM_ARCH_V8R_CRC ARM_FEATURE_CORE (ARM_AEXT_V8R, \ + ARM_AEXT2_V8R | ARM_EXT2_CRC) #define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \ ARM_AEXT2_V8_1M_MAIN) #define ARM_ARCH_V9A ARM_FEATURE_ALL(ARM_AEXT_V8A, \ diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index d1d7ca309934d31daf47bc529d2c1bb8313022f5..2bcc1d2c828e4931213ded390e23d026a69bcb64 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -10050,7 +10050,14 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if ((given & insn->mask) != insn->value) continue; - if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) + if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features) + /* If we are dealing with a bx instruction and arvm4, with a + relocation, then it is likely this was assembled with --fix-v4bx + and thus intended as a mode changing instruction, so disassemble + it as such. */ + && (insn->value != 0x12fff10 + || info->mach != bfd_mach_arm_4 + || ((info->flags & INSN_HAS_RELOC) == 0))) continue; /* Special case: an instruction with all bits set in the condition field @@ -12292,7 +12299,7 @@ select_arm_features (unsigned long mach, ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset); break; } - case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; + case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R_CRC); break; case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; case bfd_mach_arm_8_1M_MAIN: @@ -12358,7 +12365,8 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bool little) { static struct arm_private_data private; - if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) + if (info->flavour != bfd_target_elf_flavour + && (info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) /* If the user did not use the -m command line switch then default to disassembling all types of ARM instruction. From patchwork Wed Oct 30 17:15:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 99835 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B07EF3858429 for ; Wed, 30 Oct 2024 17:15:47 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id BCE3F385843D for ; Wed, 30 Oct 2024 17:15:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BCE3F385843D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BCE3F385843D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730308520; cv=none; b=Taexf/tVQ4wsMj5WYuRqnNMAMa2QtR9SoyGaw/ADZ19q+dx3WrDcmAYuTEM4MhnLIitZ7MmE6os9XO13noDB8MPpoed2N/p+L8aM6bwB3Ib0j2ql6EBfUzDTLeXCOlfO9j9iDoOMl7YKFQyV12Pi2kHkZmDvhBxcOxqrq8S41gE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730308520; c=relaxed/simple; bh=ZFUVAopqkqJZXufq4P5LqZozdk9AAqgp/qrt4SXMy24=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=soOiBlvLrBhCVd1VZLF7SH9S5J8T0Km7jxBMp9yFyyroGGKOc3XWtwfhOZYUbq7VjdqahT19W2/j9YVRuOKQIIs58B7g3G4TkCHmlE5Nv1KL7pfKwZyIbYQ0dpWOPcbTjLOpriRbM3vH/qS02AGZjFJ3t1YGE4dUpJ0OxgCQ3RY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1DD92113E; Wed, 30 Oct 2024 10:15:44 -0700 (PDT) Received: from [10.57.24.83] (unknown [10.57.24.83]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF3A93F66E; Wed, 30 Oct 2024 10:15:13 -0700 (PDT) Message-ID: <19e053de-38f3-4777-a7b9-b71189955426@arm.com> Date: Wed, 30 Oct 2024 17:15:12 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/2] arm: print obsolote warning when 26-bit set in instructions To: binutils@sourceware.org References: <37e1e3d7-ada9-47a7-9830-9f8f9aaa145b@arm.com> Content-Language: en-US Cc: "richard.earnshaw@arm.com" From: "Andre Vieira (lists)" In-Reply-To: <37e1e3d7-ada9-47a7-9830-9f8f9aaa145b@arm.com> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Arm has obsoleted the 26-bit addressing mode. Diagnose this when disassembling these instructions by printing OBSOLETE. diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d index 3ae310a2fb777598a3402c58b3af990c2d78dc3b..1e0df1e999d1c84f3b1df4d082c1fc23e9b50926 100644 --- a/gas/testsuite/gas/arm/armv1.d +++ b/gas/testsuite/gas/arm/armv1.d @@ -30,16 +30,16 @@ Disassembly of section .text: 0+4c <[^>]*> e1d00000 ? bics r0, r0, r0 0+50 <[^>]*> e1100000 ? tst r0, r0 0+54 <[^>]*> e1100000 ? tst r0, r0 -0+58 <[^>]*> e110f000 ? tstp r0, r0 +0+58 <[^>]*> e110f000 ? tstp r0, r0 @ p-variant is OBSOLETE 0+5c <[^>]*> e1300000 ? teq r0, r0 0+60 <[^>]*> e1300000 ? teq r0, r0 -0+64 <[^>]*> e130f000 ? teqp r0, r0 +0+64 <[^>]*> e130f000 ? teqp r0, r0 @ p-variant is OBSOLETE 0+68 <[^>]*> e1500000 ? cmp r0, r0 0+6c <[^>]*> e1500000 ? cmp r0, r0 -0+70 <[^>]*> e150f000 ? cmpp r0, r0 +0+70 <[^>]*> e150f000 ? cmpp r0, r0 @ p-variant is OBSOLETE 0+74 <[^>]*> e1700000 ? cmn r0, r0 0+78 <[^>]*> e1700000 ? cmn r0, r0 -0+7c <[^>]*> e170f000 ? cmnp r0, r0 +0+7c <[^>]*> e170f000 ? cmnp r0, r0 @ p-variant is OBSOLETE 0+80 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\) 0+84 <[^>]*> e1b00000 ? movs r0, r0 0+88 <[^>]*> e1e00000 ? mvn r0, r0 diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index 3fda9465193398695a37ffa146487ab6db7f6e71..78f4958d6ebf9c517cfa9d747cfa062d7e1f2119 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -95,22 +95,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 -0+15c <[^>]*> e132f004 ? teqp r2, r4 -0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 -0+16c <[^>]*> e172f004 ? cmnp r2, r4 -0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 -0+17c <[^>]*> e152f004 ? cmpp r2, r4 -0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 -0+18c <[^>]*> e112f004 ? tstp r2, r4 -0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 +0+158 <[^>]*> e330f00a ? teqp r0, #10 @ p-variant is OBSOLETE +0+15c <[^>]*> e132f004 ? teqp r2, r4 @ p-variant is OBSOLETE +0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+168 <[^>]*> e370f00a ? cmnp r0, #10 @ p-variant is OBSOLETE +0+16c <[^>]*> e172f004 ? cmnp r2, r4 @ p-variant is OBSOLETE +0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+178 <[^>]*> e350f00a ? cmpp r0, #10 @ p-variant is OBSOLETE +0+17c <[^>]*> e152f004 ? cmpp r2, r4 @ p-variant is OBSOLETE +0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+188 <[^>]*> e310f00a ? tstp r0, #10 @ p-variant is OBSOLETE +0+18c <[^>]*> e112f004 ? tstp r2, r4 @ p-variant is OBSOLETE +0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 @ p-variant is OBSOLETE 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/gas/testsuite/gas/arm/pinsn.d b/gas/testsuite/gas/arm/pinsn.d deleted file mode 100644 index 792843e4cdd133f1634731bc7daed736c660a3d5..0000000000000000000000000000000000000000 --- a/gas/testsuite/gas/arm/pinsn.d +++ /dev/null @@ -1,24 +0,0 @@ -# name: 26-bit teq/cmn/tst/cmp instructions -# objdump: -dr --prefix-addresses --show-raw-insn -marmv4 -# skip: *-*-pe *-*-wince - -.*: +file format .*arm.* - - -Disassembly of section .text: -0+000 <[^>]*> e330f00a ? teqp r0, #10 -0+004 <[^>]*> e132f004 ? teqp r2, r4 -0+008 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+00c <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+010 <[^>]*> e370f00a ? cmnp r0, #10 -0+014 <[^>]*> e172f004 ? cmnp r2, r4 -0+018 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+01c <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+020 <[^>]*> e350f00a ? cmpp r0, #10 -0+024 <[^>]*> e152f004 ? cmpp r2, r4 -0+028 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+02c <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+030 <[^>]*> e310f00a ? tstp r0, #10 -0+034 <[^>]*> e112f004 ? tstp r2, r4 -0+038 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+03c <[^>]*> e111f113 ? tstp r1, r3, lsl r1 diff --git a/gas/testsuite/gas/arm/pinsn.s b/gas/testsuite/gas/arm/pinsn.s deleted file mode 100644 index d0afc4655acbd1cf2f29837785082d7c69088be1..0000000000000000000000000000000000000000 --- a/gas/testsuite/gas/arm/pinsn.s +++ /dev/null @@ -1,16 +0,0 @@ -teqp r0, #10 -teqp r2, r4 -teqp r5, r7, lsl #5 -teqp r1, r3, lsl r1 -cmnp r0, #10 -cmnp r2, r4 -cmnp r5, r7, lsl #5 -cmnp r1, r3, lsl r1 -cmpp r0, #10 -cmpp r2, r4 -cmpp r5, r7, lsl #5 -cmpp r1, r3, lsl r1 -tstp r0, #10 -tstp r2, r4 -tstp r5, r7, lsl #5 -tstp r1, r3, lsl r1 diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d index 390e4536ae6d9d9c98d3c4e73614156777877798..4bbac43861d983159f78a502c7481a6361c2398e 100644 --- a/gas/testsuite/gas/arm/wince_inst.d +++ b/gas/testsuite/gas/arm/wince_inst.d @@ -97,22 +97,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teq r0, #10 @ -0+15c <[^>]*> e132f004 ? teq r2, r4 @ -0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ -0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ -0+168 <[^>]*> e370f00a ? cmn r0, #10 @ -0+16c <[^>]*> e172f004 ? cmn r2, r4 @ -0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ -0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ -0+178 <[^>]*> e350f00a ? cmp r0, #10 @ -0+17c <[^>]*> e152f004 ? cmp r2, r4 @ -0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ -0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ -0+188 <[^>]*> e310f00a ? tst r0, #10 @ -0+18c <[^>]*> e112f004 ? tst r2, r4 @ -0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ -0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ +0+158 <[^>]*> e330f00a ? teqp r0, #10 @ p-variant is OBSOLETE +0+15c <[^>]*> e132f004 ? teqp r2, r4 @ p-variant is OBSOLETE +0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+168 <[^>]*> e370f00a ? cmnp r0, #10 @ p-variant is OBSOLETE +0+16c <[^>]*> e172f004 ? cmnp r2, r4 @ p-variant is OBSOLETE +0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+178 <[^>]*> e350f00a ? cmpp r0, #10 @ p-variant is OBSOLETE +0+17c <[^>]*> e152f004 ? cmpp r2, r4 @ p-variant is OBSOLETE +0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+188 <[^>]*> e310f00a ? tstp r0, #10 @ p-variant is OBSOLETE +0+18c <[^>]*> e112f004 ? tstp r2, r4 @ p-variant is OBSOLETE +0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 @ p-variant is OBSOLETE 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 2bcc1d2c828e4931213ded390e23d026a69bcb64..be6d148c5fd5c62c2f6b42c1002ab9a748836659 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -3359,6 +3359,7 @@ static const struct mopcode32 mve_opcodes[] = %m print register mask for ldm/stm instruction %o print operand2 (immediate or register + shift) %p print 'p' iff bits 12-15 are 15 + %O print OBSOLETE if the 26-bit mode bit is set %t print 't' iff bit 21 set and bit 24 clear %B print arm BLX(1) destination %C print the PSR sub type. @@ -3968,32 +3969,32 @@ static const struct opcode32 arm_opcodes[] = 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, + 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, + 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, + 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, + 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, + 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, + 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, + 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, + 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, + 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, + 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, + 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, + 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, @@ -10321,19 +10322,12 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'p': if ((given & 0x0000f000) == 0x0000f000) - { - arm_feature_set arm_ext_v6 = - ARM_FEATURE_CORE_LOW (ARM_EXT_V6); - - /* The p-variants of tst/cmp/cmn/teq are the pre-V6 - mechanism for setting PSR flag bits. They are - obsolete in V6 onwards. */ - if (! ARM_CPU_HAS_FEATURE (private_data->features, \ - arm_ext_v6)) - func (stream, dis_style_mnemonic, "p"); - else - is_unpredictable = true; - } + func (stream, dis_style_mnemonic, "p"); + break; + case 'O': + if ((given & 0x0000f000) == 0x0000f000) + func (stream, dis_style_text, + "\t@ p-variant is OBSOLETE"); break; case 't':