From patchwork Wed Oct 30 14:10:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Craig Blackmore X-Patchwork-Id: 99823 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D025B385828E for ; Wed, 30 Oct 2024 14:11:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by sourceware.org (Postfix) with ESMTPS id 1FAEB3858D28 for ; Wed, 30 Oct 2024 14:10:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1FAEB3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1FAEB3858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::129 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730297459; cv=none; b=T9IVcgOhjnAaWq8jNP7iIWOIly2H1oZH+8f9SJEreY9+IV11tGTeDI4MkzJYW0fQ1E64ZSPF2OuOFxV8vc8Gkkdu4RPdjJfshqnLXyJqfrTc31AqXRUR90R+z7WAgG9Vgnz1OTBymPcYrzCAeC+plGd3y8IVSuLcSkkAHldDyjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730297459; c=relaxed/simple; bh=PYuNSJHRf6DKORmK7qZQDNslJoWFrlW/GyVvD99m6Gc=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=xfWUtDQ30CNPknMWvh0AbMBV4sZdMOW2Rt0oloIjr/MmMHS/Sa2N1wkhbR2d53tyz1W30XMcd41udMyhl3SJfIliero/gohJXLSPVkUf3we6Ih++HWx3OzTktffYmgzTnBATOZLbwCMGtip+HzRVDVf6UED6jUH6/QxbsQ1pOg8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-539f4d8ef66so8719766e87.1 for ; Wed, 30 Oct 2024 07:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1730297455; x=1730902255; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3vwKdk775FHA1AdmNnh3PJKoTcWkvorSMXaKFhmmLSs=; b=gPLcoxIvrZPD896ifOeDV63dqJOU9Z0rXze2qA7XxYv2GZLYKDEFXha5ccK51VXzq9 ymJCgHSqNWciivexDZvAo8HR70aGMv8yDJ8VqB7GWKC0vyDF8duXJCMNKDVC6dPBg9R7 ueyG2tolgsxweFmcDKhEcIHu4ZZqQw45KPi1vLrx89Inp/dX9OW1DxbgZ/NmzzA91xay PCfJTuPDDRny7rwG4NpTz94R6aDzCPu15HE/WN4wsl2j/Bitt+nnO9ynWeUwxyfkq25+ Tz0q3oPVtcemc4+9lAUyMDEC8+2WXG6bUGny2SuXMMKt0Ju75L9OnKVBNfp5f0xabThO 0hLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730297455; x=1730902255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3vwKdk775FHA1AdmNnh3PJKoTcWkvorSMXaKFhmmLSs=; b=DbU3Wl0fxCRXe3a25nqWxI8tKrFjL0xKd9DGx1iOxIey9eSn/HZKxPRoeB1O5F0/bB Wc0Lc171oNRvp5IrJaNlQd/BLGmYWorCPMdYQStk7tseO69FP7395rTS3eNoH0BJ1Qyo xwATZmBuplVDlgV0sAow7XKdhItsflthSlzzVduNBjddW0J4y6lo5JVIgdHwt1VtJAfK Ru4KYdvwteJp7kjSkUPVU+Ga1mMfaNsU23y1vDk1odLzUbjbhXQw8gF0XjIPrvrAHhqg 7ju3bdtT1gU4Z9oiT6YqSxqdA/9i3VKjScCt1JlI2GBip78LG7NDvgXwHJfd8sRj+kqv eL8A== X-Gm-Message-State: AOJu0YxfPYlhhA9HCeGRg+IoHI0Pzzzcm1Sv/M/l3Wsxoxzi/4TA+fAL iaXvq3/hkfZ68V3aKq5XHbGwVE381iEJW9/h5+Yhl1Tr1sT1rK1Ju4xQimCcIqhgR/HmjzDyIic J X-Google-Smtp-Source: AGHT+IEKx+soMqxnOLeaLJz7k9LgBlsMKm3IGJprFDrNDfiMC/7cRWRooJ441kWR0e5vZVU6npKFJA== X-Received: by 2002:a05:6512:12c5:b0:52e:767a:ada3 with SMTP id 2adb3069b0e04-53b34c5fa21mr8369471e87.47.1730297455469; Wed, 30 Oct 2024 07:10:55 -0700 (PDT) Received: from dorian.. (sals-04-b2-v4wan-167965-cust660.vm36.cable.virginm.net. [80.3.10.149]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd99fd60sm22286215e9.46.2024.10.30.07.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 07:10:55 -0700 (PDT) From: Craig Blackmore To: gcc-patches@gcc.gnu.org Cc: Craig Blackmore Subject: [PATCH v2] RISC-V: Fix gcc.target/riscv/rvv/base/cpymem-1.c f3 Date: Wed, 30 Oct 2024 14:10:42 +0000 Message-ID: <20241030141042.929294-1-craig.blackmore@embecosm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241030134948.927478-1-craig.blackmore@embecosm.com> References: <20241030134948.927478-1-craig.blackmore@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org The function body checks for f3 only ran with -mcmodel explicitly set which meant I missed a regression in my local testing of: commit b039d06c9a810a3fab4c5eb9d50b0c7aff94b2d8 Author: Craig Blackmore Date: Fri Oct 18 09:17:21 2024 -0600 [PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generation The failure showed up in the rivos CI and it is due to f3 now using LMUL m1 instead of m8. I have reworked the test to make it more robust and maintainable. This allowed most of the special casing of command line arguments to be removed. It also fixes an issue where some targets would enable multiple versions of the function body check e.g. `-march=rv32gcv -mcmodel=medany`. Changes since v1: Added missing ChangeLog. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/cpymem-1.c: Fix and rework f3. --- .../gcc.target/riscv/rvv/base/cpymem-1.c | 107 ++++++++---------- 1 file changed, 48 insertions(+), 59 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 6edb4c9253a..81d14d83633 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -9,6 +9,8 @@ extern void *memcpy(void *__restrict dest, const void *__restrict src, __SIZE_TYPE__ n); #endif +#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) + /* memcpy should be implemented using the cpymem pattern. ** f1: XX \.L\d+: # local label is ignored @@ -50,70 +52,57 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) Use extern here so that we get a known alignment, lest DATA_ALIGNMENT force us to make the scan pattern accomodate code for different alignments depending on word size. -** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m2" "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-vector-bits=zvl" } } } -** lui\s+[ta][0-7],%hi\(a_a\) -** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) -** lui\s+[ta][0-7],%hi\(a_b\) -** addi\s+a4,[ta][0-7],%lo\(a_b\) -** vsetivli\s+zero,16,e32,m8,ta,ma -** vle32.v\s+v\d+,0\([ta][0-7]\) -** vse32\.v\s+v\d+,0\([ta][0-7]\) -** ret -*/ - -/* -** f3: { target { { any-opts "-mcmodel=medlow -mrvv-vector-bits=zvl" "-mcmodel=medlow -march=rv64gcv_zvl512b -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } -** lui\s+[ta][0-7],%hi\(a_a\) -** lui\s+[ta][0-7],%hi\(a_b\) -** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) -** addi\s+a4,[ta][0-7],%lo\(a_b\) -** vl(1|4|2)re32\.v\s+v\d+,0\([ta][0-7]\) -** vs(1|4|2)r\.v\s+v\d+,0\([ta][0-7]\) -** ret -*/ - -/* -** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "-mrvv-vector-bits=zvl" } } } -** lui\s+[ta][0-7],%hi\(a_a\) -** lui\s+[ta][0-7],%hi\(a_b\) -** addi\s+a4,[ta][0-7],%lo\(a_b\) -** vsetivli\s+zero,16,e32,(m1|m4|mf2),ta,ma -** vle32.v\s+v\d+,0\([ta][0-7]\) -** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) -** vse32\.v\s+v\d+,0\([ta][0-7]\) -** ret -*/ - -/* -** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=m4" "-mrvv-vector-bits=zvl" } } } -** lla\s+[ta][0-7],a_a -** lla\s+[ta][0-7],a_b -** vsetivli\s+zero,16,e32,m8,ta,ma -** vle32.v\s+v\d+,0\([ta][0-7]\) -** vse32\.v\s+v\d+,0\([ta][0-7]\) -** ret -*/ - -/* -** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv" "-march=rv64gc_zve64d" "-march=rv64gc_zve32f" } } } -** lla\s+[ta][0-7],a_b -** vsetivli\s+zero,16,e32,m(f2|1|4),ta,ma -** vle32.v\s+v\d+,0\([ta][0-7]\) -** lla\s+[ta][0-7],a_a -** vse32\.v\s+v\d+,0\([ta][0-7]\) -** ret +** f3: { target { no-opts "-mrvv-vector-bits=zvl" } } +** ( +** lui\s+[ta][0-7],%hi\(a_a\) +** lui\s+[ta][0-7],%hi\(a_b\) +** addi\s+[ta][0-7],[ta][0-7],%lo\(a_b\) +** vsetivli\s+zero,4,e32,m1,ta,ma +** | +** lui\s+[ta][0-7],%hi\(a_a\) +** lui\s+[ta][0-7],%hi\(a_b\) +** li\s+[ta][0-7],\d+ +** addi\s+[ta][0-7],[ta][0-7],%lo\(a_b\) +** vsetvli\s+zero,[ta][0-7],e32,m1,ta,ma +** | +** lla\s+[ta][0-7],a_b +** vsetivli\s+zero,4,e32,m1,ta,ma +** | +** li\s+[ta][0-7],\d+ +** lla\s+[ta][0-7],a_b +** vsetvli\s+zero,[ta][0-7],e32,m1,ta,ma +** | +** lla\s+[ta][0-7],a_b +** li\s+[ta][0-7],32 +** vsetvli\s+zero,[ta][0-7],e32,m1,ta,ma +** ) +** vle32.v\s+v\d+,0\([ta][0-7]\) +** ( +** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) +** | +** lla\s+[ta][0-7],a_a +** ) +** vse32.v\s+v\d+,0\([ta][0-7]\) +** ret */ /* -** f3: { target { { any-opts "-mcmodel=medany -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } -** lla\s+[ta][0-7],a_a -** lla\s+[ta][0-7],a_b -** vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\) -** vs(1|2|4)r\.v\s+v\d+,0\([ta][0-7]\) -** ret +** f3: { target { any-opts "-mrvv-vector-bits=zvl" } } +** ( +** lui\s+[ta][0-7],%hi\(a_a\) +** lui\s+[ta][0-7],%hi\(a_b\) +** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) +** addi\s+[ta][0-7],[ta][0-7],%lo\(a_b\) +** | +** lla\s+[ta][0-7],a_a +** lla\s+[ta][0-7],a_b +** ) +** vl1re32.v\s+v\d+,0\([ta][0-7]\) +** vs1r.v\s+v\d+,0\([ta][0-7]\) +** ret */ -extern struct { __INT32_TYPE__ a[16]; } a_a, a_b; +extern struct { __INT32_TYPE__ a[MIN_VECTOR_BYTES / 4]; } a_a, a_b; void f3 () {