From patchwork Wed Oct 30 11:55:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 99814 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ED3D43858D28 for ; Wed, 30 Oct 2024 11:58:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by sourceware.org (Postfix) with ESMTPS id 3E25B3858C98 for ; Wed, 30 Oct 2024 11:57:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3E25B3858C98 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3E25B3858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730289456; cv=none; b=S3Pu0AB5Y9bkWy5L2XyLZrJqAARsRUUEei8nZII43sK1+NmUjJUsgfjsRuk3bz9s4PTjd2Uf/ULIfebwNDEuR+1MEZiXR7O2o8TwY849kcRwptbpBUkQIJSN3BzuPEuF3Qkeq57byOxGR/waTSN9SxHIRcVLaXeSF8bNody68V0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730289456; c=relaxed/simple; bh=3W9OlTgltK2u0ip9HBX0Q+7kkcvgECFMfUTRQ5aRBNw=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=bWDgypUTGOWOxwFdBP3HFNuBcY/ZEPfHqlBZQOl+CF+aNqJIWxM0BhRyqSW6PB8l3uV2qY5wP0RJqMge5PpmFhi2XOBHdmruMlARdZItYW4EtMfAXCtwgxEvFhRIcgdMp081ZSNhe6b/lr28BjySZuNpdI/3dJNiNAANlh3uK9s= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730289453; x=1761825453; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=3W9OlTgltK2u0ip9HBX0Q+7kkcvgECFMfUTRQ5aRBNw=; b=cNHI/lJVlcqCUawlzkggWTCFpoqQADnGthb9MHz53hh/vEqk1wT/YJnR q7vOyVTi3w/vQghIs+rdeyitzwLkjF7JyQrGvHwjlJ6JAvFtURz6SO+vc DcN1lYRF+bPiCzq/v9BgzC6o6drB0Af+9uxiZ0FCBZcfryb3LvyXygrTy +IGLveM6W/gPuQvwN9wDjCJJPvgPp9YHLPkHcE/B1FLBmz3siGq6HBIeY cxAvICnj6PWTHyVpmPcaiEZ9OjKUQQSQTqYte12a39/WaCtUgH/OOA02Z CQPp8ZHe7EjX9QBHG9vEnvh1E/wtGpz2xN3InRPCpuX+eHx+pZpr6bvht w==; X-CSE-ConnectionGUID: rHNZy/9GRjGudXtURmOsNw== X-CSE-MsgGUID: I4/rbsfcRfa/iuq5UUZwbA== X-IronPort-AV: E=McAfee;i="6700,10204,11240"; a="29883106" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="29883106" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 04:57:32 -0700 X-CSE-ConnectionGUID: flSpVJC3S9KX2CGBQNTZ2g== X-CSE-MsgGUID: HKwKizFpRa+vcJ1mh25b/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="87075564" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa003.jf.intel.com with ESMTP; 30 Oct 2024 04:57:29 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v2] Doc: Add doc for standard name mask_len_strided_load{store}m Date: Wed, 30 Oct 2024 19:55:37 +0800 Message-ID: <20241030115537.382336-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li This patch would like to add doc for the below 2 standard names. 1. strided load: v = mask_len_strided_load (ptr, stried, mask, len, bias) 2. strided store: mask_len_stried_store (ptr, stride, v, mask, len, bias) gcc/ChangeLog: * doc/md.texi: Add doc for mask_len_stried_load{store}. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong Signed-off-by: Pan Li --- gcc/doc/md.texi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 6d9c8643739..25ded86f0d1 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5135,6 +5135,20 @@ Bit @var{i} of the mask is set if element @var{i} of the result should be loaded from memory and clear if element @var{i} of the result should be undefined. Mask elements @var{i} with @var{i} > (operand 6 + operand 7) are ignored. +@cindex @code{mask_len_strided_load@var{m}} instruction pattern +@item @samp{mask_len_strided_load@var{m}} +Load several separate memory locations into a destination vector of mode @var{m}. +Operand 0 is a destination vector of mode @var{m}. +Operand 1 is a scalar base address and operand 2 is a scalar stride of Pmode. +operand 3 is mask operand, operand 4 is length operand and operand 5 is bias operand. +The instruction can be seen as a special case of @code{mask_len_gather_load@var{m}@var{n}} +with an offset vector that is a @code{vec_series} with zero as base and operand 2 as step. +For each element the load address is operand 1 + @var{i} * operand 2. +Similar to mask_len_load, the instruction loads at most (operand 4 + operand 5) elements from memory. +Element @var{i} of the mask (operand 3) is set if element @var{i} of the result should +be loaded from memory and clear if element @var{i} of the result should be zero. +Mask elements @var{i} with @var{i} > (operand 4 + operand 5) are ignored. + @cindex @code{scatter_store@var{m}@var{n}} instruction pattern @item @samp{scatter_store@var{m}@var{n}} Store a vector of mode @var{m} into several distinct memory locations. @@ -5172,6 +5186,19 @@ at most (operand 6 + operand 7) elements of (operand 4) to memory. Bit @var{i} of the mask is set if element @var{i} of (operand 4) should be stored. Mask elements @var{i} with @var{i} > (operand 6 + operand 7) are ignored. +@cindex @code{mask_len_strided_store@var{m}} instruction pattern +@item @samp{mask_len_strided_store@var{m}} +Store a vector of mode m into several distinct memory locations. +Operand 0 is a scalar base address and operand 1 is scalar stride of Pmode. +Operand 2 is the vector of values that should be stored, which is of mode @var{m}. +operand 3 is mask operand, operand 4 is length operand and operand 5 is bias operand. +The instruction can be seen as a special case of @code{mask_len_scatter_store@var{m}@var{n}} +with an offset vector that is a @code{vec_series} with zero as base and operand 1 as step. +For each element the store address is operand 0 + @var{i} * operand 1. +Similar to mask_len_store, the instruction stores at most (operand 4 + operand 5) elements of +mask (operand 3) to memory. Element @var{i} of the mask is set if element @var{i} of (operand 3) +should be stored. Mask elements @var{i} with @var{i} > (operand 4 + operand 5) are ignored. + @cindex @code{vec_set@var{m}} instruction pattern @item @samp{vec_set@var{m}} Set given field in the vector value. Operand 0 is the vector to modify,