From patchwork Fri Oct 25 01:22:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "xuli1@eswincomputing.com" X-Patchwork-Id: 99515 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3A4523858D34 for ; Fri, 25 Oct 2024 01:23:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from sgoci-sdnproxy-4.icoremail.net (sgoci-sdnproxy-4.icoremail.net [129.150.39.64]) by sourceware.org (Postfix) with ESMTP id 1E67B3858D33 for ; Fri, 25 Oct 2024 01:22:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1E67B3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1E67B3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=129.150.39.64 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729819342; cv=none; b=SV9jEGDTbexOFverzWk9OHc/SGgGhZXJ9JgbRtHHiZhlFsjzUqaUzay0P6VZVWBNMvvASZ4gvyOuG/rcmnGjIBuiEeg+Gka6gEP1lN3bwHhlF8OBNJKNfYyfX5GOGOdyIbel9GzDhT20QKfbdielAQSPf7b4d2uiVl9vIaiVtRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729819342; c=relaxed/simple; bh=tWuyvRn1zezCDZ1b8GzxkgUVS525eOC8gcJuIKOC/jo=; h=From:To:Subject:Date:Message-Id; b=e9QCasD7a6Ng+fIPIyGkg8WPKu6NXNbx60GrCqRcc55Q0MBizruCC23Gf70jJ3QqWwcUkVsSqCk+/iGEKBuGNDXAanVs6I0lGFVglI5qRmz3Qb60yNW7/aMzZXAUv0yBBWrsq5AaF26QWxFpXdAJGI5qTILW/mBc+Ctm/Bs6DlY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgCXWuTF8hpnUE4QAA--.10206S4; Fri, 25 Oct 2024 09:22:14 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, pan2.li@intel.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, pinskia@gmail.com, xuli Subject: [PATCH v4 1/2] Match: Simplify (x != 0 ? x + ~0 : 0) to (x - x != 0). Date: Fri, 25 Oct 2024 01:22:11 +0000 Message-Id: <20241025012212.33101-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TQJkCgCXWuTF8hpnUE4QAA--.10206S4 X-Coremail-Antispam: 1UD129KBjvJXoWxZryfuw1DCFW7Kw47trWkJFb_yoWrWFyUp3 48Xa9YgrW8JF1xGFs3GF15AF13K3Z3GFyUWrZrWwnFkFn7Arn2gFy0k3yfAr4fGa43Wr43 WanrWF4F93WxX3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9I14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1l748vw2CE2IxIcs4lc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMxC20s026x CaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_ JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r 1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_ Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVWUJVW8Jb IYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, PLING_QUERY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: xuli When the imm operand op1=1 in the unsigned scalar sat_sub form2 below, we can simplify (x != 0 ? x + ~0 : 0) to (x - x != 0), thereby eliminating a branch instruction.This simplification also applies to signed integer. Form2: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \ { \ return x >= (T)IMM ? x - (T)IMM : 0; \ } Take below form 2 as example: DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1) Before this patch: __attribute__((noinline)) uint8_t sat_u_sub_imm1_uint8_t_fmt_2 (uint8_t x) { uint8_t _1; uint8_t _3; [local count: 1073741824]: if (x_2(D) != 0) goto ; [50.00%] else goto ; [50.00%] [local count: 536870912]: _3 = x_2(D) + 255; [local count: 1073741824]: # _1 = PHI return _1; } Assembly code: sat_u_sub_imm1_uint8_t_fmt_2: beq a0,zero,.L2 addiw a0,a0,-1 andi a0,a0,0xff .L2: ret After this patch: __attribute__((noinline)) uint8_t sat_u_sub_imm1_uint8_t_fmt_2 (uint8_t x) { _Bool _1; unsigned char _2; uint8_t _4; [local count: 1073741824]: _1 = x_3(D) != 0; _2 = (unsigned char) _1; _4 = x_3(D) - _2; return _4; } Assembly code: sat_u_sub_imm1_uint8_t_fmt_2: snez a5,a0 subw a0,a0,a5 andi a0,a0,0xff ret The below test suites are passed for this patch: 1. The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. Signed-off-by: Li Xu gcc/ChangeLog: * match.pd: Simplify (x != 0 ? x + ~0 : 0) to (x - x != 0). gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/phi-opt-44.c: New test. --- gcc/match.pd | 10 +++++++++ gcc/testsuite/gcc.dg/tree-ssa/phi-opt-44.c | 26 ++++++++++++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/phi-opt-45.c | 26 ++++++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/phi-opt-44.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/phi-opt-45.c diff --git a/gcc/match.pd b/gcc/match.pd index 0455dfa6993..f48fd7d52ba 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3383,6 +3383,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) } (if (wi::eq_p (sum, wi::uhwi (0, precision))))))) +/* The boundary condition for case 10: IMM = 1: + SAT_U_SUB = X >= IMM ? (X - IMM) : 0. + simplify (X != 0 ? X + ~0 : 0) to (X - X != 0). */ +(simplify + (cond (ne@1 @0 integer_zerop) + (nop_convert? (plus (nop_convert? @0) integer_all_onesp)) + integer_zerop) + (if (INTEGRAL_TYPE_P (type)) + (minus @0 (convert @1)))) + /* Signed saturation sub, case 1: T minus = (T)((UT)X - (UT)Y); SAT_S_SUB = (X ^ Y) & (X ^ minus) < 0 ? (-(T)(X < 0) ^ MAX) : minus; diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-44.c b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-44.c new file mode 100644 index 00000000000..962bf0954f6 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-44.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-phiopt1" } */ + +#include + +uint8_t f1 (uint8_t x) +{ + return x >= (uint8_t)1 ? x - (uint8_t)1 : 0; +} + +uint16_t f2 (uint16_t x) +{ + return x >= (uint16_t)1 ? x - (uint16_t)1 : 0; +} + +uint32_t f3 (uint32_t x) +{ + return x >= (uint32_t)1 ? x - (uint32_t)1 : 0; +} + +uint64_t f4 (uint64_t x) +{ + return x >= (uint64_t)1 ? x - (uint64_t)1 : 0; +} + +/* { dg-final { scan-tree-dump-not "goto" "phiopt1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-45.c b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-45.c new file mode 100644 index 00000000000..62a2ab63184 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-45.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-phiopt1" } */ + +#include + +int8_t f1 (int8_t x) +{ + return x != 0 ? x - (int8_t)1 : 0; +} + +int16_t f2 (int16_t x) +{ + return x != 0 ? x - (int16_t)1 : 0; +} + +int32_t f3 (int32_t x) +{ + return x != 0 ? x - (int32_t)1 : 0; +} + +int64_t f4 (int64_t x) +{ + return x != 0 ? x - (int64_t)1 : 0; +} + +/* { dg-final { scan-tree-dump-not "goto" "phiopt1" } } */ From patchwork Fri Oct 25 01:22:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "xuli1@eswincomputing.com" X-Patchwork-Id: 99514 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1F69B3858C2B for ; Fri, 25 Oct 2024 01:22:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [20.231.56.155]) by sourceware.org (Postfix) with ESMTP id 96B1F3858D21 for ; Fri, 25 Oct 2024 01:22:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 96B1F3858D21 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 96B1F3858D21 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=20.231.56.155 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729819342; cv=none; b=ndHCfDMDGNvWKL63Fq2H3yKGFjauUjSIrgkAfsPOvoHEmxy+gJoesR6LX145AtHsePeJX7oZi/+PTvNN7to/J2WhYZiqjuPbGrvwxDmS5D+es5if8UfihJ46orTMNM7l76acCYVm8hr1SFLmBbqBG+aXErGOCkjryWhPOXmbKVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729819342; c=relaxed/simple; bh=Yrzm9EY71kmD0EpPUvtVFzkOX8b/+Dhb7avob615Ee4=; h=From:To:Subject:Date:Message-Id; b=VsHmJc0uRoYZvSJ6eo+RHGqVCtgem/BtKp1FeblleVDaJbXM1mRY17xnZA5+Z/OiqC1p440bOjcaorMHnVi4hfsRSo8O5fqI3Jen7wEHipUPWE8W+81QE4i2+4nE74SKQ4VRkOyqYrUBUbKqMRbujnyA8C3H6a0SfX6j+0ZmD7I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgCXWuTF8hpnUE4QAA--.10206S5; Fri, 25 Oct 2024 09:22:15 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, richard.guenther@gmail.com, Tamar.Christina@arm.com, juzhe.zhong@rivai.ai, pan2.li@intel.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, pinskia@gmail.com, xuli Subject: [PATCH v4 2/2] RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1. Date: Fri, 25 Oct 2024 01:22:12 +0000 Message-Id: <20241025012212.33101-2-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025012212.33101-1-xuli1@eswincomputing.com> References: <20241025012212.33101-1-xuli1@eswincomputing.com> X-CM-TRANSID: TQJkCgCXWuTF8hpnUE4QAA--.10206S5 X-Coremail-Antispam: 1UD129KBjvJXoW3XF1fJw1DCF4DZr4rtw1UWrg_yoW3Jr1Dpa n5Ga12gr4fJF97GF1SyFyYvr4aywsagry5u39rAw1xGw4ftrW2q3Zrta17Gr48GF4Uurna kay7uw1fCr42qwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPq14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr1j6rxdM2 8EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkIecxEwVCm-wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s02 6c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw 0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvE c7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14 v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x 0JUqAp5UUUUU= X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: xuli form2: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \ { \ return x >= (T)IMM ? x - (T)IMM : 0; \ } Passed the rv64gcv regression test. Signed-off-by: Li Xu gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_sub_imm-run-5.c: add run case for imm=1. * gcc.target/riscv/sat_u_sub_imm-run-6.c: Ditto. * gcc.target/riscv/sat_u_sub_imm-run-7.c: Ditto. * gcc.target/riscv/sat_u_sub_imm-run-8.c: Ditto. * gcc.target/riscv/sat_u_sub_imm-5_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-6_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-7_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-8_1.c: New test. --- .../gcc.target/riscv/sat_u_sub_imm-5_3.c | 18 ++++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-6_3.c | 19 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-7_3.c | 17 +++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-8_1.c | 17 +++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-run-5.c | 1 + .../gcc.target/riscv/sat_u_sub_imm-run-6.c | 1 + .../gcc.target/riscv/sat_u_sub_imm-run-7.c | 1 + .../gcc.target/riscv/sat_u_sub_imm-run-8.c | 1 + 8 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c new file mode 100644 index 00000000000..42edfc59f8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm1_uint8_t_fmt_2: +** snez\s+[atx][0-9]+,\s*a0 +** subw\s+a0,\s*a0,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1) + +/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c new file mode 100644 index 00000000000..5250b90418a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm1_uint16_t_fmt_2: +** snez\s+[atx][0-9]+,\s*a0 +** subw\s+a0,\s*a0,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1) + +/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c new file mode 100644 index 00000000000..99df0e4b683 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm1_uint32_t_fmt_2: +** snez\s+[atx][0-9]+,\s*a0 +** subw\s+a0,\s*a0,\s*[atx][0-9]+ +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1) + +/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c new file mode 100644 index 00000000000..cbbc08339f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm1_uint64_t_fmt_2: +** snez\s+[atx][0-9]+,\s*a0 +** sub\s+a0,\s*a0,\s*[atx][0-9]+ +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1) + +/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c index 627e81bca4b..fc3809590de 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c @@ -4,6 +4,7 @@ #include "sat_arith.h" DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 0) +DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1) DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 2) DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 6) DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 129) diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c index 8deed2bf28f..0f4f9e40f1f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c @@ -4,6 +4,7 @@ #include "sat_arith.h" DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 0) +DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1) DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 2) DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 6) DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 32767) diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c index 7a3d7b0176f..ea15d85782d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c @@ -4,6 +4,7 @@ #include "sat_arith.h" DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 0) +DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1) DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2) DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 6) DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483647) diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c index 3ed1c90f78f..612da9212cd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c @@ -4,6 +4,7 @@ #include "sat_arith.h" DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 0) +DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1) DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 2) DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 6) DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 18446744073709551614u)