From patchwork Tue Oct 15 01:19:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayshao-oc X-Patchwork-Id: 98900 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B53433856DD1 for ; Tue, 15 Oct 2024 01:25:39 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from zxbjcas.zhaoxin.com (zxbjcas.zhaoxin.com [124.127.214.139]) by sourceware.org (Postfix) with ESMTPS id 8CB503857000 for ; Tue, 15 Oct 2024 01:25:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8CB503857000 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=zhaoxin.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8CB503857000 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=124.127.214.139 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728955511; cv=none; b=xmFfXoV8Q3YsPoo/H76XkL4VHReVvk/xqXkVfKg5vuUtjaVek3mLq6A42uxxWGLtU8UutzYi7Zfd/Ges/HAHpz8W/7/T7zJHtRQPI+xVnrLq//jFYYnl9JDh4VgT+mCt07Y4+FVuE2BzEFAURpATwJTvufJYkfukw8unQ0b1W3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728955511; c=relaxed/simple; bh=yfDocI9p0OphHwo75QIosP84pZKd49C/rPQuYCArQu0=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=YhLS9xuQHUOGLk35NGyt71oZ0PHAZTW/jOG7ugWxHW6hCIcrnqIdDgoL3s82VFt7yEeWNW+W2RTYDoTcgLLDfLOp9vjK375yeNUb2uEW4eYKXYJRFqlTSxqfUZgA1xxCO7cZ9KoFl2WOtR8LzSVcjdLG3qeXG0hPxgYVk4j+cIc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from zxbjmbx1.zhaoxin.com (zxbjmbx1.zhaoxin.com [10.29.252.163]) by zxbjcas.zhaoxin.com with ESMTP id 49F1JSpo040744; Tue, 15 Oct 2024 09:19:28 +0800 (GMT-8) (envelope-from Mayshao-oc@zhaoxin.com) Received: from ZXSHMBX1.zhaoxin.com (10.28.252.163) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Oct 2024 09:19:27 +0800 Received: from ZXSHMBX1.zhaoxin.com ([fe80::3066:e339:e3d6:5264]) by ZXSHMBX1.zhaoxin.com ([fe80::3066:e339:e3d6:5264%7]) with mapi id 15.01.2507.039; Tue, 15 Oct 2024 09:19:27 +0800 Received: from [10.30.150.6] (59.172.24.74) by ZXBJMBX02.zhaoxin.com (10.29.252.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Oct 2024 09:19:07 +0800 Message-ID: Date: Tue, 15 Oct 2024 09:19:06 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2] x86: Support ZHAOXIN GMI instructions To: Jan Beulich CC: "H.J. Lu" , "timhu@zhaoxin.com" , "louisqi@zhaoxin.com" , "cobechen@zhaoxin.com" , "binutils@sourceware.org" , "Jiang, Haochen" References: <5178f91f-d43d-4f1f-88d0-b132fdec5d0b@suse.com> <4a725312-73fc-4456-b168-50daa03c2170@suse.com> Content-Language: en-US From: mayshao-oc In-Reply-To: <4a725312-73fc-4456-b168-50daa03c2170@suse.com> X-Originating-IP: [59.172.24.74] X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Moderation-Data: 10/15/2024 9:19:25 AM X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: zxbjcas.zhaoxin.com 49F1JSpo040744 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Hi all: Thanks for the very insightful comments of Jan hand haochen, I refine the patch. Test ok, ok for trunk? BR Mayshao From 5f51e0f69c6ee4b9f5c5381a03390ce6de5f37f4 Mon Sep 17 00:00:00 2001 From: MayShao-oc Date: Tue, 15 Oct 2024 08:53:54 +0800 Subject: [PATCH v2] x86: Support ZHAOXIN GMI Hi all: I refine the ZHAOXIN GMI patch, according to the very insightful comments of Jan and Haochen.Thanks to Jan and Haochen. Test ok, ok for trunk? BR Mayshao gas/ChangeLog: * NEWS: Support x86 ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MONTMUL_Fixup): New fixup function to disassemble montmul. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto. --- gas/NEWS | 2 ++ gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 6 ++-- gas/testsuite/gas/i386/gmi.d | 12 ++++++++ gas/testsuite/gas/i386/gmi.s | 8 ++++++ gas/testsuite/gas/i386/i386.exp | 1 + opcodes/i386-dis.c | 49 ++++++++++++++++++++++++++++++++- opcodes/i386-gen.c | 1 + opcodes/i386-opc.h | 3 ++ opcodes/i386-opc.tbl | 5 ++++ 10 files changed, 85 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/i386/gmi.d create mode 100644 gas/testsuite/gas/i386/gmi.s diff --git a/gas/NEWS b/gas/NEWS index d64330143b0..053b2bcac87 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -5,6 +5,8 @@ * Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi and CORE-V (xcvbitmanip, xcvsimd) extensions with version 1.0. +* Add support for the x86 Zhaoxin GMI instructions. + Changes in 2.43: * Add support for LoongArch .option for fine-grained control of assembly diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index cdefde03717..735154ee721 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1219,6 +1219,7 @@ static const arch_entry cpu_arch[] = SUBARCH (user_msr, USER_MSR, USER_MSR, false), SUBARCH (apx_f, APX_F, APX_F, false), VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set), + SUBARCH (gmi, GMI, GMI, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 9667061752d..952ddbc7377 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -274,7 +274,8 @@ accept various extension mnemonics. For example, @code{snp}, @code{invlpgb}, @code{tlbsync}, -@code{svme} and +@code{svme}, +@code{gmi} and @code{padlock}. Note that these extension mnemonics can be prefixed with @code{no} to revoke the respective (and any dependent) functionality. Note further that the @@ -1705,7 +1706,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} -@item @samp{.tlbsync} @tab @samp{.apx_f} +@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi} + @end multitable Apart from the warning, there are only two other effects on diff --git a/gas/testsuite/gas/i386/gmi.d b/gas/testsuite/gas/i386/gmi.d new file mode 100644 index 00000000000..063da8e120a --- /dev/null +++ b/gas/testsuite/gas/i386/gmi.d @@ -0,0 +1,12 @@ +#objdump: -dw +#name: zhaoxin gmi + +.*: +file format .* + +Disassembly of section .text: + +0+000 : + 0:[ ]*f2 0f a6 c0 [ ]*sm2 + 4:[ ]*f3 0f a6 e8 [ ]*sm3 + 8:[ ]*f3 0f a7 f0 [ ]*sm4 +#pass diff --git a/gas/testsuite/gas/i386/gmi.s b/gas/testsuite/gas/i386/gmi.s new file mode 100644 index 00000000000..c412de55d31 --- /dev/null +++ b/gas/testsuite/gas/i386/gmi.s @@ -0,0 +1,8 @@ +# ZHAOXIN GMI instructions + + .text +foo: + sm2 + sm3 + sm4 + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 699e2004bef..4aaa2239069 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -114,6 +114,7 @@ if [gas_32_check] then { run_dump_test "quoted2" run_dump_test "unary" run_dump_test "padlock" + run_dump_test "gmi" run_dump_test "crx" run_list_test "cr-err" "" run_dump_test "cdr" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 3a4af4d61a3..e012937e303 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -90,6 +90,7 @@ static bool PCLMUL_Fixup (instr_info *, int, int); static bool VPCMP_Fixup (instr_info *, int, int); static bool VPCOM_Fixup (instr_info *, int, int); static bool NOP_Fixup (instr_info *, int, int); +static bool MONTMUL_Fixup (instr_info *, int, int); static bool OP_3DNowSuffix (instr_info *, int, int); static bool CMP_Fixup (instr_info *, int, int); static bool REP_Fixup (instr_info *, int, int); @@ -1050,6 +1051,9 @@ enum PREFIX_0F7D, PREFIX_0F7E, PREFIX_0F7F, + PREFIX_0FA6_REG_0_MOD_3, + PREFIX_0FA6_REG_5_MOD_3, + PREFIX_0FA7_REG_6_MOD_3, PREFIX_0FAE_REG_0_MOD_3, PREFIX_0FAE_REG_1_MOD_3, PREFIX_0FAE_REG_2_MOD_3, @@ -2850,9 +2854,12 @@ static const struct dis386 reg_table[][8] = { }, /* REG_0FA6 */ { - { "montmul", { { OP_0f07, 0 } }, 0 }, + { PREFIX_TABLE (PREFIX_0FA6_REG_0_MOD_3) }, { "xsha1", { { OP_0f07, 0 } }, 0 }, { "xsha256", { { OP_0f07, 0 } }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0FA6_REG_5_MOD_3) }, }, /* REG_0FA7 */ { @@ -2862,6 +2869,7 @@ static const struct dis386 reg_table[][8] = { { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, + { PREFIX_TABLE (PREFIX_0FA7_REG_6_MOD_3) }, }, /* REG_0FAE */ { @@ -3438,6 +3446,30 @@ static const struct dis386 prefix_table[][4] = { { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, }, + /* PREFIX_0FA6_REG_0_MOD_3 */ + { + { Bad_Opcode }, + { "montmul", { { MONTMUL_Fixup, 0 } }, 0}, + { Bad_Opcode }, + { "sm2", { Skip_MODRM }, 0 }, + }, + + /* PREFIX_0FA6_REG_5_MOD_3 */ + { + { Bad_Opcode }, + { "sm3", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + + /* PREFIX_0FA7_REG_6_MOD_3 */ + { + { Bad_Opcode }, + { "sm4", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* PREFIX_0FAE_REG_0_MOD_3 */ { { Bad_Opcode }, @@ -13086,6 +13118,21 @@ OP_0f07 (instr_info *ins, int bytemode, int sizeflag) return OP_E (ins, bytemode, sizeflag); } +/* montmul instruction need display repz and skip modrm */ + +static bool +MONTMUL_Fixup (instr_info *ins, int bytemode, int sizeflag) +{ + (void) bytemode; + (void) sizeflag; + /* The 0xf3 prefix should be displayed as "repz" for montmul. */ + if (ins->prefixes & PREFIX_REPZ) + ins->all_prefixes[ins->last_repz_prefix] = 0xf3; + ins->codep++; + ins->has_skipped_modrm = true; + return true; +} + /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in 32bit mode and "xchg %rax,%rax" in 64bit mode. */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 565aae722f8..0f7ab4c6a56 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -334,6 +334,7 @@ static bitfield cpu_flags[] = BITFIELD (3dnow), BITFIELD (3dnowA), BITFIELD (PadLock), + BITFIELD (GMI), BITFIELD (SVME), BITFIELD (VMX), BITFIELD (SMX), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index c0d5e44d461..d404fbc6b05 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -66,6 +66,8 @@ enum i386_cpu CpuSSE3, /* VIA PadLock required */ CpuPadLock, + /* ZHAOXIN GMI required */ + CpuGMI, /* AMD Secure Virtual Machine Ext-s required */ CpuSVME, /* VMX Instructions required */ @@ -400,6 +402,7 @@ typedef union i386_cpu_flags unsigned int cpusse2:1; unsigned int cpusse3:1; unsigned int cpupadlock:1; + unsigned int cpugmi:1; unsigned int cpusvme:1; unsigned int cpuvmx:1; unsigned int cpusmx:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 9a14a4d1819..7ded4e64133 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2131,6 +2131,11 @@ xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {} // Alias for xstore-rng. xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} +// ZHAOXIN GMI instructions +sm2, 0xf20fa6c0, GMI, NoSuf, {} +sm3, 0xf30fa6e8, GMI, NoSuf, {} +sm4, 0xf30fa7f0, GMI, NoSuf, {} + // Multy-precision Add Carry, rdseed instructions. adx, 0x66, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -- 2.27.0