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Date: Tue, 8 Oct 2024 12:44:59 +0800 Message-Id: <20241008044459.486559-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: qwCowADnz37ZuARnCM7vBA--.51503S2 X-Coremail-Antispam: 1UD129KBjvJXoW3tr1fZFy3Zw17Kr1kKFykKrg_yoWDtr1UpF WkCF929r95CFnrJr97Kr1qyan7Aw1Sgr90vw4fCw1Skr4xGrWYq34vyw4avFs5XF4UGwna 9w4fAr45Z3y3GaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr 1j6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkF7I0En4kS14v2 6r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrV AFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCI c40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267 AKxVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_ Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbSfO7 UUUUU== X-Originating-IP: [39.108.67.220] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBwsEAGcEeJze3gAAsP X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch supports Ssqosid extension[1]. The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. [1] https://github.com/riscv/riscv-ssqosid bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: New extension. * config/tc-riscv.c (enum riscv_csr_class): New CSR class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_SRMCFG): New CSR. (DECLARE_CSR): Ditto. --- bfd/elfxx-riscv.c | 2 ++ gas/NEWS | 4 ++-- gas/config/tc-riscv.c | 4 ++++ gas/testsuite/gas/riscv/csr-version-1p10.d | 2 ++ gas/testsuite/gas/riscv/csr-version-1p10.l | 4 ++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 2 ++ gas/testsuite/gas/riscv/csr-version-1p11.l | 4 ++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 2 ++ gas/testsuite/gas/riscv/csr-version-1p12.l | 4 ++++ gas/testsuite/gas/riscv/csr.s | 3 +++ gas/testsuite/gas/riscv/march-help.l | 1 + include/opcode/riscv-opc.h | 4 ++++ 12 files changed, 34 insertions(+), 2 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 26ec664d88a..0ce9549a052 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1261,6 +1261,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"sscsrind", "+zicsr", check_implicit_always}, {"sscofpmf", "+zicsr", check_implicit_always}, {"sscounterenw", "+zicsr", check_implicit_always}, + {"ssqosid", "+zicsr", check_implicit_always}, {"ssstateen", "+zicsr", check_implicit_always}, {"sstc", "+zicsr", check_implicit_always}, {"sstvala", "+zicsr", check_implicit_always}, @@ -1446,6 +1447,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssqosid", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/NEWS b/gas/NEWS index d64330143b0..ec43e9aa922 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -2,8 +2,8 @@ * On x86 emulation support (for secondary targets) was dropped. -* Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi and CORE-V - (xcvbitmanip, xcvsimd) extensions with version 1.0. +* Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi, Ssqosid + and CORE-V (xcvbitmanip, xcvsimd) extensions with version 1.0. Changes in 2.43: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index ef455e449b9..3eb9da20384 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -92,6 +92,7 @@ enum riscv_csr_class CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, /* Ssaia/Smcsrind with H */ CSR_CLASS_SSCSRIND, /* Sscsrind */ CSR_CLASS_SSCSRIND_AND_H, /* Sscsrind with H */ + CSR_CLASS_SSQOSID, /* Ssqosid */ CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */ CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */ @@ -1121,6 +1122,9 @@ riscv_csr_address (const char *csr_name, is_h_required = (csr_class == CSR_CLASS_SSCSRIND_AND_H); extension = "sscsrind"; break; + case CSR_CLASS_SSQOSID: + extension = "ssqosid"; + break; case CSR_CLASS_SSSTATEEN_AND_H_32: is_rv32_only = true; /* Fall through. */ diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index ce28f59fa74..78e1640248e 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -823,6 +823,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+73e59073[ ]+csrw[ ]+mhpmevent30h,a1 [ ]+[0-9a-f]+:[ ]+73f02573[ ]+csrr[ ]+a0,mhpmevent31h [ ]+[0-9a-f]+:[ ]+73f59073[ ]+csrw[ ]+mhpmevent31h,a1 +[ ]+[0-9a-f]+:[ ]+18102573[ ]+csrr[ ]+a0,srmcfg +[ ]+[0-9a-f]+:[ ]+18159073[ ]+csrw[ ]+srmcfg,a1 [ ]+[0-9a-f]+:[ ]+14d02573[ ]+csrr[ ]+a0,stimecmp [ ]+[0-9a-f]+:[ ]+14d59073[ ]+csrw[ ]+stimecmp,a1 [ ]+[0-9a-f]+:[ ]+15d02573[ ]+csrr[ ]+a0,stimecmph diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index 5f6a956af5f..658ed27e724 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -1607,6 +1607,10 @@ .*Info: macro .* .*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension .*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* .*Warning: invalid CSR `stimecmp', needs `sstc' extension .*Info: macro .* .*Warning: invalid CSR `stimecmp', needs `sstc' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index 7bbcf33048e..b130ccc33c4 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -823,6 +823,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+73e59073[ ]+csrw[ ]+mhpmevent30h,a1 [ ]+[0-9a-f]+:[ ]+73f02573[ ]+csrr[ ]+a0,mhpmevent31h [ ]+[0-9a-f]+:[ ]+73f59073[ ]+csrw[ ]+mhpmevent31h,a1 +[ ]+[0-9a-f]+:[ ]+18102573[ ]+csrr[ ]+a0,srmcfg +[ ]+[0-9a-f]+:[ ]+18159073[ ]+csrw[ ]+srmcfg,a1 [ ]+[0-9a-f]+:[ ]+14d02573[ ]+csrr[ ]+a0,stimecmp [ ]+[0-9a-f]+:[ ]+14d59073[ ]+csrw[ ]+stimecmp,a1 [ ]+[0-9a-f]+:[ ]+15d02573[ ]+csrr[ ]+a0,stimecmph diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index 412271ccdfd..e381aad211b 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -1603,6 +1603,10 @@ .*Info: macro .* .*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension .*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* .*Warning: invalid CSR `stimecmp', needs `sstc' extension .*Info: macro .* .*Warning: invalid CSR `stimecmp', needs `sstc' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index 25518dc8646..81f39104f3d 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -823,6 +823,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+73e59073[ ]+csrw[ ]+mhpmevent30h,a1 [ ]+[0-9a-f]+:[ ]+73f02573[ ]+csrr[ ]+a0,mhpmevent31h [ ]+[0-9a-f]+:[ ]+73f59073[ ]+csrw[ ]+mhpmevent31h,a1 +[ ]+[0-9a-f]+:[ ]+18102573[ ]+csrr[ ]+a0,srmcfg +[ ]+[0-9a-f]+:[ ]+18159073[ ]+csrw[ ]+srmcfg,a1 [ ]+[0-9a-f]+:[ ]+14d02573[ ]+csrr[ ]+a0,stimecmp [ ]+[0-9a-f]+:[ ]+14d59073[ ]+csrw[ ]+stimecmp,a1 [ ]+[0-9a-f]+:[ ]+15d02573[ ]+csrr[ ]+a0,stimecmph diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index 4848a68a8d9..6d161423378 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -1327,6 +1327,10 @@ .*Info: macro .* .*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension .*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* .*Warning: invalid CSR `stimecmp', needs `sstc' extension .*Info: macro .* .*Warning: invalid CSR `stimecmp', needs `sstc' extension diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s index 8378e14d07d..d00c1bcb5d8 100644 --- a/gas/testsuite/gas/riscv/csr.s +++ b/gas/testsuite/gas/riscv/csr.s @@ -464,6 +464,9 @@ csr mhpmevent30h csr mhpmevent31h + # Sscofpmf extension + csr srmcfg + # Sstc extension csr stimecmp csr stimecmph diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 003359242d0..4a45948dde9 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -121,6 +121,7 @@ All available -march extensions for RISC-V: sscsrind 1.0 sscofpmf 1.0 sscounterenw 1.0 + ssqosid 1.0 ssstateen 1.0 sstc 1.0 sstvala 1.0 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 2209e1a48c1..f088a710254 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -4164,6 +4164,8 @@ #define CSR_MHPMEVENT29H 0x73d #define CSR_MHPMEVENT30H 0x73e #define CSR_MHPMEVENT31H 0x73f +/* Ssqosid extension */ +#define CSR_SRMCFG 0x181 /* Sstc extension */ #define CSR_STIMECMP 0x14d #define CSR_STIMECMPH 0x15d @@ -5267,6 +5269,8 @@ DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLA DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Ssqosid extension. */ +DECLARE_CSR(srmcfg, CSR_SRMCFG, CSR_CLASS_SSQOSID, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Sstc extension */ DECLARE_CSR(stimecmp, CSR_STIMECMP, CSR_CLASS_SSTC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)