From patchwork Mon Sep 23 08:35:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 97846 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 33BD83858402 for ; Mon, 23 Sep 2024 08:36:43 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTPS id B68123858D20 for ; Mon, 23 Sep 2024 08:36:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B68123858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B68123858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1727080574; cv=none; b=fyUDDGAkDEUNbSGzGFdJIRiQs4qB5qA8zI7oNnvp0qUPR0HcrBJ5YVGlgLU272kdomEpOqvSTder0Kz84iV3YJdqbXCR5xfwzcUkv159xtJQasFgwV83E8pp99g7ysXoAmvhzHkA78OGxB43T07w24OiUAnMaXVEQramvYCn+ZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1727080574; c=relaxed/simple; bh=X86on90vl8SUhxIrx9BNq0f6k1uLrov9KexCSHqu0sU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=geR9q0KhbZTWqphxjJCN127dinT2sx11wYXPXfPJetTGm04xxWbl+3c6BWHx2r25IyhTGevok8IonzogEj0rlwrxSX0Rcz3QzYMEw/aINMeD3YWhNwFvqt7/mhKjtLv+fQymzueAV/XlQDbfu0LMCHJMo4qAFr371mFAjKAee2U= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [112.74.111.65]) by APP-01 (Coremail) with SMTP id qwCowABXPn1wKPFmbPFsAA--.16572S2; Mon, 23 Sep 2024 16:36:02 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, jbeulich@suse.com, kito.cheng@gmail.com, palmer@rivosinc.com, christoph.muellner@vrull.eu, Jiawei Subject: [PATCH v2] RISC-V: Add Smrnmi extension csrs. Date: Mon, 23 Sep 2024 16:35:08 +0800 Message-Id: <20240923083508.292400-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: qwCowABXPn1wKPFmbPFsAA--.16572S2 X-Coremail-Antispam: 1UD129KBjvAXoW3KFWrWr18XFWUKFyDuF15Arb_yoW8Jw1fCo WxGF43Aa1rWFsFkwn8Cw48Ja1vgFyjg398Aa95uanrWa1rCr4rX3s0k3WkCw18Kr18Xr4q 9aykZF18XF93Arsxn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYo7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8 JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI0_ JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67 AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIY rxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8 JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUBVbkUUU UU= X-Originating-IP: [112.74.111.65] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiDAcJAGbxDUdqtQAAsA X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/lily689/Risc-manual/blob/main/src/priv-csrs.adoc Version log: Update patch description info, Update 'mnstatus' address into '0x744'. bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations. --- bfd/elfxx-riscv.c | 1 + gas/NEWS | 2 ++ gas/config/tc-riscv.c | 4 ++++ gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p10.l | 16 ++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p11.l | 16 ++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p12.l | 16 ++++++++++++++++ gas/testsuite/gas/riscv/csr.s | 6 ++++++ gas/testsuite/gas/riscv/march-help.l | 1 + include/opcode/riscv-opc.h | 10 ++++++++++ 12 files changed, 96 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 64b7d71f2cb..26ec664d88a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1439,6 +1439,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"smcsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smrnmi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/NEWS b/gas/NEWS index 24055d2f5e9..ade7f728e95 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -3,6 +3,8 @@ * Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01) and CORE-V (xcvbitmanip, xcvsimd) extensions with version 1.0. +* Add support for RISC-V Smrnmi extension with version 1.0. + Changes in 2.43: * Add support for LoongArch .option for fine-grained control of assembly diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index bf2020d656b..301607b0aad 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -81,6 +81,7 @@ enum riscv_csr_class CSR_CLASS_SMCSRIND, /* Smcsrind */ CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */ CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */ + CSR_CLASS_SMRNMI, /* Smrnmi */ CSR_CLASS_SMSTATEEN, /* Smstateen only */ CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ CSR_CLASS_SSAIA, /* Ssaia */ @@ -1082,6 +1083,9 @@ riscv_csr_address (const char *csr_name, need_check_version = true; extension = "smcntrpmf"; break; + case CSR_CLASS_SMRNMI: + extension = "smrnmi"; + break; case CSR_CLASS_SMSTATEEN_32: is_rv32_only = true; /* Fall through. */ diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index 5165f4bea0d..ce28f59fa74 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -645,6 +645,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1 [ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh [ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index 17a8bb638e8..5f6a956af5f 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -941,6 +941,22 @@ .*Info: macro .* .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension .*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index 1cb5a917f1a..7bbcf33048e 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -645,6 +645,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1 [ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh [ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index 8b797e8893e..412271ccdfd 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -937,6 +937,22 @@ .*Info: macro .* .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension .*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index ac88d9370f8..25518dc8646 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -645,6 +645,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1 [ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh [ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index 81a7aba25c8..4848a68a8d9 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -661,6 +661,22 @@ .*Info: macro .* .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension .*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Info: macro .* .*Warning: invalid CSR `mstateen0', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s index 378caef35b0..8378e14d07d 100644 --- a/gas/testsuite/gas/riscv/csr.s +++ b/gas/testsuite/gas/riscv/csr.s @@ -365,6 +365,12 @@ csr mcyclecfgh csr minstretcfgh + # smrnmi + csr mnepc + csr mncause + csr mnscratch + csr mnstatus + # Smstateen/Ssstateen extensions csr mstateen0 csr mstateen1 diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 0c33d1ee76d..003359242d0 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -114,6 +114,7 @@ All available -march extensions for RISC-V: smcsrind 1.0 smcntrpmf 1.0 smepmp 1.0 + smrnmi 1.0 smstateen 1.0 ssaia 1.0 ssccptr 1.0 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 73ee81158ae..2209e1a48c1 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -4074,6 +4074,11 @@ #define CSR_MINSTRETCFG 0x322 #define CSR_MCYCLECFGH 0x721 #define CSR_MINSTRETCFGH 0x722 +/* Smrnmi extension. */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 /* Smstateen extension */ #define CSR_MSTATEEN0 0x30c #define CSR_MSTATEEN1 0x30d @@ -5172,6 +5177,11 @@ DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mcyclecfgh, CSR_MCYCLECFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(minstretcfgh, CSR_MINSTRETCFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +/* Smrnmi extensions. */ +DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Smstateen/Ssstateen extensions. */ DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)