From patchwork Fri Oct 15 05:06:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 46258 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 00E923857825 for ; Fri, 15 Oct 2021 05:07:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 00E923857825 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1634274445; bh=+nEhVXvfoZXISNqLfw6Qx2nnnPClB8E3p9LON9H66Ks=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=dfpnmGErYDJwjCDjDD4AHBu2CHWj+ew3fE9TYvyjS+GGIfp9md/spmbzfC/XJnDc6 hEHKckKaqvNPMSBjmZNPUkFr31fxKVLvFKpH6xbfUIXlxU7V/u14LFR2W3tXY7ILay aoHxZAwFpfTSum3r4qzHI0mUPaPOKEITrQXokzYA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id A97F23857C71 for ; Fri, 15 Oct 2021 05:06:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A97F23857C71 X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="288716634" X-IronPort-AV: E=Sophos;i="5.85,374,1624345200"; d="scan'208";a="288716634" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 22:06:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,374,1624345200"; d="scan'208";a="716406124" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga006.fm.intel.com with ESMTP; 14 Oct 2021 22:06:04 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 19F563Se010019; Thu, 14 Oct 2021 22:06:04 -0700 To: hongtao.liu@intel.com Subject: [PATCH] AVX512FP16: Fix ICE for 2 v4hf vector concat Date: Fri, 15 Oct 2021 13:06:03 +0800 Message-Id: <20211015050603.59842-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_SOFTFAIL, SPOOFED_FREEMAIL, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hongyu Wang via Gcc-patches From: Hongyu Wang Reply-To: Hongyu Wang Cc: gcc-patches@gcc.gnu.org Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, For V4HFmode, doing vector concat like __builtin_shufflevector (a, b, {0, 1, 2, 3, 4, 5, 6, 7}) could trigger ICE since it is not handled in ix86_vector_init (). Handle HFmode like HImode to avoid such ICE. Bootstrappted/regtested on x86_64-pc-linux-gnu{-m32,} and sde{-m32,} OK for master? gcc/ChangeLog: * config/i386/i386-expand.c (ix86_expand_vector_init): For half_vector concat for HFmode, handle them like HImode. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-v4hf-concat.c: New test. --- gcc/config/i386/i386-expand.c | 3 ++- .../gcc.target/i386/avx512fp16-v4hf-concat.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 95274201f4f..1b011047251 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -15122,7 +15122,8 @@ ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals) rtx ops[2] = { XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1) }; if (inner_mode == QImode || inner_mode == HImode - || inner_mode == TImode) + || inner_mode == TImode + || inner_mode == HFmode) { unsigned int n_bits = n_elts * GET_MODE_SIZE (inner_mode); scalar_mode elt_mode = inner_mode == TImode ? DImode : SImode; diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c new file mode 100644 index 00000000000..3b8a7f39b85 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vpunpcklqdq" 1 } } */ + +typedef _Float16 v8hf __attribute__((vector_size (16))); +typedef _Float16 v4hf __attribute__((vector_size (8))); + +v8hf foov (v4hf a, v4hf b) +{ + return __builtin_shufflevector (a, b, 0, 1, 2, 3, 4, 5, 6, 7); +} + +v8hf foov2 (v4hf a) +{ + return __builtin_shufflevector (a, (v4hf){0}, 0, 1, 2, 3, 4, 5, 6, 7); +}