From patchwork Thu Sep 5 18:03:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 97186 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D112E384AB66 for ; Thu, 5 Sep 2024 18:03:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 427B1385840E for ; Thu, 5 Sep 2024 18:03:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 427B1385840E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 427B1385840E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::636 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725559406; cv=none; b=aOxa+g2DMJMRHBOcK3XZRLguqsoBx7xuh5X3zif25p+3uCnrrvrRdVZ8gAA7IR6jVnYaCjqn+Ny+d0+dFOdQrB0yZKfbq57qvF1I4wAAXZC+aj0hrQFUTLHRwV72MivlEA29FBJIzhep2RgiIlnzEYE50r8S00Y8QfSilNeVoRs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725559406; c=relaxed/simple; bh=EO2lvFs38P5M30db8C51z8nXMDtYypc+Cq+j6rFz708=; h=DKIM-Signature:Message-ID:Date:MIME-Version:From:Subject:To; b=L05bp+jZsDC/iQZIh3EvCw7uCY65bEF4HrOVAsmgGW/kVMdudlTTIuwXdKFv7p6pJqH2XWC7DtLDllazdK2ggsRqoBg9J0UStH6DugZoDLCe3/ri4Uv/OGeidcAjh+lvZmjibRBb21umpdeKeAQZk3wxd8v21XqQLEUqYeNcAFc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2054e22ce3fso11323345ad.2 for ; Thu, 05 Sep 2024 11:03:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725559403; x=1726164203; darn=gcc.gnu.org; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=V3kEwsmusjocqTZAxhP3/ykL+jYcAG1xL8awtliO484=; b=EzbPA7hM4TsYFZE2a0DdBvt+CnjPilNv5AhybjFLodPQ3Ej9Ukkv6DPpUhzSqYvnZV tqvqy8lXx+8zAgh5pUDDhz7vKBfD2Yv+KP/zMuTrfxN48bCEYAGKqiDLSQtUBBJnh6Qd L5vsztFYrlmE93wT2nPBU6oD5HPI+AlUOmO1mhiu0KXobxmc64uLHe1+CNjeT/WWT1pF 3W2TGYIoJ3pDmoVCzYnnSKqvXTRxUXDN8tBOYVuboRSvS7GFO2qFP+z8fy3DG9H0Hjiw DUgKO7rVsgv1fWtgwyaR86ZRZ8lOOMGCxuS2GL1tWRe0bEpdQIHcGEE/4xhc1YQpbmNU wI8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725559403; x=1726164203; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=V3kEwsmusjocqTZAxhP3/ykL+jYcAG1xL8awtliO484=; b=FPtGtwXLu3my4zE+1IOMmu7mJ/YzDVgq2NdLK6iduZNpFAshMXxRaaMHMDCUdRFvuF hC8qmxkQekgPpkhq65VWepYHFmOX8jWHzdmFq0PySvkfMisEAUkKAhFaBKS/XV4wnDp3 GRd2Oc1TedJ/jHQJYw5JVsuNVqEz5vvCDJOsWyaFDHStjFzyq2yEZRVflQgzFllSfz6e oJjKd5eSGDW3L0Ruv6ge5JXbiNxh78nu4wpVY6A0vZBmjYgsgGzJVBoAdYbr8MU6BvLV ZOYaPR5/sVKwfF/BQ7Dx2YKkGvJ46qqV7pMQpIpsYygWYGeOalTTlKy4SKj1EgGYmxyq FdLA== X-Gm-Message-State: AOJu0YxPBYZZhFWglhdHRPMvy/8BxK30XnkfbY2hrBsA7RQ8nOsg1Kki BIvEdQszq3Kaopsd91tKtnZqariw2CEO8sKj9gGp6ZXkMJx+IO+LGFFfPA== X-Google-Smtp-Source: AGHT+IG/K2VozS8YLn7L4t5GuS2MAdA0ZQhkLnWrYPbFEkcbvDX05wcshYBChWfxuJfLtnKR3wkEmw== X-Received: by 2002:a17:902:e849:b0:205:894b:b5b0 with SMTP id d9443c01a7336-20699af231bmr117506605ad.33.1725559402753; Thu, 05 Sep 2024 11:03:22 -0700 (PDT) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-206aea559adsm31283635ad.215.2024.09.05.11.03.20 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Sep 2024 11:03:22 -0700 (PDT) Message-ID: Date: Thu, 5 Sep 2024 12:03:18 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US From: Jeff Law Subject: [to-be-committed][V2][RISC-V] Avoid unnecessary extensions after sCC insns To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org So the first patch failed the pre-commit CI; it didn't fail in my testing because I'm using --with-arch to set a default configuration that includes things like zicond to ensure that's always tested. And the failing test is skipped when zicond is enabled by default. The failing test is designed to ensure that we don't miss an if-conversion due to costing issues around the extension that was typically done in an sCC sequence (which is why it's only run when zicond is off). The test failed because we have a little routine that is highly dependent on the code generated by the sCC expander and will adjust the costing to account for expansion quirks that usually go away in register allocation. That code needs to be enhanced to work after the sCC expansion change. Essentially it needs to account for the subreg extraction that shows up in the sequence as well as being a bit looser on mode checking. I kept the code working for the old sequences -- in theory a user could conjure up the old sequence so handling them seems useful. This also drops the testsuite changes. Palmer's change makes them unnecessary. Waiting on pre-commit CI before taking any further action... Jeff diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a38cb72f09f..39489c4377e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4218,11 +4218,29 @@ riscv_noce_conversion_profitable_p (rtx_insn *seq, riscv_if_info.original_cost += COSTS_N_INSNS (1); riscv_if_info.max_seq_cost += COSTS_N_INSNS (1); } - last_dest = NULL_RTX; + rtx dest = SET_DEST (x); - if (COMPARISON_P (src) + + /* Do something similar for the moves that are likely to + turn into NOP moves by the time the register allocator is + done. These are also side effects of how our sCC expanders + work. We'll want to check and update LAST_DEST here too. */ + if (last_dest && REG_P (dest) - && GET_MODE (dest) == SImode) + && GET_MODE (dest) == SImode + && SUBREG_P (src) + && SUBREG_PROMOTED_VAR_P (src) + && REGNO (SUBREG_REG (src)) == REGNO (last_dest)) + { + riscv_if_info.original_cost += COSTS_N_INSNS (1); + riscv_if_info.max_seq_cost += COSTS_N_INSNS (1); + if (last_dest) + last_dest = dest; + } + else + last_dest = NULL_RTX; + + if (COMPARISON_P (src) && REG_P (dest)) last_dest = dest; } else @@ -4904,13 +4922,31 @@ riscv_expand_int_scc (rtx target, enum rtx_code code, rtx op0, rtx op1, bool *in riscv_extend_comparands (code, &op0, &op1); op0 = force_reg (word_mode, op0); + /* For sub-word targets on rv64, do the computation in DImode + then extract the lowpart for the final target, marking it + as sign extended. Note that it's also properly zero extended, + but it's probably more profitable to expose it as sign extended. */ + rtx t; + if (TARGET_64BIT && GET_MODE (target) == SImode) + t = gen_reg_rtx (DImode); + else + t = target; + if (code == EQ || code == NE) { rtx zie = riscv_zero_if_equal (op0, op1); - riscv_emit_binary (code, target, zie, const0_rtx); + riscv_emit_binary (code, t, zie, const0_rtx); } else - riscv_emit_int_order_test (code, invert_ptr, target, op0, op1); + riscv_emit_int_order_test (code, invert_ptr, t, op0, op1); + + if (t != target) + { + t = gen_lowpart (SImode, t); + SUBREG_PROMOTED_VAR_P (t) = 1; + SUBREG_PROMOTED_SET (t, SRP_SIGNED); + emit_move_insn (target, t); + } } /* Like riscv_expand_int_scc, but for floating-point comparisons. */