From patchwork Thu Oct 14 01:11:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 46191 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 38A243858022 for ; Thu, 14 Oct 2021 01:11:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cmx-mtlrgo001.bell.net (mta-mtl-003.bell.net [209.71.208.13]) by sourceware.org (Postfix) with ESMTP id D48273858D39 for ; Thu, 14 Oct 2021 01:11:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D48273858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=bell.net Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=bell.net X-RG-CM-BuS: 0 X-RG-CM-SC: 0 X-RG-CM: Clean X-Originating-IP: [67.71.8.137] X-RG-Env-Sender: dave.anglin@bell.net X-RG-Rigid: 60C893820893C2EF X-CM-Envelope: MS4xfIgyHfuEIWP3pVWQlpTSprrepW41Qc+1KmcPQubJc6wpPVEKn3XhjrqVZ4A7TSrSV/dK9mp1Uv+MFmVWm/D0WQKfInIIQQ7vkDIeIP2szCkbHIHnMpX9 BRLS+mjUW3YC8F9Oh9xzTR1RXErl77bHLD6x6R6vEJc18l4ykRIoSZhMF3xG930RxYqfhQ+536hvnan0jhJacxCrc1eJsqe2mc9sF3NQ/XMsw3D2H5o92FB2 g0H4sgEl8bCjlBocX5DeQQ== X-CM-Analysis: v=2.4 cv=Z6GPoFdA c=1 sm=1 tr=0 ts=616783cb a=jrdA9tB8yuRqUzQ1EpSZjA==:117 a=jrdA9tB8yuRqUzQ1EpSZjA==:17 a=IkcTkHD0fZMA:10 a=mDV3o1hIAAAA:8 a=_Sw0tGzCeUde31WptgEA:9 a=QEXdDO2ut3YA:10 a=_FVE-zBwftR9WsbkzFJk:22 Received: from [192.168.2.49] (67.71.8.137) by cmx-mtlrgo001.bell.net (5.8.716.03) (authenticated as dave.anglin@bell.net) id 60C893820893C2EF; Wed, 13 Oct 2021 21:11:39 -0400 Message-ID: <98c1c4e3-91b5-1232-02d8-d8961415b1b1@bell.net> Date: Wed, 13 Oct 2021 21:11:39 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Content-Language: en-US To: GCC Patches From: John David Anglin Subject: [committed] hppa: Fix TARGET_SOFT_FLOAT patterns in pa.md X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, MEDICAL_SUBJECT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This change fixes building libgcc with -msoft-float. Getting soft float to work in libgcc is still a work in progress. Tested on hppa-unkown-linux-gnu, hppa2.0w-hp-hpux11.11 and hppa64-hp-hpux11.11. Committed to active branches. Dave --- Fix TARGET_SOFT_FLOAT patterns in pa.md 2021-10-13 John David Anglin gcc/ChangeLog: * config/pa/pa.md (cbranchsf4): Disable if TARGET_SOFT_FLOAT. (cbranchdf4): Likewise. Add missing move patterns for TARGET_SOFT_FLOAT. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index b314f96de35..ba947ab1be9 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -1383,7 +1383,7 @@ (match_operand:SF 2 "reg_or_0_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] - "" + "! TARGET_SOFT_FLOAT" " { pa_emit_bcond_fp (operands); @@ -1398,7 +1398,7 @@ (match_operand:DF 2 "reg_or_0_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] - "" + "! TARGET_SOFT_FLOAT" " { pa_emit_bcond_fp (operands); @@ -2236,6 +2236,29 @@ (set_attr "pa_combine_type" "addmove") (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) +(define_insn "" + [(set (match_operand:SI 0 "move_dest_operand" + "=r,r,r,r,r,r,Q,!*q,!r") + (match_operand:SI 1 "move_src_operand" + "A,r,J,N,K,RQ,rM,!rM,!*q"))] + "(register_operand (operands[0], SImode) + || reg_or_0_operand (operands[1], SImode)) + && TARGET_SOFT_FLOAT + && TARGET_64BIT" + "@ + ldw RT'%A1,%0 + copy %1,%0 + ldi %1,%0 + ldil L'%1,%0 + {zdepi|depwi,z} %Z1,%0 + ldw%M1 %1,%0 + stw%M0 %r1,%0 + mtsar %r1 + {mfctl|mfctl,w} %%sar,%0" + [(set_attr "type" "load,move,move,move,shift,load,store,move,move") + (set_attr "pa_combine_type" "addmove") + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) + (define_insn "" [(set (match_operand:SI 0 "indexed_memory_operand" "=R") (match_operand:SI 1 "register_operand" "f"))] @@ -4042,6 +4065,25 @@ (set_attr "pa_combine_type" "addmove") (set_attr "length" "4,4,4,4,4,4,4,4,4")]) +(define_insn "" + [(set (match_operand:DF 0 "move_dest_operand" + "=!*r,*r,*r,*r,*r,Q") + (match_operand:DF 1 "move_src_operand" + "!*r,J,N,K,RQ,*rG"))] + "(register_operand (operands[0], DFmode) + || reg_or_0_operand (operands[1], DFmode)) + && TARGET_SOFT_FLOAT && TARGET_64BIT" + "@ + copy %1,%0 + ldi %1,%0 + ldil L'%1,%0 + depdi,z %z1,%0 + ldd%M1 %1,%0 + std%M0 %r1,%0" + [(set_attr "type" "move,move,move,shift,load,store") + (set_attr "pa_combine_type" "addmove") + (set_attr "length" "4,4,4,4,4,4")]) + (define_expand "movdi" [(set (match_operand:DI 0 "general_operand" "") @@ -4200,6 +4242,28 @@ (set_attr "pa_combine_type" "addmove") (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) +(define_insn "" + [(set (match_operand:DI 0 "move_dest_operand" + "=r,r,r,r,r,r,Q,!*q,!r") + (match_operand:DI 1 "move_src_operand" + "A,r,J,N,K,RQ,rM,!rM,!*q"))] + "(register_operand (operands[0], DImode) + || reg_or_0_operand (operands[1], DImode)) + && TARGET_SOFT_FLOAT && TARGET_64BIT" + "@ + ldd RT'%A1,%0 + copy %1,%0 + ldi %1,%0 + ldil L'%1,%0 + depdi,z %z1,%0 + ldd%M1 %1,%0 + std%M0 %r1,%0 + mtsar %r1 + {mfctl|mfctl,w} %%sar,%0" + [(set_attr "type" "load,move,move,move,shift,load,store,move,move") + (set_attr "pa_combine_type" "addmove") + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) + (define_insn "" [(set (match_operand:DI 0 "indexed_memory_operand" "=R") (match_operand:DI 1 "register_operand" "f"))] @@ -4405,6 +4469,23 @@ (set_attr "pa_combine_type" "addmove") (set_attr "length" "4,4,4,4,4,4")]) +(define_insn "" + [(set (match_operand:SF 0 "move_dest_operand" + "=!*r,*r,Q") + (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand" + "!*rG,RQ,*rG"))] + "(register_operand (operands[0], SFmode) + || reg_or_0_operand (operands[1], SFmode)) + && TARGET_SOFT_FLOAT + && TARGET_64BIT" + "@ + copy %r1,%0 + ldw%M1 %1,%0 + stw%M0 %r1,%0" + [(set_attr "type" "move,load,store") + (set_attr "pa_combine_type" "addmove") + (set_attr "length" "4,4,4")]) + (define_insn "" [(set (match_operand:SF 0 "indexed_memory_operand" "=R") (match_operand:SF 1 "register_operand" "f"))]