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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ac6578344fsm8605309a12.91.2024.07.31.04.54.50 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 04:54:50 -0700 (PDT) Message-ID: <3bfd6cff-3477-4ac2-a945-f24098c4a414@suse.com> Date: Wed, 31 Jul 2024 13:54:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 1/9] gas: have scrubber also respect quoted labels From: Jan Beulich To: Binutils References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_FILL_THIS_FORM_SHORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org For the handling of ':' elsewhere in the scrubber to be correct with regard to labels, the state after parsing a string found at the start of a line must match that after finding a symbol character at the start of a line. (Things are largely okay when there's whitespace ahead of the label: Whitespace after the colon then is retained rather than dropped for typical targets like x86, but read.c will know to deal with that.) --- v3: New. --- a/gas/app.c +++ b/gas/app.c @@ -1113,6 +1113,8 @@ do_scrub_chars (size_t (*get) (char *, s } else if (state == 3) old_state = 9; + else if (state == 0) + old_state = 11; /* Now seeing label definition. */ else old_state = state; state = 5; --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -477,6 +477,7 @@ if [is_elf_format] { } run_dump_test quoted-sym-names +run_dump_test quoted-label-blank # Targets where # is not a line comment character don't transform # "# " into .linefile (PR gas/29120). --- /dev/null +++ b/gas/testsuite/gas/all/quoted-label-blank.d @@ -0,0 +1,9 @@ +#nm: --extern-only --numeric-sort +#name: quoted label name followed by whitespace +# No quoted strings handling (TC_STRING_ESCAPES set to 0): +#notarget: powerpc*-*-aix* powerpc*-*-beos* powerpc-*-macos* rs6000-*-* +# Certain LABELS_WITHOUT_COLONS targets: +#notarget: mmix-*-* tic54*-*-* z80-*-* + +#... +0+00 D blank-after --- /dev/null +++ b/gas/testsuite/gas/all/quoted-label-blank.s @@ -0,0 +1,4 @@ + .data + .globl "blank-after" +"blank-after" : + .byte 0 From patchwork Wed Jul 31 11:55:40 2024 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ac655811d6sm8652576a12.83.2024.07.31.04.55.41 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 04:55:41 -0700 (PDT) Message-ID: Date: Wed, 31 Jul 2024 13:55:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 2/9] gas: respect CR_EOL also for scrubbing From: Jan Beulich To: Binutils References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3023.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org While apparently intended to be only externally controlled (e.g. via specifying CFLAGS at make invocation), we should still keep scrubber and lexer in sync in this regard. There's one place which imo was previously wrong already, but would go further wrong and hence is being adjusted right here: An .mri directive can be terminated by any kind of "line" (really: statement) separators. --- Btw, is it actually correct to honor line_comment_chars[] after other than a physical line break (LEX_IS_NEWLINE), possibly followed by whitespace? Aren't these forms of comments meant to remove entire physical lines only, but not tails thereof? After all the processing of such a comment looks for a newline, not just a line separator. --- v3: New. --- a/gas/app.c +++ b/gas/app.c @@ -93,7 +93,11 @@ static char last_char; static char lex[256] = { [' '] = LEX_IS_WHITESPACE, ['\t'] = LEX_IS_WHITESPACE, +#ifdef CR_EOL + ['\r'] = LEX_IS_LINE_SEPARATOR, +#else ['\r'] = LEX_IS_WHITESPACE, +#endif ['\n'] = LEX_IS_NEWLINE, [':'] = LEX_IS_COLON, ['$'] = LEX_IS_SYMBOL_COMPONENT, @@ -862,7 +866,9 @@ do_scrub_chars (size_t (*get) (char *, s ++mri_state; } else if (*mri_state != '\0' - || (!IS_WHITESPACE (ch) && !IS_NEWLINE (ch))) + || (!IS_WHITESPACE (ch) + && !IS_LINE_SEPARATOR (ch) + && !IS_NEWLINE (ch))) { /* We did not get the expected character, or we didn't get a valid terminating character after seeing the From patchwork Wed Jul 31 11:56:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 94861 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D4523858294 for ; Wed, 31 Jul 2024 11:57:27 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 550103858420 for ; Wed, 31 Jul 2024 11:56:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 550103858420 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 550103858420 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::636 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722426984; cv=none; b=Jt7PbO6nU/Tn2F+CGzG80vdAR/lCFQhCMaRDJBOVV45jACQ69abkMUPif2uEg3HOcE1UzbZIXpcXP096ro5XzuaCACfKnd2RzVEbuQ0LJAy7l65WSPQZtthssvLrWCPc+pLu27/eUZzuOJjjJE3z95K9mYBcOxqyXzv5hkqVJ8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722426984; c=relaxed/simple; bh=MxtPU322a4yW4yfv61pKbKPpr8WzaS7oyfyVfPR+jE0=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:From:To; b=WzUSkabJRqfL0cOvRrgGyyWtB4PdPkAOQoOEhebR5CXbwuvndufUaRdpwJKi9kSVOERwWVmxEKtbq2ULlkJdSw2p1bdyoTJp7nEL7NJcok+eGaYJc6BRf6pjIHCv4cIgrdF89QkatKbLUqHA5e2l2XuzlDFPLl9NkCNcvU1IZ4c= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a7aada2358fso147550066b.0 for ; Wed, 31 Jul 2024 04:56:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1722426982; x=1723031782; darn=sourceware.org; h=content-transfer-encoding:in-reply-to:autocrypt:cc:content-language :references:to:from:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=wXGqawW7OzUQ+JMrHoiASw9h5JEJuv/HBStvMk3JieQ=; b=Tr/XKvT3/noDh0jYcPYrK3jOuRE6zb2p18I1rwYBvIki9e/sQY+zQkNgobtyZZ7Iwk d/Gj2X+sRNWTUVJbhdi6OvbCpgBh8y+YR2CwL1phL4iPIAlyj9niwyiHBMM3vNoe7Ltc cHDDcoBy8IkhMhafJYWeltnBK3msTpBgXYobXN4IGJRtWDqi1VtVWae4OInHiffc+7uA x+T1pDE2+uxIFPVvcjmksVXBeyfjgLSF40E1QhM87DQghqayIcIYt+v1yglWPPI6mRzi 4U8S60+NV0DCbAJCRsqQf0yzGHfFt1CWxrI96cjUyXfkt9tpxBN0qzNDLUB7n7V225Wo iDdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722426982; x=1723031782; h=content-transfer-encoding:in-reply-to:autocrypt:cc:content-language :references:to:from:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=wXGqawW7OzUQ+JMrHoiASw9h5JEJuv/HBStvMk3JieQ=; b=SbxuHhTk0EHPgrOvf8TkrgS9xHhtoZNsGo0w+KBStCH1JwLwalT/ttQvncRmPqPlPo RfJI/DeuOog7PxwMgHuXNYvFWms2TL1K+Mz3Em7dFgPYziWiBsFRgdMnPhYbcJIT6BaO PmLrhmZKu+bRVne3DeOZWkAlMGXBAfmZ2tX5bQISk0derYQ3lirdrhQPR0no0INNVEDm eP69ksubnzgyh6RXjMh2TPDa2zOSNj9cdlfZmeh8vYMPM/yF7szkX/wA8zJF3a1PKuDS JC2sv5LGSOs8ie8vgLv03u0lKH2YL8Q0aiAwor13IA5VlwnyAMYffJnQu64ZidtV55nR c9oQ== X-Gm-Message-State: AOJu0YxIF8h4SLTvvTSON2KgZgfPiRoG1TElSmUoSXGjFB1K2sFI5MTm wrT77PSaOW8a2GcNr2LkGxp6BiC1vs6hjO64fsafyDQG2SbJX8Da7CKJlyTeG++zpQ4clQO0orQ = X-Google-Smtp-Source: AGHT+IEI6kPD8z9EwIpod/30hLXEf0xqklRzZXhmGnh8EEgCzW5b4XvrJ6zeB42I35mcXMHEJqw1bQ== X-Received: by 2002:a17:907:31ca:b0:a77:ca3b:996c with SMTP id a640c23a62f3a-a7d85963ecdmr548595466b.16.1722426981799; Wed, 31 Jul 2024 04:56:21 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. [37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acadb0225sm761024966b.191.2024.07.31.04.56.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 04:56:21 -0700 (PDT) Message-ID: <1cd82183-9300-4855-972f-f8a807089342@suse.com> Date: Wed, 31 Jul 2024 13:56:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 3/9] Arm: respect line separators for .symver scrubber special case From: Jan Beulich To: Binutils References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Cc: Nick Clifton , "ramana.radhakrishnan@arm.com" , Richard Earnshaw Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Directives end at "line" (really: statement) separators, not just at new-line chars. --- v3: New. --- a/gas/app.c +++ b/gas/app.c @@ -831,7 +831,7 @@ do_scrub_chars (size_t (*get) (char *, s { /* We've read the entire pseudo-op. If this is the end of the line, go back to the beginning. */ - if (IS_NEWLINE (ch)) + if (IS_NEWLINE (ch) || IS_LINE_SEPARATOR (ch)) symver_state = NULL; } } From patchwork Wed Jul 31 11:57:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 94862 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3F10E385828B for ; Wed, 31 Jul 2024 11:58:21 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id DCEA03858C56 for ; Wed, 31 Jul 2024 11:57:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DCEA03858C56 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DCEA03858C56 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::52e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722427052; cv=none; b=DpivquruHG25Mm5q4U1gyMeYfRQ2lFenGXXwMzKl5sZAc3B/r4bssg7ROAw7JoXB8SCAfRbOhXB3EdIh9lX0RRxCvzeixg/q7U7gLJZ1Mkk0AEE+8NaSuiiiqGz0y52507WaD9RDqogP8YHaeGgJ+7sbZJkQUbADw4JaFwXnf0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722427052; c=relaxed/simple; bh=XcZVC9PUHmH42I86YmFGr08Q3zztQ6sxTstgtFhlBRw=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:From:To; b=eKC3FrX1LWWfz0mSsGBX2fYhrmEzxlCvaakQNP1XU/OT4W4C0OkvPvjLSSk+qDC+VyY7xAhcjm8xrV+UnIviW+uq0FcMuwEZlx6bL8HQgBao7FAVc5UeDc03iVzpOLhbe3qVsv3BTGiPegPx4P5UQE9Gz//Gm48Oy5CPm4B6eVA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-5a2ffc3447fso7742073a12.1 for ; Wed, 31 Jul 2024 04:57:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1722427049; x=1723031849; darn=sourceware.org; h=content-transfer-encoding:in-reply-to:autocrypt:cc:content-language :references:to:from:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=ZtqvGXfVLVpdaZMINtZ9I0tNhcUCzrdjgFvJ0g7CwcE=; b=A3rGLYgAafLgDLtCn97dcEFfbCFjm53Myyqq9BfnoraMO2ukttvHTnfrh/QtZSrLIW 7fbfiWvJvOR/VALpFTFNRRx3D3ZzCj8YgohJma6qWvlkvkdAsG1IVwKiFVp2vI/27fSx zE5/fsYAZgY9LeLgW9qkR/QvOsvactTk1GOYVZCyQ4myn77ElLOs4BWsa3Ck7q8tMtCX mBzC0BZ16jGwI4V+UIh4zM2muCHKaRWNgtgoDbWfcLd2WKmbZHwgGKcdngqNzuxIgdD0 EAgJ4qM1u43j3n/vak6jW1I/2O3l1mVjtKM6+gYryQexbAEYPYzatu4dydyXSUqqQaUi jWSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722427049; x=1723031849; h=content-transfer-encoding:in-reply-to:autocrypt:cc:content-language :references:to:from:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZtqvGXfVLVpdaZMINtZ9I0tNhcUCzrdjgFvJ0g7CwcE=; b=HFDmkDrlFbqhX0hFDNR6Z5puW2eLiJ8V5ghtva//yjcWRx9hHGYM9cSq9d2eqLYN+V 5YKCU9RR1bPyqR9nroVdJ2gE15Pc8kzNETlJ7lQT834EIQUazTNoK2sUYAmoUvzx4T/F TZIDR0wI2+NXp6FOEI+P6yONOqEmJz5t3mYwQmkFl6ReCYh3M41RNcBTwT+AOqATZgNZ zz3DhRxJfTcOHx1rywxYevFGobTRUxHyIyueZ7gS6JZdiye4IrSebekjrcN5kGSw7qf3 C8DlsG/0DyiM3B+sbrfZqLMhGU0nMOfaecJyj2PTmU6C4CZrqO5EIExsdu2hvEbBu7wz Pcpg== X-Gm-Message-State: AOJu0YydWLpeM3TnBkqx7cpTzLGICZs2N+sgKTpiGkYXfTA0dvkzK7V5 cKYyAj1Ynxw9XIzmy2g2UOLHyYno9c+CyT0HTbBN+DGGe53LKlzWZt9DfOdLqM3B/ljQ/Nes9/s = X-Google-Smtp-Source: AGHT+IErzhj0d/QFiq7bEKyyaod4a7e9BGr+sNsrQeHVFs1WVCHIdKtpsDHphvGGjZgYtHFn9sEBdQ== X-Received: by 2002:a50:8e4d:0:b0:5a8:2f2b:d2d3 with SMTP id 4fb4d7f45d1cf-5b0224ceda6mr8872607a12.37.1722427049323; Wed, 31 Jul 2024 04:57:29 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. [37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ac63590ac3sm8603678a12.34.2024.07.31.04.57.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 04:57:29 -0700 (PDT) Message-ID: Date: Wed, 31 Jul 2024 13:57:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 4/9] m32r: move scrubber override to target header From: Jan Beulich To: Binutils References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Cc: Doug Evans Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Other than LEX_IS_* settings, such #define-s don't belong into the common source file. --- v3: New. --- a/gas/app.c +++ b/gas/app.c @@ -71,9 +71,6 @@ static char last_char; #ifdef TC_V850 #define LEX_IS_DOUBLEDASH_1ST 12 #endif -#ifdef TC_M32R -#define DOUBLEBAR_PARALLEL -#endif #ifdef DOUBLEBAR_PARALLEL #define LEX_IS_DOUBLEBAR_1ST 13 #endif --- a/gas/config/tc-m32r.h +++ b/gas/config/tc-m32r.h @@ -42,6 +42,9 @@ extern const char *m32r_target_format (v /* Permit temporary numeric labels. */ #define LOCAL_LABELS_FB 1 +/* '||' denotes parallel instruction */ +#define DOUBLEBAR_PARALLEL + #define DIFF_EXPR_OK /* .-foo gets turned into PC relative relocs. */ /* We don't need to handle .word strangely. */ From patchwork Wed Jul 31 11:58:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 94863 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 806573857011 for ; Wed, 31 Jul 2024 11:59:26 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 3C6D43858C3A for ; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acab23d56sm759814166b.38.2024.07.31.04.58.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 04:58:22 -0700 (PDT) Message-ID: Date: Wed, 31 Jul 2024 13:58:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 5/9] Arm: relax gas testsuite whitespace expectations From: Jan Beulich To: Binutils Cc: Nick Clifton , "ramana.radhakrishnan@arm.com" , Richard Earnshaw References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org In a subsequent change the scrubber is going to be changed to retain further whitespace. Test case expectations generally would better not depend on the specific whitespace treatment by the scrubber, unless of course a test is specifically about it. Adjust relevant test cases to permit blanks where those will subsequently appear. --- This is adding just the blanks that are going to be needed; imo it would generally be better if test case expectations were, from the very beginning, written to focus on what is being tested, rather than taking verbatim copies of the respective tool's output. --- a/gas/testsuite/gas/arm/addthumb2err.l +++ b/gas/testsuite/gas/arm/addthumb2err.l @@ -1,21 +1,21 @@ [^:]*: Assembler messages: -[^:]*:9: Error: shift value over 3 not allowed in thumb mode -- `add sp,sp,r0,LSL#4' -[^:]*:10: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,LSR#3' -[^:]*:11: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ASR#3' -[^:]*:12: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ROR#3' +[^:]*:9: Error: shift value over 3 not allowed in thumb mode -- `add sp,sp,r0,LSL ?#4' +[^:]*:10: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,LSR ?#3' +[^:]*:11: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ASR ?#3' +[^:]*:12: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ROR ?#3' [^:]*:13: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,RRX' -[^:]*:14: Error: shift value over 3 not allowed in thumb mode -- `adds sp,sp,r0,LSL#4' -[^:]*:15: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,LSR#3' -[^:]*:16: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ASR#3' -[^:]*:17: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ROR#3' +[^:]*:14: Error: shift value over 3 not allowed in thumb mode -- `adds sp,sp,r0,LSL ?#4' +[^:]*:15: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,LSR ?#3' +[^:]*:16: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ASR ?#3' +[^:]*:17: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ROR ?#3' [^:]*:18: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,RRX' -[^:]*:19: Error: shift value over 3 not allowed in thumb mode -- `sub sp,sp,r0,LSL#4' -[^:]*:20: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,LSR#3' -[^:]*:21: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ASR#3' -[^:]*:22: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ROR#3' +[^:]*:19: Error: shift value over 3 not allowed in thumb mode -- `sub sp,sp,r0,LSL ?#4' +[^:]*:20: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,LSR ?#3' +[^:]*:21: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ASR ?#3' +[^:]*:22: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ROR ?#3' [^:]*:23: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,RRX' -[^:]*:24: Error: shift value over 3 not allowed in thumb mode -- `subs sp,sp,r0,LSL#4' -[^:]*:25: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,LSR#3' -[^:]*:26: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ASR#3' -[^:]*:27: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ROR#3' +[^:]*:24: Error: shift value over 3 not allowed in thumb mode -- `subs sp,sp,r0,LSL ?#4' +[^:]*:25: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,LSR ?#3' +[^:]*:26: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ASR ?#3' +[^:]*:27: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ROR ?#3' [^:]*:28: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,RRX' --- a/gas/testsuite/gas/arm/arch7em-bad.l +++ b/gas/testsuite/gas/arm/arch7em-bad.l @@ -3,10 +3,10 @@ [^:]*:9: Error: selected processor does not support `pkhbt r9,r0,r0' in Thumb mode [^:]*:10: Error: selected processor does not support `pkhbt r0,r9,r0' in Thumb mode [^:]*:11: Error: selected processor does not support `pkhbt r0,r0,r9' in Thumb mode -[^:]*:12: Error: selected processor does not support `pkhbt r0,r0,r0,lsl#0x14' in Thumb mode -[^:]*:13: Error: selected processor does not support `pkhbt r0,r0,r0,lsl#3' in Thumb mode +[^:]*:12: Error: selected processor does not support `pkhbt r0,r0,r0,lsl ?#0x14' in Thumb mode +[^:]*:13: Error: selected processor does not support `pkhbt r0,r0,r0,lsl ?#3' in Thumb mode [^:]*:14: Error: selected processor does not support `pkhtb r1,r2,r3' in Thumb mode -[^:]*:15: Error: selected processor does not support `pkhtb r1,r2,r3,asr#0x11' in Thumb mode +[^:]*:15: Error: selected processor does not support `pkhtb r1,r2,r3,asr ?#0x11' in Thumb mode [^:]*:18: Error: selected processor does not support `qadd r1,r2,r3' in Thumb mode [^:]*:19: Error: selected processor does not support `qadd16 r1,r2,r3' in Thumb mode [^:]*:20: Error: selected processor does not support `qadd8 r1,r2,r3' in Thumb mode @@ -121,10 +121,10 @@ [^:]*:143: Error: selected processor does not support `uxtb16 r1,r2' in Thumb mode [^:]*:144: Error: selected processor does not support `uxtb16 r8,r9' in Thumb mode [^:]*:147: Error: selected processor does not support `sxtab r0,r0,r0' in Thumb mode -[^:]*:148: Error: selected processor does not support `sxtab r0,r0,r0,ror#0' in Thumb mode -[^:]*:149: Error: selected processor does not support `sxtab r9,r0,r0,ror#8' in Thumb mode -[^:]*:150: Error: selected processor does not support `sxtab r0,r9,r0,ror#16' in Thumb mode -[^:]*:151: Error: selected processor does not support `sxtab r0,r0,r9,ror#24' in Thumb mode +[^:]*:148: Error: selected processor does not support `sxtab r0,r0,r0,ror ?#0' in Thumb mode +[^:]*:149: Error: selected processor does not support `sxtab r9,r0,r0,ror ?#8' in Thumb mode +[^:]*:150: Error: selected processor does not support `sxtab r0,r9,r0,ror ?#16' in Thumb mode +[^:]*:151: Error: selected processor does not support `sxtab r0,r0,r9,ror ?#24' in Thumb mode [^:]*:153: Error: selected processor does not support `sxtab16 r1,r2,r3' in Thumb mode [^:]*:154: Error: selected processor does not support `sxtah r1,r2,r3' in Thumb mode [^:]*:155: Error: selected processor does not support `uxtab r1,r2,r3' in Thumb mode --- a/gas/testsuite/gas/arm/mve-vldr-bad-1.l +++ b/gas/testsuite/gas/arm/mve-vldr-bad-1.l @@ -103,20 +103,20 @@ [^:]*:88: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[r0,q1\]' [^:]*:90: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[r0,q1\]' [^:]*:92: Error: shift expression expected -- `vldrb.u8 q0,\[r0,q1,#0\]' -[^:]*:93: Error: can not shift offsets when accessing less than half-word -- `vldrb.u8 q0,\[r0,q1,UXTW#1\]' -[^:]*:94: Error: can not shift offsets when accessing less than half-word -- `vldrb.u16 q0,\[r0,q1,UXTW#1\]' -[^:]*:95: Error: can not shift offsets when accessing less than half-word -- `vldrb.u32 q0,\[r0,q1,UXTW#1\]' +[^:]*:93: Error: can not shift offsets when accessing less than half-word -- `vldrb.u8 q0,\[r0,q1,UXTW ?#1\]' +[^:]*:94: Error: can not shift offsets when accessing less than half-word -- `vldrb.u16 q0,\[r0,q1,UXTW ?#1\]' +[^:]*:95: Error: can not shift offsets when accessing less than half-word -- `vldrb.u32 q0,\[r0,q1,UXTW ?#1\]' [^:]*:96: Error: shift expression expected -- `vldrh.u16 q0,\[r0,q1,#1\]' -[^:]*:97: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#2\]' -[^:]*:98: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#2\]' -[^:]*:99: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#3\]' -[^:]*:100: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#3\]' +[^:]*:97: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW ?#2\]' +[^:]*:98: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW ?#2\]' +[^:]*:99: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW ?#3\]' +[^:]*:100: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW ?#3\]' [^:]*:101: Error: shift expression expected -- `vldrw.u32 q0,\[r0,q1,#2\]' -[^:]*:102: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#1\]' -[^:]*:103: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#3\]' +[^:]*:102: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW ?#1\]' +[^:]*:103: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW ?#3\]' [^:]*:104: Error: shift expression expected -- `vldrd.u64 q0,\[r0,q1,#3\]' -[^:]*:105: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#1\]' -[^:]*:106: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#2\]' -[^:]*:107: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#4\]' +[^:]*:105: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW ?#1\]' +[^:]*:106: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW ?#2\]' +[^:]*:107: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW ?#4\]' --- a/gas/testsuite/gas/arm/mve-vldr-bad-3.l +++ b/gas/testsuite/gas/arm/mve-vldr-bad-3.l @@ -161,27 +161,27 @@ [^:]*:139: Error: bad element type for instruction -- `vldrb.p32 q0,\[r2,q3\]' [^:]*:139: Error: bad element type for instruction -- `vldrb.p64 q0,\[r2,q3\]' [^:]*:139: Error: bad element type for instruction -- `vldrb.s8 q0,\[r2,q3\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.8 q0,\[r2,q3,uxtw#1\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.32 q0,\[r2,q3,uxtw#1\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.64 q0,\[r2,q3,uxtw#1\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.f32 q0,\[r2,q3,uxtw#1\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.f64 q0,\[r2,q3,uxtw#1\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.p32 q0,\[r2,q3,uxtw#1\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.p64 q0,\[r2,q3,uxtw#1\]' -[^:]*:142: Error: bad element type for instruction -- `vldrh.s16 q0,\[r2,q3,uxtw#1\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.8 q0,\[r2,q3,uxtw#2\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.16 q0,\[r2,q3,uxtw#2\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.64 q0,\[r2,q3,uxtw#2\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.f16 q0,\[r2,q3,uxtw#2\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.f64 q0,\[r2,q3,uxtw#2\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.p16 q0,\[r2,q3,uxtw#2\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.p64 q0,\[r2,q3,uxtw#2\]' -[^:]*:145: Error: bad element type for instruction -- `vldrw.s32 q0,\[r2,q3,uxtw#2\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.8 q0,\[r2,q3,uxtw#3\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.16 q0,\[r2,q3,uxtw#3\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.32 q0,\[r2,q3,uxtw#3\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.f16 q0,\[r2,q3,uxtw#3\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.f32 q0,\[r2,q3,uxtw#3\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.p16 q0,\[r2,q3,uxtw#3\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.p32 q0,\[r2,q3,uxtw#3\]' -[^:]*:148: Error: bad element type for instruction -- `vldrd.s64 q0,\[r2,q3,uxtw#3\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.8 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.32 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.64 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.f32 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.f64 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.p32 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.p64 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:142: Error: bad element type for instruction -- `vldrh.s16 q0,\[r2,q3,uxtw ?#1\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.8 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.16 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.64 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.f16 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.f64 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.p16 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.p64 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:145: Error: bad element type for instruction -- `vldrw.s32 q0,\[r2,q3,uxtw ?#2\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.8 q0,\[r2,q3,uxtw ?#3\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.16 q0,\[r2,q3,uxtw ?#3\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.32 q0,\[r2,q3,uxtw ?#3\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.f16 q0,\[r2,q3,uxtw ?#3\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.f32 q0,\[r2,q3,uxtw ?#3\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.p16 q0,\[r2,q3,uxtw ?#3\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.p32 q0,\[r2,q3,uxtw ?#3\]' +[^:]*:148: Error: bad element type for instruction -- `vldrd.s64 q0,\[r2,q3,uxtw ?#3\]' --- a/gas/testsuite/gas/arm/mve-vstr-bad-1.l +++ b/gas/testsuite/gas/arm/mve-vstr-bad-1.l @@ -45,7 +45,7 @@ [^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block [^:]*:36: *Info: macro .* [^:]*:39: Error: shift expression expected -- `vstrh.16 q0,\[r0,q1,#1\]' -[^:]*:40: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrh.16 q0,\[r0,q1,UXTW#2\]' +[^:]*:40: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrh.16 q0,\[r0,q1,UXTW ?#2\]' [^:]*:41: Error: bad element type for instruction -- `vstrw.8 q0,\[r0,q1\]' [^:]*:42: Error: bad element type for instruction -- `vstrw.u8 q0,\[r0,q1\]' [^:]*:43: Error: bad element type for instruction -- `vstrw.s8 q0,\[r0,q1\]' @@ -71,8 +71,8 @@ [^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block [^:]*:53: *Info: macro .* [^:]*:56: Error: shift expression expected -- `vstrw.32 q0,\[r0,q1,#2\]' -[^:]*:57: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#1\]' -[^:]*:58: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#3\]' +[^:]*:57: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW ?#1\]' +[^:]*:58: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW ?#3\]' [^:]*:59: Error: bad element type for instruction -- `vstrd.8 q0,\[r0,q1\]' [^:]*:60: Error: bad element type for instruction -- `vstrd.u8 q0,\[r0,q1\]' [^:]*:61: Error: bad element type for instruction -- `vstrd.s8 q0,\[r0,q1\]' @@ -100,9 +100,9 @@ [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block [^:]*:83: *Info: macro .* [^:]*:84: Error: shift expression expected -- `vstrd.64 q0,\[r0,q1,#3\]' -[^:]*:85: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#1\]' -[^:]*:86: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#2\]' -[^:]*:87: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#4\]' +[^:]*:85: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW ?#1\]' +[^:]*:86: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW ?#2\]' +[^:]*:87: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW ?#4\]' [^:]*:90: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]' [^:]*:91: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]' [^:]*:93: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]' --- a/gas/testsuite/gas/arm/neon-ldst-align-bad.l +++ b/gas/testsuite/gas/arm/neon-ldst-align-bad.l @@ -1,3 +1,3 @@ [^:]*: Assembler messages: -[^:]*:1: Error: bad alignment -- `vld1.8 {d0},\[r0:128\]' -[^:]*:2: Error: bad alignment -- `vld1.8 {q0},\[r0:256\]' +[^:]*:1: Error: bad alignment -- `vld1.8 {d0},\[r0 ?:128\]' +[^:]*:2: Error: bad alignment -- `vld1.8 {q0},\[r0 ?:256\]' --- a/gas/testsuite/gas/arm/shift-bad.l +++ b/gas/testsuite/gas/arm/shift-bad.l @@ -1,9 +1,9 @@ .*shift-bad.s: Assembler messages: -.*shift-bad.s:2: Error: extraneous shift as part of operand to shift insn -- `asr r0,r1,r2,ror#5' +.*shift-bad.s:2: Error: extraneous shift as part of operand to shift insn -- `asr r0,r1,r2,ror ?#5' .*shift-bad.s:3: Error: extraneous shift as part of operand to shift insn -- `ror r0,r1,r2,lsl r3' -.*shift-bad.s:7: Error: extraneous shift as part of operand to shift insn -- `ror r0,r0,r2,lsl#1' -.*shift-bad.s:8: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r0,r2,lsl#1' +.*shift-bad.s:7: Error: extraneous shift as part of operand to shift insn -- `ror r0,r0,r2,lsl ?#1' +.*shift-bad.s:8: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r0,r2,lsl ?#1' .*shift-bad.s:9: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r0,r2,asr r0' -.*shift-bad.s:13: Error: extraneous shift as part of operand to shift insn -- `ror r0,r1,r2,lsl#1' -.*shift-bad.s:14: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r1,r2,lsl#1' +.*shift-bad.s:13: Error: extraneous shift as part of operand to shift insn -- `ror r0,r1,r2,lsl ?#1' +.*shift-bad.s:14: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r1,r2,lsl ?#1' .*shift-bad.s:15: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r1,r2,asr r0' --- a/gas/testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l +++ b/gas/testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l @@ -131,7 +131,7 @@ [^:]*:12: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R [^:]*:21: *Info: macro .* [^:]*:45: *Info: macro .* -[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]' +[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL ?#2\]' [^:]*:21: *Info: macro .* [^:]*:45: *Info: macro .* [^:]*:48: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]' @@ -144,8 +144,8 @@ [^:]*:66: Error: r15 not allowed here -- `ldrb pc,\[r0,r1\]' [^:]*:67: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc,r1\]' [^:]*:68: Error: r15 not allowed here -- `ldrb r0,\[r1,pc\]' -[^:]*:69: Error: r15 not allowed here -- `ldrb.w pc,\[r0,r1,LSL#1\]' -[^:]*:71: Error: r15 not allowed here -- `ldrb.w r2,\[r0,pc,LSL#2\]' +[^:]*:69: Error: r15 not allowed here -- `ldrb.w pc,\[r0,r1,LSL ?#1\]' +[^:]*:71: Error: r15 not allowed here -- `ldrb.w r2,\[r0,pc,LSL ?#2\]' [^:]*:75: Error: r15 not allowed here -- `ldrbt pc,\[r0,#4\]' [^:]*:79: Error: r15 not allowed here -- `ldrd pc,r0,\[r1\]' [^:]*:81: Error: r12 not allowed here -- `ldrd r12,\[r1\]' @@ -184,8 +184,8 @@ [^:]*:149: Error: r15 not allowed here -- `ldrh pc,\[r0,r1\]' [^:]*:150: Error: cannot use register index with PC-relative addressing -- `ldrh r0,\[pc,r1\]' [^:]*:151: Error: r15 not allowed here -- `ldrh r0,\[r1,pc\]' -[^:]*:152: Error: r15 not allowed here -- `ldrh.w pc,\[r0,r1,LSL#1\]' -[^:]*:154: Error: r15 not allowed here -- `ldrh.w r2,\[r0,pc,LSL#1\]' +[^:]*:152: Error: r15 not allowed here -- `ldrh.w pc,\[r0,r1,LSL ?#1\]' +[^:]*:154: Error: r15 not allowed here -- `ldrh.w r2,\[r0,pc,LSL ?#1\]' [^:]*:158: Error: r15 not allowed here -- `ldrht pc,\[r0,#4\]' [^:]*:162: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]' [^:]*:165: Error: r15 not allowed here -- `ldrsb pc,\[r0,#-4\]' @@ -196,8 +196,8 @@ [^:]*:179: Error: r15 not allowed here -- `ldrsb pc,\[r0,r1\]' [^:]*:180: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[pc,r1\]' [^:]*:181: Error: r15 not allowed here -- `ldrsb r0,\[r1,pc\]' -[^:]*:182: Error: r15 not allowed here -- `ldrsb.w pc,\[r0,r1,LSL#2\]' -[^:]*:185: Error: r15 not allowed here -- `ldrsb.w r2,\[r0,pc,LSL#2\]' +[^:]*:182: Error: r15 not allowed here -- `ldrsb.w pc,\[r0,r1,LSL ?#2\]' +[^:]*:185: Error: r15 not allowed here -- `ldrsb.w r2,\[r0,pc,LSL ?#2\]' [^:]*:190: Error: r15 not allowed here -- `ldrsbt pc,\[r0,#4\]' [^:]*:195: Error: r15 not allowed here -- `ldrsh pc,\[r0,#4\]' [^:]*:197: Error: r15 not allowed here -- `ldrsh pc,\[r0,#-4\]' @@ -207,8 +207,8 @@ [^:]*:210: Error: r15 not allowed here -- `ldrsh pc,\[r0,r1\]' [^:]*:211: Error: cannot use register index with PC-relative addressing -- `ldrsh r0,\[pc,r1\]' [^:]*:212: Error: r15 not allowed here -- `ldrsh r0,\[r1,pc\]' -[^:]*:214: Error: r15 not allowed here -- `ldrsh.w pc,\[r0,r1,LSL#3\]' -[^:]*:217: Error: r15 not allowed here -- `ldrsh.w r0,\[r1,pc,LSL#3\]' +[^:]*:214: Error: r15 not allowed here -- `ldrsh.w pc,\[r0,r1,LSL ?#3\]' +[^:]*:217: Error: r15 not allowed here -- `ldrsh.w r0,\[r1,pc,LSL ?#3\]' [^:]*:221: Error: r15 not allowed here -- `ldrsht pc,\[r0,#4\]' [^:]*:226: Error: r15 not allowed here -- `ldrt pc,\[r0,#4\]' [^:]*:232: Error: r15 not allowed here -- `str pc,\[r0,#4\]' @@ -217,7 +217,7 @@ [^:]*:235: Error: cannot use post-indexing with PC-relative addressing -- `str r0,\[pc\],#4' [^:]*:236: Error: cannot use writeback with PC-relative addressing -- `str r0,\[pc,#4\]!' [^:]*:239: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1\]' -[^:]*:240: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1,LSL#2\]' +[^:]*:240: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1,LSL ?#2\]' [^:]*:246: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,#4\]' [^:]*:247: Error: r15 not allowed here -- `strb.w pc,\[r0,#4\]' [^:]*:249: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc,#-4\]' @@ -227,11 +227,11 @@ [^:]*:253: Error: r15 not allowed here -- `strb pc,\[r0\],#4' [^:]*:254: Error: r15 not allowed here -- `strb pc,\[r0,#4\]!' [^:]*:260: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1\]' -[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1,LSL#2\]' +[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1,LSL ?#2\]' [^:]*:262: Error: r15 not allowed here -- `strb.w pc,\[r0,r1\]' -[^:]*:263: Error: r15 not allowed here -- `strb.w pc,\[r0,r1,LSL#2\]' +[^:]*:263: Error: r15 not allowed here -- `strb.w pc,\[r0,r1,LSL ?#2\]' [^:]*:266: Error: r15 not allowed here -- `strb.w r0,\[r1,pc\]' -[^:]*:267: Error: r15 not allowed here -- `strb.w r0,\[r1,pc,LSL#2\]' +[^:]*:267: Error: r15 not allowed here -- `strb.w r0,\[r1,pc,LSL ?#2\]' [^:]*:272: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc,#4\]' [^:]*:273: Error: r15 not allowed here -- `strbt pc,\[r0,#4\]' [^:]*:277: Error: cannot use register index with PC-relative addressing -- `strd r0,r1,\[pc,#4\]' @@ -265,7 +265,7 @@ [^:]*:335: Error: cannot use post-indexing with PC-relative addressing -- `strh r0,\[pc\],#4' [^:]*:336: Error: cannot use writeback with PC-relative addressing -- `strh r0,\[pc,#4\]!' [^:]*:339: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1\]' -[^:]*:340: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1,LSL#2\]' +[^:]*:340: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1,LSL ?#2\]' [^:]*:341: Error: r15 not allowed here -- `strh.w pc,\[r0,#4\]' [^:]*:342: Error: r15 not allowed here -- `strh.w pc,\[r0\]' [^:]*:345: Error: r15 not allowed here -- `strh pc,\[r0,#-4\]' @@ -273,8 +273,8 @@ [^:]*:347: Error: r15 not allowed here -- `strh pc,\[r0,#4\]!' [^:]*:351: Error: r15 not allowed here -- `strh.w pc,\[r0,r1\]' [^:]*:353: Error: r15 not allowed here -- `strh.w r0,\[r1,pc\]' -[^:]*:355: Error: r15 not allowed here -- `strh.w pc,\[r0,r1,LSL#2\]' -[^:]*:357: Error: r15 not allowed here -- `strh.w r0,\[r1,pc,LSL#2\]' +[^:]*:355: Error: r15 not allowed here -- `strh.w pc,\[r0,r1,LSL ?#2\]' +[^:]*:357: Error: r15 not allowed here -- `strh.w r0,\[r1,pc,LSL ?#2\]' [^:]*:361: Error: cannot use register index with PC-relative addressing -- `strht r0,\[pc,#4\]' [^:]*:362: Error: r15 not allowed here -- `strht pc,\[r0,#4\]' [^:]*:363: Error: cannot use register index with PC-relative addressing -- `strht sp,\[pc,#4\]' --- a/gas/testsuite/gas/arm/sp-pc-validations-bad-t.l +++ b/gas/testsuite/gas/arm/sp-pc-validations-bad-t.l @@ -41,7 +41,7 @@ [^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1\]' [^:]*:21: *Info: macro .* [^:]*:44: *Info: macro .* -[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]' +[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL ?#2\]' [^:]*:21: *Info: macro .* [^:]*:45: *Info: macro .* [^:]*:48: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]' @@ -59,10 +59,10 @@ [^:]*:66: Error: r15 not allowed here -- `ldrb pc,\[r0,r1\]' [^:]*:67: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc,r1\]' [^:]*:68: Error: r15 not allowed here -- `ldrb r0,\[r1,pc\]' -[^:]*:69: Error: r15 not allowed here -- `ldrb.w pc,\[r0,r1,LSL#1\]' +[^:]*:69: Error: r15 not allowed here -- `ldrb.w pc,\[r0,r1,LSL ?#1\]' [^:]*:70: Error: r13 not allowed here -- `ldrb.w sp,\[r0,r1\]' -[^:]*:71: Error: r15 not allowed here -- `ldrb.w r2,\[r0,pc,LSL#2\]' -[^:]*:72: Error: r13 not allowed here -- `ldrb.w r2,\[r0,sp,LSL#2\]' +[^:]*:71: Error: r15 not allowed here -- `ldrb.w r2,\[r0,pc,LSL ?#2\]' +[^:]*:72: Error: r13 not allowed here -- `ldrb.w r2,\[r0,sp,LSL ?#2\]' [^:]*:75: Error: r15 not allowed here -- `ldrbt pc,\[r0,#4\]' [^:]*:76: Error: r13 not allowed here -- `ldrbt sp,\[r0,#4\]' [^:]*:79: Error: r15 not allowed here -- `ldrd pc,r0,\[r1\]' @@ -123,10 +123,10 @@ [^:]*:149: Error: r15 not allowed here -- `ldrh pc,\[r0,r1\]' [^:]*:150: Error: cannot use register index with PC-relative addressing -- `ldrh r0,\[pc,r1\]' [^:]*:151: Error: r15 not allowed here -- `ldrh r0,\[r1,pc\]' -[^:]*:152: Error: r15 not allowed here -- `ldrh.w pc,\[r0,r1,LSL#1\]' -[^:]*:153: Error: r13 not allowed here -- `ldrh.w sp,\[r0,r1,LSL#1\]' -[^:]*:154: Error: r15 not allowed here -- `ldrh.w r2,\[r0,pc,LSL#1\]' -[^:]*:155: Error: r13 not allowed here -- `ldrh.w r2,\[r0,sp,LSL#1\]' +[^:]*:152: Error: r15 not allowed here -- `ldrh.w pc,\[r0,r1,LSL ?#1\]' +[^:]*:153: Error: r13 not allowed here -- `ldrh.w sp,\[r0,r1,LSL ?#1\]' +[^:]*:154: Error: r15 not allowed here -- `ldrh.w r2,\[r0,pc,LSL ?#1\]' +[^:]*:155: Error: r13 not allowed here -- `ldrh.w r2,\[r0,sp,LSL ?#1\]' [^:]*:158: Error: r15 not allowed here -- `ldrht pc,\[r0,#4\]' [^:]*:159: Error: r13 not allowed here -- `ldrht sp,\[r0,#4\]' [^:]*:162: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]' @@ -144,10 +144,10 @@ [^:]*:179: Error: r15 not allowed here -- `ldrsb pc,\[r0,r1\]' [^:]*:180: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[pc,r1\]' [^:]*:181: Error: r15 not allowed here -- `ldrsb r0,\[r1,pc\]' -[^:]*:182: Error: r15 not allowed here -- `ldrsb.w pc,\[r0,r1,LSL#2\]' -[^:]*:184: Error: r13 not allowed here -- `ldrsb.w sp,\[r0,r1,LSL#2\]' -[^:]*:185: Error: r15 not allowed here -- `ldrsb.w r2,\[r0,pc,LSL#2\]' -[^:]*:186: Error: r13 not allowed here -- `ldrsb.w r2,\[r0,sp,LSL#2\]' +[^:]*:182: Error: r15 not allowed here -- `ldrsb.w pc,\[r0,r1,LSL ?#2\]' +[^:]*:184: Error: r13 not allowed here -- `ldrsb.w sp,\[r0,r1,LSL ?#2\]' +[^:]*:185: Error: r15 not allowed here -- `ldrsb.w r2,\[r0,pc,LSL ?#2\]' +[^:]*:186: Error: r13 not allowed here -- `ldrsb.w r2,\[r0,sp,LSL ?#2\]' [^:]*:190: Error: r15 not allowed here -- `ldrsbt pc,\[r0,#4\]' [^:]*:191: Error: r13 not allowed here -- `ldrsbt sp,\[r0,#4\]' [^:]*:195: Error: r15 not allowed here -- `ldrsh pc,\[r0,#4\]' @@ -164,10 +164,10 @@ [^:]*:210: Error: r15 not allowed here -- `ldrsh pc,\[r0,r1\]' [^:]*:211: Error: cannot use register index with PC-relative addressing -- `ldrsh r0,\[pc,r1\]' [^:]*:212: Error: r15 not allowed here -- `ldrsh r0,\[r1,pc\]' -[^:]*:214: Error: r15 not allowed here -- `ldrsh.w pc,\[r0,r1,LSL#3\]' -[^:]*:215: Error: r13 not allowed here -- `ldrsh.w sp,\[r0,r1,LSL#3\]' -[^:]*:216: Error: r13 not allowed here -- `ldrsh.w r0,\[r1,sp,LSL#3\]' -[^:]*:217: Error: r15 not allowed here -- `ldrsh.w r0,\[r1,pc,LSL#3\]' +[^:]*:214: Error: r15 not allowed here -- `ldrsh.w pc,\[r0,r1,LSL ?#3\]' +[^:]*:215: Error: r13 not allowed here -- `ldrsh.w sp,\[r0,r1,LSL ?#3\]' +[^:]*:216: Error: r13 not allowed here -- `ldrsh.w r0,\[r1,sp,LSL ?#3\]' +[^:]*:217: Error: r15 not allowed here -- `ldrsh.w r0,\[r1,pc,LSL ?#3\]' [^:]*:221: Error: r15 not allowed here -- `ldrsht pc,\[r0,#4\]' [^:]*:222: Error: r13 not allowed here -- `ldrsht sp,\[r0,#4\]' [^:]*:226: Error: r15 not allowed here -- `ldrt pc,\[r0,#4\]' @@ -178,7 +178,7 @@ [^:]*:235: Error: cannot use post-indexing with PC-relative addressing -- `str r0,\[pc\],#4' [^:]*:236: Error: cannot use writeback with PC-relative addressing -- `str r0,\[pc,#4\]!' [^:]*:239: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1\]' -[^:]*:240: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1,LSL#2\]' +[^:]*:240: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1,LSL ?#2\]' [^:]*:246: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,#4\]' [^:]*:247: Error: r15 not allowed here -- `strb.w pc,\[r0,#4\]' [^:]*:248: Error: r13 not allowed here -- `strb.w sp,\[r0,#4\]' @@ -192,15 +192,15 @@ [^:]*:256: Error: r13 not allowed here -- `strb sp,\[r0\],#4' [^:]*:257: Error: r13 not allowed here -- `strb sp,\[r0,#4\]!' [^:]*:260: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1\]' -[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1,LSL#2\]' +[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1,LSL ?#2\]' [^:]*:262: Error: r15 not allowed here -- `strb.w pc,\[r0,r1\]' -[^:]*:263: Error: r15 not allowed here -- `strb.w pc,\[r0,r1,LSL#2\]' +[^:]*:263: Error: r15 not allowed here -- `strb.w pc,\[r0,r1,LSL ?#2\]' [^:]*:264: Error: r13 not allowed here -- `strb.w sp,\[r0,r1\]' -[^:]*:265: Error: r13 not allowed here -- `strb.w sp,\[r0,r1,LSL#2\]' +[^:]*:265: Error: r13 not allowed here -- `strb.w sp,\[r0,r1,LSL ?#2\]' [^:]*:266: Error: r15 not allowed here -- `strb.w r0,\[r1,pc\]' -[^:]*:267: Error: r15 not allowed here -- `strb.w r0,\[r1,pc,LSL#2\]' +[^:]*:267: Error: r15 not allowed here -- `strb.w r0,\[r1,pc,LSL ?#2\]' [^:]*:268: Error: r13 not allowed here -- `strb.w r0,\[r1,sp\]' -[^:]*:269: Error: r13 not allowed here -- `strb.w r0,\[r1,sp,LSL#2\]' +[^:]*:269: Error: r13 not allowed here -- `strb.w r0,\[r1,sp,LSL ?#2\]' [^:]*:272: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc,#4\]' [^:]*:273: Error: r15 not allowed here -- `strbt pc,\[r0,#4\]' [^:]*:274: Error: r13 not allowed here -- `strbt sp,\[r0,#4\]' @@ -252,7 +252,7 @@ [^:]*:335: Error: cannot use post-indexing with PC-relative addressing -- `strh r0,\[pc\],#4' [^:]*:336: Error: cannot use writeback with PC-relative addressing -- `strh r0,\[pc,#4\]!' [^:]*:339: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1\]' -[^:]*:340: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1,LSL#2\]' +[^:]*:340: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1,LSL ?#2\]' [^:]*:341: Error: r15 not allowed here -- `strh.w pc,\[r0,#4\]' [^:]*:342: Error: r15 not allowed here -- `strh.w pc,\[r0\]' [^:]*:343: Error: r13 not allowed here -- `strh.w sp,\[r0,#4\]' @@ -267,10 +267,10 @@ [^:]*:352: Error: r13 not allowed here -- `strh.w sp,\[r0,r1\]' [^:]*:353: Error: r15 not allowed here -- `strh.w r0,\[r1,pc\]' [^:]*:354: Error: r13 not allowed here -- `strh.w r0,\[r1,sp\]' -[^:]*:355: Error: r15 not allowed here -- `strh.w pc,\[r0,r1,LSL#2\]' -[^:]*:356: Error: r13 not allowed here -- `strh.w sp,\[r0,r1,LSL#2\]' -[^:]*:357: Error: r15 not allowed here -- `strh.w r0,\[r1,pc,LSL#2\]' -[^:]*:358: Error: r13 not allowed here -- `strh.w r0,\[r1,sp,LSL#2\]' +[^:]*:355: Error: r15 not allowed here -- `strh.w pc,\[r0,r1,LSL ?#2\]' +[^:]*:356: Error: r13 not allowed here -- `strh.w sp,\[r0,r1,LSL ?#2\]' +[^:]*:357: Error: r15 not allowed here -- `strh.w r0,\[r1,pc,LSL ?#2\]' +[^:]*:358: Error: r13 not allowed here -- `strh.w r0,\[r1,sp,LSL ?#2\]' [^:]*:361: Error: cannot use register index with PC-relative addressing -- `strht r0,\[pc,#4\]' [^:]*:362: Error: r15 not allowed here -- `strht pc,\[r0,#4\]' [^:]*:363: Error: r13 not allowed here -- `strht sp,\[pc,#4\]' --- a/gas/testsuite/gas/arm/sp-pc-validations-bad.l +++ b/gas/testsuite/gas/arm/sp-pc-validations-bad.l @@ -1,27 +1,27 @@ [^:]*: Assembler messages: -[^:]*:11: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1,pc,LSL#2\]' -[^:]*:12: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1,pc,LSL#2\]!' -[^:]*:13: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1\],pc,LSL#2' -[^:]*:14: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[pc,r1,LSL#2\]!' -[^:]*:15: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[pc\],r1,LSL#2' +[^:]*:11: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1,pc,LSL ?#2\]' +[^:]*:12: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1,pc,LSL ?#2\]!' +[^:]*:13: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1\],pc,LSL ?#2' +[^:]*:14: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[pc,r1,LSL ?#2\]!' +[^:]*:15: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[pc\],r1,LSL ?#2' [^:]*:18: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]' [^:]*:19: Error: r15 not allowed here -- `ldrb pc,\[r0\],#4' [^:]*:20: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]!' [^:]*:23: Error: r15 not allowed here -- `ldrb pc,label' [^:]*:24: Error: r15 not allowed here -- `ldrb pc,\[pc,#-0\]' -[^:]*:27: Error: r15 not allowed here -- `ldrb pc,\[r0,r1,LSL#2\]' -[^:]*:28: Error: r15 not allowed here -- `ldrb pc,\[r0,r1,LSL#2\]!' -[^:]*:29: Error: r15 not allowed here -- `ldrb pc,\[r0\],r1,LSL#2' -[^:]*:30: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1,pc,LSL#2\]' -[^:]*:31: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1,pc,LSL#2\]!' -[^:]*:32: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1\],pc,LSL#2' -[^:]*:33: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc,r1,LSL#2\]!' -[^:]*:34: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc\],r1,LSL#2' +[^:]*:27: Error: r15 not allowed here -- `ldrb pc,\[r0,r1,LSL ?#2\]' +[^:]*:28: Error: r15 not allowed here -- `ldrb pc,\[r0,r1,LSL ?#2\]!' +[^:]*:29: Error: r15 not allowed here -- `ldrb pc,\[r0\],r1,LSL ?#2' +[^:]*:30: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1,pc,LSL ?#2\]' +[^:]*:31: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1,pc,LSL ?#2\]!' +[^:]*:32: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1\],pc,LSL ?#2' +[^:]*:33: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc,r1,LSL ?#2\]!' +[^:]*:34: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc\],r1,LSL ?#2' [^:]*:37: Error: r15 not allowed here -- `ldrbt pc,\[r0\],#4' [^:]*:38: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[pc\],#4' -[^:]*:39: Error: r15 not allowed here -- `ldrbt pc,\[r0\],r1,LSL#4' -[^:]*:40: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[pc\],r1,LSL#4' -[^:]*:41: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[r1\],pc,LSL#4' +[^:]*:39: Error: r15 not allowed here -- `ldrbt pc,\[r0\],r1,LSL ?#4' +[^:]*:40: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[pc\],r1,LSL ?#4' +[^:]*:41: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[r1\],pc,LSL ?#4' [^:]*:44: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,#4\]' [^:]*:45: Error: r15 not allowed here -- `ldrd r0,pc,\[r1\],#4' [^:]*:46: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,#4\]!' @@ -98,32 +98,32 @@ [^:]*:153: Error: cannot use register index with PC-relative addressing -- `ldrsht r0,\[r1\],pc' [^:]*:156: Error: r15 not allowed here -- `ldrt pc,\[r0\],#4' [^:]*:157: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],#4' -[^:]*:158: Error: r15 not allowed here -- `ldrt pc,\[r0\],r1,LSL#4' -[^:]*:159: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],r1,LSL#4' -[^:]*:160: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[r1\],pc,LSL#4' +[^:]*:158: Error: r15 not allowed here -- `ldrt pc,\[r0\],r1,LSL ?#4' +[^:]*:159: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],r1,LSL ?#4' +[^:]*:160: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[r1\],pc,LSL ?#4' [^:]*:166: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc\],#4' [^:]*:167: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,#4\]!' -[^:]*:170: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL#4\]' -[^:]*:171: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL#4\]!' -[^:]*:172: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1\],pc,LSL#4' +[^:]*:170: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL ?#4\]' +[^:]*:171: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL ?#4\]!' +[^:]*:172: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1\],pc,LSL ?#4' [^:]*:175: Error: r15 not allowed here -- `strb pc,\[r0,#4\]' [^:]*:176: Error: r15 not allowed here -- `strb pc,\[r0\],#4' [^:]*:177: Error: r15 not allowed here -- `strb pc,\[r0,#4\]!' [^:]*:178: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc\],#4' [^:]*:179: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc,#4\]!' -[^:]*:182: Error: r15 not allowed here -- `strb pc,\[r0,r1,LSL#4\]' -[^:]*:183: Error: r15 not allowed here -- `strb pc,\[r0,r1,LSL#4\]!' -[^:]*:184: Error: r15 not allowed here -- `strb pc,\[r0\],r1,LSL#4' -[^:]*:185: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0,pc,LSL#4\]' -[^:]*:186: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0,pc,LSL#4\]!' -[^:]*:187: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0\],pc,LSL#4' -[^:]*:188: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc,r1,LSL#4\]!' -[^:]*:189: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc\],r1,LSL#4' +[^:]*:182: Error: r15 not allowed here -- `strb pc,\[r0,r1,LSL ?#4\]' +[^:]*:183: Error: r15 not allowed here -- `strb pc,\[r0,r1,LSL ?#4\]!' +[^:]*:184: Error: r15 not allowed here -- `strb pc,\[r0\],r1,LSL ?#4' +[^:]*:185: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0,pc,LSL ?#4\]' +[^:]*:186: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0,pc,LSL ?#4\]!' +[^:]*:187: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0\],pc,LSL ?#4' +[^:]*:188: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc,r1,LSL ?#4\]!' +[^:]*:189: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc\],r1,LSL ?#4' [^:]*:192: Error: r15 not allowed here -- `strbt pc,\[r0\],#4' [^:]*:193: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc\],#4' -[^:]*:194: Error: r15 not allowed here -- `strbt pc,\[r0\],r1,LSL#4' -[^:]*:195: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc\],r1,LSL#4' -[^:]*:196: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[r1\],pc,LSL#4' +[^:]*:194: Error: r15 not allowed here -- `strbt pc,\[r0\],r1,LSL ?#4' +[^:]*:195: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc\],r1,LSL ?#4' +[^:]*:196: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[r1\],pc,LSL ?#4' [^:]*:199: Error: r15 not allowed here -- `strd r0,pc,\[r1,#4\]' [^:]*:200: Error: r15 not allowed here -- `strd r0,pc,\[r1\],#4' [^:]*:201: Error: r15 not allowed here -- `strd r0,pc,\[r1,#4\]!' @@ -167,5 +167,5 @@ [^:]*:255: Error: cannot use register index with PC-relative addressing -- `strht r0,\[pc\],r1' [^:]*:256: Error: cannot use register index with PC-relative addressing -- `strht r0,\[r1\],pc' [^:]*:259: Error: cannot use register index with PC-relative addressing -- `strt r0,\[pc\],#4' -[^:]*:260: Error: cannot use register index with PC-relative addressing -- `strt r0,\[pc\],r1,LSL#4' -[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strt r0,\[r1\],pc,LSL#4' +[^:]*:260: Error: cannot use register index with PC-relative addressing -- `strt r0,\[pc\],r1,LSL ?#4' +[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strt r0,\[r1\],pc,LSL ?#4' --- a/gas/testsuite/gas/arm/t16-bad.l +++ b/gas/testsuite/gas/arm/t16-bad.l @@ -7,7 +7,7 @@ [^:]*:36: *Info: macro .* [^:]*:16: Error: unshifted register required -- `tst r0,#12' [^:]*:36: *Info: macro .* -[^:]*:17: Error: unshifted register required -- `tst r0,r1,lsl#2' +[^:]*:17: Error: unshifted register required -- `tst r0,r1,lsl ?#2' [^:]*:36: *Info: macro .* [^:]*:18: Error: unshifted register required -- `tst r0,r1,lsl r3' [^:]*:36: *Info: macro .* @@ -19,7 +19,7 @@ [^:]*:37: *Info: macro .* [^:]*:16: Error: unshifted register required -- `cmn r0,#12' [^:]*:37: *Info: macro .* -[^:]*:17: Error: unshifted register required -- `cmn r0,r1,lsl#2' +[^:]*:17: Error: unshifted register required -- `cmn r0,r1,lsl ?#2' [^:]*:37: *Info: macro .* [^:]*:18: Error: unshifted register required -- `cmn r0,r1,lsl r3' [^:]*:37: *Info: macro .* @@ -31,7 +31,7 @@ [^:]*:38: *Info: macro .* [^:]*:16: Error: unshifted register required -- `mvn r0,#12' [^:]*:38: *Info: macro .* -[^:]*:17: Error: unshifted register required -- `mvn r0,r1,lsl#2' +[^:]*:17: Error: unshifted register required -- `mvn r0,r1,lsl ?#2' [^:]*:38: *Info: macro .* [^:]*:18: Error: unshifted register required -- `mvn r0,r1,lsl r3' [^:]*:38: *Info: macro .* @@ -57,7 +57,7 @@ [^:]*:12: Error: lo register required -- `sxtb r0,r8' [^:]*:21: *Info: macro .* [^:]*:43: *Info: macro .* -[^:]*:22: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror#8' +[^:]*:22: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror ?#8' [^:]*:43: *Info: macro .* [^:]*:11: Error: lo register required -- `sxth r8,r0' [^:]*:21: *Info: macro .* @@ -65,7 +65,7 @@ [^:]*:12: Error: lo register required -- `sxth r0,r8' [^:]*:21: *Info: macro .* [^:]*:44: *Info: macro .* -[^:]*:22: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror#8' +[^:]*:22: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror ?#8' [^:]*:44: *Info: macro .* [^:]*:11: Error: lo register required -- `uxtb r8,r0' [^:]*:21: *Info: macro .* @@ -73,7 +73,7 @@ [^:]*:12: Error: lo register required -- `uxtb r0,r8' [^:]*:21: *Info: macro .* [^:]*:45: *Info: macro .* -[^:]*:22: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror#8' +[^:]*:22: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror ?#8' [^:]*:45: *Info: macro .* [^:]*:11: Error: lo register required -- `uxth r8,r0' [^:]*:21: *Info: macro .* @@ -81,7 +81,7 @@ [^:]*:12: Error: lo register required -- `uxth r0,r8' [^:]*:21: *Info: macro .* [^:]*:46: *Info: macro .* -[^:]*:22: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror#8' +[^:]*:22: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror ?#8' [^:]*:46: *Info: macro .* [^:]*:25: Error: dest must overlap one source register -- `adc r1,r2,r3' [^:]*:30: *Info: macro .* @@ -94,7 +94,7 @@ [^:]*:48: *Info: macro .* [^:]*:31: Error: unshifted register required -- `adc r0,#12' [^:]*:48: *Info: macro .* -[^:]*:32: Error: unshifted register required -- `adc r0,r1,lsl#2' +[^:]*:32: Error: unshifted register required -- `adc r0,r1,lsl ?#2' [^:]*:48: *Info: macro .* [^:]*:33: Error: unshifted register required -- `adc r0,r1,lsl r3' [^:]*:48: *Info: macro .* @@ -109,7 +109,7 @@ [^:]*:49: *Info: macro .* [^:]*:31: Error: unshifted register required -- `and r0,#12' [^:]*:49: *Info: macro .* -[^:]*:32: Error: unshifted register required -- `and r0,r1,lsl#2' +[^:]*:32: Error: unshifted register required -- `and r0,r1,lsl ?#2' [^:]*:49: *Info: macro .* [^:]*:33: Error: unshifted register required -- `and r0,r1,lsl r3' [^:]*:49: *Info: macro .* @@ -124,7 +124,7 @@ [^:]*:50: *Info: macro .* [^:]*:31: Error: unshifted register required -- `bic r0,#12' [^:]*:50: *Info: macro .* -[^:]*:32: Error: unshifted register required -- `bic r0,r1,lsl#2' +[^:]*:32: Error: unshifted register required -- `bic r0,r1,lsl ?#2' [^:]*:50: *Info: macro .* [^:]*:33: Error: unshifted register required -- `bic r0,r1,lsl r3' [^:]*:50: *Info: macro .* @@ -139,7 +139,7 @@ [^:]*:51: *Info: macro .* [^:]*:31: Error: unshifted register required -- `eor r0,#12' [^:]*:51: *Info: macro .* -[^:]*:32: Error: unshifted register required -- `eor r0,r1,lsl#2' +[^:]*:32: Error: unshifted register required -- `eor r0,r1,lsl ?#2' [^:]*:51: *Info: macro .* [^:]*:33: Error: unshifted register required -- `eor r0,r1,lsl r3' [^:]*:51: *Info: macro .* @@ -154,7 +154,7 @@ [^:]*:52: *Info: macro .* [^:]*:31: Error: unshifted register required -- `orr r0,#12' [^:]*:52: *Info: macro .* -[^:]*:32: Error: unshifted register required -- `orr r0,r1,lsl#2' +[^:]*:32: Error: unshifted register required -- `orr r0,r1,lsl ?#2' [^:]*:52: *Info: macro .* [^:]*:33: Error: unshifted register required -- `orr r0,r1,lsl r3' [^:]*:52: *Info: macro .* @@ -169,7 +169,7 @@ [^:]*:53: *Info: macro .* [^:]*:31: Error: unshifted register required -- `sbc r0,#12' [^:]*:53: *Info: macro .* -[^:]*:32: Error: unshifted register required -- `sbc r0,r1,lsl#2' +[^:]*:32: Error: unshifted register required -- `sbc r0,r1,lsl ?#2' [^:]*:53: *Info: macro .* [^:]*:33: Error: unshifted register required -- `sbc r0,r1,lsl r3' [^:]*:53: *Info: macro .* @@ -220,7 +220,7 @@ [^:]*:60: *Info: macro .* [^:]*:65: *Info: macro .* [^:]*:66: Error: ror #imm not supported -- `ror r0,r1,#12' -[^:]*:69: Error: unshifted register required -- `add r0,r1,lsl#2' +[^:]*:69: Error: unshifted register required -- `add r0,r1,lsl ?#2' [^:]*:70: Error: unshifted register required -- `add r0,r1,lsl r3' [^:]*:71: Error: lo register required -- `add r8,r0,#1' [^:]*:72: Error: lo register required -- `add r0,r8,#1' @@ -236,7 +236,7 @@ [^:]*:27: Error: lo register required -- `sub r0,r8' [^:]*:30: *Info: macro .* [^:]*:80: *Info: macro .* -[^:]*:32: Error: unshifted register required -- `sub r0,r1,lsl#2' +[^:]*:32: Error: unshifted register required -- `sub r0,r1,lsl ?#2' [^:]*:80: *Info: macro .* [^:]*:33: Error: unshifted register required -- `sub r0,r1,lsl r3' [^:]*:80: *Info: macro .* @@ -246,10 +246,10 @@ [^:]*:84: Error: lo register required -- `sub r8,r1,r2' [^:]*:85: Error: lo register required -- `sub r1,r8,r2' [^:]*:86: Error: lo register required -- `sub r1,r2,r8' -[^:]*:88: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `cmp r0,r1,lsl#2' +[^:]*:88: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `cmp r0,r1,lsl ?#2' [^:]*:89: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `cmp r0,r1,lsl r3' [^:]*:90: Error: only lo regs allowed with immediate -- `cmp r8,#255' -[^:]*:92: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `mov r0,r1,lsl#2' +[^:]*:92: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `mov r0,r1,lsl ?#2' [^:]*:93: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `mov r0,r1,lsl r3' [^:]*:94: Error: only lo regs allowed with immediate -- `mov r8,#255' [^:]*:98: Error: lo register required -- `ldr r8,\[r0\]' @@ -364,8 +364,8 @@ [^:]*:113: *Info: macro .* [^:]*:104: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],r2' [^:]*:113: *Info: macro .* -[^:]*:115: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,r2,lsl#1\]' -[^:]*:116: Error: Thumb does not support this addressing mode -- `str r0,\[r1,r2,lsl#1\]' +[^:]*:115: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,r2,lsl ?#1\]' +[^:]*:116: Error: Thumb does not support this addressing mode -- `str r0,\[r1,r2,lsl ?#1\]' [^:]*:119: Error: lo register required -- `ldmia r8!,{r1,r2}' [^:]*:120: Error: lo register required -- `ldmia r7!,{r8}' [^:]*:121: Warning: this instruction will write back the base register --- a/gas/testsuite/gas/arm/thumb2_bad_reg.l +++ b/gas/testsuite/gas/arm/thumb2_bad_reg.l @@ -514,7 +514,7 @@ [^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r15,#1,r0' [^:]*:[0-9]+: Error: r13 not allowed here -- `ssat r0,#1,r13' [^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r0,#1,r15' -[^:]*:[0-9]+: Error: shift expression is too large -- `ssat r1,#1,r3,asr#32' +[^:]*:[0-9]+: Error: shift expression is too large -- `ssat r1,#1,r3,asr ?#32' [^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r13,#1,r0' [^:]*:[0-9]+: Error: r15 not allowed here -- `ssat16 r15,#1,r0' [^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r0,#1,r13' @@ -742,7 +742,7 @@ [^:]*:[0-9]+: Error: r15 not allowed here -- `usat r15,#1,r0' [^:]*:[0-9]+: Error: r13 not allowed here -- `usat r0,#1,r13' [^:]*:[0-9]+: Error: r15 not allowed here -- `usat r0,#1,r15' -[^:]*:[0-9]+: Error: shift expression is too large -- `usat r1,#1,r3,asr#32' +[^:]*:[0-9]+: Error: shift expression is too large -- `usat r1,#1,r3,asr ?#32' [^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r13,#1,r0' [^:]*:[0-9]+: Error: r15 not allowed here -- `usat16 r15,#1,r0' [^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r0,#1,r13' From patchwork Wed Jul 31 12:00:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 94864 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3F06D385ED40 for ; Wed, 31 Jul 2024 12:00:55 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 39569385EC2A for ; Wed, 31 Jul 2024 12:00:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acab23828sm773732666b.19.2024.07.31.05.00.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 05:00:10 -0700 (PDT) Message-ID: <48e62df0-df6b-452c-bd6e-384bac326f87@suse.com> Date: Wed, 31 Jul 2024 14:00:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 7/9] MIPS: relax gas testsuite whitespace expectations From: Jan Beulich To: Binutils Cc: "Maciej W. Rozycki" , Chenghua Xu References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3023.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org In a subsequent change the scrubber is going to be changed to retain further whitespace. Test case expectations generally would better not depend on the specific whitespace treatment by the scrubber, unless of course a test is specifically about it. Adjust relevant test cases to permit blanks where those will subsequently appear. Reviewed-by: Maciej W. Rozycki --- This is adding just the blanks that are going to be needed; imo it would generally be better if test case expectations were, from the very beginning, written to focus on what is being tested, rather than taking verbatim copies of the respective tool's output. --- v2: New. --- a/gas/testsuite/gas/mips/micromips.l +++ b/gas/testsuite/gas/mips/micromips.l @@ -64,18 +64,18 @@ .*:3133: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,16' .*:3134: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,20' .*:3135: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,24' -.*:3137: Error: opcode not supported in the `insn32' mode `addiusp 2<<2' -.*:3138: Error: opcode not supported in the `insn32' mode `addiusp 3<<2' -.*:3139: Error: opcode not supported in the `insn32' mode `addiusp 254<<2' -.*:3140: Error: opcode not supported in the `insn32' mode `addiusp 255<<2' -.*:3141: Error: opcode not supported in the `insn32' mode `addiusp 256<<2' -.*:3142: Error: opcode not supported in the `insn32' mode `addiusp 257<<2' -.*:3143: Error: opcode not supported in the `insn32' mode `addiusp -3<<2' -.*:3144: Error: opcode not supported in the `insn32' mode `addiusp -4<<2' -.*:3145: Error: opcode not supported in the `insn32' mode `addiusp -255<<2' -.*:3146: Error: opcode not supported in the `insn32' mode `addiusp -256<<2' -.*:3147: Error: opcode not supported in the `insn32' mode `addiusp -257<<2' -.*:3148: Error: opcode not supported in the `insn32' mode `addiusp -258<<2' +.*:3137: Error: opcode not supported in the `insn32' mode `addiusp 2 ?<< ?2' +.*:3138: Error: opcode not supported in the `insn32' mode `addiusp 3 ?<< ?2' +.*:3139: Error: opcode not supported in the `insn32' mode `addiusp 254 ?<< ?2' +.*:3140: Error: opcode not supported in the `insn32' mode `addiusp 255 ?<< ?2' +.*:3141: Error: opcode not supported in the `insn32' mode `addiusp 256 ?<< ?2' +.*:3142: Error: opcode not supported in the `insn32' mode `addiusp 257 ?<< ?2' +.*:3143: Error: opcode not supported in the `insn32' mode `addiusp -3 ?<< ?2' +.*:3144: Error: opcode not supported in the `insn32' mode `addiusp -4 ?<< ?2' +.*:3145: Error: opcode not supported in the `insn32' mode `addiusp -255 ?<< ?2' +.*:3146: Error: opcode not supported in the `insn32' mode `addiusp -256 ?<< ?2' +.*:3147: Error: opcode not supported in the `insn32' mode `addiusp -257 ?<< ?2' +.*:3148: Error: opcode not supported in the `insn32' mode `addiusp -258 ?<< ?2' .*:3150: Error: opcode not supported in the `insn32' mode `addius5 \$0,0' .*:3151: Error: opcode not supported in the `insn32' mode `addius5 \$2,0' .*:3152: Error: opcode not supported in the `insn32' mode `addius5 \$3,0' --- a/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.l +++ b/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.l @@ -117,12 +117,12 @@ .*:171: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$29,0' .*:172: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$29,\$29,0' .*:174: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.e \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.e \$16,\.-3' +.*:175: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.e \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$16,0' .*:177: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,0' .*:179: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: mips1 \(mips1\) `dla\.e \$16,\.-1' +.*:181: Error: opcode not supported on this processor: mips1 \(mips1\) `dla\.e \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,\$sp,0' .*:10: Warning: extended operand requested but not required --- a/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.l +++ b/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.l @@ -44,11 +44,11 @@ .*:171: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$29,0' .*:172: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$29,\$29,0' .*:174: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.t \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.t \$16,\.-3' +.*:175: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.t \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$16,0' .*:177: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,0' .*:179: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: mips1 \(mips1\) `dla\.t \$16,\.-1' +.*:181: Error: opcode not supported on this processor: mips1 \(mips1\) `dla\.t \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,\$sp,0' --- a/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.l +++ b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.l @@ -115,12 +115,12 @@ .*:171: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$29,0' .*:172: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$29,\$29,0' .*:174: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.e \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.e \$16,\.-3' +.*:175: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.e \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$16,0' .*:177: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,0' .*:179: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: mips32 \(mips32\) `dla\.e \$16,\.-1' +.*:181: Error: opcode not supported on this processor: mips32 \(mips32\) `dla\.e \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,\$sp,0' .*:10: Warning: extended operand requested but not required --- a/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.l +++ b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.l @@ -33,11 +33,11 @@ .*:171: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$29,0' .*:172: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$29,\$29,0' .*:174: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.t \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.t \$16,\.-3' +.*:175: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.t \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$16,0' .*:177: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,0' .*:179: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: mips32 \(mips32\) `dla\.t \$16,\.-1' +.*:181: Error: opcode not supported on this processor: mips32 \(mips32\) `dla\.t \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,\$sp,0' --- a/gas/testsuite/gas/mips/mips16e2-32@mips16-insn-e.l +++ b/gas/testsuite/gas/mips/mips16e2-32@mips16-insn-e.l @@ -115,12 +115,12 @@ .*:171: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.e \$29,0' .*:172: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.e \$29,\$29,0' .*:174: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `ld\.e \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `ld\.e \$16,\.-3' +.*:175: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `ld\.e \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddiu\.e \$16,0' .*:177: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.e \$16,0' .*:179: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddiu\.e \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.e \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `dla\.e \$16,\.-1' +.*:181: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `dla\.e \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddiu\.e \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.e \$16,\$sp,0' .*:10: Warning: extended operand requested but not required --- a/gas/testsuite/gas/mips/mips16e2-32@mips16-insn-t.l +++ b/gas/testsuite/gas/mips/mips16e2-32@mips16-insn-t.l @@ -33,11 +33,11 @@ .*:171: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.t \$29,0' .*:172: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.t \$29,\$29,0' .*:174: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `ld\.t \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `ld\.t \$16,\.-3' +.*:175: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `ld\.t \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddiu\.t \$16,0' .*:177: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.t \$16,0' .*:179: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddiu\.t \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.t \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `dla\.t \$16,\.-1' +.*:181: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `dla\.t \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddiu\.t \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: mips32r2 \(mips32r2\) `daddu\.t \$16,\$sp,0' --- a/gas/testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l +++ b/gas/testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l @@ -115,12 +115,12 @@ .*:171: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$29,0' .*:172: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$29,\$29,0' .*:174: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.e \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.e \$16,\.-3' +.*:175: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.e \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$16,0' .*:177: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,0' .*:179: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dla\.e \$16,\.-1' +.*:181: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dla\.e \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.e \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.e \$16,\$sp,0' .*:10: Warning: extended operand requested but not required --- a/gas/testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l +++ b/gas/testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l @@ -33,11 +33,11 @@ .*:171: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$29,0' .*:172: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$29,\$29,0' .*:174: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.t \$16,0\(\$pc\)' -.*:175: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.t \$16,\.-3' +.*:175: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `ld\.t \$16,\. ?- ?3' .*:176: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$16,0' .*:177: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,0' .*:179: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$16,\$pc,0' .*:180: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,\$pc,0' -.*:181: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dla\.t \$16,\.-1' +.*:181: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `dla\.t \$16,\. ?- ?1' .*:182: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddiu\.t \$16,\$sp,0' .*:183: Error: opcode not supported on this processor: interaptiv-mr2 \(mips32r3\) `daddu\.t \$16,\$sp,0' --- a/gas/testsuite/gas/mips/mips16e2@lui-2.l +++ b/gas/testsuite/gas/mips/mips16e2@lui-2.l @@ -1,5 +1,5 @@ .*: Assembler messages: -.*:7: Error: operand 2 must be constant `lui \$2,bar-foo' -.*:8: Error: operand 2 must be constant `lui \$2,baz-bar' -.*:9: Error: operand 2 must be constant `lui \$2,foo-baz' -.*:10: Error: operand 2 must be constant `lui \$2,bar/baz' +.*:7: Error: operand 2 must be constant `lui \$2,bar ?- ?foo' +.*:8: Error: operand 2 must be constant `lui \$2,baz ?- ?bar' +.*:9: Error: operand 2 must be constant `lui \$2,foo ?- ?baz' +.*:10: Error: operand 2 must be constant `lui \$2,bar ?/ ?baz' From patchwork Wed Jul 31 12:04:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ac6339b06esm8558902a12.10.2024.07.31.05.04.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 05:04:38 -0700 (PDT) Message-ID: Date: Wed, 31 Jul 2024 14:04:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 8/9] gas: have scrubber retain more whitespace From: Jan Beulich To: Binutils Cc: Richard Earnshaw , Marcus Shawcroft , Nick Clifton , "ramana.radhakrishnan@arm.com" , Lifang Xia , Yunhai Shang , "David S. Miller" , "Jose E. Marchesi" , "H.J. Lu" , Doug Evans , "Frank Ch. Eigler" , Kuan-Lin Chen , Wei-Cheng Wang References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3021.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org According to the description of the state machine, the expectation appears to be that (leaving aside labels) any insn mnemonic or directive would be followed by a comma separated list of operands. That may have been true very long ago, but the latest with the advent of more elaborate macros this isn't rhe case anymore. Neither macro parameters in macro definitions nor macro arguments in macro invocations are required to be separated by commas. Hence whitespace serves a crucial role there. Plus even without "real" macros issues exist, in e.g. .irp n, ... insn\n\(suffix) operand1, operand2 .endr Whitespace following the closing parenthesis would have been removed (ahead of even processing the .irp), as the "opcode" was deemed to have ended earlier already. Therefore, squash the distinction between "opcode" and operands, i.e. fold state 10 back into state 3. Also drop most of the distinction between "symbol chars" and "relatively normal" ones. Not entirely unexpectedly this results in the need to skip whitespace in a few more places in arch-specific code (and quite likely more changes are needed for insn forms not covered by the testsuite). As a result the D10V special case is no longer necessary. In config/tc-sparc.c also move a comment to be next to the code being commented. In opcodes/cgen-asm.in some further cleanup is done, following the local var adjustments. --- Diffs of updates to generated files (CGEN) omitted here. --- In config/tc-sparc.c the second of the "else if" touched looks suspicious: Without looking at s1[-2], how can s1[-3] be reliably of the expected meaning? Is there perhaps ISDIGIT(s1[-2]) missing? --- v3: Add NEWS entry. v2: Further target-specific adjustments. However, drop the earlier x86 adjustment as no longer necessary. --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,12 @@ -*- text -*- +* The scrubber (pre-processor) now leaves in place more whitespace, to permit + various constructs not fitting the basic "insn opnd1,opnd2[,...]" scheme to + work. This, however, means that macro invocations like "m 1 + 2", i.e. not + using double quotes or parentheses around the (apparently) sole argument, + will now be treated as passing three arguments. Such lack of quotation / + parenthesization was never reliable to use. + Changes in 2.43: * The MIPS '--trap' command-line option now causes GAS to dynamically --- a/gas/app.c +++ b/gas/app.c @@ -472,16 +472,18 @@ do_scrub_chars (size_t (*get) (char *, s /*State 0: beginning of normal line 1: After first whitespace on line (flush more white) - 2: After first non-white (opcode) on line (keep 1white) - 3: after second white on line (into operands) (flush white) + 2: After first non-white (opcode or maybe label when they're followed + by colons) on line (keep 1white) + 3: after subsequent white on line (typically into operands) + (flush more white) 4: after putting out a .linefile, put out digits 5: parsing a string, then go to old-state 6: putting out \ escape in a "d string. 7: no longer used 8: no longer used - 9: After seeing symbol char in state 3 (keep 1white after symchar) - 10: After seeing whitespace in state 9 (keep white before symchar) - 11: After seeing a symbol character in state 0 (eg a label definition) + 9: After seeing non-white in state 3 (keep 1white) + 10: no longer used + 11: After seeing a non-white character in state 0 (eg a label definition) -1: output string in out_string and go to the state in old_state 12: no longer used #ifdef DOUBLEBAR_PARALLEL @@ -944,7 +946,11 @@ do_scrub_chars (size_t (*get) (char *, s && (state < 1 || strchr (tc_comment_chars, ch))) || IS_NEWLINE (ch) || IS_LINE_SEPARATOR (ch) - || IS_PARALLEL_SEPARATOR (ch)) + || IS_PARALLEL_SEPARATOR (ch) + /* See comma related comment near the bottom of the function. + Reasoning equally applies to whitespace preceding a comma in + most cases. */ + || (ch == ',' && state > 2 && state != 11)) { if (scrub_m68k_mri) { @@ -987,6 +993,7 @@ do_scrub_chars (size_t (*get) (char *, s character at the beginning of a line. */ goto recycle; case 2: + case 9: state = 3; if (to + 1 < toend) { @@ -1010,20 +1017,6 @@ do_scrub_chars (size_t (*get) (char *, s break; } goto recycle; /* Sp in operands */ - case 9: - case 10: -#ifndef TC_KEEP_OPERAND_SPACES - if (scrub_m68k_mri) -#endif - { - /* In MRI mode, we keep these spaces. */ - state = 3; - UNGET (ch); - PUT (' '); - break; - } - state = 10; /* Sp after symbol char */ - goto recycle; case 11: if (LABELS_WITHOUT_COLONS || flag_m68k_mri) state = 1; @@ -1094,27 +1087,17 @@ do_scrub_chars (size_t (*get) (char *, s { if (ch2 != EOF) UNGET (ch2); - if (state == 9 || state == 10) - state = 3; + if (state == 1) + state = 2; + else if (state == 3) + state = 9; PUT (ch); } break; case LEX_IS_STRINGQUOTE: quotechar = ch; - if (state == 10) - { - /* Preserve the whitespace in foo "bar". */ - UNGET (ch); - state = 3; - PUT (' '); - - /* PUT didn't jump out. We could just break, but we - know what will happen, so optimize a bit. */ - ch = GET (); - old_state = 9; - } - else if (state == 3) + if (state == 3) old_state = 9; else if (state == 0) old_state = 11; /* Now seeing label definition. */ @@ -1135,14 +1118,6 @@ do_scrub_chars (size_t (*get) (char *, s UNGET (c); } #endif - if (state == 10) - { - /* Preserve the whitespace in foo 'b'. */ - UNGET (ch); - state = 3; - PUT (' '); - break; - } ch = GET (); if (ch == EOF) { @@ -1177,10 +1152,7 @@ do_scrub_chars (size_t (*get) (char *, s PUT (out_buf[0]); break; } - if (state == 9) - old_state = 3; - else - old_state = state; + old_state = state; state = -1; out_string = out_buf; PUT (*out_string++); @@ -1190,10 +1162,10 @@ do_scrub_chars (size_t (*get) (char *, s #ifdef KEEP_WHITE_AROUND_COLON state = 9; #else - if (state == 9 || state == 10) - state = 3; - else if (state != 3) + if (state == 2 || state == 11) state = 1; + else + state = 9; #endif PUT (ch); break; @@ -1318,20 +1290,6 @@ do_scrub_chars (size_t (*get) (char *, s break; } -#ifdef TC_D10V - /* All insns end in a char for which LEX_IS_SYMBOL_COMPONENT is true. - Trap is the only short insn that has a first operand that is - neither register nor label. - We must prevent exef0f ||trap #1 to degenerate to exef0f ||trap#1 . - We can't make '#' LEX_IS_SYMBOL_COMPONENT because it is - already LEX_IS_LINE_COMMENT_START. However, it is the - only character in line_comment_chars for d10v, hence we - can recognize it as such. */ - /* An alternative approach would be to reset the state to 1 when - we see '||', '<'- or '->', but that seems to be overkill. */ - if (state == 10) - PUT (' '); -#endif /* We have a line comment character which is not at the start of a line. If this is also a normal comment character, fall through. Otherwise treat it as a default @@ -1395,17 +1353,6 @@ do_scrub_chars (size_t (*get) (char *, s /* Fall through. */ case LEX_IS_SYMBOL_COMPONENT: - if (state == 10) - { - /* This is a symbol character following another symbol - character, with whitespace in between. We skipped - the whitespace earlier, so output it now. */ - UNGET (ch); - state = 3; - PUT (' '); - break; - } - #ifdef TC_Z80 /* "af'" is a symbol containing '\''. */ if (state == 3 && (ch == 'a' || ch == 'A')) @@ -1431,7 +1378,16 @@ do_scrub_chars (size_t (*get) (char *, s } } #endif - if (state == 3) + + /* Fall through. */ + default: + de_fault: + /* Some relatively `normal' character. */ + if (state == 0) + state = 11; /* Now seeing label definition. */ + else if (state == 1) + state = 2; /* Ditto. */ + else if (state == 3) state = 9; /* This is a common case. Quickly copy CH and all the @@ -1441,6 +1397,10 @@ do_scrub_chars (size_t (*get) (char *, s #if defined TC_ARM && defined OBJ_ELF && symver_state == NULL #endif +#ifdef TC_Z80 + /* See comma related comment below. */ + && ch != ',' +#endif ) { char *s; @@ -1455,6 +1415,12 @@ do_scrub_chars (size_t (*get) (char *, s if (type != 0 && type != LEX_IS_SYMBOL_COMPONENT) break; +#ifdef TC_Z80 + /* Need to split at commas, to be able to enter state 16 + when needed. */ + if (ch2 == ',') + break; +#endif } if (s > from) @@ -1479,52 +1445,15 @@ do_scrub_chars (size_t (*get) (char *, s } } - /* Fall through. */ - default: - de_fault: - /* Some relatively `normal' character. */ - if (state == 0) - { - state = 11; /* Now seeing label definition. */ - } - else if (state == 1) - { - state = 2; /* Ditto. */ - } - else if (state == 9) - { - if (!IS_SYMBOL_COMPONENT (ch)) - state = 3; - } - else if (state == 10) - { - if (ch == '\\') - { - /* Special handling for backslash: a backslash may - be the beginning of a formal parameter (of a - macro) following another symbol character, with - whitespace in between. If that is the case, we - output a space before the parameter. Strictly - speaking, correct handling depends upon what the - macro parameter expands into; if the parameter - expands into something which does not start with - an operand character, then we don't want to keep - the space. We don't have enough information to - make the right choice, so here we are making the - choice which is more likely to be correct. */ - if (to + 1 >= toend) - { - /* If we're near the end of the buffer, save the - character for the next time round. Otherwise - we'll lose our state. */ - UNGET (ch); - goto tofull; - } - *to++ = ' '; - } + /* As a special case, to limit the delta to previous behavior, e.g. + also affecting listings, go straight to state 3 when seeing a + comma. Commas are special: While they can be used to separate + macro parameters or arguments, they cannot (on their own, i.e. + without quoting) be arguments (or parameter default values). + Hence successive whitespace is not meaningful there. */ + if (ch == ',' && state == 9) + state = 3; - state = 3; - } PUT (ch); break; } --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -643,6 +643,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXeEpP static inline bool skip_past_char (char **str, char c) { + skip_whitespace (*str); if (**str == c) { (*str)++; @@ -893,6 +894,7 @@ parse_reg (char **ccp) start++; #endif + skip_whitespace (start); p = start; if (!ISALPHA (*p) || !is_name_beginner (*p)) return NULL; @@ -1202,13 +1204,17 @@ parse_typed_reg (char **ccp, aarch64_reg struct vector_type_el *typeinfo, unsigned int flags) { char *str = *ccp; - bool is_alpha = ISALPHA (*str); - const reg_entry *reg = parse_reg (&str); + bool is_alpha; + const reg_entry *reg; struct vector_type_el atype; struct vector_type_el parsetype; bool is_typed_vecreg = false; unsigned int err_flags = (flags & PTR_IN_REGLIST) ? SEF_IN_REGLIST : 0; + skip_whitespace (str); + is_alpha = ISALPHA (*str); + reg = parse_reg (&str); + atype.defined = 0; atype.type = NT_invtype; atype.width = -1; @@ -1429,10 +1435,7 @@ parse_vector_reg_list (char **ccp, aarch do { if (in_range) - { - str++; /* skip over '-' */ - val_range = val; - } + val_range = val; const reg_entry *reg; if (has_qualifier) @@ -1494,7 +1497,8 @@ parse_vector_reg_list (char **ccp, aarch in_range = 0; ptr_flags |= PTR_GOOD_MATCH; } - while (skip_past_comma (&str) || (in_range = 1, *str == '-')); + while (skip_past_comma (&str) + || (in_range = 1, skip_past_char (&str, '-'))); skip_whitespace (str); if (*str != '}') @@ -8289,6 +8293,7 @@ parse_operands (char *str, const aarch64 } /* Check if we have parsed all the operands. */ + skip_whitespace (str); if (*str != '\0' && ! error_p ()) { /* Set I to the index of the last present operand; this is --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -1148,6 +1148,8 @@ my_get_expression (expressionS * ep, cha prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode : GE_OPT_PREFIX; + skip_whitespace (*str); + switch (prefix_mode) { case GE_NO_PREFIX: break; --- a/gas/config/tc-crx.c +++ b/gas/config/tc-crx.c @@ -1723,9 +1723,13 @@ preprocess_reglist (char *param, int *al while (*paramP != '}') { - regP = paramP; memset (®_name, '\0', sizeof (reg_name)); + while (ISSPACE (*paramP)) + paramP++; + + regP = paramP; + while (ISALNUM (*paramP)) paramP++; --- a/gas/config/tc-csky.c +++ b/gas/config/tc-csky.c @@ -2409,10 +2409,18 @@ parse_rt (char *s, /* Indicate nothing there. */ ep->X_op = O_absent; + /* Skip whitespace. */ + while (ISSPACE (*s)) + ++s; + if (*s == '[') { s = parse_exp (s + 1, &e); + /* Skip whitespace. */ + while (ISSPACE (*s)) + ++s; + if (*s == ']') s++; else @@ -2935,6 +2943,11 @@ is_reg_lshift_illegal (char **oper, int } *oper += len; + + /* Skip whitespace. */ + while (ISSPACE (**oper)) + ++*oper; + if ((*oper)[0] != '<' || (*oper)[1] != '<') { SET_ERROR_STRING (ERROR_UNDEFINE, @@ -3461,6 +3474,9 @@ get_operand_value (struct csky_opcode_in return false; } + while (ISSPACE (**oper)) + ++*oper; + if (!get_operand_value (op, oper, &soprnd->subs[0])) { *s = rc; @@ -3481,7 +3497,7 @@ get_operand_value (struct csky_opcode_in } *s = rc; - *oper += 1; + *oper = s + 1; return true; } @@ -4277,11 +4293,16 @@ get_operand_value (struct csky_opcode_in case OPRND_TYPE_VREG_WITH_INDEX: if (parse_type_freg (oper, 0)) { + /* Skip whitespace. */ + while (ISSPACE (**oper)) + ++*oper; if (**oper == '[') { (*oper)++; if (is_imm_within_range (oper, 0, 0xf)) { + while (ISSPACE (**oper)) + ++*oper; if (**oper == ']') { unsigned int idx = --csky_insn.idx; --- a/gas/config/tc-pru.c +++ b/gas/config/tc-pru.c @@ -1399,7 +1399,6 @@ pru_parse_args (pru_insn_infoS *insn ATT const char *parsestr, char **parsed_args) { char *p; - char *end = NULL; int i; p = argstr; i = 0; @@ -1426,14 +1425,7 @@ pru_parse_args (pru_insn_infoS *insn ATT else { /* Check that the argument string has no trailing arguments. */ - /* If we've got a %pmem relocation, we've zapped the parens with - spaces. */ - if (strprefix (p, "%pmem") || strprefix (p, "%label")) - end = strpbrk (p, ","); - else - end = strpbrk (p, " ,"); - - if (end != NULL) + if (strpbrk (p, ",") != NULL) as_bad (_("too many arguments")); } --- a/gas/config/tc-sparc.c +++ b/gas/config/tc-sparc.c @@ -1778,6 +1778,9 @@ sparc_ip (char *str, const struct sparc_ operands match. */ for (args = insn->args;; ++args) { + if (*s == ' ' && *args != ' ') + ++s; + switch (*args) { case 'K': @@ -2717,11 +2720,6 @@ sparc_ip (char *str, const struct sparc_ 'symbols' in the input string. Try not to create U symbols for registers, etc. */ - /* This stuff checks to see if the expression ends in - +%reg. If it does, it removes the register from - the expression, and re-sets 's' to point to the - right place. */ - if (op_arg) { int npar = 0; @@ -2751,6 +2749,8 @@ sparc_ip (char *str, const struct sparc_ return special_case; } s = s1 + 1; + if (*s == ' ') + s++; if (*s == ',' || *s == ']' || !*s) continue; if (*s != '+' && *s != '-') @@ -2764,17 +2764,45 @@ sparc_ip (char *str, const struct sparc_ memset (&the_insn.exp, 0, sizeof (the_insn.exp)); } + /* This stuff checks to see if the expression ends in + +%reg. If it does, it removes the register from + the expression, and re-sets 's' to point to the + right place. */ + for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ; + if (s1 != s && s1[-1] == ' ') + --s1; if (s1 != s && ISDIGIT (s1[-1])) { if (s1[-2] == '%' && s1[-3] == '+') - s1 -= 3; - else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') - s1 -= 4; - else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') - s1 -= 5; + { + if (s1[-3] == '+') + s1 -= 3; + else if (s1[-3] == ' ' && s1[-4] == '+') + s1 -= 4; + else + s1 = NULL; + } + else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%') + { + if (s1[-4] == '+') + s1 -= 4; + else if (s1[-4] == ' ' && s1[-5] == '+') + s1 -= 5; + else + s1 = NULL; + } + else if (s1[-3] == 'r' && s1[-4] == '%') + { + if (s1[-5] == '+') + s1 -= 5; + else if (s1[-5] == ' ' && s1[-6] == '+') + s1 -= 6; + else + s1 = NULL; + } else s1 = NULL; if (s1) --- a/gas/config/tc-v850.c +++ b/gas/config/tc-v850.c @@ -1456,6 +1456,8 @@ parse_register_list (unsigned long *insn } } + skip_white_space (); + if (*input_line_pointer == '}') { input_line_pointer++; @@ -1475,6 +1477,8 @@ parse_register_list (unsigned long *insn /* Skip the dash. */ ++input_line_pointer; + skip_white_space (); + /* Get the second register in the range. */ if (! register_name (&exp2)) { --- a/gas/testsuite/gas/all/macro.l +++ b/gas/testsuite/gas/all/macro.l @@ -22,4 +22,14 @@ [ ]*[1-9][0-9]*[ ]+.... 0+70*[ ]+> .byte 7 [ ]*[1-9][0-9]*[ ]+.... 0+80*[ ]+> .byte 8 [ ]*[1-9][0-9]*[ ]+m[ ]+""[ ]+""[ ]+"" +[ ]*[1-9][0-9]*[ ]+ +[ ]*[1-9][0-9]*[ ]+m[ ]+1[ ]+\+2 +[ ]*[1-9][0-9]*[ ]+.... 0+10*[ ]+> .byte 1 +[ ]*[1-9][0-9]*[ ]+.... 0+20*[ ]+> .byte \+2 +[ ]*[1-9][0-9]*[ ]+m[ ]+\(3\)[ ]+\+4 +[ ]*[1-9][0-9]*[ ]+.... 0+30*[ ]+> .byte \(3\) +[ ]*[1-9][0-9]*[ ]+.... 0+40*[ ]+> .byte \+4 +[ ]*[1-9][0-9]*[ ]+m[ ]+\(5\)[ ]+\(6\) +[ ]*[1-9][0-9]*[ ]+.... 0+50*[ ]+> .byte \(5\) +[ ]*[1-9][0-9]*[ ]+.... 0+60*[ ]+> .byte \(6\) #pass --- a/gas/testsuite/gas/all/macro.s +++ b/gas/testsuite/gas/all/macro.s @@ -9,8 +9,8 @@ m "7" "8" m "" "" "" - .if 0 m 1 +2 m (3) +4 m (5) (6) - .endif + + .byte -1 --- a/gas/testsuite/gas/i386/x86-64-apx-nf.s +++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s @@ -1390,13 +1390,13 @@ optimize: {nf} \op $128, %ecx, %edx {nf} \op $128, %r9 {nf} \op $128, %r9, %r31 - {nf} \op\()b $128, (%rax) + {nf} \op\(b) $128, (%rax) {nf} \op $128, (%rax), %bl - {nf} \op\()w $128, (%rax) + {nf} \op\(w) $128, (%rax) {nf} \op $128, (%rax), %dx - {nf} \op\()l $128, (%rax) + {nf} \op\(l) $128, (%rax) {nf} \op $128, (%rax), %ecx - {nf} \op\()q $128, (%rax) + {nf} \op\(q) $128, (%rax) {nf} \op $128, (%rax), %r9 {nf} \op $1, %bl @@ -1407,13 +1407,13 @@ optimize: {nf} \op $1, %ecx, %edx {nf} \op $1, %r9 {nf} \op $1, %r9, %r31 - {nf} \op\()b $1, (%rax) + {nf} \op\(b) $1, (%rax) {nf} \op $1, (%rax), %bl - {nf} \op\()w $1, (%rax) + {nf} \op\(w) $1, (%rax) {nf} \op $1, (%rax), %dx - {nf} \op\()l $1, (%rax) + {nf} \op\(l) $1, (%rax) {nf} \op $1, (%rax), %ecx - {nf} \op\()q $1, (%rax) + {nf} \op\(q) $1, (%rax) {nf} \op $1, (%rax), %r9 {nf} \op $0xff, %bl @@ -1424,13 +1424,13 @@ optimize: {nf} \op $-1, %ecx, %edx {nf} \op $-1, %r9 {nf} \op $-1, %r9, %r31 - {nf} \op\()b $0xff, (%rax) + {nf} \op\(b) $0xff, (%rax) {nf} \op $-1, (%rax), %bl - {nf} \op\()w $0xffff, (%rax) + {nf} \op\(w) $0xffff, (%rax) {nf} \op $-1, (%rax), %dx - {nf} \op\()l $0xffffffff, (%rax) + {nf} \op\(l) $0xffffffff, (%rax) {nf} \op $-1, (%rax), %ecx - {nf} \op\()q $-1, (%rax) + {nf} \op\(q) $-1, (%rax) {nf} \op $-1, (%rax), %r9 .endr @@ -1444,13 +1444,13 @@ optimize: {nf} ro\dir $63, %rdx {nf} ro\dir $63, %rdx, %rax - {nf} ro\dir\()b $7, (%rdx) + {nf} ro\dir\(b) $7, (%rdx) {nf} ro\dir $7, (%rdx), %al - {nf} ro\dir\()w $15, (%rdx) + {nf} ro\dir\(w) $15, (%rdx) {nf} ro\dir $15, (%rdx), %ax - {nf} ro\dir\()l $31, (%rdx) + {nf} ro\dir\(l) $31, (%rdx) {nf} ro\dir $31, (%rdx), %eax - {nf} ro\dir\()q $63, (%rdx) + {nf} ro\dir\(q) $63, (%rdx) {nf} ro\dir $63, (%rdx), %rax .endr @@ -1476,10 +1476,10 @@ optimize: # Note: 2-6 want leaving alone with -Os. .irp n, 1, 2, 6, 7 # Note: 16-bit 3-operand src!=dst non-ZU form needs leaving alone. - {nf} imul $1<<\n, %\r\()dx, %\r\()cx - {nf} imul $1<<\n, (%rdx), %\r\()cx - {nf} imul $1<<\n, %\r\()cx, %\r\()cx - {nf} imul $1<<\n, %\r\()cx + {nf} imul $1<<\n, %\r\(dx), %\r\(cx) + {nf} imul $1<<\n, (%rdx), %\r\(cx) + {nf} imul $1<<\n, %\r\(cx), %\r\(cx) + {nf} imul $1<<\n, %\r\(cx) .ifeqs "\r","" {nf} imulzu $1<<\n, %dx, %cx --- a/opcodes/cgen-asm.in +++ b/opcodes/cgen-asm.in @@ -68,6 +68,7 @@ char * char rxbuf[CGEN_MAX_RX_ELEMENTS]; char *rx = rxbuf; const CGEN_SYNTAX_CHAR_TYPE *syn; + char prev_syntax_char = 0; int reg_err; syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); @@ -105,6 +106,15 @@ char * { char c = CGEN_SYNTAX_CHAR (* syn); + /* See whitespace related comments in parse_insn_normal(). */ + if (c != ' ' && prev_syntax_char != ' ' + && (!ISALNUM (c) || !ISALNUM (prev_syntax_char))) + { + *rx++ = ' '; + *rx++ = '*'; + } + prev_syntax_char = c; + switch (c) { /* Escape any regex metacharacters in the syntax. */ @@ -138,6 +148,7 @@ char * /* Replace non-syntax fields with globs. */ *rx++ = '.'; *rx++ = '*'; + prev_syntax_char = 0; } } @@ -195,10 +206,8 @@ parse_insn_normal (CGEN_CPU_DESC cd, const char *errmsg; const char *p; const CGEN_SYNTAX_CHAR_TYPE * syn; -#ifdef CGEN_MNEMONIC_OPERANDS - /* FIXME: wip */ - int past_opcode_p; -#endif + char prev_syntax_char = 0; + bool past_opcode_p; /* For now we assume the mnemonic is first (there are no leading operands). We can parse it without needing to set up operand parsing. @@ -214,13 +223,13 @@ parse_insn_normal (CGEN_CPU_DESC cd, #ifndef CGEN_MNEMONIC_OPERANDS if (* str && ! ISSPACE (* str)) return _("unrecognized instruction"); + past_opcode_p = true; +#else + past_opcode_p = false; #endif CGEN_INIT_PARSE (cd); cgen_init_parse_operand (cd); -#ifdef CGEN_MNEMONIC_OPERANDS - past_opcode_p = 0; -#endif /* We don't check for (*str != '\0') here because we want to parse any trailing fake arguments in the syntax string. */ @@ -234,18 +243,28 @@ parse_insn_normal (CGEN_CPU_DESC cd, while (* syn != 0) { + char c = CGEN_SYNTAX_CHAR_P (*syn) ? CGEN_SYNTAX_CHAR (*syn) : 0; + + /* FIXME: Despite this check we may still take inappropriate advantage of + the fact that GAS's input scrubber will remove extraneous whitespace. + We may also be a little too lax with this now, yet being more strict + would require targets to indicate where whitespace is permissible. */ + if (past_opcode_p && c != ' ' && ISSPACE (*str) + /* No whitespace between consecutive alphanumeric syntax elements. */ + && (!ISALNUM (c) || !ISALNUM (prev_syntax_char))) + ++str; + prev_syntax_char = c; + /* Non operand chars must match exactly. */ - if (CGEN_SYNTAX_CHAR_P (* syn)) + if (c != 0) { /* FIXME: While we allow for non-GAS callers above, we assume the first char after the mnemonic part is a space. */ - /* FIXME: We also take inappropriate advantage of the fact that - GAS's input scrubber will remove extraneous blanks. */ - if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + if (TOLOWER (*str) == TOLOWER (c)) { #ifdef CGEN_MNEMONIC_OPERANDS - if (CGEN_SYNTAX_CHAR(* syn) == ' ') - past_opcode_p = 1; + if (c == ' ') + past_opcode_p = true; #endif ++ syn; ++ str; @@ -257,7 +276,7 @@ parse_insn_normal (CGEN_CPU_DESC cd, /* xgettext:c-format */ sprintf (msg, _("syntax error (expected char `%c', found `%c')"), - CGEN_SYNTAX_CHAR(*syn), *str); + c, *str); return msg; } else @@ -267,15 +286,12 @@ parse_insn_normal (CGEN_CPU_DESC cd, /* xgettext:c-format */ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), - CGEN_SYNTAX_CHAR(*syn)); + c); return msg; } continue; } -#ifdef CGEN_MNEMONIC_OPERANDS - (void) past_opcode_p; -#endif /* We have an operand of some sort. */ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); if (errmsg) --- a/opcodes/nds32-asm.c +++ b/opcodes/nds32-asm.c @@ -2486,6 +2486,9 @@ parse_insn (nds32_asm_desc_t *pdesc, nds while (*plex) { + if (ISSPACE (*p)) + ++p; + if (IS_LEX_CHAR (*plex)) { /* If it's a plain char, just compare it. */ @@ -2530,6 +2533,8 @@ parse_insn (nds32_asm_desc_t *pdesc, nds } /* Check whether this syntax is accepted. */ + if (ISSPACE (*p)) + ++p; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7acab535a6sm757901966b.88.2024.07.31.05.06.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 Jul 2024 05:06:05 -0700 (PDT) Message-ID: <32cdb0b9-1ba8-44b7-8bc4-a8159bb863c1@suse.com> Date: Wed, 31 Jul 2024 14:06:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 9/9] gas: drop scrubber states 14 and 15 From: Jan Beulich To: Binutils Cc: Jim Wilson , Joseph Myers References: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7e951d11-cccf-4851-84a6-3a85cda8254a@suse.com> X-Spam-Status: No, score=-3022.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_NUMSUBJECT, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org While sadly 5262831592fb doesn't say anything on why these would have been needed, the latest with the removal of most of the opcode vs operands distinction in the scrubber these shouldn't be needed anymore. The implementation was a little questionable anyway, in moving back to states expecting labels, when clearly labels shouldn't really be following predicates (in practice, due to another bug, at least ia64 permits such). --- v3: New. --- a/gas/app.c +++ b/gas/app.c @@ -490,12 +490,6 @@ do_scrub_chars (size_t (*get) (char *, s 13: After seeing a vertical bar, looking for a second vertical bar as a parallel expression separator. #endif -#ifdef TC_PREDICATE_START_CHAR - 14: After seeing a predicate start character at state 0, looking - for a predicate end character as predicate. - 15: After seeing a predicate start character at state 1, looking - for a predicate end character as predicate. -#endif #ifdef TC_Z80 16: After seeing an 'a' or an 'A' at the start of a symbol 17: After seeing an 'f' or an 'F' in state 16 @@ -782,29 +776,6 @@ do_scrub_chars (size_t (*get) (char *, s /* flushchar: */ ch = GET (); -#ifdef TC_PREDICATE_START_CHAR - if (ch == TC_PREDICATE_START_CHAR && (state == 0 || state == 1)) - { - state += 14; - PUT (ch); - continue; - } - else if (state == 14 || state == 15) - { - if (ch == TC_PREDICATE_END_CHAR) - { - state -= 14; - PUT (ch); - ch = GET (); - } - else - { - PUT (ch); - continue; - } - } -#endif - recycle: #if defined TC_ARM && defined OBJ_ELF --- a/gas/config/tc-ia64.h +++ b/gas/config/tc-ia64.h @@ -78,9 +78,6 @@ extern const char *ia64_target_format (v #define LEX_QM (LEX_NAME|LEX_BEGIN_NAME) /* allow `?' inside name */ #define LEX_HASH LEX_END_NAME /* allow `#' ending a name */ -#define TC_PREDICATE_START_CHAR '(' -#define TC_PREDICATE_END_CHAR ')' - extern const char ia64_symbol_chars[]; #define tc_symbol_chars ia64_symbol_chars --- a/gas/config/tc-tic6x.h +++ b/gas/config/tc-tic6x.h @@ -24,8 +24,6 @@ #define DOUBLEBAR_PARALLEL #define DWARF2_LINE_MIN_INSN_LENGTH 2 #define MD_APPLY_SYM_VALUE(FIX) 0 -#define TC_PREDICATE_START_CHAR '[' -#define TC_PREDICATE_END_CHAR ']' /* For TI C6X, we keep spaces in what the preprocessor considers operands as they may separate functional unit specifiers from operands. */