From patchwork Mon Oct 11 05:54:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fangrui Song X-Patchwork-Id: 46057 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DB34C3858418 for ; Mon, 11 Oct 2021 05:55:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DB34C3858418 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1633931746; bh=S3p4LZ360huh1MxvB29LW8WGhuGxnmZWGIKL9iJkcKg=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=DtrGTL0fJ30ZXFEY8a8U/n8MWMU2sZ3ZZ0Ssah12CsYAbajFGek2xNl7/rkVY0duF Blk1km6VnNYN/G1E2KesV9tD5NExEcSTfzrNrM1D2gAzkWB6ZpwqPLtKxq5ZVbR5/r Dzyvk7lt7iMOxTohDVFU8CUrUIktP7nX34397Zw8= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by sourceware.org (Postfix) with ESMTPS id 71D133858D28 for ; Mon, 11 Oct 2021 05:55:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 71D133858D28 Received: by mail-yb1-xb49.google.com with SMTP id v203-20020a25c5d4000000b005bb21580411so9231679ybe.19 for ; Sun, 10 Oct 2021 22:55:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=S3p4LZ360huh1MxvB29LW8WGhuGxnmZWGIKL9iJkcKg=; b=i65l3nJx5akSTuFKVFmRh+sdimMkmy/xb2HTYu7gAPa4pP/JHvyb+iNaQv+AcRxNgd yBHVaemxfempqVbQrXl2giH63+Huw4ZDXbKQnm+pFB+z3HBNTJsqsDiJyZDIO3/pKQzZ sAuCGe9eoySuxT6X+9fcbYX2rQ30rmrncL34N2C1K5lWx9ujiUIru4r4AadtPNZ76zQK kpEAbE61kQIn3IggnmrJZL0LNZmB7F0zZiPQLo0AsB1m/e42mRDsegWPFQZx5VJmCcxD MyhhBfaXmvNnt+Z6ggUujUQfiEmb4sjS4LwEJymp9yPeV8jA887ns8Mw5QZgSC8dulha bKuw== X-Gm-Message-State: AOAM530+OekjcME9Y7Ud0uNTKXRMsJ7i3Usmq+E0sRfLaTiIC1mVG0Q8 sRQrmIN6dt7/V7kxp2aSObIMqcvXlfDlsSc6rIcSf0rd7JDPP+cEtV9LAYLHU5YYIvdHDwrJsec Wqag8MvJ641arXRpWs+OfBp5yi0CvQLMSAOPzqCsyLL83ESipnwp9eaHx7uPbkK7+b5mb X-Google-Smtp-Source: ABdhPJyZD/hsVVY7++uA+krIDmq44DCM88a6UTOfGDmvtebWLgCflBJgDCOF+TzEn0vI5tVJU6/2asqJAEKI X-Received: from maskray1.svl.corp.google.com ([2620:15c:2ce:200:f9c1:a45d:226f:b90b]) (user=maskray job=sendgmr) by 2002:a25:1487:: with SMTP id 129mr20899374ybu.206.1633931722948; Sun, 10 Oct 2021 22:55:22 -0700 (PDT) Date: Sun, 10 Oct 2021 22:54:54 -0700 Message-Id: <20211011055454.3440068-1-maskray@google.com> Mime-Version: 1.0 Subject: [PATCH v2] elf: Remove Intel MPX support (lazy PLT, ld.so profile, and LD_AUDIT) To: libc-alpha@sourceware.org, "H.J. Lu" , Florian Weimer X-Spam-Status: No, score=-19.8 required=5.0 tests=BAYES_00, DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Fangrui Song via Libc-alpha From: Fangrui Song Reply-To: Fangrui Song Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Intel MPX failed to gain wide adoption and has been deprecated for a while. GCC 9.1 removed Intel MPX support. Linux kernel removed MPX in 2019. This patch removes the support code from the dynamic loader. Reviewed-by: H.J. Lu --- Changes from v1: * Remove LRV_BND0_OFFSET, LRV_BND1_OFFSET,BND_SIZE from sysdeps/x86_64/link-defines.sym * Rename bnd members to __glibc_unused* in sysdeps/x86/bits/link.h --- NEWS | 2 ++ config.h.in | 3 -- sysdeps/i386/configure | 27 ----------------- sysdeps/i386/configure.ac | 15 --------- sysdeps/i386/dl-trampoline.S | 21 ------------- sysdeps/i386/link-defines.sym | 2 -- sysdeps/x86/bits/link.h | 10 +++--- sysdeps/x86_64/configure | 27 ----------------- sysdeps/x86_64/configure.ac | 15 --------- sysdeps/x86_64/dl-trampoline.S | 9 ------ sysdeps/x86_64/dl-trampoline.h | 54 --------------------------------- sysdeps/x86_64/link-defines.sym | 8 ----- 12 files changed, 7 insertions(+), 186 deletions(-) diff --git a/NEWS b/NEWS index 2e3804e4d8..220d327071 100644 --- a/NEWS +++ b/NEWS @@ -61,6 +61,8 @@ Deprecated and removed features, and other changes affecting compatibility: when audit modules or dlmopen are used. +* Intel MPX support (lazy PLT, ld.so profile, and LD_AUDIT) has been removed. + Changes to build and runtime requirements: [Add changes to build and runtime requirements here] diff --git a/config.h.in b/config.h.in index 964873f27e..0a6f57b006 100644 --- a/config.h.in +++ b/config.h.in @@ -84,9 +84,6 @@ /* Define if assembler supports arch13 instructions on S390. */ #undef HAVE_S390_ARCH13_ASM_SUPPORT -/* Define if assembler supports Intel MPX. */ -#undef HAVE_MPX_SUPPORT - /* Define if the compiler\'s exception support is based on libunwind. */ #undef HAVE_CC_WITH_LIBUNWIND diff --git a/sysdeps/i386/configure b/sysdeps/i386/configure index bb482ca16c..ed46d53314 100644 --- a/sysdeps/i386/configure +++ b/sysdeps/i386/configure @@ -83,33 +83,6 @@ $as_echo "$libc_cv_ld_static_pie" >&6; } fi fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for Intel MPX support" >&5 -$as_echo_n "checking for Intel MPX support... " >&6; } -if ${libc_cv_asm_mpx+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat > conftest.s <<\EOF - bndmov %bnd0,(%esp) -EOF -if { ac_try='${CC-cc} -c $ASFLAGS conftest.s 1>&5' - { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 - (eval $ac_try) 2>&5 - ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; }; then - libc_cv_asm_mpx=yes -else - libc_cv_asm_mpx=no -fi -rm -f conftest* -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_mpx" >&5 -$as_echo "$libc_cv_asm_mpx" >&6; } -if test $libc_cv_asm_mpx = yes; then - $as_echo "#define HAVE_MPX_SUPPORT 1" >>confdefs.h - -fi - $as_echo "#define PI_STATIC_AND_HIDDEN 1" >>confdefs.h diff --git a/sysdeps/i386/configure.ac b/sysdeps/i386/configure.ac index 5e43eb0adf..a6a0672835 100644 --- a/sysdeps/i386/configure.ac +++ b/sysdeps/i386/configure.ac @@ -53,21 +53,6 @@ rm -f conftest*]) fi fi -dnl Check whether asm supports Intel MPX -AC_CACHE_CHECK(for Intel MPX support, libc_cv_asm_mpx, [dnl -cat > conftest.s <<\EOF - bndmov %bnd0,(%esp) -EOF -if AC_TRY_COMMAND(${CC-cc} -c $ASFLAGS conftest.s 1>&AS_MESSAGE_LOG_FD); then - libc_cv_asm_mpx=yes -else - libc_cv_asm_mpx=no -fi -rm -f conftest*]) -if test $libc_cv_asm_mpx = yes; then - AC_DEFINE(HAVE_MPX_SUPPORT) -fi - dnl It is always possible to access static and hidden symbols in an dnl position independent way. AC_DEFINE(PI_STATIC_AND_HIDDEN) diff --git a/sysdeps/i386/dl-trampoline.S b/sysdeps/i386/dl-trampoline.S index b5ec0326df..5669ab18f5 100644 --- a/sysdeps/i386/dl-trampoline.S +++ b/sysdeps/i386/dl-trampoline.S @@ -19,12 +19,6 @@ #include #include -#ifdef HAVE_MPX_SUPPORT -# define PRESERVE_BND_REGS_PREFIX bnd -#else -# define PRESERVE_BND_REGS_PREFIX .byte 0xf2 -#endif - .text .globl _dl_runtime_resolve .type _dl_runtime_resolve, @function @@ -250,13 +244,6 @@ _dl_runtime_profile: movl %edx, LRV_EDX_OFFSET(%esp) fstpt LRV_ST0_OFFSET(%esp) fstpt LRV_ST1_OFFSET(%esp) -#ifdef HAVE_MPX_SUPPORT - bndmov %bnd0, LRV_BND0_OFFSET(%esp) - bndmov %bnd1, LRV_BND1_OFFSET(%esp) -#else - .byte 0x66,0x0f,0x1b,0x44,0x24,LRV_BND0_OFFSET - .byte 0x66,0x0f,0x1b,0x4c,0x24,LRV_BND1_OFFSET -#endif pushl %esp cfi_adjust_cfa_offset (4) # Address of La_i86_regs area. @@ -270,17 +257,9 @@ _dl_runtime_profile: movl LRV_EDX_OFFSET(%esp), %edx fldt LRV_ST1_OFFSET(%esp) fldt LRV_ST0_OFFSET(%esp) -#ifdef HAVE_MPX_SUPPORT - bndmov LRV_BND0_OFFSET(%esp), %bnd0 - bndmov LRV_BND1_OFFSET(%esp), %bnd1 -#else - .byte 0x66,0x0f,0x1a,0x44,0x24,LRV_BND0_OFFSET - .byte 0x66,0x0f,0x1a,0x4c,0x24,LRV_BND1_OFFSET -#endif # Restore stack before return. addl $(LRV_SIZE + 4 + LR_SIZE + 4), %esp cfi_adjust_cfa_offset (-(LRV_SIZE + 4 + LR_SIZE + 4)) - PRESERVE_BND_REGS_PREFIX ret cfi_endproc .size _dl_runtime_profile, .-_dl_runtime_profile diff --git a/sysdeps/i386/link-defines.sym b/sysdeps/i386/link-defines.sym index 0995adb37f..a63dcb9218 100644 --- a/sysdeps/i386/link-defines.sym +++ b/sysdeps/i386/link-defines.sym @@ -16,5 +16,3 @@ LRV_EAX_OFFSET offsetof (struct La_i86_retval, lrv_eax) LRV_EDX_OFFSET offsetof (struct La_i86_retval, lrv_edx) LRV_ST0_OFFSET offsetof (struct La_i86_retval, lrv_st0) LRV_ST1_OFFSET offsetof (struct La_i86_retval, lrv_st1) -LRV_BND0_OFFSET offsetof (struct La_i86_retval, lrv_bnd0) -LRV_BND1_OFFSET offsetof (struct La_i86_retval, lrv_bnd1) diff --git a/sysdeps/x86/bits/link.h b/sysdeps/x86/bits/link.h index 0e1db1a164..d0e1a55446 100644 --- a/sysdeps/x86/bits/link.h +++ b/sysdeps/x86/bits/link.h @@ -38,8 +38,8 @@ typedef struct La_i86_retval uint32_t lrv_edx; long double lrv_st0; long double lrv_st1; - uint64_t lrv_bnd0; - uint64_t lrv_bnd1; + uint64_t __glibc_unused1; + uint64_t __glibc_unused2; } La_i86_retval; @@ -96,7 +96,7 @@ typedef struct La_x86_64_regs La_x86_64_xmm lr_xmm[8]; La_x86_64_vector lr_vector[8]; #ifndef __ILP32__ - __int128_t lr_bnd[4]; + __int128_t __glibc_unused1[4]; #endif } La_x86_64_regs; @@ -112,8 +112,8 @@ typedef struct La_x86_64_retval La_x86_64_vector lrv_vector0; La_x86_64_vector lrv_vector1; #ifndef __ILP32__ - __int128_t lrv_bnd0; - __int128_t lrv_bnd1; + __int128_t __glibc_unused1; + __int128_t __glibc_unused2; #endif } La_x86_64_retval; diff --git a/sysdeps/x86_64/configure b/sysdeps/x86_64/configure index 585279f83d..d4dd0aa7df 100755 --- a/sysdeps/x86_64/configure +++ b/sysdeps/x86_64/configure @@ -23,33 +23,6 @@ $as_echo "$libc_cv_cc_mprefer_vector_width" >&6; } config_vars="$config_vars config-cflags-mprefer-vector-width = $libc_cv_cc_mprefer_vector_width" -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for Intel MPX support" >&5 -$as_echo_n "checking for Intel MPX support... " >&6; } -if ${libc_cv_asm_mpx+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat > conftest.s <<\EOF - bndmov %bnd0,(%rsp) -EOF -if { ac_try='${CC-cc} -c $ASFLAGS conftest.s 1>&5' - { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 - (eval $ac_try) 2>&5 - ac_status=$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; }; then - libc_cv_asm_mpx=yes -else - libc_cv_asm_mpx=no -fi -rm -f conftest* -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_mpx" >&5 -$as_echo "$libc_cv_asm_mpx" >&6; } -if test $libc_cv_asm_mpx = yes; then - $as_echo "#define HAVE_MPX_SUPPORT 1" >>confdefs.h - -fi - if test x"$build_mathvec" = xnotset; then build_mathvec=yes fi diff --git a/sysdeps/x86_64/configure.ac b/sysdeps/x86_64/configure.ac index 29e14033c0..c4c748c1d0 100644 --- a/sysdeps/x86_64/configure.ac +++ b/sysdeps/x86_64/configure.ac @@ -10,21 +10,6 @@ LIBC_TRY_CC_OPTION([-mprefer-vector-width=128], LIBC_CONFIG_VAR([config-cflags-mprefer-vector-width], [$libc_cv_cc_mprefer_vector_width]) -dnl Check whether asm supports Intel MPX -AC_CACHE_CHECK(for Intel MPX support, libc_cv_asm_mpx, [dnl -cat > conftest.s <<\EOF - bndmov %bnd0,(%rsp) -EOF -if AC_TRY_COMMAND(${CC-cc} -c $ASFLAGS conftest.s 1>&AS_MESSAGE_LOG_FD); then - libc_cv_asm_mpx=yes -else - libc_cv_asm_mpx=no -fi -rm -f conftest*]) -if test $libc_cv_asm_mpx = yes; then - AC_DEFINE(HAVE_MPX_SUPPORT) -fi - if test x"$build_mathvec" = xnotset; then build_mathvec=yes fi diff --git a/sysdeps/x86_64/dl-trampoline.S b/sysdeps/x86_64/dl-trampoline.S index 90b2a6ce56..fa71330be2 100644 --- a/sysdeps/x86_64/dl-trampoline.S +++ b/sysdeps/x86_64/dl-trampoline.S @@ -42,15 +42,6 @@ /* Area on stack to save and restore registers used for parameter passing when calling _dl_fixup. */ -#ifdef __ILP32__ -# define PRESERVE_BND_REGS_PREFIX -#else -# ifdef HAVE_MPX_SUPPORT -# define PRESERVE_BND_REGS_PREFIX bnd -# else -# define PRESERVE_BND_REGS_PREFIX .byte 0xf2 -# endif -#endif #define REGISTER_SAVE_RAX 0 #define REGISTER_SAVE_RCX (REGISTER_SAVE_RAX + 8) #define REGISTER_SAVE_RDX (REGISTER_SAVE_RCX + 8) diff --git a/sysdeps/x86_64/dl-trampoline.h b/sysdeps/x86_64/dl-trampoline.h index b9a12970cd..dfbfefbd4a 100644 --- a/sysdeps/x86_64/dl-trampoline.h +++ b/sysdeps/x86_64/dl-trampoline.h @@ -149,8 +149,6 @@ _dl_runtime_resolve: # Adjust stack(PLT did 2 pushes) add $(LOCAL_STORAGE_AREA + 16), %RSP_LP cfi_adjust_cfa_offset(-(LOCAL_STORAGE_AREA + 16)) - # Preserve bound registers. - PRESERVE_BND_REGS_PREFIX jmp *%r11 # Jump to function address. cfi_endproc .size _dl_runtime_resolve, .-_dl_runtime_resolve @@ -230,20 +228,6 @@ _dl_runtime_profile: movaps %xmm6, (LR_XMM_OFFSET + XMM_SIZE*6)(%rsp) movaps %xmm7, (LR_XMM_OFFSET + XMM_SIZE*7)(%rsp) -# ifndef __ILP32__ -# ifdef HAVE_MPX_SUPPORT - bndmov %bnd0, (LR_BND_OFFSET)(%rsp) # Preserve bound - bndmov %bnd1, (LR_BND_OFFSET + BND_SIZE)(%rsp) # registers. Nops if - bndmov %bnd2, (LR_BND_OFFSET + BND_SIZE*2)(%rsp) # MPX not available - bndmov %bnd3, (LR_BND_OFFSET + BND_SIZE*3)(%rsp) # or disabled. -# else - .byte 0x66,0x0f,0x1b,0x84,0x24;.long (LR_BND_OFFSET) - .byte 0x66,0x0f,0x1b,0x8c,0x24;.long (LR_BND_OFFSET + BND_SIZE) - .byte 0x66,0x0f,0x1b,0x94,0x24;.long (LR_BND_OFFSET + BND_SIZE*2) - .byte 0x66,0x0f,0x1b,0x9c,0x24;.long (LR_BND_OFFSET + BND_SIZE*3) -# endif -# endif - # ifdef RESTORE_AVX /* This is to support AVX audit modules. */ VMOVA %VEC(0), (LR_VECTOR_OFFSET)(%rsp) @@ -366,25 +350,10 @@ _dl_runtime_profile: vmovdqa %xmm7, (LR_XMM_OFFSET + XMM_SIZE*7)(%rsp) 1: -# endif - -# ifndef __ILP32__ -# ifdef HAVE_MPX_SUPPORT - bndmov (LR_BND_OFFSET)(%rsp), %bnd0 # Restore bound - bndmov (LR_BND_OFFSET + BND_SIZE)(%rsp), %bnd1 # registers. - bndmov (LR_BND_OFFSET + BND_SIZE*2)(%rsp), %bnd2 - bndmov (LR_BND_OFFSET + BND_SIZE*3)(%rsp), %bnd3 -# else - .byte 0x66,0x0f,0x1a,0x84,0x24;.long (LR_BND_OFFSET) - .byte 0x66,0x0f,0x1a,0x8c,0x24;.long (LR_BND_OFFSET + BND_SIZE) - .byte 0x66,0x0f,0x1a,0x94,0x24;.long (LR_BND_OFFSET + BND_SIZE*2) - .byte 0x66,0x0f,0x1a,0x9c,0x24;.long (LR_BND_OFFSET + BND_SIZE*3) -# endif # endif mov 16(%rbx), %R10_LP # Anything in framesize? test %R10_LP, %R10_LP - PRESERVE_BND_REGS_PREFIX jns 3f /* There's nothing in the frame size, so there @@ -403,7 +372,6 @@ _dl_runtime_profile: add $48, %RSP_LP # Adjust the stack to the return value # (eats the reloc index and link_map) cfi_adjust_cfa_offset(-48) - PRESERVE_BND_REGS_PREFIX jmp *%r11 # Jump to function address. 3: @@ -430,7 +398,6 @@ _dl_runtime_profile: movq 32(%rdi), %rsi movq 40(%rdi), %rdi - PRESERVE_BND_REGS_PREFIX call *%r11 mov 24(%rbx), %RSP_LP # Drop the copied stack content @@ -475,16 +442,6 @@ _dl_runtime_profile: vmovdqa %xmm1, (LRV_SIZE + XMM_SIZE)(%rcx) # endif -# ifndef __ILP32__ -# ifdef HAVE_MPX_SUPPORT - bndmov %bnd0, LRV_BND0_OFFSET(%rcx) # Preserve returned bounds. - bndmov %bnd1, LRV_BND1_OFFSET(%rcx) -# else - .byte 0x66,0x0f,0x1b,0x81;.long (LRV_BND0_OFFSET) - .byte 0x66,0x0f,0x1b,0x89;.long (LRV_BND1_OFFSET) -# endif -# endif - fstpt LRV_ST0_OFFSET(%rcx) fstpt LRV_ST1_OFFSET(%rcx) @@ -515,16 +472,6 @@ _dl_runtime_profile: VMOVA LRV_VECTOR1_OFFSET(%rsp), %VEC(1) 1: -# endif - -# ifndef __ILP32__ -# ifdef HAVE_MPX_SUPPORT - bndmov LRV_BND0_OFFSET(%rsp), %bnd0 # Restore bound registers. - bndmov LRV_BND1_OFFSET(%rsp), %bnd1 -# else - .byte 0x66,0x0f,0x1a,0x84,0x24;.long (LRV_BND0_OFFSET) - .byte 0x66,0x0f,0x1a,0x8c,0x24;.long (LRV_BND1_OFFSET) -# endif # endif fldt LRV_ST1_OFFSET(%rsp) @@ -538,7 +485,6 @@ _dl_runtime_profile: add $48, %RSP_LP # Adjust the stack to the return value # (eats the reloc index and link_map) cfi_adjust_cfa_offset(-48) - PRESERVE_BND_REGS_PREFIX retq cfi_endproc diff --git a/sysdeps/x86_64/link-defines.sym b/sysdeps/x86_64/link-defines.sym index 963c69b320..85d35ad034 100644 --- a/sysdeps/x86_64/link-defines.sym +++ b/sysdeps/x86_64/link-defines.sym @@ -6,7 +6,6 @@ VECTOR_SIZE sizeof (La_x86_64_vector) XMM_SIZE sizeof (La_x86_64_xmm) YMM_SIZE sizeof (La_x86_64_ymm) ZMM_SIZE sizeof (La_x86_64_zmm) -BND_SIZE sizeof (__int128_t) LR_SIZE sizeof (struct La_x86_64_regs) LR_RDX_OFFSET offsetof (struct La_x86_64_regs, lr_rdx) @@ -19,9 +18,6 @@ LR_RBP_OFFSET offsetof (struct La_x86_64_regs, lr_rbp) LR_RSP_OFFSET offsetof (struct La_x86_64_regs, lr_rsp) LR_XMM_OFFSET offsetof (struct La_x86_64_regs, lr_xmm) LR_VECTOR_OFFSET offsetof (struct La_x86_64_regs, lr_vector) -#ifndef __ILP32__ -LR_BND_OFFSET offsetof (struct La_x86_64_regs, lr_bnd) -#endif LRV_SIZE sizeof (struct La_x86_64_retval) LRV_RAX_OFFSET offsetof (struct La_x86_64_retval, lrv_rax) @@ -32,7 +28,3 @@ LRV_ST0_OFFSET offsetof (struct La_x86_64_retval, lrv_st0) LRV_ST1_OFFSET offsetof (struct La_x86_64_retval, lrv_st1) LRV_VECTOR0_OFFSET offsetof (struct La_x86_64_retval, lrv_vector0) LRV_VECTOR1_OFFSET offsetof (struct La_x86_64_retval, lrv_vector1) -#ifndef __ILP32__ -LRV_BND0_OFFSET offsetof (struct La_x86_64_retval, lrv_bnd0) -LRV_BND1_OFFSET offsetof (struct La_x86_64_retval, lrv_bnd1) -#endif