From patchwork Sun Oct 10 23:05:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fangrui Song X-Patchwork-Id: 46049 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E7D0F3858415 for ; Sun, 10 Oct 2021 23:06:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by sourceware.org (Postfix) with ESMTPS id 39A593858D28 for ; Sun, 10 Oct 2021 23:06:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 39A593858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=maskray.me Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pl1-f172.google.com with SMTP id a11so10041135plm.0 for ; Sun, 10 Oct 2021 16:06:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=XMupK4qeNOALsm+O+eednM7oy4bChcQMZdLdr/0E3YU=; b=amOmL85rVScQxF5kiODiKXo7SxOU+IFOaSNUmkgBG2/FKga+omejFEqLOgZHYWea7Z XGPOr3/yjlxqNm9cnrdRfTiWJdqMzfXozM+fFX2aZtxbJTDLXrdT+6ND7FqbOYYeekGf 2nr5IYsBJ5oV2R90vP45d02alRvzpw3r41qjefhxrzGWcyAGvX9pjmTMoqMl+wWKY314 evFx4ibcOtdTiMHdIJpePejurzkRlDx1jtmDgvaLScw1GIQaO7sJ9JA1AiXMWko5DzqF JG6w+c3vdhFnqHkzUlnn0XqXkRRon7l59fz8R2QPPnbz6crbhK+dkf1uetuhIzGdm+BK vzzQ== X-Gm-Message-State: AOAM530+PHQ9SOP0F9NgX3GyL0nVqIO+C52mx4xnujHv9+qp51FEQgsF /Ua20TaTosfKraupghevlZS0og0XCzs= X-Google-Smtp-Source: ABdhPJzQDJqEY7SNHjxA4SCiss7YQyT0R79j238YD3Qj4YaXtbL3bj6t/nSW87+lnrufvfUwaVCNpQ== X-Received: by 2002:a17:902:e144:b0:13f:4b7:68c0 with SMTP id d4-20020a170902e14400b0013f04b768c0mr21143023pla.77.1633907167480; Sun, 10 Oct 2021 16:06:07 -0700 (PDT) Received: from localhost ([2601:647:6300:b760:401a:d197:665:fed0]) by smtp.gmail.com with ESMTPSA id j12sm5460017pff.127.2021.10.10.16.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 16:06:07 -0700 (PDT) From: Fangrui Song To: gcc-patches@gcc.gnu.org Subject: [PATCH] include/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints Date: Sun, 10 Oct 2021 16:05:43 -0700 Message-Id: <20211010230543.1039276-1-i@maskray.me> MIME-Version: 1.0 X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_INFOUSMEBIZ, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TO_NO_BRKTS_PCNT, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Pinski , Fangrui Song Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" An output constraint takes a lvalue. While GCC happily strips the incorrect lvalue to rvalue conversion, Clang rejects the code by default: error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions The file appears to share the same origin with gmplib longlong.h but they differ much now (gmplib version is much longer). I don't have write access to the git repo. --- include/longlong.h | 186 ++++++++++++++++++++++----------------------- 1 file changed, 93 insertions(+), 93 deletions(-) diff --git a/include/longlong.h b/include/longlong.h index c3e92e54ecc..0a21a441d2d 100644 --- a/include/longlong.h +++ b/include/longlong.h @@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); #if defined (__arc__) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%r" ((USItype) (ah)), \ "rICal" ((USItype) (bh)), \ "%r" ((USItype) (al)), \ @@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); : "cc") #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "r" ((USItype) (ah)), \ "rICal" ((USItype) (bh)), \ "r" ((USItype) (al)), \ @@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%r" ((USItype) (ah)), \ "rI" ((USItype) (bh)), \ "%r" ((USItype) (al)), \ "rI" ((USItype) (bl)) __CLOBBER_CC) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "r" ((USItype) (ah)), \ "rI" ((USItype) (bh)), \ "r" ((USItype) (al)), \ @@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); " addcs %0, %0, #65536\n" \ " adds %1, %1, %3, lsl #16\n" \ " adc %0, %0, %3, lsr #16" \ - : "=&r" ((USItype) (xh)), \ - "=r" ((USItype) (xl)), \ + : "=&r" (xh), \ + "=r" (xl), \ "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ : "r" ((USItype) (a)), \ "r" ((USItype) (b)) __CLOBBER_CC ); \ @@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__hppa) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%rM" ((USItype) (ah)), \ "rM" ((USItype) (bh)), \ "%rM" ((USItype) (al)), \ "rM" ((USItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "rM" ((USItype) (ah)), \ "rM" ((USItype) (bh)), \ "rM" ((USItype) (al)), \ @@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype); #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%0" ((USItype) (ah)), \ "g" ((USItype) (bh)), \ "%1" ((USItype) (al)), \ "g" ((USItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "0" ((USItype) (ah)), \ "g" ((USItype) (bh)), \ "1" ((USItype) (al)), \ "g" ((USItype) (bl))) #define umul_ppmm(w1, w0, u, v) \ __asm__ ("mul{l} %3" \ - : "=a" ((USItype) (w0)), \ - "=d" ((USItype) (w1)) \ + : "=a" (w0), \ + "=d" (w1) \ : "%0" ((USItype) (u)), \ "rm" ((USItype) (v))) #define udiv_qrnnd(q, r, n1, n0, dv) \ __asm__ ("div{l} %4" \ - : "=a" ((USItype) (q)), \ - "=d" ((USItype) (r)) \ + : "=a" (q), \ + "=d" (r) \ : "0" ((USItype) (n0)), \ "1" ((USItype) (n1)), \ "rm" ((USItype) (dv))) @@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__x86_64__) && W_TYPE_SIZE == 64 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \ - : "=r" ((UDItype) (sh)), \ - "=&r" ((UDItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%0" ((UDItype) (ah)), \ "rme" ((UDItype) (bh)), \ "%1" ((UDItype) (al)), \ "rme" ((UDItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \ - : "=r" ((UDItype) (sh)), \ - "=&r" ((UDItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "0" ((UDItype) (ah)), \ "rme" ((UDItype) (bh)), \ "1" ((UDItype) (al)), \ "rme" ((UDItype) (bl))) #define umul_ppmm(w1, w0, u, v) \ __asm__ ("mul{q} %3" \ - : "=a" ((UDItype) (w0)), \ - "=d" ((UDItype) (w1)) \ + : "=a" (w0), \ + "=d" (w1) \ : "%0" ((UDItype) (u)), \ "rm" ((UDItype) (v))) #define udiv_qrnnd(q, r, n1, n0, dv) \ __asm__ ("div{q} %4" \ - : "=a" ((UDItype) (q)), \ - "=d" ((UDItype) (r)) \ + : "=a" (q), \ + "=d" (r) \ : "0" ((UDItype) (n0)), \ "1" ((UDItype) (n1)), \ "rm" ((UDItype) (dv))) @@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype); #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ /* The cmp clears the condition bit. */ \ __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "0" ((USItype) (ah)), \ "r" ((USItype) (bh)), \ "1" ((USItype) (al)), \ @@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype); #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ /* The cmp clears the condition bit. */ \ __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "0" ((USItype) (ah)), \ "r" ((USItype) (bh)), \ "1" ((USItype) (al)), \ @@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__mc68000__) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \ - : "=d" ((USItype) (sh)), \ - "=&d" ((USItype) (sl)) \ + : "=d" (sh), \ + "=&d" (sl) \ : "%0" ((USItype) (ah)), \ "d" ((USItype) (bh)), \ "%1" ((USItype) (al)), \ "g" ((USItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \ - : "=d" ((USItype) (sh)), \ - "=&d" ((USItype) (sl)) \ + : "=d" (sh), \ + "=&d" (sl) \ : "0" ((USItype) (ah)), \ "d" ((USItype) (bh)), \ "1" ((USItype) (al)), \ @@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype); #if (defined (__mc68020__) && !defined (__mc68060__)) #define umul_ppmm(w1, w0, u, v) \ __asm__ ("mulu%.l %3,%1:%0" \ - : "=d" ((USItype) (w0)), \ - "=d" ((USItype) (w1)) \ + : "=d" (w0), \ + "=d" (w1) \ : "%0" ((USItype) (u)), \ "dmi" ((USItype) (v))) #define UMUL_TIME 45 #define udiv_qrnnd(q, r, n1, n0, d) \ __asm__ ("divu%.l %4,%1:%0" \ - : "=d" ((USItype) (q)), \ - "=d" ((USItype) (r)) \ + : "=d" (q), \ + "=d" (r) \ : "0" ((USItype) (n0)), \ "1" ((USItype) (n1)), \ "dmi" ((USItype) (d))) #define UDIV_TIME 90 #define sdiv_qrnnd(q, r, n1, n0, d) \ __asm__ ("divs%.l %4,%1:%0" \ - : "=d" ((USItype) (q)), \ - "=d" ((USItype) (r)) \ + : "=d" (q), \ + "=d" (r) \ : "0" ((USItype) (n0)), \ "1" ((USItype) (n1)), \ "dmi" ((USItype) (d))) @@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype); " move%.l %/d2,%1\n" \ " add%.l %/d1,%/d0\n" \ " move%.l %/d0,%0" \ - : "=g" ((USItype) (xh)), \ - "=g" ((USItype) (xl)) \ + : "=g" (xh)), \ + "=g" (xl) \ : "g" ((USItype) (a)), \ "g" ((USItype) (b)) \ : "d0", "d1", "d2", "d3", "d4") @@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype); " move%.l %/d2,%1\n" \ " add%.l %/d1,%/d0\n" \ " move%.l %/d0,%0" \ - : "=g" ((USItype) (xh)), \ - "=g" ((USItype) (xl)) \ + : "=g" (xh)), \ + "=g" (xl) \ : "g" ((USItype) (a)), \ "g" ((USItype) (b)) \ : "d0", "d1", "d2", "d3", "d4") @@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__mc68020__) && !defined (__mcpu32__) #define count_leading_zeros(count, x) \ __asm__ ("bfffo %1{%b2:%b2},%0" \ - : "=d" ((USItype) (count)) \ + : "=d" (count) \ : "od" ((USItype) (x)), "n" (0)) /* Some ColdFire architectures have a ff1 instruction supported via __builtin_clz. */ @@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__m88000__) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%rJ" ((USItype) (ah)), \ "rJ" ((USItype) (bh)), \ "%rJ" ((USItype) (al)), \ "rJ" ((USItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "rJ" ((USItype) (ah)), \ "rJ" ((USItype) (bh)), \ "rJ" ((USItype) (al)), \ @@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("a %1,%5\n\tae %0,%3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%0" ((USItype) (ah)), \ "r" ((USItype) (bh)), \ "%1" ((USItype) (al)), \ "r" ((USItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("s %1,%5\n\tse %0,%3" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "0" ((USItype) (ah)), \ "r" ((USItype) (bh)), \ "1" ((USItype) (al)), \ @@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype); " m r2,%3\n" \ " cas %0,r2,r0\n" \ " mfs r10,%1" \ - : "=r" ((USItype) (ph)), \ - "=r" ((USItype) (pl)) \ + : "=r" (ph), \ + "=r" (pl) \ : "%r" (__m0), \ "r" (__m1) \ : "r2"); \ @@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype); do { \ if ((x) >= 0x10000) \ __asm__ ("clz %0,%1" \ - : "=r" ((USItype) (count)) \ + : "=r" (count) \ : "r" ((USItype) (x) >> 16)); \ else \ { \ __asm__ ("clz %0,%1" \ - : "=r" ((USItype) (count)) \ + : "=r" (count) \ : "r" ((USItype) (x))); \ (count) += 16; \ } \ @@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype); #define umul_ppmm(w1, w0, u, v) \ __asm__ ( \ "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \ - : "=r<" ((USItype)(w1)), \ - "=r<" ((USItype)(w0)) \ + : "=r<" (w1), \ + "=r<" (w0) \ : "r" ((USItype)(u)), \ "r" ((USItype)(v)) \ : "macl", "mach") @@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype); && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%rJ" ((USItype) (ah)), \ "rI" ((USItype) (bh)), \ "%rJ" ((USItype) (al)), \ @@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype); __CLOBBER_CC) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \ - : "=r" ((USItype) (sh)), \ - "=&r" ((USItype) (sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "rJ" ((USItype) (ah)), \ "rI" ((USItype) (bh)), \ "rJ" ((USItype) (al)), \ @@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype); register USItype __g1 asm ("g1"); \ __asm__ ("umul\t%2,%3,%1\n\t" \ "srlx\t%1, 32, %0" \ - : "=r" ((USItype) (w1)), \ + : "=r" (w1), \ "=r" (__g1) \ : "r" ((USItype) (u)), \ "r" ((USItype) (v))); \ @@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype); "udiv\t%3,%4,%0\n\t" \ "umul\t%0,%4,%1\n\t" \ "sub\t%3,%1,%1" \ - : "=&r" ((USItype) (__q)), \ - "=&r" ((USItype) (__r)) \ + : "=&r" (__q), \ + "=&r" (__r) \ : "r" ((USItype) (__n1)), \ "r" ((USItype) (__n0)), \ "r" ((USItype) (__d))) @@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__sparc_v8__) #define umul_ppmm(w1, w0, u, v) \ __asm__ ("umul %2,%3,%1;rd %%y,%0" \ - : "=r" ((USItype) (w1)), \ - "=r" ((USItype) (w0)) \ + : "=r" (w1), \ + "=r" (w0) \ : "r" ((USItype) (u)), \ "r" ((USItype) (v))) #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\ - : "=&r" ((USItype) (__q)), \ - "=&r" ((USItype) (__r)) \ + : "=&r" (__q), \ + "=&r" (__r) \ : "r" ((USItype) (__n1)), \ "r" ((USItype) (__n0)), \ "r" ((USItype) (__d))) @@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype); instructions scan (ffs from high bit) and divscc. */ #define umul_ppmm(w1, w0, u, v) \ __asm__ ("umul %2,%3,%1;rd %%y,%0" \ - : "=r" ((USItype) (w1)), \ - "=r" ((USItype) (w0)) \ + : "=r" (w1), \ + "=r" (w0) \ : "r" ((USItype) (u)), \ "r" ((USItype) (v))) #define udiv_qrnnd(q, r, n1, n0, d) \ @@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype); " bl,a 1f\n" \ " add %1,%4,%1\n" \ "1: ! End of inline udiv_qrnnd" \ - : "=r" ((USItype) (q)), \ - "=r" ((USItype) (r)) \ + : "=r" (q), \ + "=r" (r) \ : "r" ((USItype) (n1)), \ "r" ((USItype) (n0)), \ "rI" ((USItype) (d)) \ @@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype); #define count_leading_zeros(count, x) \ do { \ __asm__ ("scan %1,1,%0" \ - : "=r" ((USItype) (count)) \ + : "=r" (count) \ : "r" ((USItype) (x))); \ } while (0) /* Early sparclites return 63 for an argument of 0, but they warn that future @@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype); " mulscc %%g1,0,%%g1\n" \ " add %%g1,%%o5,%0\n" \ " rd %%y,%1" \ - : "=r" ((USItype) (w1)), \ - "=r" ((USItype) (w0)) \ + : "=r" (w1), \ + "=r" (w0) \ : "%rI" ((USItype) (u)), \ "r" ((USItype) (v)) \ : "g1", "o5" __AND_CLOBBER_CC) @@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype); " sub %1,%2,%1\n" \ "3: xnor %0,0,%0\n" \ " ! End of inline udiv_qrnnd" \ - : "=&r" ((USItype) (__q)), \ - "=&r" ((USItype) (__r)) \ + : "=&r" (__q), \ + "=&r" (__r) \ : "r" ((USItype) (__d)), \ "1" ((USItype) (__n1)), \ "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC) @@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype); "add\t%r3,%4,%0\n\t" \ "movcs\t%%xcc, 1, %2\n\t" \ "add\t%0, %2, %0" \ - : "=r" ((UDItype)(sh)), \ - "=&r" ((UDItype)(sl)), \ + : "=r" (sh), \ + "=&r" (sl), \ "+r" (__carry) \ : "%rJ" ((UDItype)(ah)), \ "rI" ((UDItype)(bh)), \ @@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype); "sub\t%r3,%4,%0\n\t" \ "movcs\t%%xcc, 1, %2\n\t" \ "sub\t%0, %2, %0" \ - : "=r" ((UDItype)(sh)), \ - "=&r" ((UDItype)(sl)), \ + : "=r" (sh), \ + "=&r" (sl), \ "+r" (__carry) \ : "%rJ" ((UDItype)(ah)), \ "rI" ((UDItype)(bh)), \ @@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype); "sllx %3,32,%3\n\t" \ "add %1,%3,%1\n\t" \ "add %5,%2,%0" \ - : "=r" ((UDItype)(wh)), \ - "=&r" ((UDItype)(wl)), \ + : "=r" (wh), \ + "=&r" (wl), \ "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ : "r" ((UDItype)(u)), \ "r" ((UDItype)(v)) \ @@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype); #if defined (__vax__) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \ - : "=g" ((USItype) (sh)), \ - "=&g" ((USItype) (sl)) \ + : "=g" (sh)), \ + "=&g" (sl) \ : "%0" ((USItype) (ah)), \ "g" ((USItype) (bh)), \ "%1" ((USItype) (al)), \ "g" ((USItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \ - : "=g" ((USItype) (sh)), \ - "=&g" ((USItype) (sl)) \ + : "=g" (sh)), \ + "=&g" (sl) \ : "0" ((USItype) (ah)), \ "g" ((USItype) (bh)), \ "1" ((USItype) (al)), \