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Fri, 19 Jul 2024 12:14:48 +0000 From: Srinath Parvathaneni To: CC: , , Srinath Parvathaneni Subject: [PATCH v2 1/5] aarch64: Add support for FEAT_SVE_B16B16 feature. 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In the new spec available here[1], FEAT_B16B16 is replaced with FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16". This patch supports the SVE Z-targeting non-widening BFloat16 instructions with command line flag "+sve-b16b16+sve2". [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en --- gas/config/tc-aarch64.c | 5 +- .../gas/aarch64/bfloat16-1-invalid.d | 2 +- gas/testsuite/gas/aarch64/bfloat16-1.d | 3 +- .../gas/aarch64/bfloat16-2-invalid.d | 3 +- include/opcode/aarch64.h | 6 ++- opcodes/aarch64-tbl.h | 48 +++++++++---------- 6 files changed, 33 insertions(+), 34 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index e94a0cff406..4249374cf64 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10721,9 +10721,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"rasv2", AARCH64_FEATURE (RASv2), AARCH64_FEATURE (RAS)}, {"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES}, {"d128", AARCH64_FEATURE (D128), D128_FEATURE_DEPS}, - // Feature b16b16 is currently incomplete. - // TODO: finish implementation and enable relevant flags. - //{"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)}, + {"sve-b16b16", AARCH64_FEATURE (SVE_B16B16), AARCH64_NO_FEATURES}, {"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)}, {"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)}, {"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)}, @@ -10766,6 +10764,7 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = { {AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)}, /* TODO: Add SME_F16F16->SME_F16F16_F8F16 when SME_F16F16 is added. */ {AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)}, + {AARCH64_FEATURES (2, SVE_B16B16, SVE2), AARCH64_FEATURE (SVE_SVE2_B16B16)}, }; static aarch64_feature_set diff --git a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d index 531a59717c8..a5cd4479b6e 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d +++ b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d @@ -1,4 +1,4 @@ -#name: Negative test with missing +b16b16 flag. +#name: Negative test with missing +sve-b16b16 flag. #as: -march=armv9.4-a #source: bfloat16-1-invalid.s #error_output: bfloat16-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d index 68a47f5afc5..5581b4ef11e 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-1.d +++ b/gas/testsuite/gas/aarch64/bfloat16-1.d @@ -1,7 +1,6 @@ #name: Test of SVE2.1 and SME2.1 non-widening BFloat16 instructions. -#as: -march=armv9.4-a+b16b16 +#as: -march=armv9.4-a+sve-b16b16 #objdump: -dr -#xfail: *-*-* [^:]+: file format .* diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d index 1e1b701c0e3..e939878ccbe 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d +++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d @@ -1,5 +1,4 @@ #name: Test Bfloat16 instructions with wrong operand combinations -#as: -march=armv9.4-a+b16b16 +#as: -march=armv9.4-a+sve-b16b16 #source: bfloat16-2-invalid.s #error_output: bfloat16-2-invalid.l -#xfail: *-*-* diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index bc779c973d6..72b48183882 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -226,8 +226,6 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SPMU2, /* Performance Monitors Synchronous-Exception-Based Event Extension. */ AARCH64_FEATURE_SEBEP, - /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */ - AARCH64_FEATURE_B16B16, /* SME2.1 instructions. */ AARCH64_FEATURE_SME2p1, /* SVE2.1 instructions. */ @@ -264,6 +262,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_F8F32, /* SME F8F16 instructions. */ AARCH64_FEATURE_SME_F8F16, + /* SVE2 non-widening BFloat16 instructions. */ + AARCH64_FEATURE_SVE_B16B16, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -277,6 +277,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_F16F16_F8F16, /* Armv9.5-A processors. */ AARCH64_FEATURE_V9_5A, + /* +sve-b16b16+sve2. */ + AARCH64_FEATURE_SVE_SVE2_B16B16, AARCH64_NUM_FEATURES }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 172c9a44845..ea30fb31ba5 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2811,8 +2811,8 @@ static const aarch64_feature_set aarch64_feature_the = AARCH64_FEATURE (THE); static const aarch64_feature_set aarch64_feature_d128_the = AARCH64_FEATURES (2, D128, THE); -static const aarch64_feature_set aarch64_feature_b16b16_sve2 = - AARCH64_FEATURES (2, B16B16, SVE2); +static const aarch64_feature_set aarch64_feature_sve_sve2_b16b16 = + AARCH64_FEATURES (3, SVE_B16B16, SVE2, SVE_SVE2_B16B16); static const aarch64_feature_set aarch64_feature_sme2p1 = AARCH64_FEATURE (SME2p1); static const aarch64_feature_set aarch64_feature_sve2p1 = @@ -2923,7 +2923,7 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = #define D128 &aarch64_feature_d128 #define THE &aarch64_feature_the #define D128_THE &aarch64_feature_d128_the -#define B16B16_SVE2 &aarch64_feature_b16b16_sve2 +#define SVE_SVE2_B16B16 &aarch64_feature_sve_sve2_b16b16 #define SME2p1 &aarch64_feature_sme2p1 #define SVE2p1 &aarch64_feature_sve2p1 #define RCPC3 &aarch64_feature_rcpc3 @@ -3020,11 +3020,11 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } -#define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \ +#define SVE_SVE2_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE_SVE2_B16B16, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } -#define B16B16_SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ - { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \ +#define SVE_SVE2_B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE_SVE2_B16B16, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \ @@ -6625,23 +6625,23 @@ const struct aarch64_opcode aarch64_opcode_table[] = D128_THE_INSN("rcwsswppal", 0x59e0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), -/* BFloat16 SVE Instructions. */ - B16B16_SVE2_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), - B16B16_SVE2_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), - B16B16_SVE2_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), - B16B16_SVE2_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), - B16B16_SVE2_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), - B16B16_SVE2_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0), - B16B16_SVE2_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0), - B16B16_SVE2_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), - B16B16_SVE2_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), - B16B16_SVE2_INSNC("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0), - B16B16_SVE2_INSNC("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), - B16B16_SVE2_INSNC("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), - B16B16_SVE2_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0), - B16B16_SVE2_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0), - B16B16_SVE2_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0), - B16B16_SVE2_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0), +/* SVE Z-targeting non-widening BFloat16 instructions. */ + SVE_SVE2_B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), + SVE_SVE2_B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), + SVE_SVE2_B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), + SVE_SVE2_B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), + SVE_SVE2_B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), + SVE_SVE2_B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0), + SVE_SVE2_B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0), + SVE_SVE2_B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), + SVE_SVE2_B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2), + SVE_SVE2_B16B16_INSNC("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0), + SVE_SVE2_B16B16_INSNC("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), + SVE_SVE2_B16B16_INSNC("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0), + SVE_SVE2_B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0), + SVE_SVE2_B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0), + SVE_SVE2_B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0), + SVE_SVE2_B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0), /* SME2.1 movaz instructions. */ SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0), From patchwork Fri Jul 19 12:14:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 94212 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ADCDB3861826 for ; Fri, 19 Jul 2024 12:16:03 +0000 (GMT) X-Original-To: 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support for FEAT_SVE_B16B16 min and max instructions. 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The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en --- gas/config/tc-aarch64.c | 2 + .../gas/aarch64/bfloat16-2-invalid.l | 4 +- .../gas/aarch64/bfloat16-sme2-2-bad.d | 4 + .../gas/aarch64/bfloat16-sme2-2-bad.l | 159 ++++++++++++++++++ .../gas/aarch64/bfloat16-sme2-2-bad.s | 136 +++++++++++++++ gas/testsuite/gas/aarch64/bfloat16-sme2-2.d | 122 ++++++++++++++ gas/testsuite/gas/aarch64/bfloat16-sme2-2.s | 138 +++++++++++++++ include/opcode/aarch64.h | 2 + opcodes/aarch64-tbl.h | 29 ++++ 9 files changed, 594 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.d create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.l create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.s create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-2.d create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-2.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 4249374cf64..0699bd0eaed 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10765,6 +10765,8 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = { /* TODO: Add SME_F16F16->SME_F16F16_F8F16 when SME_F16F16 is added. */ {AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)}, {AARCH64_FEATURES (2, SVE_B16B16, SVE2), AARCH64_FEATURE (SVE_SVE2_B16B16)}, + {AARCH64_FEATURES (2, SVE_B16B16, SME2), AARCH64_FEATURES (2, SVE_SME2_B16B16, + SVE_SVE2_B16B16)}, }; static aarch64_feature_set diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l index 5da96c72ae5..7742e9d4865 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l +++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l @@ -183,8 +183,8 @@ .*: Error: operand mismatch -- `bfclamp z31.b,z31.s,z31.d' .*: Info: did you mean this\? .*: Info: bfclamp z31.h, z31.h, z31.h -.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h},z0.h,z0.h' -.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h-z0.h},z0.h' +.*: Error: expected a list of 2 or 4 registers at operand 1 -- `bfclamp {z0.h},z0.h,z0.h' +.*: Error: invalid range in vector register list at operand 1 -- `bfclamp {z0.h-z0.h},z0.h' .*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h' .*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]' .*: Info: did you mean this\? diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.d b/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.d new file mode 100644 index 00000000000..0ec94674a4a --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.d @@ -0,0 +1,4 @@ +#name: Test of invalid SME2 non-widening BFloat16 min max instructions. +#as: -march=armv9.4-a+sve-b16b16+sme2 +#source: bfloat16-sme2-2-bad.s +#error_output: bfloat16-sme2-2-bad.l diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.l b/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.l new file mode 100644 index 00000000000..657f87d002a --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.l @@ -0,0 +1,159 @@ +.*: Assembler messages: +.*: Error: too many registers in vector register list at operand 2 -- `bfmax {z30.h-z31.h},{z0.h-z31.h},z0.h' +.*: Error: z0-z15 expected at operand 3 -- `bfmax {z0.h-z1.h},{z0.h-z1.h},z16.h' +.*: Error: operand mismatch -- `bfmax {z14.s-z15.s},{z14.s-z15.s},z1.h' +.*: Info: did you mean this\? +.*: Info: bfmax {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z2.h-z7.h},{z30.h-z7.h},z3.d' +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z4.h-z3.h},{z4.h-z3.h},z7.b' +.*: Error: operand mismatch -- `bfmax {z28.h-z31.h},{z28.s-z31.h},z0.h' +.*: Info: did you mean this\? +.*: Info: bfmax {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: Error: z0-z15 expected at operand 3 -- `bfmax {z0.h-z3.h},{z0.h-z3.h},z16.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z10.h-z15.h},{z10.h-z15.h},z1.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z14.h-z7.h},{z4.h-z7.h},z3.s' +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z4.h-z17.h},{z1.h-z7.h},z17.b' +.*: Error: operand mismatch -- `bfmax {z0.s-z1.h},{z0.h-z1.h},{z0.h-z1.h}' +.*: Info: did you mean this\? +.*: Info: bfmax {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: Error: invalid range in vector register list at operand 2 -- `bfmax {z30.h-z31.h},{z31.s-z31.h},{z0.h-z1.h}' +.*: Error: operand mismatch -- `bfmax {z0.h-z1.h},{z0.h-z1.h},{z30.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfmax {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfmax {z14.h-z15.h},{z14.h-z15.h},{z14.s-z10.s}' +.*: Error: operand 2 must be the same register as operand 1 -- `bfmax {z6.h-z7.h},{z16.h-z17.h},{z30.h-z31.h}' +.*: Error: comma expected between operands at operand 3 -- `bfmax {z2.h-z3.h},{z2.h-z3.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z20.h-z31.h},{z0.h-z3.h},{z0.h-z3.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfmax {z28.h-z31.h},{z21.s-z31.s},{z0.h-z3.h}' +.*: Error: operand mismatch -- `bfmax {z0.h-z3.h},{z0.h-z3.h},{z28.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfmax {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfmax {z12.h-z15.h},{z12.h-z15.h},{z10.h-z25.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z4.h-z17.h},{z4.h-z7.h},{z14.h-z17.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmax {z14.h-z7.h},{z4.s-z7.b},{z10.h-z3.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfmaxnm {z30.h-z31.h},{z0.h-z31.h},z0.h' +.*: Error: z0-z15 expected at operand 3 -- `bfmaxnm {z0.h-z1.h},{z0.h-z1.h},z16.h' +.*: Error: operand mismatch -- `bfmaxnm {z14.s-z15.s},{z14.s-z15.s},z1.h' +.*: Info: did you mean this\? +.*: Info: bfmaxnm {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z2.h-z7.h},{z30.h-z7.h},z3.d' +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z4.h-z3.h},{z4.h-z3.h},z7.b' +.*: Error: operand mismatch -- `bfmaxnm {z28.h-z31.h},{z28.s-z31.h},z0.h' +.*: Info: did you mean this\? +.*: Info: bfmaxnm {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: Error: z0-z15 expected at operand 3 -- `bfmaxnm {z0.h-z3.h},{z0.h-z3.h},z16.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z10.h-z15.h},{z10.h-z15.h},z1.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z14.h-z7.h},{z4.h-z7.h},z3.s' +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z4.h-z17.h},{z1.h-z7.h},z17.b' +.*: Error: operand mismatch -- `bfmaxnm {z0.s-z1.h},{z0.h-z1.h},{z0.h-z1.h}' +.*: Info: did you mean this\? +.*: Info: bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: Error: invalid range in vector register list at operand 2 -- `bfmaxnm {z30.h-z31.h},{z31.s-z31.h},{z0.h-z1.h}' +.*: Error: operand mismatch -- `bfmaxnm {z0.h-z1.h},{z0.h-z1.h},{z30.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfmaxnm {z14.h-z15.h},{z14.h-z15.h},{z14.s-z10.s}' +.*: Error: operand 2 must be the same register as operand 1 -- `bfmaxnm {z6.h-z7.h},{z16.h-z17.h},{z30.h-z31.h}' +.*: Error: comma expected between operands at operand 3 -- `bfmaxnm {z2.h-z3.h},{z2.h-z3.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z20.h-z31.h},{z0.h-z3.h},{z0.h-z3.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfmaxnm {z28.h-z31.h},{z21.s-z31.s},{z0.h-z3.h}' +.*: Error: operand mismatch -- `bfmaxnm {z0.h-z3.h},{z0.h-z3.h},{z28.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfmaxnm {z12.h-z15.h},{z12.h-z15.h},{z10.h-z25.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z4.h-z17.h},{z4.h-z7.h},{z14.h-z17.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmaxnm {z14.h-z7.h},{z4.s-z7.b},{z10.h-z3.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfmin {z30.h-z31.h},{z0.h-z31.h},z0.h' +.*: Error: z0-z15 expected at operand 3 -- `bfmin {z0.h-z1.h},{z0.h-z1.h},z16.h' +.*: Error: operand mismatch -- `bfmin {z14.s-z15.s},{z14.s-z15.s},z1.h' +.*: Info: did you mean this\? +.*: Info: bfmin {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z2.h-z7.h},{z30.h-z7.h},z3.d' +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z4.h-z3.h},{z4.h-z3.h},z7.b' +.*: Error: operand mismatch -- `bfmin {z28.h-z31.h},{z28.s-z31.h},z0.h' +.*: Info: did you mean this\? +.*: Info: bfmin {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: Error: z0-z15 expected at operand 3 -- `bfmin {z0.h-z3.h},{z0.h-z3.h},z16.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z10.h-z15.h},{z10.h-z15.h},z1.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z14.h-z7.h},{z4.h-z7.h},z3.s' +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z4.h-z17.h},{z1.h-z7.h},z17.b' +.*: Error: operand mismatch -- `bfmin {z0.s-z1.h},{z0.h-z1.h},{z0.h-z1.h}' +.*: Info: did you mean this\? +.*: Info: bfmin {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: Error: invalid range in vector register list at operand 2 -- `bfmin {z30.h-z31.h},{z31.s-z31.h},{z0.h-z1.h}' +.*: Error: operand mismatch -- `bfmin {z0.h-z1.h},{z0.h-z1.h},{z30.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfmin {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfmin {z14.h-z15.h},{z14.h-z15.h},{z14.s-z10.s}' +.*: Error: operand 2 must be the same register as operand 1 -- `bfmin {z6.h-z7.h},{z16.h-z17.h},{z30.h-z31.h}' +.*: Error: comma expected between operands at operand 3 -- `bfmin {z2.h-z3.h},{z2.h-z3.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z20.h-z31.h},{z0.h-z3.h},{z0.h-z3.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfmin {z28.h-z31.h},{z21.s-z31.s},{z0.h-z3.h}' +.*: Error: operand mismatch -- `bfmin {z0.h-z3.h},{z0.h-z3.h},{z28.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfmin {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfmin {z12.h-z15.h},{z12.h-z15.h},{z10.h-z25.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z4.h-z17.h},{z4.h-z7.h},{z14.h-z17.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfmin {z14.h-z7.h},{z4.s-z7.b},{z10.h-z3.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfminnm {z30.h-z31.h},{z0.h-z31.h},z0.h' +.*: Error: z0-z15 expected at operand 3 -- `bfminnm {z0.h-z1.h},{z0.h-z1.h},z16.h' +.*: Error: operand mismatch -- `bfminnm {z14.s-z15.s},{z14.s-z15.s},z1.h' +.*: Info: did you mean this\? +.*: Info: bfminnm {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z2.h-z7.h},{z30.h-z7.h},z3.d' +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z4.h-z3.h},{z4.h-z3.h},z7.b' +.*: Error: operand mismatch -- `bfminnm {z28.h-z31.h},{z28.s-z31.h},z0.h' +.*: Info: did you mean this\? +.*: Info: bfminnm {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: Error: z0-z15 expected at operand 3 -- `bfminnm {z0.h-z3.h},{z0.h-z3.h},z16.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z10.h-z15.h},{z10.h-z15.h},z1.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z14.h-z7.h},{z4.h-z7.h},z3.s' +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z4.h-z17.h},{z1.h-z7.h},z17.b' +.*: Error: operand mismatch -- `bfminnm {z0.s-z1.h},{z0.h-z1.h},{z0.h-z1.h}' +.*: Info: did you mean this\? +.*: Info: bfminnm {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: Error: invalid range in vector register list at operand 2 -- `bfminnm {z30.h-z31.h},{z31.s-z31.h},{z0.h-z1.h}' +.*: Error: operand mismatch -- `bfminnm {z0.h-z1.h},{z0.h-z1.h},{z30.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfminnm {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfminnm {z14.h-z15.h},{z14.h-z15.h},{z14.s-z10.s}' +.*: Error: operand 2 must be the same register as operand 1 -- `bfminnm {z6.h-z7.h},{z16.h-z17.h},{z30.h-z31.h}' +.*: Error: comma expected between operands at operand 3 -- `bfminnm {z2.h-z3.h},{z2.h-z3.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z20.h-z31.h},{z0.h-z3.h},{z0.h-z3.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfminnm {z28.h-z31.h},{z21.s-z31.s},{z0.h-z3.h}' +.*: Error: operand mismatch -- `bfminnm {z0.h-z3.h},{z0.h-z3.h},{z28.b-z31.b}' +.*: Info: did you mean this\? +.*: Info: bfminnm {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: Error: too many registers in vector register list at operand 3 -- `bfminnm {z12.h-z15.h},{z12.h-z15.h},{z10.h-z25.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z4.h-z17.h},{z4.h-z7.h},{z14.h-z17.h}' +.*: Error: too many registers in vector register list at operand 1 -- `bfminnm {z14.h-z7.h},{z4.s-z7.b},{z10.h-z3.h}' +.*: Error: operand mismatch -- `bfclamp {z0.s-z1.s},z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfclamp {z0.h-z1.h}, z0.h, z0.h +.*: Error: too many registers in vector register list at operand 1 -- `bfclamp {z31.h-z30.h},z0.h,z0.h' +.*: Error: operand mismatch -- `bfclamp {z0.h-z1.h},z31.s,z0.h' +.*: Info: did you mean this\? +.*: Info: bfclamp {z0.h-z1.h}, z31.h, z0.h +.*: Error: operand mismatch -- `bfclamp {z0.h-z1.h},z0.h,z31.d' +.*: Info: did you mean this\? +.*: Info: bfclamp {z0.h-z1.h}, z0.h, z31.h +.*: Error: operand mismatch -- `bfclamp {z16.h-z17.h},z1.b,z15.b' +.*: Info: did you mean this\? +.*: Info: bfclamp {z16.h-z17.h}, z1.h, z15.h +.*: Error: too many registers in vector register list at operand 1 -- `bfclamp {z16.h-z21.h},z3.s,z7.d' +.*: Error: invalid range in vector register list at operand 1 -- `bfclamp {z2.h-z2.h},z7.s,z31.d' +.*: Error: operand mismatch -- `bfclamp {z0.s-z3.s},z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfclamp {z0.h-z3.h}, z0.h, z0.h +.*: Error: too many registers in vector register list at operand 1 -- `bfclamp {z25.h-z31.h},z0.h,z0.h' +.*: Error: operand mismatch -- `bfclamp {z0.h-z3.h},z31.s,z0.h' +.*: Info: did you mean this\? +.*: Info: bfclamp {z0.h-z3.h}, z31.h, z0.h +.*: Error: operand mismatch -- `bfclamp {z0.h-z3.h},z0.h,z31.d' +.*: Info: did you mean this\? +.*: Info: bfclamp {z0.h-z3.h}, z0.h, z31.h +.*: Error: operand mismatch -- `bfclamp {z31.h-z2.h},z1.b,z15.b' +.*: Info: did you mean this\? +.*: Info: bfclamp {z31.h-z2.h}, z1.h, z15.h +.*: Error: too many registers in vector register list at operand 1 -- `bfclamp {z18.s-z15.s},z3.h,z7.h' +.*: Error: too many registers in vector register list at operand 1 -- `bfclamp {z14.h-z27.h},z7.s,z31.d' diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.s b/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.s new file mode 100644 index 00000000000..fb27f2d078c --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-2-bad.s @@ -0,0 +1,136 @@ +/* BFMAX. */ +bfmax {z0.h - z1.s}, {z0.h - z1.h}, z0.h +bfmax {z30.h - z31.h}, {z0.h - z31.h}, z0.h +bfmax {z0.h - z1.h}, {z0.h - z1.h}, z16.h +bfmax {z14.s - z15.s}, {z14.s - z15.s}, z1.h +bfmax {z2.h - z7.h}, {z30.h - z7.h}, z3.d +bfmax {z4.h - z3.h}, {z4.h - z3.h}, z7.b + +bfmax {z0.h - z3.s}, {z0.h - z3.h}, z0.h +bfmax {z28.h - z31.h}, {z28.s - z31.h}, z0.h +bfmax {z0.h - z3.h}, {z0.h - z3.h}, z16.h +bfmax {z10.h - z15.h}, {z10.h - z15.h}, z1.h +bfmax {z14.h - z7.h}, {z4.h - z7.h}, z3.s +bfmax {z4.h - z17.h}, {z1.h - z7.h}, z17.b + +/* BFMAX (multiple vectors). */ +bfmax {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfmax {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h} +bfmax {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b} +bfmax {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s} +bfmax {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h} +bfmax {z2.h - z3.h}, {z2.h - z3.h} + +bfmax {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfmax {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h} +bfmax {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b} +bfmax {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h} +bfmax {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h} +bfmax {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h} + +/* BFMAXNM. */ +bfmaxnm {z0.h - z1.s}, {z0.h - z1.h}, z0.h +bfmaxnm {z30.h - z31.h}, {z0.h - z31.h}, z0.h +bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, z16.h +bfmaxnm {z14.s - z15.s}, {z14.s - z15.s}, z1.h +bfmaxnm {z2.h - z7.h}, {z30.h - z7.h}, z3.d +bfmaxnm {z4.h - z3.h}, {z4.h - z3.h}, z7.b + +bfmaxnm {z0.h - z3.s}, {z0.h - z3.h}, z0.h +bfmaxnm {z28.h - z31.h}, {z28.s - z31.h}, z0.h +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z16.h +bfmaxnm {z10.h - z15.h}, {z10.h - z15.h}, z1.h +bfmaxnm {z14.h - z7.h}, {z4.h - z7.h}, z3.s +bfmaxnm {z4.h - z17.h}, {z1.h - z7.h}, z17.b + +/* BFMAXNM (multiple vectors). */ +bfmaxnm {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfmaxnm {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h} +bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b} +bfmaxnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s} +bfmaxnm {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h} +bfmaxnm {z2.h - z3.h}, {z2.h - z3.h} + +bfmaxnm {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfmaxnm {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h} +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b} +bfmaxnm {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h} +bfmaxnm {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h} +bfmaxnm {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h} + +/* BFMIN. */ +bfmin {z0.h - z1.s}, {z0.h - z1.h}, z0.h +bfmin {z30.h - z31.h}, {z0.h - z31.h}, z0.h +bfmin {z0.h - z1.h}, {z0.h - z1.h}, z16.h +bfmin {z14.s - z15.s}, {z14.s - z15.s}, z1.h +bfmin {z2.h - z7.h}, {z30.h - z7.h}, z3.d +bfmin {z4.h - z3.h}, {z4.h - z3.h}, z7.b + +bfmin {z0.h - z3.s}, {z0.h - z3.h}, z0.h +bfmin {z28.h - z31.h}, {z28.s - z31.h}, z0.h +bfmin {z0.h - z3.h}, {z0.h - z3.h}, z16.h +bfmin {z10.h - z15.h}, {z10.h - z15.h}, z1.h +bfmin {z14.h - z7.h}, {z4.h - z7.h}, z3.s +bfmin {z4.h - z17.h}, {z1.h - z7.h}, z17.b + +/* BFMIN (multiple vectors). */ +bfmin {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfmin {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h} +bfmin {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b} +bfmin {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s} +bfmin {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h} +bfmin {z2.h - z3.h}, {z2.h - z3.h} + +bfmin {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfmin {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h} +bfmin {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b} +bfmin {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h} +bfmin {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h} +bfmin {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h} + +/* BFMINNM. */ +bfminnm {z0.h - z1.s}, {z0.h - z1.h}, z0.h +bfminnm {z30.h - z31.h}, {z0.h - z31.h}, z0.h +bfminnm {z0.h - z1.h}, {z0.h - z1.h}, z16.h +bfminnm {z14.s - z15.s}, {z14.s - z15.s}, z1.h +bfminnm {z2.h - z7.h}, {z30.h - z7.h}, z3.d +bfminnm {z4.h - z3.h}, {z4.h - z3.h}, z7.b + +bfminnm {z0.h - z3.s}, {z0.h - z3.h}, z0.h +bfminnm {z28.h - z31.h}, {z28.s - z31.h}, z0.h +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, z16.h +bfminnm {z10.h - z15.h}, {z10.h - z15.h}, z1.h +bfminnm {z14.h - z7.h}, {z4.h - z7.h}, z3.s +bfminnm {z4.h - z17.h}, {z1.h - z7.h}, z17.b + +/* BFMINNM (multiple vectors). */ +bfminnm {z0.s - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfminnm {z30.h - z31.h}, {z31.s - z31.h}, {z0.h - z1.h} +bfminnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.b - z31.b} +bfminnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.s - z10.s} +bfminnm {z6.h - z7.h}, {z16.h - z17.h}, {z30.h - z31.h} +bfminnm {z2.h - z3.h}, {z2.h - z3.h} + +bfminnm {z20.h - z31.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfminnm {z28.h - z31.h}, {z21.s - z31.s}, {z0.h - z3.h} +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.b - z31.b} +bfminnm {z12.h - z15.h}, {z12.h - z15.h}, {z10.h - z25.h} +bfminnm {z4.h - z17.h}, {z4.h - z7.h}, {z14.h - z17.h} +bfminnm {z14.h - z7.h}, {z4.s - z7.b}, {z10.h - z3.h} + +/* BFCLAMP. */ +bfclamp {z0.s - z1.s}, z0.h, z0.h +bfclamp {z31.h - z30.h}, z0.h, z0.h +bfclamp {z0.h - z1.h}, z31.s, z0.h +bfclamp {z0.h - z1.h}, z0.h, z31.d +bfclamp {z16.h - z17.h}, z1.b, z15.b +bfclamp {z16.h - z21.h}, z3.s, z7.d +bfclamp {z2.h - z2.h}, z7.s, z31.d + +bfclamp {z0.s - z3.s}, z0.h, z0.h +bfclamp {z25.h - z31.h}, z0.h, z0.h +bfclamp {z0.h - z3.h}, z31.s, z0.h +bfclamp {z0.h - z3.h}, z0.h, z31.d +bfclamp {z31.h - z2.h}, z1.b, z15.b +bfclamp {z18.s - z15.s}, z3.h, z7.h +bfclamp {z14.h - z27.h}, z7.s, z31.d diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-2.d b/gas/testsuite/gas/aarch64/bfloat16-sme2-2.d new file mode 100644 index 00000000000..04e4a107636 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-2.d @@ -0,0 +1,122 @@ +#name: Test of SME2 non-widening BFloat16 min max instructions. +#as: -march=armv9.4-a+sve-b16b16+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: c120a100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, z0.h +.*: c120a11e bfmax {z30.h-z31.h}, {z30.h-z31.h}, z0.h +.*: c12fa100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, z15.h +.*: c121a10e bfmax {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: c123a106 bfmax {z6.h-z7.h}, {z6.h-z7.h}, z3.h +.*: c127a102 bfmax {z2.h-z3.h}, {z2.h-z3.h}, z7.h +.*: c120a900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, z0.h +.*: c120a91c bfmax {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: c12fa900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, z15.h +.*: c121a90c bfmax {z12.h-z15.h}, {z12.h-z15.h}, z1.h +.*: c123a904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, z3.h +.*: c127a904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, z7.h +.*: c120b100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: c120b11e bfmax {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h} +.*: c13eb100 bfmax {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: c12eb10e bfmax {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h} +.*: c126b106 bfmax {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h} +.*: c122b102 bfmax {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h} +.*: c120b900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} +.*: c120b91c bfmax {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h} +.*: c13cb900 bfmax {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: c12cb90c bfmax {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h} +.*: c124b904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h} +.*: c120b904 bfmax {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h} +.*: c120a120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, z0.h +.*: c120a13e bfmaxnm {z30.h-z31.h}, {z30.h-z31.h}, z0.h +.*: c12fa120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, z15.h +.*: c121a12e bfmaxnm {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: c123a126 bfmaxnm {z6.h-z7.h}, {z6.h-z7.h}, z3.h +.*: c127a122 bfmaxnm {z2.h-z3.h}, {z2.h-z3.h}, z7.h +.*: c120a920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, z0.h +.*: c120a93c bfmaxnm {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: c12fa920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, z15.h +.*: c121a92c bfmaxnm {z12.h-z15.h}, {z12.h-z15.h}, z1.h +.*: c123a924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, z3.h +.*: c127a924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, z7.h +.*: c120b120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: c120b13e bfmaxnm {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h} +.*: c13eb120 bfmaxnm {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: c12eb12e bfmaxnm {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h} +.*: c126b126 bfmaxnm {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h} +.*: c122b122 bfmaxnm {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h} +.*: c120b920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} +.*: c120b93c bfmaxnm {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h} +.*: c13cb920 bfmaxnm {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: c12cb92c bfmaxnm {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h} +.*: c124b924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h} +.*: c120b924 bfmaxnm {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h} +.*: c120a101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, z0.h +.*: c120a11f bfmin {z30.h-z31.h}, {z30.h-z31.h}, z0.h +.*: c12fa101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, z15.h +.*: c121a10f bfmin {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: c123a107 bfmin {z6.h-z7.h}, {z6.h-z7.h}, z3.h +.*: c127a103 bfmin {z2.h-z3.h}, {z2.h-z3.h}, z7.h +.*: c120a901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, z0.h +.*: c120a91d bfmin {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: c12fa901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, z15.h +.*: c121a90d bfmin {z12.h-z15.h}, {z12.h-z15.h}, z1.h +.*: c123a905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, z3.h +.*: c127a905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, z7.h +.*: c120b101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: c120b11f bfmin {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h} +.*: c13eb101 bfmin {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: c12eb10f bfmin {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h} +.*: c126b107 bfmin {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h} +.*: c122b103 bfmin {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h} +.*: c120b901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} +.*: c120b91d bfmin {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h} +.*: c13cb901 bfmin {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: c12cb90d bfmin {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h} +.*: c124b905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h} +.*: c120b905 bfmin {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h} +.*: c120a121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, z0.h +.*: c120a13f bfminnm {z30.h-z31.h}, {z30.h-z31.h}, z0.h +.*: c12fa121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, z15.h +.*: c121a12f bfminnm {z14.h-z15.h}, {z14.h-z15.h}, z1.h +.*: c123a127 bfminnm {z6.h-z7.h}, {z6.h-z7.h}, z3.h +.*: c127a123 bfminnm {z2.h-z3.h}, {z2.h-z3.h}, z7.h +.*: c120a921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, z0.h +.*: c120a93d bfminnm {z28.h-z31.h}, {z28.h-z31.h}, z0.h +.*: c12fa921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, z15.h +.*: c121a92d bfminnm {z12.h-z15.h}, {z12.h-z15.h}, z1.h +.*: c123a925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, z3.h +.*: c127a925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, z7.h +.*: c120b121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} +.*: c120b13f bfminnm {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h} +.*: c13eb121 bfminnm {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h} +.*: c12eb12f bfminnm {z14.h-z15.h}, {z14.h-z15.h}, {z14.h-z15.h} +.*: c126b127 bfminnm {z6.h-z7.h}, {z6.h-z7.h}, {z6.h-z7.h} +.*: c122b123 bfminnm {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h} +.*: c120b921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} +.*: c120b93d bfminnm {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h} +.*: c13cb921 bfminnm {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h} +.*: c12cb92d bfminnm {z12.h-z15.h}, {z12.h-z15.h}, {z12.h-z15.h} +.*: c124b925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h} +.*: c120b925 bfminnm {z4.h-z7.h}, {z4.h-z7.h}, {z0.h-z3.h} +.*: c120c000 bfclamp {z0.h-z1.h}, z0.h, z0.h +.*: c120c01e bfclamp {z30.h-z31.h}, z0.h, z0.h +.*: c120c3e0 bfclamp {z0.h-z1.h}, z31.h, z0.h +.*: c13fc000 bfclamp {z0.h-z1.h}, z0.h, z31.h +.*: c12fc02e bfclamp {z14.h-z15.h}, z1.h, z15.h +.*: c127c066 bfclamp {z6.h-z7.h}, z3.h, z7.h +.*: c123c0e2 bfclamp {z2.h-z3.h}, z7.h, z3.h +.*: c121c1f4 bfclamp {z20.h-z21.h}, z15.h, z1.h +.*: c120c800 bfclamp {z0.h-z3.h}, z0.h, z0.h +.*: c120c81c bfclamp {z28.h-z31.h}, z0.h, z0.h +.*: c120cbe0 bfclamp {z0.h-z3.h}, z31.h, z0.h +.*: c13fc800 bfclamp {z0.h-z3.h}, z0.h, z31.h +.*: c12fc82c bfclamp {z12.h-z15.h}, z1.h, z15.h +.*: c127c868 bfclamp {z8.h-z11.h}, z3.h, z7.h +.*: c123c8e4 bfclamp {z4.h-z7.h}, z7.h, z3.h +.*: c121c9f4 bfclamp {z20.h-z23.h}, z15.h, z1.h diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-2.s b/gas/testsuite/gas/aarch64/bfloat16-sme2-2.s new file mode 100644 index 00000000000..94cec19df49 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-2.s @@ -0,0 +1,138 @@ +/* BFMAX. */ +bfmax {z0.h - z1.h}, {z0.h - z1.h}, z0.h +bfmax {z30.h - z31.h}, {z30.h - z31.h}, z0.h +bfmax {z0.h - z1.h}, {z0.h - z1.h}, z15.h +bfmax {z14.h - z15.h}, {z14.h - z15.h}, z1.h +bfmax {z6.h - z7.h}, {z6.h - z7.h}, z3.h +bfmax {z2.h - z3.h}, {z2.h - z3.h}, z7.h + +bfmax {z0.h - z3.h}, {z0.h - z3.h}, z0.h +bfmax {z28.h - z31.h}, {z28.h - z31.h}, z0.h +bfmax {z0.h - z3.h}, {z0.h - z3.h}, z15.h +bfmax {z12.h - z15.h}, {z12.h - z15.h}, z1.h +bfmax {z4.h - z7.h}, {z4.h - z7.h}, z3.h +bfmax {z4.h - z7.h}, {z4.h - z7.h}, z7.h + +/* BFMAX (multiple vectors). */ +bfmax {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfmax {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h} +bfmax {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h} +bfmax {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h} +bfmax {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h} +bfmax {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h} + +bfmax {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfmax {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h} +bfmax {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h} +bfmax {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h} +bfmax {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h} +bfmax {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h} + +/* BFMAXNM. */ +bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, z0.h +bfmaxnm {z30.h - z31.h}, {z30.h - z31.h}, z0.h +bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, z15.h +bfmaxnm {z14.h - z15.h}, {z14.h - z15.h}, z1.h +bfmaxnm {z6.h - z7.h}, {z6.h - z7.h}, z3.h +bfmaxnm {z2.h - z3.h}, {z2.h - z3.h}, z7.h + +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h +bfmaxnm {z28.h - z31.h}, {z28.h - z31.h}, z0.h +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z15.h +bfmaxnm {z12.h - z15.h}, {z12.h - z15.h}, z1.h +bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, z3.h +bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, z7.h + +/* BFMAXNM (multiple vectors). */ +bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfmaxnm {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h} +bfmaxnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h} +bfmaxnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h} +bfmaxnm {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h} +bfmaxnm {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h} + +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfmaxnm {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h} +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h} +bfmaxnm {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h} +bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h} +bfmaxnm {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h} + +/* BFMIN. */ +bfmin {z0.h - z1.h}, {z0.h - z1.h}, z0.h +bfmin {z30.h - z31.h}, {z30.h - z31.h}, z0.h +bfmin {z0.h - z1.h}, {z0.h - z1.h}, z15.h +bfmin {z14.h - z15.h}, {z14.h - z15.h}, z1.h +bfmin {z6.h - z7.h}, {z6.h - z7.h}, z3.h +bfmin {z2.h - z3.h}, {z2.h - z3.h}, z7.h + +bfmin {z0.h - z3.h}, {z0.h - z3.h}, z0.h +bfmin {z28.h - z31.h}, {z28.h - z31.h}, z0.h +bfmin {z0.h - z3.h}, {z0.h - z3.h}, z15.h +bfmin {z12.h - z15.h}, {z12.h - z15.h}, z1.h +bfmin {z4.h - z7.h}, {z4.h - z7.h}, z3.h +bfmin {z4.h - z7.h}, {z4.h - z7.h}, z7.h + +/* BFMIN (multiple vectors). */ +bfmin {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfmin {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h} +bfmin {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h} +bfmin {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h} +bfmin {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h} +bfmin {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h} + +bfmin {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfmin {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h} +bfmin {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h} +bfmin {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h} +bfmin {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h} +bfmin {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h} + +/* BFMINNM. */ +bfminnm {z0.h - z1.h}, {z0.h - z1.h}, z0.h +bfminnm {z30.h - z31.h}, {z30.h - z31.h}, z0.h +bfminnm {z0.h - z1.h}, {z0.h - z1.h}, z15.h +bfminnm {z14.h - z15.h}, {z14.h - z15.h}, z1.h +bfminnm {z6.h - z7.h}, {z6.h - z7.h}, z3.h +bfminnm {z2.h - z3.h}, {z2.h - z3.h}, z7.h + +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h +bfminnm {z28.h - z31.h}, {z28.h - z31.h}, z0.h +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, z15.h +bfminnm {z12.h - z15.h}, {z12.h - z15.h}, z1.h +bfminnm {z4.h - z7.h}, {z4.h - z7.h}, z3.h +bfminnm {z4.h - z7.h}, {z4.h - z7.h}, z7.h + +/* BFMINNM (multiple vectors). */ +bfminnm {z0.h - z1.h}, {z0.h - z1.h}, {z0.h - z1.h} +bfminnm {z30.h - z31.h}, {z30.h - z31.h}, {z0.h - z1.h} +bfminnm {z0.h - z1.h}, {z0.h - z1.h}, {z30.h - z31.h} +bfminnm {z14.h - z15.h}, {z14.h - z15.h}, {z14.h - z15.h} +bfminnm {z6.h - z7.h}, {z6.h - z7.h}, {z6.h - z7.h} +bfminnm {z2.h - z3.h}, {z2.h - z3.h}, {z2.h - z3.h} + +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} +bfminnm {z28.h - z31.h}, {z28.h - z31.h}, {z0.h - z3.h} +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, {z28.h - z31.h} +bfminnm {z12.h - z15.h}, {z12.h - z15.h}, {z12.h - z15.h} +bfminnm {z4.h - z7.h}, {z4.h - z7.h}, {z4.h - z7.h} +bfminnm {z4.h - z7.h}, {z4.h - z7.h}, {z0.h - z3.h} + +/* BFCLAMP. */ +bfclamp {z0.h - z1.h}, z0.h, z0.h +bfclamp {z30.h - z31.h}, z0.h, z0.h +bfclamp {z0.h - z1.h}, z31.h, z0.h +bfclamp {z0.h - z1.h}, z0.h, z31.h +bfclamp {z14.h - z15.h}, z1.h, z15.h +bfclamp {z6.h - z7.h}, z3.h, z7.h +bfclamp {z2.h - z3.h}, z7.h, z3.h +bfclamp {z20.h - z21.h}, z15.h, z1.h + +bfclamp {z0.h - z3.h}, z0.h, z0.h +bfclamp {z28.h - z31.h}, z0.h, z0.h +bfclamp {z0.h - z3.h}, z31.h, z0.h +bfclamp {z0.h - z3.h}, z0.h, z31.h +bfclamp {z12.h - z15.h}, z1.h, z15.h +bfclamp {z8.h - z11.h}, z3.h, z7.h +bfclamp {z4.h - z7.h}, z7.h, z3.h +bfclamp {z20.h - z23.h}, z15.h, z1.h diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 72b48183882..5f43a235dd1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -279,6 +279,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_V9_5A, /* +sve-b16b16+sve2. */ AARCH64_FEATURE_SVE_SVE2_B16B16, + /* +sve-b16b16+sme2. */ + AARCH64_FEATURE_SVE_SME2_B16B16, AARCH64_NUM_FEATURES }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ea30fb31ba5..82816d5db38 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2813,6 +2813,8 @@ static const aarch64_feature_set aarch64_feature_d128_the = AARCH64_FEATURES (2, D128, THE); static const aarch64_feature_set aarch64_feature_sve_sve2_b16b16 = AARCH64_FEATURES (3, SVE_B16B16, SVE2, SVE_SVE2_B16B16); +static const aarch64_feature_set aarch64_feature_sve_sme2_b16b16 = + AARCH64_FEATURES (3, SVE_B16B16, SME2, SVE_SME2_B16B16); static const aarch64_feature_set aarch64_feature_sme2p1 = AARCH64_FEATURE (SME2p1); static const aarch64_feature_set aarch64_feature_sve2p1 = @@ -2924,6 +2926,7 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = #define THE &aarch64_feature_the #define D128_THE &aarch64_feature_d128_the #define SVE_SVE2_B16B16 &aarch64_feature_sve_sve2_b16b16 +#define SVE_SME2_B16B16 &aarch64_feature_sve_sme2_b16b16 #define SME2p1 &aarch64_feature_sme2p1 #define SVE2p1 &aarch64_feature_sve2p1 #define RCPC3 &aarch64_feature_rcpc3 @@ -3026,6 +3029,12 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = #define SVE_SVE2_B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_SVE2_B16B16, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } +#define SVE_SME2_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE_SME2_B16B16, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE_SME2_B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE_SME2_B16B16, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -6643,6 +6652,26 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE_SVE2_B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0), SVE_SVE2_B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0), +/* SME Z-targeting multi-vector non-widening BFloat16 instructions. */ + SVE_SME2_B16B16_INSN("bfmax", 0xc120a100, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfmax", 0xc120a900, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfmax", 0xc120b100, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfmax", 0xc120b900, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfmaxnm", 0xc120a120, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfmaxnm", 0xc120a920, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfmaxnm", 0xc120b120, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfmaxnm", 0xc120b920, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfmin", 0xc120a101, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfmin", 0xc120a901, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfmin", 0xc120b101, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfmin", 0xc120b901, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfminnm", 0xc120a121, 0xfff0ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfminnm", 0xc120a921, 0xfff0ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfminnm", 0xc120b121, 0xffe1ffe1, sme_misc, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 1), + SVE_SME2_B16B16_INSN("bfminnm", 0xc120b921, 0xffe3ffe3, sme_misc, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 1), + SVE_SME2_B16B16_INSN("bfclamp", 0xc120c000, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, F_OD(2), 0), + SVE_SME2_B16B16_INSN("bfclamp", 0xc120c800, 0xffe0fc03, sme_misc, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, F_OD(4), 0), + /* SME2.1 movaz instructions. */ SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0), SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0), From patchwork Fri Jul 19 12:14:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 94215 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C0A663860C3D for ; Fri, 19 Jul 2024 12:17:16 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from EUR03-AM7-obe.outbound.protection.outlook.com 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support for FEAT_SVE_B16B16 min and max instructions (autogenerated files). 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+ return 3330; } else { @@ -224,7 +224,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000100x0010xxxxxx1xxxxxxxxx movaz. */ - return 3314; + return 3332; } } else @@ -235,7 +235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x0010xxxxxx1xxxxxxxxx movaz. */ - return 3313; + return 3331; } else { @@ -243,7 +243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x0010xxxxxx1xxxxxxxxx movaz. */ - return 3315; + return 3333; } } } @@ -253,7 +253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x0011xxxxxx1xxxxxxxxx movaz. */ - return 3316; + return 3334; } } } @@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x000101x00xxxxxxxxxxxxxx luti4. */ - return 3428; + return 3446; } else { @@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101x00xxxxxxxxxxxxxx luti4. */ - return 3429; + return 3447; } else { @@ -318,7 +318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101x10xxxxxxxxxxxxxx luti4. */ - return 3309; + return 3327; } } else @@ -327,7 +327,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101xx1xxxxxxxxxxxxxx luti4. */ - return 3308; + return 3326; } } } @@ -369,7 +369,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000x011xxxxx001xxxxxxxxx movaz. */ - return 3302; + return 3320; } else { @@ -377,7 +377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000100x011xxxxx001xxxxxxxxx movaz. */ - return 3304; + return 3322; } } else @@ -388,7 +388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x011xxxxx001xxxxxxxxx movaz. */ - return 3303; + return 3321; } else { @@ -396,7 +396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x011xxxxx001xxxxxxxxx movaz. */ - return 3305; + return 3323; } } } @@ -420,7 +420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011000xxx00xxxxxxxxxx zero. */ - return 3317; + return 3335; } else { @@ -428,7 +428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011100xxx00xxxxxxxxxx zero. */ - return 3318; + return 3336; } } else @@ -439,7 +439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011010xxx00xxxxxxxxxx zero. */ - return 3320; + return 3338; } else { @@ -447,7 +447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011110xxx00xxxxxxxxxx zero. */ - return 3323; + return 3341; } } } @@ -461,7 +461,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011001xxx00xxxxxxxxxx zero. */ - return 3319; + return 3337; } else { @@ -469,7 +469,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011101xxx00xxxxxxxxxx zero. */ - return 3322; + return 3340; } } else @@ -480,7 +480,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011011xxx00xxxxxxxxxx zero. */ - return 3321; + return 3339; } else { @@ -488,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011111xxx00xxxxxxxxxx zero. */ - return 3324; + return 3342; } } } @@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010011x1xxxx00xxxxxxxxxx movt. */ - return 3430; + return 3448; } } else @@ -563,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0111xxx0xx00xxxxxxxxxx luti2. */ - return 3307; + return 3325; } else { @@ -571,7 +571,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0111xxx1xx00xxxxxxxxxx luti2. */ - return 3306; + return 3324; } } } @@ -602,7 +602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx101xxxxxxxxx movaz. */ - return 3310; + return 3328; } } } @@ -639,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000xx11xxxxx011xxxxxxxxx movaz. */ - return 3298; + return 3316; } else { @@ -647,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000100xx11xxxxx011xxxxxxxxx movaz. */ - return 3300; + return 3318; } } else @@ -658,7 +658,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010xx11xxxxx011xxxxxxxxx movaz. */ - return 3299; + return 3317; } else { @@ -666,7 +666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110xx11xxxxx011xxxxxxxxx movaz. */ - return 3301; + return 3319; } } } @@ -698,7 +698,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx111xxxxxxxxx movaz. */ - return 3311; + return 3329; } } } @@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx00xxx fmopa. */ - return 3496; + return 3514; } else { @@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx01xxx fmopa. */ - return 3495; + return 3513; } } else @@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xx0xxxxx1000xxx fmlall. */ - return 3489; + return 3507; } } } @@ -1752,7 +1752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxxxxx1xxxxxx00xxxx fdot. */ - return 3474; + return 3492; } } else @@ -2124,7 +2124,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx0xxxxxx100xxx fmlall. */ - return 3488; + return 3506; } } } @@ -2229,7 +2229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx10xxxx fmlal. */ - return 3481; + return 3499; } } } @@ -2402,7 +2402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx11xxxx fmlal. */ - return 3480; + return 3498; } } } @@ -2444,7 +2444,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010100xxxxxxxxxxxxxxxx0xxx fmlall. */ - return 3487; + return 3505; } else { @@ -2812,7 +2812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx111xxx fdot. */ - return 3467; + return 3485; } else { @@ -2881,7 +2881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx001xxx fdot. */ - return 3468; + return 3486; } else { @@ -2960,7 +2960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx0xxxxxxx0xxxx fmlal. */ - return 3479; + return 3497; } else { @@ -3015,7 +3015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx01xxxxx00xxxx fvdotb. */ - return 3498; + return 3516; } else { @@ -3033,7 +3033,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx0xxxxxx10xxxx fdot. */ - return 3473; + return 3491; } } } @@ -3107,7 +3107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx1xxxxxx10xxxx fvdot. */ - return 3497; + return 3515; } } } @@ -3187,7 +3187,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx01xxxxxx1xxxx fvdott. */ - return 3499; + return 3517; } else { @@ -3364,7 +3364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxx10000x fmlall. */ - return 3493; + return 3511; } else { @@ -3372,7 +3372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxx10000x fmlall. */ - return 3494; + return 3512; } } } @@ -3427,7 +3427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx000xxxxx00x1x fmlall. */ - return 3491; + return 3509; } else { @@ -3435,7 +3435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx000xxxxx00x1x fmlall. */ - return 3492; + return 3510; } } } @@ -3489,7 +3489,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx100xxx fdot. */ - return 3477; + return 3495; } else { @@ -3497,7 +3497,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx100xxx fdot. */ - return 3478; + return 3496; } } } @@ -3559,7 +3559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx010xxxx1000xx fmlal. */ - return 3485; + return 3503; } else { @@ -3567,7 +3567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx010xxxx1000xx fmlal. */ - return 3486; + return 3504; } } } @@ -3622,7 +3622,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx010xxxxx001xx fmlal. */ - return 3483; + return 3501; } else { @@ -3630,7 +3630,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx010xxxxx001xx fmlal. */ - return 3484; + return 3502; } } } @@ -3699,7 +3699,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx001xxxxx000xx fmlall. */ - return 3490; + return 3508; } } else @@ -3782,7 +3782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx011xxxxx00xxx fmlal. */ - return 3482; + return 3500; } } else @@ -3803,7 +3803,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx00xxx fadd. */ - return 3431; + return 3449; } } else @@ -3822,7 +3822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx00xxx fadd. */ - return 3432; + return 3450; } } } @@ -3948,7 +3948,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx110xxx fdot. */ - return 3471; + return 3489; } else { @@ -3956,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx110xxx fdot. */ - return 3472; + return 3490; } } } @@ -4247,7 +4247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx01xxx fdot. */ - return 3475; + return 3493; } else { @@ -4255,7 +4255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx01xxx fdot. */ - return 3476; + return 3494; } } } @@ -4526,7 +4526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx01xxx fsub. */ - return 3433; + return 3451; } } else @@ -4545,7 +4545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx01xxx fsub. */ - return 3434; + return 3452; } } } @@ -4607,7 +4607,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx11xxx fdot. */ - return 3469; + return 3487; } else { @@ -4615,7 +4615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx11xxx fdot. */ - return 3470; + return 3488; } } } @@ -5150,7 +5150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000xx1x0xxxx0 fscale. */ - return 3405; + return 3423; } } else @@ -5298,7 +5298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x0100100111000xxxx0xxxxx fcvt. */ - return 3402; + return 3420; } else { @@ -5306,7 +5306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x1100100111000xxxx0xxxxx bfcvt. */ - return 3397; + return 3415; } } else @@ -5315,7 +5315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx110100111000xxxx0xxxxx fcvt. */ - return 3403; + return 3421; } } else @@ -5366,7 +5366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx100111000xxxx1xxxxx fcvtn. */ - return 3404; + return 3422; } } } @@ -5449,7 +5449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010x110111000xxxxxxxxx0 f1cvt. */ - return 3398; + return 3416; } else { @@ -5457,7 +5457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011010x110111000xxxxxxxxx0 f2cvt. */ - return 3399; + return 3417; } } else @@ -5468,7 +5468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110x110111000xxxxxxxxx0 bf1cvt. */ - return 3393; + return 3411; } else { @@ -5476,7 +5476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011110x110111000xxxxxxxxx0 bf2cvt. */ - return 3394; + return 3412; } } } @@ -5511,7 +5511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001001xxx10111000xxxxxxxxx1 f1cvtl. */ - return 3400; + return 3418; } else { @@ -5519,7 +5519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxx10111000xxxxxxxxx1 f2cvtl. */ - return 3401; + return 3419; } } else @@ -5530,7 +5530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001011xxx10111000xxxxxxxxx1 bf1cvtl. */ - return 3395; + return 3413; } else { @@ -5538,7 +5538,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxx10111000xxxxxxxxx1 bf2cvtl. */ - return 3396; + return 3414; } } } @@ -5807,7 +5807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100xx100xxxx0 fscale. */ - return 3407; + return 3425; } } else @@ -5983,7 +5983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010xx100xxxx0 fscale. */ - return 3406; + return 3424; } else { @@ -5991,7 +5991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110xx100xxxx0 fscale. */ - return 3408; + return 3426; } } } @@ -11159,7 +11159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x11010000xxxxxxx1xxxxxxxxxxxxx addpt. */ - return 3409; + return 3427; } else { @@ -11167,7 +11167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010000xxxxxxx1xxxxxxxxxxxxx subpt. */ - return 3410; + return 3428; } } } @@ -12085,7 +12085,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx0xxxxxxxxxxxxxxx maddpt. */ - return 3411; + return 3429; } else { @@ -12093,7 +12093,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx1xxxxxxxxxxxxxxx msubpt. */ - return 3412; + return 3430; } } } @@ -12178,7 +12178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000100000xxxxxxxxxxxxx addpt. */ - return 3413; + return 3431; } else { @@ -12285,7 +12285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000101000xxxxxxxxxxxxx subpt. */ - return 3415; + return 3433; } else { @@ -12490,7 +12490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000010xxxxxxxxxx addpt. */ - return 3414; + return 3432; } else { @@ -12531,7 +12531,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000011xxxxxxxxxx subpt. */ - return 3416; + return 3434; } else { @@ -14189,7 +14189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110100xxxxxxxxxx mlapt. */ - return 3418; + return 3436; } } else @@ -14219,7 +14219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110110xxxxxxxxxx madpt. */ - return 3417; + return 3435; } } } @@ -14527,7 +14527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x100001xxxxxxxxxxxxx smaxqv. */ - return 3327; + return 3345; } else { @@ -14535,7 +14535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x100001xxxxxxxxxxxxx orqv. */ - return 3338; + return 3356; } } else @@ -14546,7 +14546,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0x0101001xxxxxxxxxxxxx addqv. */ - return 3325; + return 3343; } else { @@ -14556,7 +14556,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx001101001xxxxxxxxxxxxx umaxqv. */ - return 3329; + return 3347; } else { @@ -14564,7 +14564,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx011101001xxxxxxxxxxxxx eorqv. */ - return 3331; + return 3349; } } } @@ -14601,7 +14601,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x110001xxxxxxxxxxxxx sminqv. */ - return 3328; + return 3346; } else { @@ -14609,7 +14609,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x110001xxxxxxxxxxxxx andqv. */ - return 3326; + return 3344; } } } @@ -14629,7 +14629,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0xx111001xxxxxxxxxxxxx uminqv. */ - return 3330; + return 3348; } } } @@ -15373,7 +15373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 110001x0x00xxxxx101xxxxxxxxxxxxx ld1q. */ - return 3354; + return 3372; } else { @@ -16387,7 +16387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x00xxxxxxxxxx zipq1. */ - return 3344; + return 3362; } else { @@ -16397,7 +16397,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111010xxxxxxxxxx uzpq1. */ - return 3342; + return 3360; } else { @@ -16405,7 +16405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111110xxxxxxxxxx tblq. */ - return 3339; + return 3357; } } } @@ -16417,7 +16417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x01xxxxxxxxxx zipq2. */ - return 3345; + return 3363; } else { @@ -16425,7 +16425,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x11xxxxxxxxxx uzpq2. */ - return 3343; + return 3361; } } } @@ -16905,7 +16905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0x00xxxxx000xxxxxxxxxxxxx st3q. */ - return 3363; + return 3381; } else { @@ -16915,7 +16915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0010xxxxx000xxxxxxxxxxxxx st2q. */ - return 3362; + return 3380; } else { @@ -16923,7 +16923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0110xxxxx000xxxxxxxxxxxxx st4q. */ - return 3364; + return 3382; } } } @@ -17370,7 +17370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0x0000101xxxxxxxxxxxxx faddqv. */ - return 3332; + return 3350; } else { @@ -17387,7 +17387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx100101xxxxxxxxxxxxx fmaxnmqv. */ - return 3333; + return 3351; } } else @@ -17428,7 +17428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx110101xxxxxxxxxxxxx fmaxqv. */ - return 3334; + return 3352; } } } @@ -17450,7 +17450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx101101xxxxxxxxxxxxx fminnmqv. */ - return 3335; + return 3353; } } else @@ -17469,7 +17469,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx111101xxxxxxxxxxxxx fminqv. */ - return 3336; + return 3354; } } } @@ -17589,7 +17589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx01xxxx111xxxxxxxxxxxxx ld2q. */ - return 3355; + return 3373; } } } @@ -17725,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx1xxxxx100xxxxxxxxxxxxx ld2q. */ - return 3358; + return 3376; } } else @@ -17870,7 +17870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x00x1xxxxx000xxxxxxxxxxxxx st2q. */ - return 3365; + return 3383; } } else @@ -17913,7 +17913,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0101xxxxx000xxxxxxxxxxxxx st3q. */ - return 3366; + return 3384; } } else @@ -17954,7 +17954,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0111xxxxx000xxxxxxxxxxxxx st4q. */ - return 3367; + return 3385; } } } @@ -17983,7 +17983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0100x1xxxxxxxxxx fdot. */ - return 3454; + return 3472; } } else @@ -17992,7 +17992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0101xxxxxxxxxxxx fmlalb. */ - return 3456; + return 3474; } } else @@ -18033,7 +18033,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 3466; + return 3484; } } else @@ -18066,7 +18066,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xx1xxxxxxxxxx fdot. */ - return 3452; + return 3470; } } else @@ -18137,7 +18137,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx100010xxxxxxxxxx fmlallbb. */ - return 3457; + return 3475; } } else @@ -18146,7 +18146,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1000x1xxxxxxxxxx fdot. */ - return 3453; + return 3471; } } else @@ -18155,7 +18155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1100xxxxxxxxxxxx fmlallbb. */ - return 3458; + return 3476; } } else @@ -18164,7 +18164,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1x01xxxxxxxxxxxx fmlallbt. */ - return 3459; + return 3477; } } else @@ -18191,7 +18191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx100010xxxxxxxxxx fmlalb. */ - return 3455; + return 3473; } } else @@ -18209,7 +18209,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1100xxxxxxxxxxxx fmlalltb. */ - return 3462; + return 3480; } } else @@ -18218,7 +18218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 3465; + return 3483; } } else @@ -18251,7 +18251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx100xx1xxxxxxxxxx fdot. */ - return 3451; + return 3469; } } else @@ -18260,7 +18260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx110xxxxxxxxxxxxx fmlallbt. */ - return 3460; + return 3478; } } else @@ -18292,7 +18292,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx110xxxxxxxxxxxxx fmlalltt. */ - return 3464; + return 3482; } } else @@ -18591,7 +18591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0xx1xxxxx001xxxxxxxxxxxxx st1q. */ - return 3361; + return 3379; } } else @@ -18606,7 +18606,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1010xxxxxxxxxxxx fmlalltb. */ - return 3461; + return 3479; } else { @@ -18614,7 +18614,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1011xxxxxxxxxxxx fmlalltt. */ - return 3463; + return 3481; } } else @@ -19332,7 +19332,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001010x0001110xxxxxxxxxx pmov. */ - return 3346; + return 3364; } else { @@ -19340,7 +19340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001011x0001110xxxxxxxxxx pmov. */ - return 3347; + return 3365; } } else @@ -19349,7 +19349,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x101101xx0001110xxxxxxxxxx pmov. */ - return 3348; + return 3366; } } else @@ -19358,7 +19358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x101xx0001110xxxxxxxxxx pmov. */ - return 3349; + return 3367; } } else @@ -19404,7 +19404,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x10x1001110xxxxxxxxxx pmov. */ - return 3350; + return 3368; } else { @@ -19412,7 +19412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x11x1001110xxxxxxxxxx pmov. */ - return 3351; + return 3369; } } else @@ -19421,7 +19421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1011x1xx1001110xxxxxxxxxx pmov. */ - return 3352; + return 3370; } } else @@ -19430,7 +19430,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x1x1xx1001110xxxxxxxxxx pmov. */ - return 3353; + return 3371; } } } @@ -19449,7 +19449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x01xxxxx001001xxxxxxxxxx dupq. */ - return 3337; + return 3355; } else { @@ -19457,7 +19457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x11xxxxx001001xxxxxxxxxx extq. */ - return 3341; + return 3359; } } else @@ -19466,7 +19466,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1xx1xxxxx001101xxxxxxxxxx tbxq. */ - return 3340; + return 3358; } } else @@ -21069,7 +21069,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101100xxxxxxxxxx luti2. */ - return 3423; + return 3441; } } else @@ -21078,7 +21078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x10xxxxxxxxxx luti2. */ - return 3424; + return 3442; } } else @@ -21091,7 +21091,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101001xxxxxxxxxx luti4. */ - return 3425; + return 3443; } else { @@ -21099,7 +21099,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101101xxxxxxxxxx luti4. */ - return 3426; + return 3444; } } else @@ -21108,7 +21108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x11xxxxxxxxxx luti4. */ - return 3427; + return 3445; } } } @@ -22059,7 +22059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x00xxxxxxxxxx f1cvt. */ - return 3385; + return 3403; } else { @@ -22067,7 +22067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x10xxxxxxxxxx bf1cvt. */ - return 3381; + return 3399; } } else @@ -22078,7 +22078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x01xxxxxxxxxx f2cvt. */ - return 3386; + return 3404; } else { @@ -22086,7 +22086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x11xxxxxxxxxx bf2cvt. */ - return 3382; + return 3400; } } } @@ -22131,7 +22131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x00xxxxxxxxxx fcvtn. */ - return 3390; + return 3408; } else { @@ -22139,7 +22139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x10xxxxxxxxxx bfcvtn. */ - return 3389; + return 3407; } } else @@ -22150,7 +22150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x01xxxxxxxxxx fcvtnb. */ - return 3391; + return 3409; } else { @@ -22158,7 +22158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x11xxxxxxxxxx fcvtnt. */ - return 3392; + return 3410; } } } @@ -22219,7 +22219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x00xxxxxxxxxx f1cvtlt. */ - return 3387; + return 3405; } else { @@ -22227,7 +22227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x10xxxxxxxxxx bf1cvtlt. */ - return 3383; + return 3401; } } else @@ -22238,7 +22238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x01xxxxxxxxxx f2cvtlt. */ - return 3388; + return 3406; } else { @@ -22246,7 +22246,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x11xxxxxxxxxx bf2cvtlt. */ - return 3384; + return 3402; } } } @@ -23572,7 +23572,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x01xxxx111xxxxxxxxxxxxx ld3q. */ - return 3356; + return 3374; } else { @@ -23580,7 +23580,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x01xxxx111xxxxxxxxxxxxx ld4q. */ - return 3357; + return 3375; } } } @@ -24753,7 +24753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx100xxxxxxxxxxxxx ld3q. */ - return 3359; + return 3377; } else { @@ -24761,7 +24761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx100xxxxxxxxxxxxx ld4q. */ - return 3360; + return 3378; } } else @@ -26826,7 +26826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110100xxxxxxxx100xxxxxxxxxx luti2. */ - return 3419; + return 3437; } } } @@ -26840,7 +26840,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx000xxxxxxxxxx luti4. */ - return 3421; + return 3439; } else { @@ -26848,7 +26848,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx100xxxxxxxxxx luti4. */ - return 3422; + return 3440; } } else @@ -26857,7 +26857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110110xxxxxxxxx00xxxxxxxxxx luti2. */ - return 3420; + return 3438; } } } @@ -26973,7 +26973,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx10001xxxxxxxxxx fmlallbb. */ - return 3443; + return 3461; } else { @@ -26981,7 +26981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx10001xxxxxxxxxx fmlalltb. */ - return 3445; + return 3463; } } else @@ -26992,7 +26992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x10xxxxxx10001xxxxxxxxxx fmlallbt. */ - return 3444; + return 3462; } else { @@ -27000,7 +27000,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x10xxxxxx10001xxxxxxxxxx fmlalltt. */ - return 3446; + return 3464; } } } @@ -27088,7 +27088,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3376; + return 3394; } else { @@ -27096,7 +27096,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx11101xxxxxxxxxx fcvtn2. */ - return 3377; + return 3395; } } else @@ -27105,7 +27105,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x10xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3378; + return 3396; } } } @@ -27248,7 +27248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x00xxxxxx11111xxxxxxxxxx fdot. */ - return 3435; + return 3453; } else { @@ -27258,7 +27258,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxx11111xxxxxxxxxx fdot. */ - return 3437; + return 3455; } else { @@ -27268,7 +27268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110110xxxxxx11111xxxxxxxxxx fmlalb. */ - return 3439; + return 3457; } else { @@ -27276,7 +27276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110110xxxxxx11111xxxxxxxxxx fmlalt. */ - return 3440; + return 3458; } } } @@ -27550,7 +27550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110110xxxxx0x1111xxxxxxxxxx fscale. */ - return 3379; + return 3397; } } } @@ -28942,7 +28942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110001xxxx1011110xxxxxxxxxx f1cvtl. */ - return 3372; + return 3390; } else { @@ -28950,7 +28950,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110001xxxx1011110xxxxxxxxxx f1cvtl2. */ - return 3373; + return 3391; } } else @@ -28961,7 +28961,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110101xxxx1011110xxxxxxxxxx bf1cvtl. */ - return 3368; + return 3386; } else { @@ -28969,7 +28969,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110101xxxx1011110xxxxxxxxxx bf1cvtl2. */ - return 3369; + return 3387; } } } @@ -28983,7 +28983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110011xxxx1011110xxxxxxxxxx f2cvtl. */ - return 3374; + return 3392; } else { @@ -28991,7 +28991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110011xxxx1011110xxxxxxxxxx f2cvtl2. */ - return 3375; + return 3393; } } else @@ -29002,7 +29002,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110111xxxx1011110xxxxxxxxxx bf2cvtl. */ - return 3370; + return 3388; } else { @@ -29010,7 +29010,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110111xxxx1011110xxxxxxxxxx bf2cvtl2. */ - return 3371; + return 3389; } } } @@ -31009,7 +31009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011101x1xxxxx111111xxxxxxxxxx fscale. */ - return 3380; + return 3398; } } } @@ -32725,7 +32725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3436; + return 3454; } else { @@ -32755,7 +32755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3438; + return 3456; } else { @@ -32765,7 +32765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx0000x0xxxxxxxxxx fmlalb. */ - return 3441; + return 3459; } else { @@ -32773,7 +32773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx0000x0xxxxxxxxxx fmlalt. */ - return 3442; + return 3460; } } } @@ -33315,7 +33315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x010111100xxxxxx1000x0xxxxxxxxxx fmlallbb. */ - return 3447; + return 3465; } else { @@ -33323,7 +33323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x110111100xxxxxx1000x0xxxxxxxxxx fmlalltb. */ - return 3449; + return 3467; } } else @@ -33354,7 +33354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111x1xxxxxx1000x0xxxxxxxxxx fmlallbt. */ - return 3448; + return 3466; } else { @@ -33362,7 +33362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111x1xxxxxx1000x0xxxxxxxxxx fmlalltt. */ - return 3450; + return 3468; } } } @@ -34122,6 +34122,42 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2459: return NULL; /* st1d --> NULL. */ case 2445: value = 2450; break; /* ld1q --> ld1q. */ case 2450: return NULL; /* ld1q --> NULL. */ + case 2532: value = 3314; break; /* fclamp --> bfclamp. */ + case 3314: return NULL; /* bfclamp --> NULL. */ + case 2533: value = 3315; break; /* fclamp --> bfclamp. */ + case 3315: return NULL; /* bfclamp --> NULL. */ + case 2546: value = 3298; break; /* fmax --> bfmax. */ + case 3298: return NULL; /* bfmax --> NULL. */ + case 2550: value = 3302; break; /* fmaxnm --> bfmaxnm. */ + case 3302: return NULL; /* bfmaxnm --> NULL. */ + case 2554: value = 3306; break; /* fmin --> bfmin. */ + case 3306: return NULL; /* bfmin --> NULL. */ + case 2558: value = 3310; break; /* fminnm --> bfminnm. */ + case 3310: return NULL; /* bfminnm --> NULL. */ + case 2548: value = 3300; break; /* fmax --> bfmax. */ + case 3300: return NULL; /* bfmax --> NULL. */ + case 2552: value = 3304; break; /* fmaxnm --> bfmaxnm. */ + case 3304: return NULL; /* bfmaxnm --> NULL. */ + case 2556: value = 3308; break; /* fmin --> bfmin. */ + case 3308: return NULL; /* bfmin --> NULL. */ + case 2560: value = 3312; break; /* fminnm --> bfminnm. */ + case 3312: return NULL; /* bfminnm --> NULL. */ + case 2547: value = 3299; break; /* fmax --> bfmax. */ + case 3299: return NULL; /* bfmax --> NULL. */ + case 2549: value = 3301; break; /* fmax --> bfmax. */ + case 3301: return NULL; /* bfmax --> NULL. */ + case 2551: value = 3303; break; /* fmaxnm --> bfmaxnm. */ + case 3303: return NULL; /* bfmaxnm --> NULL. */ + case 2553: value = 3305; break; /* fmaxnm --> bfmaxnm. */ + case 3305: return NULL; /* bfmaxnm --> NULL. */ + case 2555: value = 3307; break; /* fmin --> bfmin. */ + case 3307: return NULL; /* bfmin --> NULL. */ + case 2557: value = 3309; break; /* fmin --> bfmin. */ + case 3309: return NULL; /* bfmin --> NULL. */ + case 2559: value = 3311; break; /* fminnm --> bfminnm. */ + case 3311: return NULL; /* bfminnm --> NULL. */ + case 2561: value = 3313; break; /* fminnm --> bfminnm. */ + case 3313: return NULL; /* bfminnm --> NULL. */ case 2455: value = 2460; break; /* st1q --> st1q. */ case 2460: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ From patchwork Fri Jul 19 12:14:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 94214 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 40E05385E83A for ; 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FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that "+sme-b16b16" enables "+sme2" and "+sve-b16b16". The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en --- gas/NEWS | 2 + gas/config/tc-aarch64.c | 2 + gas/doc/c-aarch64.texi | 8 +- .../gas/aarch64/bfloat16-2-invalid.l | 16 +- .../gas/aarch64/bfloat16-sme2-1-bad.d | 4 + .../gas/aarch64/bfloat16-sme2-1-bad.l | 193 ++++++++++++++++++ .../gas/aarch64/bfloat16-sme2-1-bad.s | 173 ++++++++++++++++ gas/testsuite/gas/aarch64/bfloat16-sme2-1.d | 122 +++++++++++ gas/testsuite/gas/aarch64/bfloat16-sme2-1.s | 139 +++++++++++++ include/opcode/aarch64.h | 2 + opcodes/aarch64-tbl.h | 30 +++ 11 files changed, 681 insertions(+), 10 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.d create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.l create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.s create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-1.d create mode 100644 gas/testsuite/gas/aarch64/bfloat16-sme2-1.s diff --git a/gas/NEWS b/gas/NEWS index a677cc67947..aa73f277714 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -18,6 +18,8 @@ * Add support for 'armv9.5-a' for -march in AArch64 GAS. +* Support for 'BFloat16' feature in AArch64 GAS. + * In x86 Intel syntax undue mnemonic suffixes are now warned about. This is a first step towards rejecting their use where unjustified. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 0699bd0eaed..30f664b72c9 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10744,6 +10744,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURES (2, FP8, SME2)}, {"sme-f8f16", AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F8F32)}, + {"sme-b16b16", AARCH64_FEATURES (3, SME_B16B16, SVE_B16B16, SME2), + AARCH64_NO_FEATURES}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 8e46038a787..5682a53f442 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -161,8 +161,6 @@ automatically cause those extensions to be disabled. @headitem Extension @tab Depends upon @tab Description @item @code{aes} @tab @code{simd} @tab Enable the AES and PMULL cryptographic extensions. -@c @item @code{b16b16} @tab @code{sve2} -@c @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2. @item @code{bf16} @tab @code{fp} @tab Enable BFloat16 extension. @item @code{brbe} @tab @@ -271,6 +269,8 @@ automatically cause those extensions to be disabled. @tab Enable the SM3 and SM4 cryptographic extensions. @item @code{sme} @tab @code{sve2}, @code{bf16} @tab Enable the Scalable Matrix Extension. +@item @code{sme-b16b16} @tab @code{sme2}, @code{sve-b16b16} + @tab Enable SME ZA-targeting non-widening BFloat16 instructions.. @item @code{sme-f8f16} @tab @code{sme-f8f32} @tab Enable the SME F8F16 Extension. @item @code{sme-f8f32} @tab @code{sme2}, @code{fp8} @@ -301,6 +301,10 @@ automatically cause those extensions to be disabled. @tab Enable the SVE2 AES and PMULL Extensions. @item @code{sve2-bitperm} @tab @code{sve2} @tab Enable the SVE2 BITPERM Extension. +@item @code{sve-b16b16} @tab @code{sve2} + @tab Enable SVE Z-targeting non-widening BFloat16 instructions in Non-streaming SVE mode. +@item @code{sve-b16b16} @tab @code{sme2} + @tab Enable SME Z-targeting multi-vector non-widening BFloat16 instructions. @item @code{sve2-sha3} @tab @code{sve2}, @code{sha3} @tab Enable the SVE2 SHA3 Extension. @item @code{sve2-sm4} @tab @code{sve2}, @code{sm4} diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l index 7742e9d4865..cd8981017ab 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l +++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l @@ -165,8 +165,8 @@ .*: Error: operand mismatch -- `bfadd z31.b,z31.s,z31.d' .*: Info: did you mean this\? .*: Info: bfadd z31.h, z31.h, z31.h -.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h},z0.h,z0.h' -.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h-z0.h},z0.h' +.*: Error: expected a register at operand 1 -- `bfadd {z0.h},z0.h,z0.h' +.*: Error: expected a register at operand 1 -- `bfadd {z0.h-z0.h},z0.h' .*: Error: comma expected between operands at operand 3 -- `bfadd z0.h,z0.h' .*: Error: operand mismatch -- `bfclamp z0.b,z0.h,z0.h' .*: Info: did you mean this\? @@ -201,8 +201,8 @@ .*: Error: operand mismatch -- `bfmla z31.b,z31.s,z31.d\[8\]' .*: Info: did you mean this\? .*: Info: bfmla z31.h, z31.h, z31.h\[8\] -.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]' -.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h-z0.h},z0.h\[2\]' +.*: Error: expected a register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]' +.*: Error: expected a register at operand 1 -- `bfmla {z0.h-z0.h},z0.h\[2\]' .*: Error: expected an SVE predicate register at operand 2 -- `bfmla z0.h,z0.h\[3\]' .*: Error: operand mismatch -- `bfmls z0.b,z0.h,z0.h\[0\]' .*: Info: did you mean this\? @@ -219,8 +219,8 @@ .*: Error: operand mismatch -- `bfmls z31.b,z31.s,z31.d\[8\]' .*: Info: did you mean this\? .*: Info: bfmls z31.h, z31.h, z31.h\[8\] -.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]' -.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h-z0.h},z0.h\[2\]' +.*: Error: expected a register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]' +.*: Error: expected a register at operand 1 -- `bfmls {z0.h-z0.h},z0.h\[2\]' .*: Error: expected an SVE predicate register at operand 2 -- `bfmls z0.h,z0.h\[3\]' .*: Error: operand mismatch -- `bfmul z0.b,z0.h,z0.h\[0\]' .*: Info: did you mean this\? @@ -255,8 +255,8 @@ .*: Error: operand mismatch -- `bfsub z31.b,z31.s,z31.d' .*: Info: did you mean this\? .*: Info: bfsub z31.h, z31.h, z31.h -.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h},z0.h,z0.h' -.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h-z0.h},z0.h' +.*: Error: expected a register at operand 1 -- `bfsub {z0.h},z0.h,z0.h' +.*: Error: expected a register at operand 1 -- `bfsub {z0.h-z0.h},z0.h' .*: Error: comma expected between operands at operand 3 -- `bfsub z0.h,z0.h' .*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z1.h,z3.h,z16.h' .*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmla z10.h,z16.h,z3.h\[7\]' diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.d b/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.d new file mode 100644 index 00000000000..e03774e1733 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.d @@ -0,0 +1,4 @@ +#name: Test of invalid SME2 non-widening BFloat16 instructions. +#as: -march=armv9.4-a+sme-b16b16 +#source: bfloat16-sme2-1-bad.s +#error_output: bfloat16-sme2-1-bad.l diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.l b/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.l new file mode 100644 index 00000000000..c77c9457e0e --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.l @@ -0,0 +1,193 @@ +.*: Assembler messages: +.*: Error: operand mismatch -- `bfadd za.s\[w8,0,vgx2\],{z0.h-z1.h}' +.*: Info: did you mean this\? +.*: Info: bfadd za.h\[w8, 0, vgx2\], {z0.h-z1.h} +.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w13,0,vgx2\],{z1.h-z0.h}' +.*: Error: invalid vector group size at operand 1 -- `bfadd za.h\[w8,11,vgx3\],{z0.h-z1.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w8,0,vgx2\],{z0.h-z4.h}' +.*: Error: operand mismatch -- `bfadd za.s\[w8,0,vgx4\],{z0.h-z3.h}' +.*: Info: did you mean this\? +.*: Info: bfadd za.h\[w8, 0, vgx4\], {z0.h-z3.h} +.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w14,0,vgx4\],{z10.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfadd za.h\[w8,15,vgx1\],{z3.h-z2.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfadd za.h\[w8,0,vgx4\],{z30.h-z31.h}' +.*: Error: operand mismatch -- `bfsub za.s\[w8,0,vgx2\],{z0.h-z1.h}' +.*: Info: did you mean this\? +.*: Info: bfsub za.h\[w8, 0, vgx2\], {z0.h-z1.h} +.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w13,0,vgx2\],{z1.h-z0.h}' +.*: Error: invalid vector group size at operand 1 -- `bfsub za.h\[w8,11,vgx3\],{z0.h-z1.h}' +.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w8,0,vgx2\],{z0.h-z4.h}' +.*: Error: operand mismatch -- `bfsub za.s\[w8,0,vgx4\],{z0.h-z3.h}' +.*: Info: did you mean this\? +.*: Info: bfsub za.h\[w8, 0, vgx4\], {z0.h-z3.h} +.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w14,0,vgx4\],{z10.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfsub za.h\[w8,15,vgx1\],{z3.h-z2.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfsub za.h\[w8,0,vgx4\],{z30.h-z31.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,0,vgx3\],{z30.h-z31.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[7\]' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0.h},z0.h\[7\]' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0.h},z0.h' +.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0-z1},z0.h\[7\]' +.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0-z1}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx1\],{z10.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{z30.h-z31.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx1\],{z0.h-z1.h},z15.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[7\]' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0.h},z0.h\[7\]' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0.h},z0.h' +.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0-z1},z0.h\[7\]' +.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0-z1}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,0,vgx3\],{z31.h-z0.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0.h},z15.h' +.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx2\],{z0.h-z1.h},z15' +.*: Info: did you mean this\? +.*: Info: bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h +.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx2\],{z0.h-z1.h},z20' +.*: Info: did you mean this\? +.*: Info: bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z20.h +.*: Error: comma expected between operands at operand 3 -- `bfmla za.h\[w8,0,vgx2\],{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w14,0,vgx1\],{z10.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{z31.h-z2.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{z0.h-z1.h},z15.h' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0.h},z15.h' +.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx4\],{z0.h-z1.h},z15' +.*: Info: did you mean this\? +.*: Info: bfmla za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z15.h +.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx4\],{z0.h-z1.h},z20' +.*: Info: did you mean this\? +.*: Info: bfmla za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z20.h +.*: Error: comma expected between operands at operand 3 -- `bfmla za.h\[w8,0,vgx4\],{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{z0.h-z1.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{z10.h-z1.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,15,vgx3\],{z0.h-z1.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{z30.h-z31.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx3\],{z0.h-z1.h},{z30.h-z31.h}' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0.h},{z30.h-z31.h}' +.*: Error: expected a list of 2 registers at operand 3 -- `bfmla za.h\[w8,0,vgx2\],{z0.h-z1.h},{z30.h}' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0.h},{z30.h}' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{z0.h},{z30.h}' +.*: Error: operand mismatch -- `bfmla za.b\[w8,20,vgx2\],{z0.h},{z30.h}' +.*: Info: did you mean this\? +.*: Info: bfmla za.h\[w8, 20, vgx2\], {z0.h}, {z30.h} +.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx1\],{z0.h-z1.h},{z0.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx1\],{z10.h-z1.h},{z0.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,15,vgx1\],{z0.h-z1.h},{z0.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{z30.h-z31.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{z0.h-z1.h},{z30.h-z31.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0.h},{z30.h-z31.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0.h-z1.h},{z30.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0.h},{z30.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{z0.h},{z30.h}' +.*: Error: operand mismatch -- `bfmla za.b\[w8,20,vgx4\],{z0.h},{z30.h}' +.*: Info: did you mean this\? +.*: Info: bfmla za.h\[w8, 20, vgx4\], {z0.h}, {z30.h} +.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,0,vgx3\],{z30.h-z31.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[7\]' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0.h},z0.h\[7\]' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0.h},z0.h' +.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0-z1},z0.h\[7\]' +.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0-z1}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx1\],{z10.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{z30.h-z31.h},z0.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx1\],{z0.h-z1.h},z15.h\[0\]' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[7\]' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0.h},z0.h\[7\]' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0.h},z0.h' +.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0-z1},z0.h\[7\]' +.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0-z1}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,0,vgx3\],{z31.h-z0.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0.h},z15.h' +.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx2\],{z0.h-z1.h},z15' +.*: Info: did you mean this\? +.*: Info: bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h +.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx2\],{z0.h-z1.h},z20' +.*: Info: did you mean this\? +.*: Info: bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z20.h +.*: Error: comma expected between operands at operand 3 -- `bfmls za.h\[w8,0,vgx2\],{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w14,0,vgx1\],{z10.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{z31.h-z2.h},z0.h' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{z0.h-z1.h},z15.h' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0.h},z15.h' +.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx4\],{z0.h-z1.h},z15' +.*: Info: did you mean this\? +.*: Info: bfmls za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z15.h +.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx4\],{z0.h-z1.h},z20' +.*: Info: did you mean this\? +.*: Info: bfmls za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z20.h +.*: Error: comma expected between operands at operand 3 -- `bfmls za.h\[w8,0,vgx4\],{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{z0.h-z1.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{z10.h-z1.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,15,vgx3\],{z0.h-z1.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{z30.h-z31.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx3\],{z0.h-z1.h},{z30.h-z31.h}' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0.h},{z30.h-z31.h}' +.*: Error: expected a list of 2 registers at operand 3 -- `bfmls za.h\[w8,0,vgx2\],{z0.h-z1.h},{z30.h}' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0.h},{z30.h}' +.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{z0.h},{z30.h}' +.*: Error: operand mismatch -- `bfmls za.b\[w8,20,vgx2\],{z0.h},{z30.h}' +.*: Info: did you mean this\? +.*: Info: bfmls za.h\[w8, 20, vgx2\], {z0.h}, {z30.h} +.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx1\],{z0.h-z1.h},{z0.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx1\],{z10.h-z1.h},{z0.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,15,vgx1\],{z0.h-z1.h},{z0.h-z3.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{z30.h-z31.h},{z0.h-z1.h}' +.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{z0.h-z1.h},{z30.h-z31.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0.h},{z30.h-z31.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0.h-z1.h},{z30.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0.h},{z30.h}' +.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{z0.h},{z30.h}' +.*: Error: operand mismatch -- `bfmls za.b\[w8,20,vgx4\],{z0.h},{z30.h}' +.*: Info: did you mean this\? +.*: Info: bfmls za.h\[w8, 20, vgx4\], {z0.h}, {z30.h} +.*: Error: operand mismatch -- `bfmopa ZA1.h,p0,p0/m,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfmopa za1.h, p0/m, p0/m, z0.h, z0.h +.*: Error: operand mismatch -- `bfmopa ZA0.h,p7/m,p0,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfmopa za0.h, p7/m, p0/m, z0.h, z0.h +.*: Error: operand mismatch -- `bfmopa ZA0.h,p0/m,p7/m,z0.s,z0.s' +.*: Info: did you mean this\? +.*: Info: bfmopa za0.h, p0/m, p7/m, z0.h, z0.h +.*: Error: operand mismatch -- `bfmopa ZA0.h,p0/m,p0/m,z31.d,z0.d' +.*: Info: did you mean this\? +.*: Info: bfmopa za0.h, p0/m, p0/m, z31.h, z0.h +.*: Error: ZA tile number out of range at operand 1 -- `bfmopa ZA2.h,p0/m,p8/m,z0.s,z31.b' +.*: Error: ZA tile number out of range at operand 1 -- `bfmopa ZA4.h,p15/m,p11/m,z0.s,z31.b' +.*: Error: operand mismatch -- `bfmops ZA1.h,p0,p0/m,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfmops za1.h, p0/m, p0/m, z0.h, z0.h +.*: Error: operand mismatch -- `bfmops ZA0.h,p7/m,p0,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfmops za0.h, p7/m, p0/m, z0.h, z0.h +.*: Error: operand mismatch -- `bfmops ZA0.h,p0/m,p7/m,z0.s,z0.s' +.*: Info: did you mean this\? +.*: Info: bfmops za0.h, p0/m, p7/m, z0.h, z0.h +.*: Error: operand mismatch -- `bfmops ZA0.h,p0/m,p0/m,z31.d,z0.d' +.*: Info: did you mean this\? +.*: Info: bfmops za0.h, p0/m, p0/m, z31.h, z0.h +.*: Error: ZA tile number out of range at operand 1 -- `bfmops ZA2.h,p0/m,p8/m,z0.s,z31.b' +.*: Error: ZA tile number out of range at operand 1 -- `bfmops ZA4.h,p15/m,p11/m,z0.s,z31.b' diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.s b/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.s new file mode 100644 index 00000000000..1ba22e18e3c --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-1-bad.s @@ -0,0 +1,173 @@ +/* BFADD. */ +bfadd za.s[w8, 0, vgx2], {z0.h - z1.h} +bfadd za.h[w13, 0, vgx2], {z1.h - z0.h} +bfadd za.h[w8, 11, vgx3], {z0.h - z1.h} +bfadd za.h[w8, 0, vgx2], {z0.h - z4.h} + +bfadd za.s[w8, 0, vgx4], {z0.h - z3.h} +bfadd za.h[w14, 0, vgx4], {z10.h - z3.h} +bfadd za.h[w8, 15, vgx1], {z3.h - z2.h} +bfadd za.h[w8, 0, vgx4], {z30.h - z31.h} + +/* BFSUB. */ +bfsub za.s[w8, 0, vgx2], {z0.h - z1.h} +bfsub za.h[w13, 0, vgx2], {z1.h - z0.h} +bfsub za.h[w8, 11, vgx3], {z0.h - z1.h} +bfsub za.h[w8, 0, vgx2], {z0.h - z4.h} + +bfsub za.s[w8, 0, vgx4], {z0.h - z3.h} +bfsub za.h[w14, 0, vgx4], {z10.h - z3.h} +bfsub za.h[w8, 15, vgx1], {z3.h - z2.h} +bfsub za.h[w8, 0, vgx4], {z30.h - z31.h} + +/* BFMLA (multiple and indexed vector). */ +bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0] +bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0] +bfmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0] +bfmla za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0] +bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0] +bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7] +bfmla za.h[w8, 0, vgx2], {z0.h}, z0.h[7] +bfmla za.h[w8, 0, vgx2], {z0.h}, z0.h +bfmla za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7] +bfmla za.h[w8, 0, vgx2], {z0 - z1} + +bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0] +bfmla za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0] +bfmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0] +bfmla za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0] +bfmla za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0] +bfmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7] +bfmla za.h[w8, 0, vgx4], {z0.h}, z0.h[7] +bfmla za.h[w8, 0, vgx4], {z0.h}, z0.h +bfmla za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7] +bfmla za.h[w8, 0, vgx4], {z0 - z1} + +/* BFMLA (multiple and single vector). */ +bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h +bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h +bfmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h +bfmla za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h +bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h +bfmla za.h[w8, 0, vgx2], {z0.h}, z15.h +bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z15 +bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z20 +bfmla za.h[w8, 0, vgx2], {z0.h -z1.h} + +bfmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h +bfmla za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h +bfmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h +bfmla za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h +bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h +bfmla za.h[w8, 0, vgx4], {z0.h}, z15.h +bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z15 +bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z20 +bfmla za.h[w8, 0, vgx4], {z0.h -z1.h} + +/* BFMLA (multiple vectors). */ +bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h} +bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h} +bfmla za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h} +bfmla za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h} +bfmla za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h} +bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h} +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h} +bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h} +bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h} +bfmla za.b[w8, 20, vgx2], {z0.h}, {z30.h} + +bfmla za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h} +bfmla za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h} +bfmla za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h} +bfmla za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h} +bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h} +bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h} +bfmla za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h} +bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h} +bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h} +bfmla za.b[w8, 20, vgx4], {z0.h}, {z30.h} + +/* BFMLS (multiple and indexed vector). */ +bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0] +bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0] +bfmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0] +bfmls za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0] +bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0] +bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7] +bfmls za.h[w8, 0, vgx2], {z0.h}, z0.h[7] +bfmls za.h[w8, 0, vgx2], {z0.h}, z0.h +bfmls za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7] +bfmls za.h[w8, 0, vgx2], {z0 - z1} + +bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0] +bfmls za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0] +bfmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0] +bfmls za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0] +bfmls za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0] +bfmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7] +bfmls za.h[w8, 0, vgx4], {z0.h}, z0.h[7] +bfmls za.h[w8, 0, vgx4], {z0.h}, z0.h +bfmls za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7] +bfmls za.h[w8, 0, vgx4], {z0 - z1} + +/* BFMLS (multiple and single vector). */ +bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h +bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h +bfmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h +bfmls za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h +bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h +bfmls za.h[w8, 0, vgx2], {z0.h}, z15.h +bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z15 +bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z20 +bfmls za.h[w8, 0, vgx2], {z0.h -z1.h} + +bfmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h +bfmls za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h +bfmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h +bfmls za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h +bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h +bfmls za.h[w8, 0, vgx4], {z0.h}, z15.h +bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z15 +bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z20 +bfmls za.h[w8, 0, vgx4], {z0.h -z1.h} + +/* BFMLS (multiple vectors). */ +bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h} +bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h} +bfmls za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h} +bfmls za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h} +bfmls za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h} +bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h} +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h} +bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h} +bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h} +bfmls za.b[w8, 20, vgx2], {z0.h}, {z30.h} + +bfmls za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h} +bfmls za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h} +bfmls za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h} +bfmls za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h} +bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h} +bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h} +bfmls za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h} +bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h} +bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h} +bfmls za.b[w8, 20, vgx4], {z0.h}, {z30.h} + +/* BFMOPA. */ +bfmopa ZA0.s, p0/m, p0/m, z0.h, z0.h +bfmopa ZA1.h, p0, p0/m, z0.h, z0.h +bfmopa ZA0.h, p7/m, p0, z0.h, z0.h +bfmopa ZA0.h, p0/m, p7/m, z0.s, z0.s +bfmopa ZA0.h, p0/m, p0/m, z31.d, z0.d +bfmopa ZA2.h, p0/m, p8/m, z0.s, z31.b +bfmopa ZA4.h, p15/m, p11/m, z0.s, z31.b + +/* BFMOPS. */ +bfmops ZA0.s, p0/m, p0/m, z0.h, z0.h +bfmops ZA1.h, p0, p0/m, z0.h, z0.h +bfmops ZA0.h, p7/m, p0, z0.h, z0.h +bfmops ZA0.h, p0/m, p7/m, z0.s, z0.s +bfmops ZA0.h, p0/m, p0/m, z31.d, z0.d +bfmops ZA2.h, p0/m, p8/m, z0.s, z31.b +bfmops ZA4.h, p15/m, p11/m, z0.s, z31.b diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-1.d b/gas/testsuite/gas/aarch64/bfloat16-sme2-1.d new file mode 100644 index 00000000000..8cbe4806842 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-1.d @@ -0,0 +1,122 @@ +#name: Test of SME2 non-widening BFloat16 instructions. +#as: -march=armv9.4-a+sme-b16b16 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: c1e41c00 bfadd za.h\[w8, 0, vgx2\], {z0.h-z1.h} +.*: c1e47c00 bfadd za.h\[w11, 0, vgx2\], {z0.h-z1.h} +.*: c1e41c07 bfadd za.h\[w8, 7, vgx2\], {z0.h-z1.h} +.*: c1e41fc0 bfadd za.h\[w8, 0, vgx2\], {z30.h-z31.h} +.*: c1e41fc3 bfadd za.h\[w8, 3, vgx2\], {z30.h-z31.h} +.*: c1e51c00 bfadd za.h\[w8, 0, vgx4\], {z0.h-z3.h} +.*: c1e57c00 bfadd za.h\[w11, 0, vgx4\], {z0.h-z3.h} +.*: c1e51c07 bfadd za.h\[w8, 7, vgx4\], {z0.h-z3.h} +.*: c1e51f80 bfadd za.h\[w8, 0, vgx4\], {z28.h-z31.h} +.*: c1e51f83 bfadd za.h\[w8, 3, vgx4\], {z28.h-z31.h} +.*: c1e41c08 bfsub za.h\[w8, 0, vgx2\], {z0.h-z1.h} +.*: c1e47c08 bfsub za.h\[w11, 0, vgx2\], {z0.h-z1.h} +.*: c1e41c0f bfsub za.h\[w8, 7, vgx2\], {z0.h-z1.h} +.*: c1e41fc8 bfsub za.h\[w8, 0, vgx2\], {z30.h-z31.h} +.*: c1e41fcb bfsub za.h\[w8, 3, vgx2\], {z30.h-z31.h} +.*: c1e51c08 bfsub za.h\[w8, 0, vgx4\], {z0.h-z3.h} +.*: c1e57c08 bfsub za.h\[w11, 0, vgx4\], {z0.h-z3.h} +.*: c1e51c0f bfsub za.h\[w8, 7, vgx4\], {z0.h-z3.h} +.*: c1e51f88 bfsub za.h\[w8, 0, vgx4\], {z28.h-z31.h} +.*: c1e51f8b bfsub za.h\[w8, 3, vgx4\], {z28.h-z31.h} +.*: c1101020 bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\] +.*: c1107020 bfmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\] +.*: c1101027 bfmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\] +.*: c11013e0 bfmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\] +.*: c11f1020 bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\] +.*: c1101c28 bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\] +.*: c1101c2b bfmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\] +.*: c1109020 bfmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\] +.*: c110f020 bfmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\] +.*: c1109027 bfmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\] +.*: c11093a0 bfmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\] +.*: c11f9020 bfmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\] +.*: c1109c28 bfmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\] +.*: c1109c2b bfmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\] +.*: c1601c00 bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h +.*: c1607c00 bfmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h +.*: c1601c07 bfmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h +.*: c1601fe0 bfmla za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h +.*: c16f1c00 bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h +.*: c16f1c03 bfmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h +.*: c1701c00 bfmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h +.*: c1707c00 bfmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h +.*: c1701c07 bfmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h +.*: c1701fe0 bfmla za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h +.*: c17f1c00 bfmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h +.*: c17f1c03 bfmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h +.*: c1e01008 bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h} +.*: c1e07008 bfmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h} +.*: c1e0100f bfmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h} +.*: c1e013c8 bfmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h} +.*: c1fe1008 bfmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h} +.*: c1fe100b bfmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h} +.*: c1e11008 bfmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h} +.*: c1e17008 bfmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h} +.*: c1e1100f bfmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h} +.*: c1e11388 bfmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h} +.*: c1fd1008 bfmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h} +.*: c1fd100b bfmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h} +.*: c1101030 bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\] +.*: c1107030 bfmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\] +.*: c1101037 bfmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\] +.*: c11013f0 bfmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\] +.*: c11f1030 bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\] +.*: c1101c38 bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\] +.*: c1101c3b bfmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\] +.*: c1109030 bfmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\] +.*: c110f030 bfmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\] +.*: c1109037 bfmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\] +.*: c11093b0 bfmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\] +.*: c11f9030 bfmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\] +.*: c1109c38 bfmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\] +.*: c1109c3b bfmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\] +.*: c1601c08 bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h +.*: c1607c08 bfmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h +.*: c1601c0f bfmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h +.*: c1601fe8 bfmls za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h +.*: c16f1c08 bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h +.*: c16f1c0b bfmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h +.*: c1701c08 bfmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h +.*: c1707c08 bfmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h +.*: c1701c0f bfmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h +.*: c1701fe8 bfmls za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h +.*: c17f1c08 bfmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h +.*: c17f1c0b bfmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h +.*: c1e01018 bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h} +.*: c1e07018 bfmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h} +.*: c1e0101f bfmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h} +.*: c1e013d8 bfmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h} +.*: c1fe1018 bfmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h} +.*: c1fe101b bfmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h} +.*: c1e11018 bfmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h} +.*: c1e17018 bfmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h} +.*: c1e1101f bfmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h} +.*: c1e11398 bfmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h} +.*: c1fd1018 bfmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h} +.*: c1fd101b bfmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h} +.*: 81a00008 bfmopa za0.h, p0/m, p0/m, z0.h, z0.h +.*: 81a00009 bfmopa za1.h, p0/m, p0/m, z0.h, z0.h +.*: 81a01c08 bfmopa za0.h, p7/m, p0/m, z0.h, z0.h +.*: 81a0e008 bfmopa za0.h, p0/m, p7/m, z0.h, z0.h +.*: 81a003e8 bfmopa za0.h, p0/m, p0/m, z31.h, z0.h +.*: 81bf0008 bfmopa za0.h, p0/m, p0/m, z0.h, z31.h +.*: 81afad48 bfmopa za0.h, p3/m, p5/m, z10.h, z15.h +.*: 81b965e9 bfmopa za1.h, p1/m, p3/m, z15.h, z25.h +.*: 81a00018 bfmops za0.h, p0/m, p0/m, z0.h, z0.h +.*: 81a00019 bfmops za1.h, p0/m, p0/m, z0.h, z0.h +.*: 81a01c18 bfmops za0.h, p7/m, p0/m, z0.h, z0.h +.*: 81a0e018 bfmops za0.h, p0/m, p7/m, z0.h, z0.h +.*: 81a003f8 bfmops za0.h, p0/m, p0/m, z31.h, z0.h +.*: 81bf0018 bfmops za0.h, p0/m, p0/m, z0.h, z31.h +.*: 81afad58 bfmops za0.h, p3/m, p5/m, z10.h, z15.h +.*: 81b965f9 bfmops za1.h, p1/m, p3/m, z15.h, z25.h diff --git a/gas/testsuite/gas/aarch64/bfloat16-sme2-1.s b/gas/testsuite/gas/aarch64/bfloat16-sme2-1.s new file mode 100644 index 00000000000..e4aefdccda7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-sme2-1.s @@ -0,0 +1,139 @@ +/* BFADD. */ +bfadd za.h[w8, 0, vgx2], {z0.h - z1.h} +bfadd za.h[w11, 0, vgx2], {z0.h - z1.h} +bfadd za.h[w8, 7, vgx2], {z0.h - z1.h} +bfadd za.h[w8, 0, vgx2], {z30.h - z31.h} +bfadd za.h[w8, 3], {z30.h - z31.h} + +bfadd za.h[w8, 0, vgx4], {z0.h - z3.h} +bfadd za.h[w11, 0, vgx4], {z0.h - z3.h} +bfadd za.h[w8, 7, vgx4], {z0.h - z3.h} +bfadd za.h[w8, 0, vgx4], {z28.h - z31.h} +bfadd za.h[w8, 3], {z28.h - z31.h} + +/* BFSUB. */ +bfsub za.h[w8, 0, vgx2], {z0.h - z1.h} +bfsub za.h[w11, 0, vgx2], {z0.h - z1.h} +bfsub za.h[w8, 7, vgx2], {z0.h - z1.h} +bfsub za.h[w8, 0, vgx2], {z30.h - z31.h} +bfsub za.h[w8, 3], {z30.h - z31.h} + +bfsub za.h[w8, 0, vgx4], {z0.h - z3.h} +bfsub za.h[w11, 0, vgx4], {z0.h - z3.h} +bfsub za.h[w8, 7, vgx4], {z0.h - z3.h} +bfsub za.h[w8, 0, vgx4], {z28.h - z31.h} +bfsub za.h[w8, 3], {z28.h - z31.h} + +/* BFMLA (multiple and indexed vector). */ +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0] +bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0] +bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0] +bfmla za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0] +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0] +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7] +bfmla za.h[w8, 3], {z0.h - z1.h}, z0.h[7] + +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] +bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0] +bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0] +bfmla za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0] +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0] +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7] +bfmla za.h[w8, 3], {z0.h - z3.h}, z0.h[7] + +/* BFMLA (multiple and single vector). */ +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h +bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h +bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h +bfmla za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h +bfmla za.h[w8, 3], {z0.h - z1.h}, z15.h + +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h +bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h +bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h +bfmla za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h +bfmla za.h[w8, 3], {z0.h - z3.h}, z15.h + +/* BFMLA (multiple vectors). */ +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h} +bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h} +bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h} +bfmla za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h} +bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h} +bfmla za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h} + +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} +bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} +bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h} +bfmla za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h} +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h} +bfmla za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h} + +/* BFMLS (multiple and indexed vector). */ +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0] +bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0] +bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0] +bfmls za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0] +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0] +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7] +bfmls za.h[w8, 3], {z0.h - z1.h}, z0.h[7] + +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] +bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0] +bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0] +bfmls za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0] +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0] +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7] +bfmls za.h[w8, 3], {z0.h - z3.h}, z0.h[7] + +/* BFMLS (multiple and single vector). */ +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h +bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h +bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h +bfmls za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h +bfmls za.h[w8, 3], {z0.h - z1.h}, z15.h + +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h +bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h +bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h +bfmls za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h +bfmls za.h[w8, 3], {z0.h - z3.h}, z15.h + +/* BFMLS (multiple vectors). */ +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h} +bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h} +bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h} +bfmls za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h} +bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h} +bfmls za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h} + +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} +bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} +bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h} +bfmls za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h} +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h} +bfmls za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h} + +/* BFMOPA. */ +bfmopa ZA0.h, p0/m, p0/m, z0.h, z0.h +bfmopa ZA1.h, p0/m, p0/m, z0.h, z0.h +bfmopa ZA0.h, p7/m, p0/m, z0.h, z0.h +bfmopa ZA0.h, p0/m, p7/m, z0.h, z0.h +bfmopa ZA0.h, p0/m, p0/m, z31.h, z0.h +bfmopa ZA0.h, p0/m, p0/m, z0.h, z31.h +bfmopa ZA0.h, p3/m, p5/m, z10.h, z15.h +bfmopa ZA1.h, p1/m, p3/m, z15.h, z25.h + +/* BFMOPS. */ +bfmops ZA0.h, p0/m, p0/m, z0.h, z0.h +bfmops ZA1.h, p0/m, p0/m, z0.h, z0.h +bfmops ZA0.h, p7/m, p0/m, z0.h, z0.h +bfmops ZA0.h, p0/m, p7/m, z0.h, z0.h +bfmops ZA0.h, p0/m, p0/m, z31.h, z0.h +bfmops ZA0.h, p0/m, p0/m, z0.h, z31.h +bfmops ZA0.h, p3/m, p5/m, z10.h, z15.h +bfmops ZA1.h, p1/m, p3/m, z15.h, z25.h diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 5f43a235dd1..9c9cb60637e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -264,6 +264,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_F8F16, /* SVE2 non-widening BFloat16 instructions. */ AARCH64_FEATURE_SVE_B16B16, + /* SME2 non-widening BFloat16 instructions. */ + AARCH64_FEATURE_SME_B16B16, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 82816d5db38..8bc6c1887f3 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1715,6 +1715,10 @@ { \ QLF5(S_H,P_M,P_M,S_B,S_B) \ } +#define OP_SVE_HMMHH \ +{ \ + QLF5(S_H,P_M,P_M,S_H,S_H) \ +} #define OP_SVE_HMS \ { \ QLF3(S_H,P_M,S_S), \ @@ -2815,6 +2819,8 @@ static const aarch64_feature_set aarch64_feature_sve_sve2_b16b16 = AARCH64_FEATURES (3, SVE_B16B16, SVE2, SVE_SVE2_B16B16); static const aarch64_feature_set aarch64_feature_sve_sme2_b16b16 = AARCH64_FEATURES (3, SVE_B16B16, SME2, SVE_SME2_B16B16); +static const aarch64_feature_set aarch64_feature_sme_b16b16 = + AARCH64_FEATURES (2, SME_B16B16, SME2); static const aarch64_feature_set aarch64_feature_sme2p1 = AARCH64_FEATURE (SME2p1); static const aarch64_feature_set aarch64_feature_sve2p1 = @@ -2927,6 +2933,7 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = #define D128_THE &aarch64_feature_d128_the #define SVE_SVE2_B16B16 &aarch64_feature_sve_sve2_b16b16 #define SVE_SME2_B16B16 &aarch64_feature_sve_sme2_b16b16 +#define SME_B16B16 &aarch64_feature_sme_b16b16 #define SME2p1 &aarch64_feature_sme2p1 #define SVE2p1 &aarch64_feature_sve2p1 #define RCPC3 &aarch64_feature_rcpc3 @@ -3035,6 +3042,9 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = #define SVE_SME2_B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_SME2_B16B16, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } +#define SME_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME_B16B16, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } #define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -6672,6 +6682,26 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE_SME2_B16B16_INSN("bfclamp", 0xc120c000, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, F_OD(2), 0), SVE_SME2_B16B16_INSN("bfclamp", 0xc120c800, 0xffe0fc03, sme_misc, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, F_OD(4), 0), +/* SME ZA-targeting non-widening BFloat16 instructions. */ + SME_B16B16_INSN("bfadd", 0xc1e41c00, 0xffff9c38, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD(2), 0), + SME_B16B16_INSN("bfadd", 0xc1e51c00, 0xffff9c78, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD(4), 0), + SME_B16B16_INSN("bfsub", 0xc1e41c08, 0xffff9c38, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD(2), 0), + SME_B16B16_INSN("bfsub", 0xc1e51c08, 0xffff9c78, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD(4), 0), + SME_B16B16_INSN("bfmla", 0xc1101020, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0), + SME_B16B16_INSN("bfmla", 0xc1109020, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0), + SME_B16B16_INSN("bfmla", 0xc1601c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(2), 0), + SME_B16B16_INSN("bfmla", 0xc1701c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(4), 0), + SME_B16B16_INSN("bfmla", 0xc1e01008, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 0), + SME_B16B16_INSN("bfmla", 0xc1e11008, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 0), + SME_B16B16_INSN("bfmls", 0xc1101030, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0), + SME_B16B16_INSN("bfmls", 0xc1109030, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0), + SME_B16B16_INSN("bfmls", 0xc1601c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(2), 0), + SME_B16B16_INSN("bfmls", 0xc1701c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(4), 0), + SME_B16B16_INSN("bfmls", 0xc1e01018, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 0), + SME_B16B16_INSN("bfmls", 0xc1e11018, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 0), + SME_B16B16_INSN("bfmopa", 0x81a00008, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0), + SME_B16B16_INSN("bfmops", 0x81a00018, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0), + /* SME2.1 movaz instructions. */ SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0), SME2p1_INSN ("movaz", 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+ return 3348; } else { @@ -224,7 +224,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000100x0010xxxxxx1xxxxxxxxx movaz. */ - return 3332; + return 3350; } } else @@ -235,7 +235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x0010xxxxxx1xxxxxxxxx movaz. */ - return 3331; + return 3349; } else { @@ -243,7 +243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x0010xxxxxx1xxxxxxxxx movaz. */ - return 3333; + return 3351; } } } @@ -253,7 +253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x0011xxxxxx1xxxxxxxxx movaz. */ - return 3334; + return 3352; } } } @@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x000101x00xxxxxxxxxxxxxx luti4. */ - return 3446; + return 3464; } else { @@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101x00xxxxxxxxxxxxxx luti4. */ - return 3447; + return 3465; } else { @@ -318,7 +318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101x10xxxxxxxxxxxxxx luti4. */ - return 3327; + return 3345; } } else @@ -327,7 +327,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101xx1xxxxxxxxxxxxxx luti4. */ - return 3326; + return 3344; } } } @@ -369,7 +369,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000x011xxxxx001xxxxxxxxx movaz. */ - return 3320; + return 3338; } else { @@ -377,7 +377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000100x011xxxxx001xxxxxxxxx movaz. */ - return 3322; + return 3340; } } else @@ -388,7 +388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x011xxxxx001xxxxxxxxx movaz. */ - return 3321; + return 3339; } else { @@ -396,7 +396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x011xxxxx001xxxxxxxxx movaz. */ - return 3323; + return 3341; } } } @@ -420,7 +420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011000xxx00xxxxxxxxxx zero. */ - return 3335; + return 3353; } else { @@ -428,7 +428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011100xxx00xxxxxxxxxx zero. */ - return 3336; + return 3354; } } else @@ -439,7 +439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011010xxx00xxxxxxxxxx zero. */ - return 3338; + return 3356; } else { @@ -447,7 +447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011110xxx00xxxxxxxxxx zero. */ - return 3341; + return 3359; } } } @@ -461,7 +461,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011001xxx00xxxxxxxxxx zero. */ - return 3337; + return 3355; } else { @@ -469,7 +469,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011101xxx00xxxxxxxxxx zero. */ - return 3340; + return 3358; } } else @@ -480,7 +480,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011011xxx00xxxxxxxxxx zero. */ - return 3339; + return 3357; } else { @@ -488,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000011111xxx00xxxxxxxxxx zero. */ - return 3342; + return 3360; } } } @@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010011x1xxxx00xxxxxxxxxx movt. */ - return 3448; + return 3466; } } else @@ -563,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0111xxx0xx00xxxxxxxxxx luti2. */ - return 3325; + return 3343; } else { @@ -571,7 +571,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0111xxx1xx00xxxxxxxxxx luti2. */ - return 3324; + return 3342; } } } @@ -602,7 +602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx101xxxxxxxxx movaz. */ - return 3328; + return 3346; } } } @@ -639,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000000xx11xxxxx011xxxxxxxxx movaz. */ - return 3316; + return 3334; } else { @@ -647,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000100xx11xxxxx011xxxxxxxxx movaz. */ - return 3318; + return 3336; } } else @@ -658,7 +658,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010xx11xxxxx011xxxxxxxxx movaz. */ - return 3317; + return 3335; } else { @@ -666,7 +666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110xx11xxxxx011xxxxxxxxx movaz. */ - return 3319; + return 3337; } } } @@ -698,7 +698,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx111xxxxxxxxx movaz. */ - return 3329; + return 3347; } } } @@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx00xxx fmopa. */ - return 3514; + return 3532; } else { @@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx01xxx fmopa. */ - return 3513; + return 3531; } } else @@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xx0xxxxx1000xxx fmlall. */ - return 3507; + return 3525; } } } @@ -1752,37 +1752,59 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxxxxx1xxxxxx00xxxx fdot. */ - return 3492; + return 3510; } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx0xxxxxxxxx10xxxx - usmlall. */ - return 2933; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx0xx0xxxxxx10xxxx + usmlall. */ + return 2933; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xx0xxxxxx10xxxx + usmlall. */ + return 2934; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx1xxxxxxxxx10xxxx - usmlall. */ - return 2934; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx0xx1xxxxxx10xxxx + bfmla. */ + return 3320; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xx1xxxxxx10xxxx + bfmla. */ + return 3321; + } } } } } else { - if (((word >> 3) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 2) & 0x1) == 0) { - if (((word >> 2) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -1794,14 +1816,25 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000010000xxxxxxxxxxxxxxx101xx - sumlall. */ - return 2848; + xx0000010000xxxxxxxxxxxxxxx110xx + umlsll. */ + return 2906; } } else { - if (((word >> 5) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010000xxxxxxxxxxxxxxx1x1xx + sumlall. */ + return 2848; + } + } + else + { + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) { if (((word >> 15) & 0x1) == 0) { @@ -1826,7 +1859,29 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000010001xxxx0xxxxxxxxx110xxx + xx0000010001xxxx0xxxxxxxxx011xxx + umlsll. */ + return 2907; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xxxxxxxxx011xxx + umlsll. */ + return 2908; + } + } + } + else + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx0xx0xxxxxx11xxxx sumlall. */ return 2849; } @@ -1834,40 +1889,29 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000010001xxxx1xxxxxxxxx110xxx + xx0000010001xxxx1xx0xxxxxx11xxxx sumlall. */ return 2850; } } - } - } - else - { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010000xxxxxxxxxxxxxxx11xxx - umlsll. */ - return 2906; - } - else - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx0xxxxxxxxxx11xxx - umlsll. */ - return 2907; - } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx1xxxxxxxxxx11xxx - umlsll. */ - return 2908; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx0xx1xxxxxx11xxxx + bfmls. */ + return 3326; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xx1xxxxxx11xxxx + bfmls. */ + return 3327; + } } } } @@ -2124,7 +2168,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx0xxxxxx100xxx fmlall. */ - return 3506; + return 3524; } } } @@ -2229,7 +2273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx10xxxx fmlal. */ - return 3499; + return 3517; } } } @@ -2402,7 +2446,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx11xxxx fmlal. */ - return 3498; + return 3516; } } } @@ -2444,7 +2488,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010100xxxxxxxxxxxxxxxx0xxx fmlall. */ - return 3505; + return 3523; } else { @@ -2812,7 +2856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx111xxx fdot. */ - return 3485; + return 3503; } else { @@ -2881,7 +2925,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx001xxx fdot. */ - return 3486; + return 3504; } else { @@ -2960,7 +3004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx0xxxxxxx0xxxx fmlal. */ - return 3497; + return 3515; } else { @@ -3015,7 +3059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx01xxxxx00xxxx fvdotb. */ - return 3516; + return 3534; } else { @@ -3033,7 +3077,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx0xxxxxx10xxxx fdot. */ - return 3491; + return 3509; } } } @@ -3107,7 +3151,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx1xxxxxx10xxxx fvdot. */ - return 3515; + return 3533; } } } @@ -3187,7 +3231,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx01xxxxxx1xxxx fvdott. */ - return 3517; + return 3535; } else { @@ -3281,21 +3325,43 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 30) & 0x1) == 0) { - if (((word >> 4) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000001xx1xxxxxxxxxxxxxxxx0xxxx - fmopa. */ - return 2415; + if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001xx1xxxxxxxxxxxxxxxx00xxx + fmopa. */ + return 2415; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001xx1xxxxxxxxxxxxxxxx10xxx + fmops. */ + return 2418; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000001xx1xxxxxxxxxxxxxxxx1xxxx - fmops. */ - return 2418; + if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001xx1xxxxxxxxxxxxxxxx01xxx + bfmopa. */ + return 3332; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001xx1xxxxxxxxxxxxxxxx11xxx + bfmops. */ + return 3333; + } } } else @@ -3364,7 +3430,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxx10000x fmlall. */ - return 3511; + return 3529; } else { @@ -3372,7 +3438,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxx10000x fmlall. */ - return 3512; + return 3530; } } } @@ -3427,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx000xxxxx00x1x fmlall. */ - return 3509; + return 3527; } else { @@ -3435,7 +3501,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx000xxxxx00x1x fmlall. */ - return 3510; + return 3528; } } } @@ -3489,7 +3555,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx100xxx fdot. */ - return 3495; + return 3513; } else { @@ -3497,7 +3563,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx100xxx fdot. */ - return 3496; + return 3514; } } } @@ -3559,7 +3625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx010xxxx1000xx fmlal. */ - return 3503; + return 3521; } else { @@ -3567,7 +3633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx010xxxx1000xx fmlal. */ - return 3504; + return 3522; } } } @@ -3622,7 +3688,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx010xxxxx001xx fmlal. */ - return 3501; + return 3519; } else { @@ -3630,7 +3696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx010xxxxx001xx fmlal. */ - return 3502; + return 3520; } } } @@ -3699,7 +3765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx001xxxxx000xx fmlall. */ - return 3508; + return 3526; } } else @@ -3782,48 +3848,92 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx011xxxxx00xxx fmlal. */ - return 3500; + return 3518; } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 18) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xx0x00xx111xxxxx00xxx - fadd. */ - return 2530; + x10000010x10xxxx0xx111xxxxx00xxx + bfmla. */ + return 3322; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xx1x00xx111xxxxx00xxx - fadd. */ - return 3449; + if (((word >> 16) & 0x1) == 0) + { + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x10x0x00xx111xxxxx00xxx + fadd. */ + return 2530; + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011010x1x00xx111xxxxx00xxx + fadd. */ + return 3467; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011110x1x00xx111xxxxx00xxx + bfadd. */ + return 3316; + } + } + } + else + { + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x10x0x10xx111xxxxx00xxx + fadd. */ + return 2531; + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011010x1x10xx111xxxxx00xxx + fadd. */ + return 3468; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011110x1x10xx111xxxxx00xxx + bfadd. */ + return 3317; + } + } + } } } else { - if (((word >> 18) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xx0x10xx111xxxxx00xxx - fadd. */ - return 2531; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xx1x10xx111xxxxx00xxx - fadd. */ - return 3450; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xxxx0xx111xxxxx00xxx + bfmla. */ + return 3323; } } } @@ -3948,7 +4058,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx110xxx fdot. */ - return 3489; + return 3507; } else { @@ -3956,7 +4066,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx110xxx fdot. */ - return 3490; + return 3508; } } } @@ -4241,21 +4351,43 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 20) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx10xxxx0xx100xxxxx01xxx - fdot. */ - return 3493; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x010xxxx0xx100xxxxx01xxx + fdot. */ + return 3511; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x011xxxx0xx100xxxxx01xxx + fdot. */ + return 3512; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx11xxxx0xx100xxxxx01xxx - fdot. */ - return 3494; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x11xxxx00xx100xxxxx01xxx + bfmla. */ + return 3324; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x11xxxx10xx100xxxxx01xxx + bfmla. */ + return 3325; + } } } } @@ -4510,43 +4642,87 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 18) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xx0x00xx111xxxxx01xxx - fsub. */ - return 2598; + x10000010x10xxxx0xx111xxxxx01xxx + bfmls. */ + return 3328; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xx1x00xx111xxxxx01xxx - fsub. */ - return 3451; + if (((word >> 16) & 0x1) == 0) + { + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x10x0x00xx111xxxxx01xxx + fsub. */ + return 2598; + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011010x1x00xx111xxxxx01xxx + fsub. */ + return 3469; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011110x1x00xx111xxxxx01xxx + bfsub. */ + return 3318; + } + } + } + else + { + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x10x0x10xx111xxxxx01xxx + fsub. */ + return 2599; + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011010x1x10xx111xxxxx01xxx + fsub. */ + return 3470; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011110x1x10xx111xxxxx01xxx + bfsub. */ + return 3319; + } + } + } } } else { - if (((word >> 18) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xx0x10xx111xxxxx01xxx - fsub. */ - return 2599; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xx1x10xx111xxxxx01xxx - fsub. */ - return 3452; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xxxx0xx111xxxxx01xxx + bfmls. */ + return 3329; } } } @@ -4601,21 +4777,43 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 20) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx10xxxx0xx100xxxxx11xxx - fdot. */ - return 3487; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x010xxxx0xx100xxxxx11xxx + fdot. */ + return 3505; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x011xxxx0xx100xxxxx11xxx + fdot. */ + return 3506; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx11xxxx0xx100xxxxx11xxx - fdot. */ - return 3488; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x11xxxx00xx100xxxxx11xxx + bfmls. */ + return 3330; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x11xxxx10xx100xxxxx11xxx + bfmls. */ + return 3331; + } } } } @@ -5150,7 +5348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000xx1x0xxxx0 fscale. */ - return 3423; + return 3441; } } else @@ -5298,7 +5496,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x0100100111000xxxx0xxxxx fcvt. */ - return 3420; + return 3438; } else { @@ -5306,7 +5504,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x1100100111000xxxx0xxxxx bfcvt. */ - return 3415; + return 3433; } } else @@ -5315,7 +5513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx110100111000xxxx0xxxxx fcvt. */ - return 3421; + return 3439; } } else @@ -5366,7 +5564,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx100111000xxxx1xxxxx fcvtn. */ - return 3422; + return 3440; } } } @@ -5449,7 +5647,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010x110111000xxxxxxxxx0 f1cvt. */ - return 3416; + return 3434; } else { @@ -5457,7 +5655,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011010x110111000xxxxxxxxx0 f2cvt. */ - return 3417; + return 3435; } } else @@ -5468,7 +5666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110x110111000xxxxxxxxx0 bf1cvt. */ - return 3411; + return 3429; } else { @@ -5476,7 +5674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011110x110111000xxxxxxxxx0 bf2cvt. */ - return 3412; + return 3430; } } } @@ -5511,7 +5709,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001001xxx10111000xxxxxxxxx1 f1cvtl. */ - return 3418; + return 3436; } else { @@ -5519,7 +5717,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxx10111000xxxxxxxxx1 f2cvtl. */ - return 3419; + return 3437; } } else @@ -5530,7 +5728,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001011xxx10111000xxxxxxxxx1 bf1cvtl. */ - return 3413; + return 3431; } else { @@ -5538,7 +5736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxx10111000xxxxxxxxx1 bf2cvtl. */ - return 3414; + return 3432; } } } @@ -5807,7 +6005,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100xx100xxxx0 fscale. */ - return 3425; + return 3443; } } else @@ -5983,7 +6181,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010xx100xxxx0 fscale. */ - return 3424; + return 3442; } else { @@ -5991,7 +6189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110xx100xxxx0 fscale. */ - return 3426; + return 3444; } } } @@ -11159,7 +11357,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x11010000xxxxxxx1xxxxxxxxxxxxx addpt. */ - return 3427; + return 3445; } else { @@ -11167,7 +11365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010000xxxxxxx1xxxxxxxxxxxxx subpt. */ - return 3428; + return 3446; } } } @@ -12085,7 +12283,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx0xxxxxxxxxxxxxxx maddpt. */ - return 3429; + return 3447; } else { @@ -12093,7 +12291,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx1xxxxxxxxxxxxxxx msubpt. */ - return 3430; + return 3448; } } } @@ -12178,7 +12376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000100000xxxxxxxxxxxxx addpt. */ - return 3431; + return 3449; } else { @@ -12285,7 +12483,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000101000xxxxxxxxxxxxx subpt. */ - return 3433; + return 3451; } else { @@ -12490,7 +12688,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000010xxxxxxxxxx addpt. */ - return 3432; + return 3450; } else { @@ -12531,7 +12729,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000011xxxxxxxxxx subpt. */ - return 3434; + return 3452; } else { @@ -14189,7 +14387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110100xxxxxxxxxx mlapt. */ - return 3436; + return 3454; } } else @@ -14219,7 +14417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110110xxxxxxxxxx madpt. */ - return 3435; + return 3453; } } } @@ -14527,7 +14725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x100001xxxxxxxxxxxxx smaxqv. */ - return 3345; + return 3363; } else { @@ -14535,7 +14733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x100001xxxxxxxxxxxxx orqv. */ - return 3356; + return 3374; } } else @@ -14546,7 +14744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0x0101001xxxxxxxxxxxxx addqv. */ - return 3343; + return 3361; } else { @@ -14556,7 +14754,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx001101001xxxxxxxxxxxxx umaxqv. */ - return 3347; + return 3365; } else { @@ -14564,7 +14762,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx011101001xxxxxxxxxxxxx eorqv. */ - return 3349; + return 3367; } } } @@ -14601,7 +14799,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x110001xxxxxxxxxxxxx sminqv. */ - return 3346; + return 3364; } else { @@ -14609,7 +14807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x110001xxxxxxxxxxxxx andqv. */ - return 3344; + return 3362; } } } @@ -14629,7 +14827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0xx111001xxxxxxxxxxxxx uminqv. */ - return 3348; + return 3366; } } } @@ -15373,7 +15571,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 110001x0x00xxxxx101xxxxxxxxxxxxx ld1q. */ - return 3372; + return 3390; } else { @@ -16387,7 +16585,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x00xxxxxxxxxx zipq1. */ - return 3362; + return 3380; } else { @@ -16397,7 +16595,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111010xxxxxxxxxx uzpq1. */ - return 3360; + return 3378; } else { @@ -16405,7 +16603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111110xxxxxxxxxx tblq. */ - return 3357; + return 3375; } } } @@ -16417,7 +16615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x01xxxxxxxxxx zipq2. */ - return 3363; + return 3381; } else { @@ -16425,7 +16623,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x11xxxxxxxxxx uzpq2. */ - return 3361; + return 3379; } } } @@ -16905,7 +17103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0x00xxxxx000xxxxxxxxxxxxx st3q. */ - return 3381; + return 3399; } else { @@ -16915,7 +17113,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0010xxxxx000xxxxxxxxxxxxx st2q. */ - return 3380; + return 3398; } else { @@ -16923,7 +17121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0110xxxxx000xxxxxxxxxxxxx st4q. */ - return 3382; + return 3400; } } } @@ -17370,7 +17568,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0x0000101xxxxxxxxxxxxx faddqv. */ - return 3350; + return 3368; } else { @@ -17387,7 +17585,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx100101xxxxxxxxxxxxx fmaxnmqv. */ - return 3351; + return 3369; } } else @@ -17428,7 +17626,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx110101xxxxxxxxxxxxx fmaxqv. */ - return 3352; + return 3370; } } } @@ -17450,7 +17648,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx101101xxxxxxxxxxxxx fminnmqv. */ - return 3353; + return 3371; } } else @@ -17469,7 +17667,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx111101xxxxxxxxxxxxx fminqv. */ - return 3354; + return 3372; } } } @@ -17589,7 +17787,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx01xxxx111xxxxxxxxxxxxx ld2q. */ - return 3373; + return 3391; } } } @@ -17725,7 +17923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx1xxxxx100xxxxxxxxxxxxx ld2q. */ - return 3376; + return 3394; } } else @@ -17870,7 +18068,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x00x1xxxxx000xxxxxxxxxxxxx st2q. */ - return 3383; + return 3401; } } else @@ -17913,7 +18111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0101xxxxx000xxxxxxxxxxxxx st3q. */ - return 3384; + return 3402; } } else @@ -17954,7 +18152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0111xxxxx000xxxxxxxxxxxxx st4q. */ - return 3385; + return 3403; } } } @@ -17983,7 +18181,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0100x1xxxxxxxxxx fdot. */ - return 3472; + return 3490; } } else @@ -17992,7 +18190,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0101xxxxxxxxxxxx fmlalb. */ - return 3474; + return 3492; } } else @@ -18033,7 +18231,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 3484; + return 3502; } } else @@ -18066,7 +18264,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xx1xxxxxxxxxx fdot. */ - return 3470; + return 3488; } } else @@ -18137,7 +18335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx100010xxxxxxxxxx fmlallbb. */ - return 3475; + return 3493; } } else @@ -18146,7 +18344,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1000x1xxxxxxxxxx fdot. */ - return 3471; + return 3489; } } else @@ -18155,7 +18353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1100xxxxxxxxxxxx fmlallbb. */ - return 3476; + return 3494; } } else @@ -18164,7 +18362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1x01xxxxxxxxxxxx fmlallbt. */ - return 3477; + return 3495; } } else @@ -18191,7 +18389,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx100010xxxxxxxxxx fmlalb. */ - return 3473; + return 3491; } } else @@ -18209,7 +18407,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1100xxxxxxxxxxxx fmlalltb. */ - return 3480; + return 3498; } } else @@ -18218,7 +18416,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 3483; + return 3501; } } else @@ -18251,7 +18449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx100xx1xxxxxxxxxx fdot. */ - return 3469; + return 3487; } } else @@ -18260,7 +18458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx110xxxxxxxxxxxxx fmlallbt. */ - return 3478; + return 3496; } } else @@ -18292,7 +18490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx110xxxxxxxxxxxxx fmlalltt. */ - return 3482; + return 3500; } } else @@ -18591,7 +18789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0xx1xxxxx001xxxxxxxxxxxxx st1q. */ - return 3379; + return 3397; } } else @@ -18606,7 +18804,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1010xxxxxxxxxxxx fmlalltb. */ - return 3479; + return 3497; } else { @@ -18614,7 +18812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1011xxxxxxxxxxxx fmlalltt. */ - return 3481; + return 3499; } } else @@ -19332,7 +19530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001010x0001110xxxxxxxxxx pmov. */ - return 3364; + return 3382; } else { @@ -19340,7 +19538,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001011x0001110xxxxxxxxxx pmov. */ - return 3365; + return 3383; } } else @@ -19349,7 +19547,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x101101xx0001110xxxxxxxxxx pmov. */ - return 3366; + return 3384; } } else @@ -19358,7 +19556,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x101xx0001110xxxxxxxxxx pmov. */ - return 3367; + return 3385; } } else @@ -19404,7 +19602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x10x1001110xxxxxxxxxx pmov. */ - return 3368; + return 3386; } else { @@ -19412,7 +19610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x11x1001110xxxxxxxxxx pmov. */ - return 3369; + return 3387; } } else @@ -19421,7 +19619,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1011x1xx1001110xxxxxxxxxx pmov. */ - return 3370; + return 3388; } } else @@ -19430,7 +19628,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x1x1xx1001110xxxxxxxxxx pmov. */ - return 3371; + return 3389; } } } @@ -19449,7 +19647,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x01xxxxx001001xxxxxxxxxx dupq. */ - return 3355; + return 3373; } else { @@ -19457,7 +19655,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x11xxxxx001001xxxxxxxxxx extq. */ - return 3359; + return 3377; } } else @@ -19466,7 +19664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1xx1xxxxx001101xxxxxxxxxx tbxq. */ - return 3358; + return 3376; } } else @@ -21069,7 +21267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101100xxxxxxxxxx luti2. */ - return 3441; + return 3459; } } else @@ -21078,7 +21276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x10xxxxxxxxxx luti2. */ - return 3442; + return 3460; } } else @@ -21091,7 +21289,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101001xxxxxxxxxx luti4. */ - return 3443; + return 3461; } else { @@ -21099,7 +21297,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101101xxxxxxxxxx luti4. */ - return 3444; + return 3462; } } else @@ -21108,7 +21306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x11xxxxxxxxxx luti4. */ - return 3445; + return 3463; } } } @@ -22059,7 +22257,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x00xxxxxxxxxx f1cvt. */ - return 3403; + return 3421; } else { @@ -22067,7 +22265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x10xxxxxxxxxx bf1cvt. */ - return 3399; + return 3417; } } else @@ -22078,7 +22276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x01xxxxxxxxxx f2cvt. */ - return 3404; + return 3422; } else { @@ -22086,7 +22284,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x11xxxxxxxxxx bf2cvt. */ - return 3400; + return 3418; } } } @@ -22131,7 +22329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x00xxxxxxxxxx fcvtn. */ - return 3408; + return 3426; } else { @@ -22139,7 +22337,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x10xxxxxxxxxx bfcvtn. */ - return 3407; + return 3425; } } else @@ -22150,7 +22348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x01xxxxxxxxxx fcvtnb. */ - return 3409; + return 3427; } else { @@ -22158,7 +22356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x11xxxxxxxxxx fcvtnt. */ - return 3410; + return 3428; } } } @@ -22219,7 +22417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x00xxxxxxxxxx f1cvtlt. */ - return 3405; + return 3423; } else { @@ -22227,7 +22425,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x10xxxxxxxxxx bf1cvtlt. */ - return 3401; + return 3419; } } else @@ -22238,7 +22436,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x01xxxxxxxxxx f2cvtlt. */ - return 3406; + return 3424; } else { @@ -22246,7 +22444,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x11xxxxxxxxxx bf2cvtlt. */ - return 3402; + return 3420; } } } @@ -23572,7 +23770,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x01xxxx111xxxxxxxxxxxxx ld3q. */ - return 3374; + return 3392; } else { @@ -23580,7 +23778,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x01xxxx111xxxxxxxxxxxxx ld4q. */ - return 3375; + return 3393; } } } @@ -24753,7 +24951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx100xxxxxxxxxxxxx ld3q. */ - return 3377; + return 3395; } else { @@ -24761,7 +24959,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx100xxxxxxxxxxxxx ld4q. */ - return 3378; + return 3396; } } else @@ -26826,7 +27024,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110100xxxxxxxx100xxxxxxxxxx luti2. */ - return 3437; + return 3455; } } } @@ -26840,7 +27038,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx000xxxxxxxxxx luti4. */ - return 3439; + return 3457; } else { @@ -26848,7 +27046,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx100xxxxxxxxxx luti4. */ - return 3440; + return 3458; } } else @@ -26857,7 +27055,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110110xxxxxxxxx00xxxxxxxxxx luti2. */ - return 3438; + return 3456; } } } @@ -26973,7 +27171,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx10001xxxxxxxxxx fmlallbb. */ - return 3461; + return 3479; } else { @@ -26981,7 +27179,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx10001xxxxxxxxxx fmlalltb. */ - return 3463; + return 3481; } } else @@ -26992,7 +27190,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x10xxxxxx10001xxxxxxxxxx fmlallbt. */ - return 3462; + return 3480; } else { @@ -27000,7 +27198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x10xxxxxx10001xxxxxxxxxx fmlalltt. */ - return 3464; + return 3482; } } } @@ -27088,7 +27286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3394; + return 3412; } else { @@ -27096,7 +27294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx11101xxxxxxxxxx fcvtn2. */ - return 3395; + return 3413; } } else @@ -27105,7 +27303,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x10xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3396; + return 3414; } } } @@ -27248,7 +27446,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x00xxxxxx11111xxxxxxxxxx fdot. */ - return 3453; + return 3471; } else { @@ -27258,7 +27456,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxx11111xxxxxxxxxx fdot. */ - return 3455; + return 3473; } else { @@ -27268,7 +27466,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110110xxxxxx11111xxxxxxxxxx fmlalb. */ - return 3457; + return 3475; } else { @@ -27276,7 +27474,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110110xxxxxx11111xxxxxxxxxx fmlalt. */ - return 3458; + return 3476; } } } @@ -27550,7 +27748,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110110xxxxx0x1111xxxxxxxxxx fscale. */ - return 3397; + return 3415; } } } @@ -28942,7 +29140,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110001xxxx1011110xxxxxxxxxx f1cvtl. */ - return 3390; + return 3408; } else { @@ -28950,7 +29148,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110001xxxx1011110xxxxxxxxxx f1cvtl2. */ - return 3391; + return 3409; } } else @@ -28961,7 +29159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110101xxxx1011110xxxxxxxxxx bf1cvtl. */ - return 3386; + return 3404; } else { @@ -28969,7 +29167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110101xxxx1011110xxxxxxxxxx bf1cvtl2. */ - return 3387; + return 3405; } } } @@ -28983,7 +29181,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110011xxxx1011110xxxxxxxxxx f2cvtl. */ - return 3392; + return 3410; } else { @@ -28991,7 +29189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110011xxxx1011110xxxxxxxxxx f2cvtl2. */ - return 3393; + return 3411; } } else @@ -29002,7 +29200,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110111xxxx1011110xxxxxxxxxx bf2cvtl. */ - return 3388; + return 3406; } else { @@ -29010,7 +29208,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110111xxxx1011110xxxxxxxxxx bf2cvtl2. */ - return 3389; + return 3407; } } } @@ -31009,7 +31207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011101x1xxxxx111111xxxxxxxxxx fscale. */ - return 3398; + return 3416; } } } @@ -32725,7 +32923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3454; + return 3472; } else { @@ -32755,7 +32953,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3456; + return 3474; } else { @@ -32765,7 +32963,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx0000x0xxxxxxxxxx fmlalb. */ - return 3459; + return 3477; } else { @@ -32773,7 +32971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx0000x0xxxxxxxxxx fmlalt. */ - return 3460; + return 3478; } } } @@ -33315,7 +33513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x010111100xxxxxx1000x0xxxxxxxxxx fmlallbb. */ - return 3465; + return 3483; } else { @@ -33323,7 +33521,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x110111100xxxxxx1000x0xxxxxxxxxx fmlalltb. */ - return 3467; + return 3485; } } else @@ -33354,7 +33552,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111x1xxxxxx1000x0xxxxxxxxxx fmlallbt. */ - return 3466; + return 3484; } else { @@ -33362,7 +33560,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111x1xxxxxx1000x0xxxxxxxxxx fmlalltt. */ - return 3468; + return 3486; } } }