From patchwork Mon Jul 15 05:39:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hu, Lin1" X-Patchwork-Id: 93919 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3E7A9384DB45 for ; Mon, 15 Jul 2024 05:39:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by sourceware.org (Postfix) with ESMTPS id 84F2C3858289 for ; Mon, 15 Jul 2024 05:39:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 84F2C3858289 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 84F2C3858289 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721021959; cv=none; b=FNi4FZHyHcDly4qnbnULJsVafU8Tecyl/Xkwmot60iwY90j1QHFSIiAx372VznIQXw7hkmAV+qvF/r1sh4NmIX19HtA5phtDgf0DCO7PKI81uyndVPOGt/F4DxIvtjrsrZDgfoK27LWsAeaG/hx0X5KmGZlpXoQxEIA5EKgvjMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721021959; c=relaxed/simple; bh=k+XgBk8AXY1KGcZ2wJ02PUUN1RVX59PXiP5xOp58/lI=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=n/xUYOVOPrvrmzT9RAS+AdQ4SvBiV7cACoC0/mLN67dM82pGhWfmGXFrbjzwOak/fOzR8eCz5ae72H5ZmAvuT/x/gxA+sZNd0GYCN9dQfvxo6ukapdxkkH80Qq6LkJZeMrl4BC0Z22dGjrTznargAh0M0XMuQPqHuBpfV4avhGk= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721021958; x=1752557958; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=k+XgBk8AXY1KGcZ2wJ02PUUN1RVX59PXiP5xOp58/lI=; b=je+l7aRZLPRTmM8YZdPOv54QbdiWS/Qjckk3fCEAPC/NKHO2cW5sl1CU 0L986F0/YZwn+w0qx50Wk3Gf1a6B+EyViMGHQhA+0aelvT3nR+VJMioAc +E2mHwNx52DXuBLirbDbUQ+qM1vgZw7YaODvwc2WXWAV2Jyp0FlV/EWtG iuzwEL4YTTjjYJe2Nsgf7ZyUtOxc8nyAFXQNz/7rYhhC7Xty6Ql++ePQG c89RIOmke1zZDQarEzJRCJvL4U0VoE44vVGNkYPl3RR57VQuY2O85O5Qy QmWfMp2nSF84yMUNQ5bH7GvqG/G9pYjH39IsicNf6OSq1zbKy4GrXOVUa w==; X-CSE-ConnectionGUID: sS3Q5zhUSKeOj0e6bg1K+Q== X-CSE-MsgGUID: 9IPCYN3yQF68hae/hpMv/Q== X-IronPort-AV: E=McAfee;i="6700,10204,11133"; a="29777827" X-IronPort-AV: E=Sophos;i="6.09,209,1716274800"; d="scan'208";a="29777827" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2024 22:39:16 -0700 X-CSE-ConnectionGUID: yACx+UEmSCiCnxR5rI9jhg== X-CSE-MsgGUID: 4+WxBj/sQpCFoRGI3O1aOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,209,1716274800"; d="scan'208";a="53879613" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 14 Jul 2024 22:39:13 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 2CE881005676; Mon, 15 Jul 2024 13:39:12 +0800 (CST) From: "Hu, Lin1" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: extend trunc{128}2{16,32,64}'s scope. Date: Mon, 15 Jul 2024 13:39:12 +0800 Message-Id: <20240715053912.2183939-1-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Hi, all Based on actual usage, trunc{128}2{16,32,64} use some instructions from sse/sse3, so extend their scope to extend the scope of optimization. Bootstraped and regtest on x86-64-linux-gnu, OK for trunk? BRs, Lin gcc/ChangeLog: PR target/107432 * config/i386/sse.md (PMOV_SRC_MODE_3_AVX2): Add TARGET_AVX2 for V4DI and V8SI. (PMOV_SRC_MODE_4): Add TARGET_AVX2 for V4DI. (trunc2): Change constraint from TARGET_AVX2 to TARGET_SSSE3. (trunc2): Ditto. (truncv2div2si2): Change constraint from TARGET_AVX2 to TARGET_SSE. gcc/testsuite/ChangeLog: PR target/107432 * gcc.target/i386/pr107432-10.c: New test. --- gcc/config/i386/sse.md | 11 +++--- gcc/testsuite/gcc.target/i386/pr107432-10.c | 41 +++++++++++++++++++++ 2 files changed, 47 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr107432-10.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b3b4697924b..72f3c7df297 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15000,7 +15000,8 @@ (define_expand "_2_mask_store" "TARGET_AVX512VL") (define_mode_iterator PMOV_SRC_MODE_3 [V4DI V2DI V8SI V4SI (V8HI "TARGET_AVX512BW")]) -(define_mode_iterator PMOV_SRC_MODE_3_AVX2 [V4DI V2DI V8SI V4SI V8HI]) +(define_mode_iterator PMOV_SRC_MODE_3_AVX2 + [(V4DI "TARGET_AVX2") V2DI (V8SI "TARGET_AVX2") V4SI V8HI]) (define_mode_attr pmov_dst_3_lower [(V4DI "v4qi") (V2DI "v2qi") (V8SI "v8qi") (V4SI "v4qi") (V8HI "v8qi")]) (define_mode_attr pmov_dst_3 @@ -15014,7 +15015,7 @@ (define_expand "trunc2" [(set (match_operand: 0 "register_operand") (truncate: (match_operand:PMOV_SRC_MODE_3_AVX2 1 "register_operand")))] - "TARGET_AVX2" + "TARGET_SSSE3" { if (TARGET_AVX512VL && (mode != V8HImode || TARGET_AVX512BW)) @@ -15390,7 +15391,7 @@ (define_insn_and_split "avx512vl_v8qi2_mask_store_2" (match_dup 2)))] "operands[0] = adjust_address_nv (operands[0], V8QImode, 0);") -(define_mode_iterator PMOV_SRC_MODE_4 [V4DI V2DI V4SI]) +(define_mode_iterator PMOV_SRC_MODE_4 [(V4DI "TARGET_AVX2") V2DI V4SI]) (define_mode_attr pmov_dst_4 [(V4DI "V4HI") (V2DI "V2HI") (V4SI "V4HI")]) (define_mode_attr pmov_dst_4_lower @@ -15404,7 +15405,7 @@ (define_expand "trunc2" [(set (match_operand: 0 "register_operand") (truncate: (match_operand:PMOV_SRC_MODE_4 1 "register_operand")))] - "TARGET_AVX2" + "TARGET_SSSE3" { if (TARGET_AVX512VL) { @@ -15659,7 +15660,7 @@ (define_expand "truncv2div2si2" [(set (match_operand:V2SI 0 "register_operand") (truncate:V2SI (match_operand:V2DI 1 "register_operand")))] - "TARGET_AVX2" + "TARGET_SSE" { if (TARGET_AVX512VL) { diff --git a/gcc/testsuite/gcc.target/i386/pr107432-10.c b/gcc/testsuite/gcc.target/i386/pr107432-10.c new file mode 100644 index 00000000000..57edf7cfc78 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107432-10.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64-v2 -O2" } */ +/* { dg-final { scan-assembler-times "shufps" 1 } } */ +/* { dg-final { scan-assembler-times "pshufb" 5 } } */ + +#include + +typedef short __v2hi __attribute__ ((__vector_size__ (4))); +typedef char __v2qi __attribute__ ((__vector_size__ (2))); +typedef char __v4qi __attribute__ ((__vector_size__ (4))); +typedef char __v8qi __attribute__ ((__vector_size__ (8))); + +__v2si mm_cvtepi64_epi32_builtin_convertvector(__v2di a) +{ + return __builtin_convertvector((__v2di)a, __v2si); +} + +__v2hi mm_cvtepi64_epi16_builtin_convertvector(__m128i a) +{ + return __builtin_convertvector((__v2di)a, __v2hi); +} + +__v4hi mm_cvtepi32_epi16_builtin_convertvector(__m128i a) +{ + return __builtin_convertvector((__v4si)a, __v4hi); +} + +__v2qi mm_cvtepi64_epi8_builtin_convertvector(__m128i a) +{ + return __builtin_convertvector((__v2di)a, __v2qi); +} + +__v4qi mm_cvtepi32_epi8_builtin_convertvector(__m128i a) +{ + return __builtin_convertvector((__v4si)a, __v4qi); +} + +__v8qi mm_cvtepi16_epi8_builtin_convertvector(__m128i a) +{ + return __builtin_convertvector((__v8hi)a, __v8qi); +}