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-struct aarch64_long_option_table -{ - const char *option; /* Substring to match. */ - const char *help; /* Help information. */ - int (*func) (const char *subopt); /* Function to decode sub-option. */ - char *deprecated; /* If non-null, print this message. */ -}; - /* Transitive closure of features depending on set. */ static aarch64_feature_set aarch64_feature_disable_set (aarch64_feature_set set) @@ -10840,6 +10832,14 @@ aarch64_parse_abi (const char *str) return 0; } +struct aarch64_long_option_table +{ + const char *option; /* Substring to match. */ + const char *help; /* Help information. */ + int (*func) (const char *subopt); /* Function to decode sub-option. */ + char *deprecated; /* If non-null, print this message. */ +}; + static struct aarch64_long_option_table aarch64_long_opts[] = { {"mabi=", N_("\t specify for ABI "), aarch64_parse_abi, NULL}, From patchwork Fri Jun 21 18:31:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 92693 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D364E3831380 for ; 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This patch add a postprocessing step to the feature parsing code to set the value of the virtual bits. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index d1ed3c930dc8902c4a4e0f9f86e837d50d971a3c..473097d701f249f4f27df017f0481b858555b5f3 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10600,6 +10600,32 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; +/* If all features in the TEST feature set are present, then every virtual + feature in the ENABLES feature set should also be enabled. */ +struct aarch64_virtual_dependency_table +{ + const aarch64_feature_set test; + const aarch64_feature_set enables; +}; + +static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = { + {AARCH64_NO_FEATURES, AARCH64_NO_FEATURES} +}; + +static aarch64_feature_set +aarch64_update_virtual_dependencies (aarch64_feature_set set) +{ + unsigned int i; + for (i = 0; i < ARRAY_SIZE (aarch64_dependencies); i++) + AARCH64_CLEAR_FEATURES (set, set, aarch64_dependencies[i].enables); + + for (i = 0; i < ARRAY_SIZE (aarch64_dependencies); i++) + if (AARCH64_CPU_HAS_ALL_FEATURES (set, aarch64_dependencies[i].test)) + AARCH64_MERGE_FEATURE_SETS (set, set, aarch64_dependencies[i].enables); + + return set; +} + /* Transitive closure of features depending on set. */ static aarch64_feature_set aarch64_feature_disable_set (aarch64_feature_set set) @@ -10638,16 +10664,23 @@ static int aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p, bool ext_only) { + /* Copy the feature set, so that we can modify it. */ + aarch64_feature_set *ext_set = XNEW (aarch64_feature_set); + *ext_set = **opt_p; + *opt_p = ext_set; + + if (str == NULL) + { + /* No extensions, so just set the virtual feature bits and return. */ + *ext_set = aarch64_update_virtual_dependencies (*ext_set); + return 1; + } + /* We insist on extensions being added before being removed. We achieve this by using the ADDING_VALUE variable to indicate whether we are adding an extension (1) or removing it (0) and only allowing it to change in the order -1 -> 1 -> 0. */ int adding_value = -1; - aarch64_feature_set *ext_set = XNEW (aarch64_feature_set); - - /* Copy the feature set, so that we can modify it. */ - *ext_set = **opt_p; - *opt_p = ext_set; while (str != NULL && *str != 0) { @@ -10727,6 +10760,7 @@ aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p, str = ext; }; + *ext_set = aarch64_update_virtual_dependencies (*ext_set); return 1; } @@ -10752,10 +10786,7 @@ aarch64_parse_cpu (const char *str) if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0) { mcpu_cpu_opt = &opt->value; - if (ext != NULL) - return aarch64_parse_features (ext, &mcpu_cpu_opt, false); - - return 1; + return aarch64_parse_features (ext, &mcpu_cpu_opt, false); } as_bad (_("unknown cpu `%s'"), str); @@ -10784,10 +10815,7 @@ aarch64_parse_arch (const char *str) if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0) { march_cpu_opt = &opt->value; - if (ext != NULL) - return aarch64_parse_features (ext, &march_cpu_opt, false); - - return 1; + return aarch64_parse_features (ext, &march_cpu_opt, false); } as_bad (_("unknown architecture `%s'\n"), str); @@ -10973,9 +11001,8 @@ s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED) && strncmp (name, opt->name, optlen) == 0) { mcpu_cpu_opt = &opt->value; - if (ext != NULL) - if (!aarch64_parse_features (ext, &mcpu_cpu_opt, false)) - return; + if (!aarch64_parse_features (ext, &mcpu_cpu_opt, false)) + return; cpu_variant = *mcpu_cpu_opt; @@ -11018,9 +11045,8 @@ s_aarch64_arch (int ignored ATTRIBUTE_UNUSED) && strncmp (name, opt->name, optlen) == 0) { mcpu_cpu_opt = &opt->value; - if (ext != NULL) - if (!aarch64_parse_features (ext, &mcpu_cpu_opt, false)) - return; + if (!aarch64_parse_features (ext, &mcpu_cpu_opt, false)) + return; cpu_variant = *mcpu_cpu_opt; From patchwork Fri Jun 21 18:31:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 92695 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5DE65382FADE for ; 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+ /* Special case S_4B. */ if (vectype->type == NT_b && vectype->width == 4) return AARCH64_OPND_QLF_S_4B; @@ -1010,7 +1014,7 @@ aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier) succeeds; otherwise return FALSE. Accept only one occurrence of: - 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d + 2b 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d b h s d q */ static bool parse_vector_type_for_operand (aarch64_reg_type reg_type, @@ -1074,6 +1078,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type, if (width != 0 && width * element_size != 64 && width * element_size != 128 && !(width == 2 && element_size == 16) + && !(width == 2 && element_size == 8) && !(width == 4 && element_size == 8)) { first_error_fmt (_ @@ -6272,6 +6277,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: operand->reglane.regno = default_value; break; @@ -6793,6 +6799,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: @@ -6818,6 +6825,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: reg_type = REG_TYPE_V; vector_reg_index: @@ -10597,6 +10605,15 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"fp8", AARCH64_FEATURE (FP8), AARCH64_FEATURE (SIMD)}, {"lut", AARCH64_FEATURE (LUT), AARCH64_FEATURE (SIMD)}, {"brbe", AARCH64_FEATURE (BRBE), AARCH64_NO_FEATURES}, + {"fp8fma", AARCH64_FEATURE (FP8FMA), AARCH64_FEATURE (FP8)}, + {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8FMA)}, + {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8DOT4)}, + {"ssve-fp8fma", AARCH64_FEATURE (SSVE_FP8FMA), + AARCH64_FEATURES (2, FP8, SME2)}, + {"ssve-fp8dot4", AARCH64_FEATURE (SSVE_FP8DOT4), + AARCH64_FEATURE (SSVE_FP8FMA)}, + {"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2), + AARCH64_FEATURE (SSVE_FP8DOT4)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; @@ -10609,7 +10626,12 @@ struct aarch64_virtual_dependency_table }; static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = { - {AARCH64_NO_FEATURES, AARCH64_NO_FEATURES} + {AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)}, + {AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)}, + {AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)}, + {AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)}, + {AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)}, + {AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)}, }; static aarch64_feature_set diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index b29da1f0e8f5ae9be9589ce098674a1c6fb0164f..530d712f55a7e0fc985b7ab04d2dadc18298d189 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -197,6 +197,12 @@ automatically cause those extensions to be disabled. @tab Enable floating-point extensions. @item @code{fp8} @tab @tab Enable the Floating Point 8 (FP8) extension. +@item @code{fp8dot2} @tab @code{fp8dot4} + @tab Enable the FP8 2-way dot product instructions. +@item @code{fp8dot4} @tab @code{fp8fma} + @tab Enable the FP8 4-way dot product instructions. +@item @code{fp8fma} @tab @code{fp8} + @tab Enable the FP8 FMA instructions. @item @code{fp16fml} @tab @code{fp16} @tab Enable Armv8.2 16-bit floating-point multiplication variant support. @item @code{fp16} @tab @code{fp} @@ -275,6 +281,12 @@ automatically cause those extensions to be disabled. @tab Enable SME2.1. @item @code{ssbs} @tab @tab Enable Speculative Store Bypassing Safe state read and write. +@item @code{ssve-fp8dot2} @tab @code{ssve-fp8dot4} + @tab Enable the Streaming SVE FP8 2-way dot product instructions. These can also be enabled using @code{+fp8dot2+sme2}. +@item @code{ssve-fp8dot4} @tab @code{ssve-fp8fma} + @tab Enable the Streaming SVE FP8 4-way dot product instructions. These can also be enabled using @code{+fp8dot4+sme2}. +@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8} + @tab Enable the Streaming SVE FP8 FMA instructions. These can also be enabled using @code{+fp8fma+sme2}. @item @code{sve} @tab @code{fcma} @tab Enable the Scalable Vector Extension. @item @code{sve2} @tab @code{sve} diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..1dac59a5d820670e94f65d7dba510b011609d631 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+fp8dot2 +#error_output: fp8-mul-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..155c24b035ccbf664cb2f26bce9f267d4d197931 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l @@ -0,0 +1,24 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.4h,v0\.8b,v16\.2b\[0\]' +[^:]*:2: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.4h,v0\.8b,v0\.2b\[8\]' +[^:]*:3: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.8h,v0\.16b,v16\.2b\[0\]' +[^:]*:4: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.8h,v0\.16b,v0\.2b\[8\]' +[^:]*:6: Error: operand mismatch -- `fmlalb v0\.4h,v0\.8b,v0\.8b' +[^:]*:6: Info: did you mean this\? +[^:]*:6: Info: \tfmlalb v0\.8h, v0\.16b, v0\.16b +[^:]*:8: Error: register number out of range 0 to 7 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v8\.b\[0\]' +[^:]*:9: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v0\.b\[16\]' +[^:]*:10: Error: register number out of range 0 to 7 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v8\.b\[0\]' +[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v0\.b\[16\]' +[^:]*:13: Error: operand mismatch -- `fmlallbb v0\.2s,v0\.8b,v0\.8b' +[^:]*:13: Info: did you mean this\? +[^:]*:13: Info: \tfmlallbb v0\.4s, v0\.16b, v0\.16b +[^:]*:15: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:16: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:17: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:18: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:19: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:21: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:22: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v0\.b\[16\]' + diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..1b75cb68a1dde911285d4d978e6180a61660c5a7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s @@ -0,0 +1,24 @@ +fdot v0.4h, v0.8b, v16.2b[0] +fdot v0.4h, v0.8b, v0.2b[8] +fdot v0.8h, v0.16b, v16.2b[0] +fdot v0.8h, v0.16b, v0.2b[8] + +fmlalb v0.4h, v0.8b, v0.8b + +fmlalb v0.8h, v0.16b, v8.b[0] +fmlalb v0.8h, v0.16b, v0.b[16] +fmlalt v0.8h, v0.16b, v8.b[0] +fmlalt v0.8h, v0.16b, v0.b[16] + +fmlallbb v0.2s, v0.8b, v0.8b + +fmlallbb v0.4s, v0.16b, v8.b[0] +fmlallbb v0.4s, v0.16b, v0.b[16] +fmlallbt v0.4s, v0.16b, v8.b[0] +fmlallbt v0.4s, v0.16b, v0.b[16] +fmlalltb v0.4s, v0.16b, v8.b[0] +fmlalltb v0.4s, v0.16b, v0.b[16] +fmlalltt v0.4s, v0.16b, v8.b[0] +fmlalltt v0.4s, v0.16b, v0.b[16] + + diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.d b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d new file mode 100644 index 0000000000000000000000000000000000000000..7d740b711d2155b7d11638f24cc106da6b3ee109 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d @@ -0,0 +1,25 @@ +#as: -march=armv8-a+fp8dot2 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0e40fc00 fdot v0\.4h, v0\.8b, v0\.8b + *[0-9a-f]+: 0e5dff77 fdot v23\.4h, v27\.8b, v29\.8b + *[0-9a-f]+: 0e53feb9 fdot v25\.4h, v21\.8b, v19\.8b + *[0-9a-f]+: 4e40fc00 fdot v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 4e5dff77 fdot v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 4e53feb9 fdot v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 0f400000 fdot v0\.4h, v0\.8b, v0\.2b\[0\] + *[0-9a-f]+: 0f500000 fdot v0\.4h, v0\.8b, v0\.2b\[1\] + *[0-9a-f]+: 0f6e0377 fdot v23\.4h, v27\.8b, v14\.2b\[2\] + *[0-9a-f]+: 0f4d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[4\] + *[0-9a-f]+: 0f7d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[7\] + *[0-9a-f]+: 4f400000 fdot v0\.8h, v0\.16b, v0\.2b\[0\] + *[0-9a-f]+: 4f500000 fdot v0\.8h, v0\.16b, v0\.2b\[1\] + *[0-9a-f]+: 4f6e0377 fdot v23\.8h, v27\.16b, v14\.2b\[2\] + *[0-9a-f]+: 4f4d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[4\] + *[0-9a-f]+: 4f7d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[7\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.s b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s new file mode 100644 index 0000000000000000000000000000000000000000..3fff78afbc96bee395523d6e50b66021d207b3f4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s @@ -0,0 +1,19 @@ +fdot v0.4h, v0.8b, v0.8b +fdot v23.4h, v27.8b, v29.8b +fdot v25.4h, v21.8b, v19.8b + +fdot v0.8h, v0.16b, v0.16b +fdot v23.8h, v27.16b, v29.16b +fdot v25.8h, v21.16b, v19.16b + +fdot v0.4h, v0.8b, v0.2b[0] +fdot v0.4h, v0.8b, v0.2b[1] +fdot v23.4h, v27.8b, v14.2b[2] +fdot v25.4h, v21.8b, v13.2b[4] +fdot v25.4h, v21.8b, v13.2b[7] + +fdot v0.8h, v0.16b, v0.2b[0] +fdot v0.8h, v0.16b, v0.2b[1] +fdot v23.8h, v27.16b, v14.2b[2] +fdot v25.8h, v21.16b, v13.2b[4] +fdot v25.8h, v21.16b, v13.2b[7] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.d b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d new file mode 100644 index 0000000000000000000000000000000000000000..bf4632c30dddf70b58ca56b8de940c9bd73c8b88 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d @@ -0,0 +1,21 @@ +#as: -march=armv8-a+fp8dot4 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0e00fc00 fdot v0\.2s, v0\.8b, v0\.8b + *[0-9a-f]+: 0e1dff77 fdot v23\.2s, v27\.8b, v29\.8b + *[0-9a-f]+: 0e13feb9 fdot v25\.2s, v21\.8b, v19\.8b + *[0-9a-f]+: 4e00fc00 fdot v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e1dff77 fdot v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e13feb9 fdot v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 0f000000 fdot v0\.2s, v0\.8b, v0\.4b\[0\] + *[0-9a-f]+: 0f3d0377 fdot v23\.2s, v27\.8b, v29\.4b\[1\] + *[0-9a-f]+: 0f330ab9 fdot v25\.2s, v21\.8b, v19\.4b\[3\] + *[0-9a-f]+: 4f000000 fdot v0\.4s, v0\.16b, v0\.4b\[0\] + *[0-9a-f]+: 4f3d0377 fdot v23\.4s, v27\.16b, v29\.4b\[1\] + *[0-9a-f]+: 4f330ab9 fdot v25\.4s, v21\.16b, v19\.4b\[3\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.s b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s new file mode 100644 index 0000000000000000000000000000000000000000..cfd7283aed6708b5dc5186cb2951969338499ac8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s @@ -0,0 +1,15 @@ +fdot v0.2s, v0.8b, v0.8b +fdot v23.2s, v27.8b, v29.8b +fdot v25.2s, v21.8b, v19.8b + +fdot v0.4s, v0.16b, v0.16b +fdot v23.4s, v27.16b, v29.16b +fdot v25.4s, v21.16b, v19.16b + +fdot v0.2s, v0.8b, v0.4b[0] +fdot v23.2s, v27.8b, v29.4b[1] +fdot v25.2s, v21.8b, v19.4b[3] + +fdot v0.4s, v0.16b, v0.4b[0] +fdot v23.4s, v27.16b, v29.4b[1] +fdot v25.4s, v21.16b, v19.4b[3] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.d b/gas/testsuite/gas/aarch64/fp8-simd-fma.d new file mode 100644 index 0000000000000000000000000000000000000000..c9c8be6ef1360fcefba802a295123662bc375db2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.d @@ -0,0 +1,51 @@ +#as: -march=armv8-a+fp8fma +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0ec0fc00 fmlalb v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 0eddff77 fmlalb v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 0ed3feb9 fmlalb v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 4ec0fc00 fmlalt v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 4eddff77 fmlalt v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 4ed3feb9 fmlalt v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 0fc00000 fmlalb v0\.8h, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 0fdd0377 fmlalb v23\.8h, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 0fe702b9 fmlalb v25\.8h, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 0fc70ab9 fmlalb v25\.8h, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 4fc00000 fmlalt v0\.8h, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 4fdd0377 fmlalt v23\.8h, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 4fe702b9 fmlalt v25\.8h, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 4fc70ab9 fmlalt v25\.8h, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 0e00c400 fmlallbb v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 0e1dc777 fmlallbb v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 0e13c6b9 fmlallbb v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 0e40c400 fmlallbt v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 0e5dc777 fmlallbt v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 0e53c6b9 fmlallbt v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 4e00c400 fmlalltb v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e1dc777 fmlalltb v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e13c6b9 fmlalltb v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 4e40c400 fmlalltt v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e5dc777 fmlalltt v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e53c6b9 fmlalltt v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 2f008000 fmlallbb v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 2f1d8377 fmlallbb v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 2f2782b9 fmlallbb v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 2f078ab9 fmlallbb v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 2f408000 fmlallbt v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 2f5d8377 fmlallbt v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 2f6782b9 fmlallbt v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 2f478ab9 fmlallbt v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 6f008000 fmlalltb v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 6f1d8377 fmlalltb v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 6f2782b9 fmlalltb v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 6f078ab9 fmlalltb v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 6f408000 fmlalltt v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 6f5d8377 fmlalltt v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 6f6782b9 fmlalltt v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 6f478ab9 fmlalltt v25\.4s, v21\.16b, v7\.b\[8\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.s b/gas/testsuite/gas/aarch64/fp8-simd-fma.s new file mode 100644 index 0000000000000000000000000000000000000000..be7951465a0e40d1fbe373bfb59fffc3fb0fa74c --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.s @@ -0,0 +1,53 @@ +fmlalb v0.8h, v0.16b, v0.16b +fmlalb v23.8h, v27.16b, v29.16b +fmlalb v25.8h, v21.16b, v19.16b + +fmlalt v0.8h, v0.16b, v0.16b +fmlalt v23.8h, v27.16b, v29.16b +fmlalt v25.8h, v21.16b, v19.16b + +fmlalb v0.8h, v0.16b, v0.b[0] +fmlalb v23.8h, v27.16b, v5.b[3] +fmlalb v25.8h, v21.16b, v7.b[4] +fmlalb v25.8h, v21.16b, v7.b[8] + +fmlalt v0.8h, v0.16b, v0.b[0] +fmlalt v23.8h, v27.16b, v5.b[3] +fmlalt v25.8h, v21.16b, v7.b[4] +fmlalt v25.8h, v21.16b, v7.b[8] + +fmlallbb v0.4s, v0.16b, v0.16b +fmlallbb v23.4s, v27.16b, v29.16b +fmlallbb v25.4s, v21.16b, v19.16b + +fmlallbt v0.4s, v0.16b, v0.16b +fmlallbt v23.4s, v27.16b, v29.16b +fmlallbt v25.4s, v21.16b, v19.16b + +fmlalltb v0.4s, v0.16b, v0.16b +fmlalltb v23.4s, v27.16b, v29.16b +fmlalltb v25.4s, v21.16b, v19.16b + +fmlalltt v0.4s, v0.16b, v0.16b +fmlalltt v23.4s, v27.16b, v29.16b +fmlalltt v25.4s, v21.16b, v19.16b + +fmlallbb v0.4s, v0.16b, v0.b[0] +fmlallbb v23.4s, v27.16b, v5.b[3] +fmlallbb v25.4s, v21.16b, v7.b[4] +fmlallbb v25.4s, v21.16b, v7.b[8] + +fmlallbt v0.4s, v0.16b, v0.b[0] +fmlallbt v23.4s, v27.16b, v5.b[3] +fmlallbt v25.4s, v21.16b, v7.b[4] +fmlallbt v25.4s, v21.16b, v7.b[8] + +fmlalltb v0.4s, v0.16b, v0.b[0] +fmlalltb v23.4s, v27.16b, v5.b[3] +fmlalltb v25.4s, v21.16b, v7.b[4] +fmlalltb v25.4s, v21.16b, v7.b[8] + +fmlalltt v0.4s, v0.16b, v0.b[0] +fmlalltt v23.4s, v27.16b, v5.b[3] +fmlalltt v25.4s, v21.16b, v7.b[4] +fmlalltt v25.4s, v21.16b, v7.b[8] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.d b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d new file mode 100644 index 0000000000000000000000000000000000000000..d2633aa84532ba74c27944639a6440e95a2d7c40 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d @@ -0,0 +1,18 @@ +#as: -march=armv8-a+sve2+fp8dot2 +#as: -march=armv8-a+ssve-fp8dot2 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64208400 fdot z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 643d8777 fdot z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 643386b9 fdot z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64204400 fdot z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 642d4f77 fdot z23\.h, z27\.b, z5\.b\[3\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 643f4eb9 fdot z25\.h, z21\.b, z7\.b\[7\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.s b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s new file mode 100644 index 0000000000000000000000000000000000000000..839222eb7ead5887ee414fc1eba7c0d924241d29 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s @@ -0,0 +1,9 @@ +fdot z0.h, z0.b, z0.b +fdot z23.h, z27.b, z29.b +movprfx z25, z31 +fdot z25.h, z21.b, z19.b + +fdot z0.h, z0.b, z0.b[0] +fdot z23.h, z27.b, z5.b[3] +movprfx z25, z31 +fdot z25.h, z21.b, z7.b[7] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.d b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d new file mode 100644 index 0000000000000000000000000000000000000000..ffb8d4ce18b7fcb43b6fe7438c9efa3f1ca68015 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d @@ -0,0 +1,18 @@ +#as: -march=armv8-a+sve2+fp8dot4 +#as: -march=armv8-a+ssve-fp8dot4 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64608400 fdot z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 647d8777 fdot z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 647386b9 fdot z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64604400 fdot z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 646d4777 fdot z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 647f46b9 fdot z25\.s, z21\.b, z7\.b\[3\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.s b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s new file mode 100644 index 0000000000000000000000000000000000000000..5cb8227f0403729857bd2fd24281a2d015a8b81b --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s @@ -0,0 +1,9 @@ +fdot z0.s, z0.b, z0.b +fdot z23.s, z27.b, z29.b +movprfx z25, z31 +fdot z25.s, z21.b, z19.b + +fdot z0.s, z0.b, z0.b[0] +fdot z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fdot z25.s, z21.b, z7.b[3] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.d b/gas/testsuite/gas/aarch64/fp8-sve-fma.d new file mode 100644 index 0000000000000000000000000000000000000000..97eae9e8c004e00658fdbdaef89a0261b50cde72 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.d @@ -0,0 +1,64 @@ +#as: -march=armv8-a+sve2+fp8fma +#as: -march=armv8-a+ssve-fp8fma +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64a08800 fmlalb z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 64bd8b77 fmlalb z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64b38ab9 fmlalb z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64205000 fmlalb z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64255777 fmlalb z23\.h, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 642f5ab9 fmlalb z25\.h, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 643f5eb9 fmlalb z25\.h, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64208800 fmlallbb z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643d8b77 fmlallbb z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64338ab9 fmlallbb z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 6420c000 fmlallbb z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 6425c777 fmlallbb z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 642fcab9 fmlallbb z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 643fceb9 fmlallbb z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64209800 fmlallbt z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643d9b77 fmlallbt z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64339ab9 fmlallbt z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 6460c000 fmlallbt z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 6465c777 fmlallbt z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 646fcab9 fmlallbt z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 647fceb9 fmlallbt z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 6420a800 fmlalltb z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643dab77 fmlalltb z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 6433aab9 fmlalltb z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64a0c000 fmlalltb z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64a5c777 fmlalltb z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64afcab9 fmlalltb z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64bfceb9 fmlalltb z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 6420b800 fmlalltt z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643dbb77 fmlalltt z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 6433bab9 fmlalltt z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64e0c000 fmlalltt z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64e5c777 fmlalltt z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64efcab9 fmlalltt z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64ffceb9 fmlalltt z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64a09800 fmlalt z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 64bd9b77 fmlalt z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64b39ab9 fmlalt z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64a05000 fmlalt z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64a55777 fmlalt z23\.h, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64af5ab9 fmlalt z25\.h, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64bf5eb9 fmlalt z25\.h, z21\.b, z7\.b\[15\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.s b/gas/testsuite/gas/aarch64/fp8-sve-fma.s new file mode 100644 index 0000000000000000000000000000000000000000..368e8da3656d755c781c493ab6f886f1edd1621d --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.s @@ -0,0 +1,65 @@ +fmlalb z0.h, z0.b, z0.b +fmlalb z23.h, z27.b, z29.b +movprfx z25, z31 +fmlalb z25.h, z21.b, z19.b + +fmlalb z0.h, z0.b, z0.b[0] +fmlalb z23.h, z27.b, z5.b[1] +movprfx z25, z31 +fmlalb z25.h, z21.b, z7.b[6] +fmlalb z25.h, z21.b, z7.b[15] + +fmlallbb z0.s, z0.b, z0.b +fmlallbb z23.s, z27.b, z29.b +movprfx z25, z31 +fmlallbb z25.s, z21.b, z19.b + +fmlallbb z0.s, z0.b, z0.b[0] +fmlallbb z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlallbb z25.s, z21.b, z7.b[6] +fmlallbb z25.s, z21.b, z7.b[15] + +fmlallbt z0.s, z0.b, z0.b +fmlallbt z23.s, z27.b, z29.b +movprfx z25, z31 +fmlallbt z25.s, z21.b, z19.b + +fmlallbt z0.s, z0.b, z0.b[0] +fmlallbt z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlallbt z25.s, z21.b, z7.b[6] +fmlallbt z25.s, z21.b, z7.b[15] + +fmlalltb z0.s, z0.b, z0.b +fmlalltb z23.s, z27.b, z29.b +movprfx z25, z31 +fmlalltb z25.s, z21.b, z19.b + +fmlalltb z0.s, z0.b, z0.b[0] +fmlalltb z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlalltb z25.s, z21.b, z7.b[6] +fmlalltb z25.s, z21.b, z7.b[15] + +fmlalltt z0.s, z0.b, z0.b +fmlalltt z23.s, z27.b, z29.b +movprfx z25, z31 +fmlalltt z25.s, z21.b, z19.b + +fmlalltt z0.s, z0.b, z0.b[0] +fmlalltt z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlalltt z25.s, z21.b, z7.b[6] +fmlalltt z25.s, z21.b, z7.b[15] + +fmlalt z0.h, z0.b, z0.b +fmlalt z23.h, z27.b, z29.b +movprfx z25, z31 +fmlalt z25.h, z21.b, z19.b + +fmlalt z0.h, z0.b, z0.b[0] +fmlalt z23.h, z27.b, z5.b[1] +movprfx z25, z31 +fmlalt z25.h, z21.b, z7.b[6] +fmlalt z25.h, z21.b, z7.b[15] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..f1d98eec161d095e59b922d7e682665634bd8d01 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sve2+fp8dot2 +#error_output: fp8-sve-mul-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..4f09c233de0921c415d032b26dc9181d891e791f --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: z0-z7 expected at operand 3 -- `fdot z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:2: Error: register element index out of range 0 to 3 at operand 3 -- `fdot z0\.s,z0\.b,z0\.b\[4\]' +[^:]*:4: Error: z0-z7 expected at operand 3 -- `fdot z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:5: Error: register element index out of range 0 to 7 at operand 3 -- `fdot z0\.h,z0\.b,z0\.b\[8\]' +[^:]*:7: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:8: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb z0\.h,z0\.b,z0\.b\[16\]' +[^:]*:10: Error: z0-z7 expected at operand 3 -- `fmlallbb z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:13: Error: z0-z7 expected at operand 3 -- `fmlallbt z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:16: Error: z0-z7 expected at operand 3 -- `fmlalltb z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:17: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:19: Error: z0-z7 expected at operand 3 -- `fmlalltt z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:22: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:23: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt z0\.h,z0\.b,z0\.b\[16\]' +[^:]*:26: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.s,z0\.b,z0\.b\[0\]' +[^:]*:29: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.h,z0\.b,z0\.b\[0\]' +[^:]*:32: Warning: predicated instruction expected after `movprfx' -- `fmlalb z25\.h,z0\.b,z0\.b\[0\]' +[^:]*:35: Warning: predicated instruction expected after `movprfx' -- `fmlallbb z25\.s,z0\.b,z0\.b\[0\]' diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..c8e3f9dc84084119984597dbd271fdce4e9bd015 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s @@ -0,0 +1,35 @@ +fdot z0.s, z0.b, z8.b[0] +fdot z0.s, z0.b, z0.b[4] + +fdot z0.h, z0.b, z8.b[0] +fdot z0.h, z0.b, z0.b[8] + +fmlalb z0.h, z0.b, z8.b[0] +fmlalb z0.h, z0.b, z0.b[16] + +fmlallbb z0.s, z0.b, z8.b[0] +fmlallbb z0.s, z0.b, z0.b[16] + +fmlallbt z0.s, z0.b, z8.b[0] +fmlallbt z0.s, z0.b, z0.b[16] + +fmlalltb z0.s, z0.b, z8.b[0] +fmlalltb z0.s, z0.b, z0.b[16] + +fmlalltt z0.s, z0.b, z8.b[0] +fmlalltt z0.s, z0.b, z0.b[16] + +fmlalt z0.h, z0.b, z8.b[0] +fmlalt z0.h, z0.b, z0.b[16] + +movprfx z25.s, p0/m, z31.s +fdot z25.s, z0.b, z0.b[0] + +movprfx z25.h, p0/z, z31.h +fdot z25.h, z0.b, z0.b[0] + +movprfx z25.h, p0/z, z31.h +fmlalb z25.h, z0.b, z0.b[0] + +movprfx z25.s, p0/m, z31.s +fmlallbb z25.s, z0.b, z0.b[0] diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 20b7a5e1d4d558aac9632e8213ee58a419f27d68..778c40d87a51cbefe17477185e0e962686ebb114 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -419,11 +419,11 @@ [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]' [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]' -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: fmlalb z0\.s, z0\.h, z0\.h\[0\] -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalb z0\.s,z0\.h,z32\.h' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d' @@ -432,11 +432,11 @@ [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]' [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]' -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: fmlalt z0\.s, z0\.h, z0\.h\[0\] -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalt z0\.s,z0\.h,z32\.h' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d' diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index c83c0a4ebb4e2c129b3363a12fce0608f852f9bf..f2bf994c23651af969f9a37f06144f5e31171519 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -240,6 +240,27 @@ enum aarch64_feature_bit { AARCH64_FEATURE_LUT, /* Branch Record Buffer Extension */ AARCH64_FEATURE_BRBE, + /* FP8FMA instructions. */ + AARCH64_FEATURE_FP8FMA, + /* FP8DOT4 instructions. */ + AARCH64_FEATURE_FP8DOT4, + /* FP8DOT2 instructions. */ + AARCH64_FEATURE_FP8DOT2, + /* SSVE FP8FMA instructions. */ + AARCH64_FEATURE_SSVE_FP8FMA, + /* SSVE FP8DOT4 instructions. */ + AARCH64_FEATURE_SSVE_FP8DOT4, + /* SSVE FP8DOT2 instructions. */ + AARCH64_FEATURE_SSVE_FP8DOT2, + + /* Virtual features. These are used to gate instructions that are enabled + by either of two (or more) sets of command line flags. */ + /* +fp8fma+sve or +ssve-fp8fma */ + AARCH64_FEATURE_FP8FMA_SVE, + /* +fp8dot4+sve or +ssve-fp8dot4 */ + AARCH64_FEATURE_FP8DOT4_SVE, + /* +fp8dot2+sve or +ssve-fp8dot2 */ + AARCH64_FEATURE_FP8DOT2_SVE, AARCH64_NUM_FEATURES }; @@ -526,7 +547,9 @@ enum aarch64_opnd AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when - qualifier is S_H. */ + qualifier is S_H or S_2B. */ + AARCH64_OPND_Em8, /* AdvSIMD Vector Element Vm restricted to V0 - V7, + used only with qualifier S_B. */ AARCH64_OPND_Em_INDEX1_14, /* AdvSIMD 1-bit encoded index in Vm at [14] */ AARCH64_OPND_Em_INDEX2_13, /* AdvSIMD 2-bit encoded index in Vm at [14:13] */ AARCH64_OPND_Em_INDEX3_12, /* AdvSIMD 3-bit encoded index in Vm at [14:12] */ @@ -748,6 +771,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm3_12_INDEX, /* SVE bit index in Zm, bits 12 plus bit [23,22]. */ AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ + AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10. */ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ @@ -862,11 +886,12 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, - /* These type qualifiers have a special meaning in that they mean 4 x 1 byte - or 2 x 2 byte are selected by the instruction. Other than that they have - no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely - for syntactical reasons and is an exception from normal AArch64 - disassembly scheme. */ + /* These type qualifiers have a special meaning in that they mean 2 x 1 byte, + 4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that + they have no difference with AARCH64_OPND_QLF_S_B in encoding. They are + here purely for syntactical reasons and is an exception from normal + AArch64 disassembly scheme. */ + AARCH64_OPND_QLF_S_2B, AARCH64_OPND_QLF_S_4B, AARCH64_OPND_QLF_S_2H, diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 5c6a31167c617f59e62a108e00c6e806cd6ec4ed..83d9dd3212751748fbbdc401310bb36d7250f32a 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -153,10 +153,15 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, { case AARCH64_OPND_QLF_S_4B: case AARCH64_OPND_QLF_S_2H: - /* L:H */ + /* H:L */ assert (reglane_index < 4); insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H); break; + case AARCH64_OPND_QLF_S_2B: + /* H:L:M */ + assert (reglane_index < 8); + insert_fields (code, reglane_index, 0, 3, FLD_M, FLD_L, FLD_H); + break; default: return false; } @@ -180,6 +185,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + assert (reglane_index < 16); + insert_fields (code, reglane_index, 0, 2, FLD_imm3_19, FLD_H); + break; case AARCH64_OPND_QLF_S_H: /* H:L:M */ assert (reglane_index < 8); diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 213df616608b3ea3159b4f6b92b65ea319999a0a..7286f178cdc02160559daf8ab797acbc737bd699 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -402,6 +402,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); info->reglane.regno &= 0x1f; break; + case AARCH64_OPND_QLF_S_2B: + /* h:l:m */ + info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, + FLD_M); + info->reglane.regno &= 0xf; + break; default: return false; } @@ -422,7 +428,15 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, return 0; switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + info->reglane.index = extract_fields (code, 0, 2, FLD_H, + FLD_imm3_19); + info->reglane.regno &= 0x7; + break; + case AARCH64_OPND_QLF_S_H: + case AARCH64_OPND_QLF_S_2B: if (info->type == AARCH64_OPND_Em16) { /* h:l:m */ @@ -437,6 +451,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, } break; case AARCH64_OPND_QLF_S_S: + case AARCH64_OPND_QLF_S_4B: /* h:l */ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); break; diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 9b734d63a3b81793d7a7d53afbfec3f1724ee8d7..3136e62375c5b9ce13a4abbf097104af2264b0f9 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -112,6 +112,7 @@ enum aarch64_field_kind FLD_SVE_i3h3, FLD_SVE_i3l, FLD_SVE_i3l2, + FLD_SVE_i4l2, FLD_SVE_imm3, FLD_SVE_imm4, FLD_SVE_imm5, @@ -169,6 +170,7 @@ enum aarch64_field_kind FLD_imm3_12, FLD_imm3_14, FLD_imm3_15, + FLD_imm3_19, FLD_imm4_0, FLD_imm4_5, FLD_imm4_10, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ea278bfdfe5f78e0bc5173a950386a97fba4cef7..903d3578c2a6822807908ba8a8c53d8de54c96bf 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -308,6 +308,7 @@ const aarch64_field fields[] = { 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ { 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */ + { 10, 2 }, /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -365,6 +366,7 @@ const aarch64_field fields[] = { 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */ { 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */ { 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */ + { 19, 3 }, /* imm3_19: general immediate in bits [21:19]. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ @@ -816,6 +818,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] = {4, 1, 0x2, "s", OQK_OPD_VARIANT}, {8, 1, 0x3, "d", OQK_OPD_VARIANT}, {16, 1, 0x4, "q", OQK_OPD_VARIANT}, + {2, 1, 0x0, "2b", OQK_OPD_VARIANT}, {4, 1, 0x0, "4b", OQK_OPD_VARIANT}, {4, 1, 0x0, "2h", OQK_OPD_VARIANT}, @@ -1814,6 +1817,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: size = get_operand_fields_width (get_operand_from_code (type)); @@ -3222,12 +3226,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, 01 0:Rm 10 M:Rm 11 RESERVED */ - if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H + if (type == AARCH64_OPND_Em16 + && (qualifier == AARCH64_OPND_QLF_S_H + || qualifier == AARCH64_OPND_QLF_S_2B) && !value_in_range_p (opnd->reglane.regno, 0, 15)) { set_regno_out_of_range_error (mismatch_detail, idx, 0, 15); return 0; } + if (type == AARCH64_OPND_Em8 + && !value_in_range_p (opnd->reglane.regno, 0, 7)) + { + set_regno_out_of_range_error (mismatch_detail, idx, 0, 7); + return 0; + } break; case AARCH64_OPND_CLASS_MODIFIED_REG: @@ -4110,6 +4122,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: snprintf (buf, size, "%s[%s]", style_reg (styler, "v%d.%s", opnd->reglane.regno, @@ -4235,6 +4248,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index bffb422583a8e27a38d3881716a28cf09ef0c4cd..aae87e1f24a21d58ffb6a0e3667b7764d00ba1f7 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2204,6 +2204,10 @@ { \ QLF3(S_S,S_B,S_B), \ } +#define OP_SVE_VVV_H_B \ +{ \ + QLF3(S_H,S_B,S_B), \ +} #define OP_SVE_VVV_Q_D \ { \ QLF3(S_Q,S_D,S_D), \ @@ -2453,6 +2457,20 @@ QLF3(V_4S, V_16B, S_4B),\ } +/* e.g. FDOT .4H, .8B, .8B. */ +#define QL_V3DOTH \ +{ \ + QLF3(V_4H, V_8B, V_8B), \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FDOT .4H, .8B, .2B[]. */ +#define QL_V2DOTH \ +{ \ + QLF3(V_4H, V_8B, S_2B),\ + QLF3(V_8H, V_16B, S_2B),\ +} + /* e.g. SHA512H , , .2D . */ #define QL_SHA512UPT \ { \ @@ -2519,6 +2537,30 @@ QLF3(V_4S, V_4H, S_H),\ } +/* e.g. FMLALB .8H, .16B, .16B. */ +#define QL_V3FML8H \ +{ \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FMLALB .8H, .16B, .B. */ +#define QL_V2FML8H \ +{ \ + QLF3(V_8H, V_16B, S_B),\ +} + +/* e.g. FMLALLBB .4S, .16B, .16B. */ +#define QL_V3FMLL4S \ +{ \ + QLF3(V_4S, V_16B, V_16B),\ +} + +/* e.g. FMLALLBB .4S, .16B, .B. */ +#define QL_V2FMLL4S \ +{ \ + QLF3(V_4S, V_16B, S_B),\ +} + /* e.g. RMIF , #, #. */ #define QL_RMIF \ { \ @@ -2752,6 +2794,18 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 = AARCH64_FEATURES (2, LUT, SVE2); static const aarch64_feature_set aarch64_feature_brbe = AARCH64_FEATURE (BRBE); +static const aarch64_feature_set aarch64_feature_fp8fma = + AARCH64_FEATURE (FP8FMA); +static const aarch64_feature_set aarch64_feature_fp8dot4 = + AARCH64_FEATURE (FP8DOT4); +static const aarch64_feature_set aarch64_feature_fp8dot2 = + AARCH64_FEATURE (FP8DOT2); +static const aarch64_feature_set aarch64_feature_fp8fma_sve = + AARCH64_FEATURES (2, FP8FMA_SVE, SVE); +static const aarch64_feature_set aarch64_feature_fp8dot4_sve = + AARCH64_FEATURES (2, FP8DOT4_SVE, SVE); +static const aarch64_feature_set aarch64_feature_fp8dot2_sve = + AARCH64_FEATURES (2, FP8DOT2_SVE, SVE); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2829,6 +2883,12 @@ static const aarch64_feature_set aarch64_feature_brbe = #define LUT &aarch64_feature_lut #define LUT_SVE2 &aarch64_feature_lut_sve2 #define BRBE &aarch64_feature_brbe +#define FP8FMA &aarch64_feature_fp8fma +#define FP8DOT4 &aarch64_feature_fp8dot4 +#define FP8DOT2 &aarch64_feature_fp8dot2 +#define FP8FMA_SVE &aarch64_feature_fp8fma_sve +#define FP8DOT4_SVE &aarch64_feature_fp8dot4_sve +#define FP8DOT2_SVE &aarch64_feature_fp8dot2_sve #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -3029,6 +3089,18 @@ static const aarch64_feature_set aarch64_feature_brbe = FLAGS, CONSTRAINTS, 0, NULL } #define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8FMA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT4_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -6615,6 +6687,42 @@ const struct aarch64_opcode aarch64_opcode_table[] = LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0), LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0), + /* FP8 multiplication AdvSIMD instructions. */ + FP8DOT4_INSN("fdot", 0x0e00fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + FP8DOT4_INSN("fdot", 0x0f000000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0e40fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOTH, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0f400000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em16), QL_V2DOTH, F_SIZEQ), + FP8FMA_INSN("fmlalb", 0x0ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalb", 0x0fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlallbb", 0x0e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x0e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x4e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x4e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbb", 0x2f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x2f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x6f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x6f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + + /* FP8 multiplication SVE instructions. */ + FP8DOT4_SVE_INSNC("fdot", 0x64608400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT4_SVE_INSNC("fdot", 0x64604400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64208400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64204400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64a08800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64205000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x64208800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x6420c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x64209800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x6460c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x6420a800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x64a0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x6420b800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x64e0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a05000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -6690,6 +6798,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a SIMD vector element") \ Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ "a SIMD vector element limited to V0-V15") \ + Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD_Rm), \ + "a SIMD vector element limited to V0-V7") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, F(FLD_Rm, FLD_imm1_14), \ "a SIMD vector without a type qualifier encoding a bit index") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, F(FLD_Rm, FLD_imm2_13), \ @@ -7113,6 +7223,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_quad_index, "SVE_Zm3_10_INDEX", \ + 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3), \ + "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ "an indexed SVE vector register") \ From patchwork Fri Jun 21 18:32:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 92694 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C0D713830B69 for ; Fri, 21 Jun 2024 18:33:14 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2070.outbound.protection.outlook.com [40.107.22.70]) by sourceware.org (Postfix) with ESMTPS id AD3553830B40 for ; Fri, 21 Jun 2024 18:32:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter 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X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 6c58452efda4bf682f6c620df3addf749b6e9f01..6c6f983be3f4a9de308f589c718476319d2ba2bc 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -651,10 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 122: case 123: case 124: - case 182: + case 125: case 183: case 184: case 185: @@ -668,30 +667,31 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 195: - case 210: + case 196: case 211: case 212: case 213: - case 222: + case 214: case 223: case 224: case 225: case 226: - case 237: - case 241: - case 245: - case 252: - case 253: - case 260: - case 261: + case 227: + case 239: + case 243: + case 247: + case 254: + case 255: case 262: case 263: + case 264: + case 265: return aarch64_ins_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 295: + case 120: case 297: + case 299: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -705,18 +705,17 @@ aarch64_insert_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 299: - return aarch64_ins_reglane (self, info, code, inst, errors); case 39: + case 301: + return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: - case 227: + case 42: case 228: - case 231: - case 264: - case 265: - case 280: - case 281: + case 229: + case 232: + case 266: + case 267: case 282: case 283: case 284: @@ -728,22 +727,23 @@ aarch64_insert_operand (const aarch64_operand *self, case 290: case 291: case 292: + case 293: + case 294: return aarch64_ins_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ins_reglist (self, info, code, inst, errors); case 43: - return aarch64_ins_ldst_reglist (self, info, code, inst, errors); + return aarch64_ins_reglist (self, info, code, inst, errors); case 44: - return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ins_lut_reglist (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ins_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -760,15 +760,15 @@ aarch64_insert_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 88: + case 77: case 89: case 90: case 91: - case 117: - case 121: - case 179: - case 181: - case 202: + case 92: + case 118: + case 122: + case 180: + case 182: case 203: case 204: case 205: @@ -776,102 +776,102 @@ aarch64_insert_operand (const aarch64_operand *self, case 207: case 208: case 209: - case 266: - case 293: - case 294: + case 210: + case 268: + case 295: case 296: case 298: - case 303: - case 304: + case 300: + case 305: + case 306: return aarch64_ins_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: + case 56: return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); - case 59: - case 169: + case 60: + case 170: return aarch64_ins_fpimm (self, info, code, inst, errors); - case 77: - case 177: - return aarch64_ins_limm (self, info, code, inst, errors); case 78: - return aarch64_ins_aimm (self, info, code, inst, errors); + case 178: + return aarch64_ins_limm (self, info, code, inst, errors); case 79: - return aarch64_ins_imm_half (self, info, code, inst, errors); + return aarch64_ins_aimm (self, info, code, inst, errors); case 80: + return aarch64_ins_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ins_fbits (self, info, code, inst, errors); - case 82: case 83: - case 174: - return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 84: - case 173: case 175: - return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 85: + case 174: + case 176: + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ins_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ins_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ins_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ins_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ins_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ins_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ins_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ins_simd_addr_post (self, info, code, inst, errors); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ins_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ins_pstatefield (self, info, code, inst, errors); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ins_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ins_barrier (self, info, code, inst, errors); + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ins_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ins_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ins_hint (self, info, code, inst, errors); - case 125: case 126: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 127: + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 128: case 129: case 130: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 131: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 132: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 133: + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 134: case 135: case 136: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 137: + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 138: case 139: case 140: @@ -886,8 +886,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 149: case 150: case 151: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 152: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: case 154: case 155: @@ -895,116 +895,118 @@ aarch64_insert_operand (const aarch64_operand *self, case 157: case 158: case 159: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 160: + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: case 162: case 163: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 164: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 166: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 167: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 168: + return aarch64_ins_sve_aimm (self, info, code, inst, errors); + case 169: return aarch64_ins_sve_asimm (self, info, code, inst, errors); - case 170: - return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 171: - return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 172: + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + case 173: return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 180: + case 181: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 196: case 197: case 198: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 199: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 200: case 201: - case 279: + case 202: + case 281: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 214: case 215: case 216: case 217: - return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 218: + return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 219: case 220: case 221: + case 222: return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); - case 229: case 230: - case 232: + case 231: case 233: case 234: case 235: case 236: - return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 237: case 238: + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 240: return aarch64_ins_sve_index_imm (self, info, code, inst, errors); - case 239: + case 241: return aarch64_ins_sve_index (self, info, code, inst, errors); - case 240: case 242: - case 259: - case 305: - case 306: + case 244: + case 261: case 307: + case 308: + case 309: return aarch64_ins_sve_reglist (self, info, code, inst, errors); - case 243: - case 244: + case 245: case 246: - case 247: case 248: case 249: - case 258: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 250: case 251: + case 260: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); + case 252: + case 253: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 254: case 256: - case 267: + case 258: + case 269: return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); - case 255: case 257: + case 259: return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 268: - case 269: case 270: case 271: case 272: case 273: case 274: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 275: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 276: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 278: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 279: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 280: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 300: - case 301: case 302: + case 303: + case 304: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 308: - case 309: case 310: case 311: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 312: + case 313: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 314: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 3d17f18c9a572ba0923e7398a364a74e4f3ce9fa..38cb3a1c52d7922fed9c9f946ed60651bf3b7c4d 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -17252,11 +17252,33 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0001xxxxx010xxxxxxxxxxxxx - fdot. */ - return 2473; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x0xxxxxxxxxx + fdot. */ + return 2473; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x1xxxxxxxxxx + fdot. */ + return 3413; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0101xxxxxxxxxxxx + fmlalb. */ + return 3415; + } } else { @@ -17271,21 +17293,32 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx010xx0xxxxxxxxxx - fmlalb. */ - return 2146; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x0xxxxxxxxxx + fmlalb. */ + return 2146; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x1xxxxxxxxxx + fmlalt. */ + return 2148; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx010xx1xxxxxxxxxx + 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 2148; + return 3425; } } else @@ -17304,11 +17337,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0011xxxxx010xxxxxxxxxxxxx - bfdot. */ - return 3066; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx0xxxxxxxxxx + bfdot. */ + return 3066; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx1xxxxxxxxxx + fdot. */ + return 3411; + } } else { @@ -17358,31 +17402,108 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0001xxxxx1x0xxxxxxxxxxxxx - fdot. */ - return 2474; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100000xxxxxxxxxx + fdot. */ + return 2474; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100010xxxxxxxxxx + fmlallbb. */ + return 3416; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1000x1xxxxxxxxxx + fdot. */ + return 3412; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1100xxxxxxxxxxxx + fmlallbb. */ + return 3417; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1x01xxxxxxxxxxxx + fmlallbt. */ + return 3418; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx0xxxxxxxxxx - fmlalb. */ - return 2147; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100000xxxxxxxxxx + fmlalb. */ + return 2147; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100010xxxxxxxxxx + fmlalb. */ + return 3414; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1000x1xxxxxxxxxx + fmlalt. */ + return 2149; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1100xxxxxxxxxxxx + fmlalltb. */ + return 3421; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx1xxxxxxxxxx + 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 2149; + return 3424; } } else @@ -17399,31 +17520,64 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0011xxxxx1x0xxxxxxxxxxxxx - bfdot. */ - return 3065; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx0xxxxxxxxxx + bfdot. */ + return 3065; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx1xxxxxxxxxx + fdot. */ + return 3410; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx110xxxxxxxxxxxxx + fmlallbt. */ + return 3419; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx0xxxxxxxxxx - bfmlalb. */ - return 3071; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx0xxxxxxxxxx + bfmlalb. */ + return 3071; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx1xxxxxxxxxx + bfmlalt. */ + return 3070; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx1xxxxxxxxxx - bfmlalt. */ - return 3070; + 011001x0111xxxxx110xxxxxxxxxxxxx + fmlalltt. */ + return 3423; } } else @@ -17729,32 +17883,54 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - if (((word >> 31) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx0xxxxxxxxxx - fmlslb. */ - return 2151; + x11001x0001xxxxx1010xxxxxxxxxxxx + fmlalltb. */ + return 3420; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx1xxxxxxxxxx - fmlslt. */ - return 2153; + x11001x0001xxxxx1011xxxxxxxxxxxx + fmlalltt. */ + return 3422; } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 111001x0x01xxxxx101xxxxxxxxxxxxx - st1h. */ - return 1954; + if (((word >> 31) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx0xxxxxxxxxx + fmlslb. */ + return 2151; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx1xxxxxxxxxx + fmlslt. */ + return 2153; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 111001x0101xxxxx101xxxxxxxxxxxxx + st1h. */ + return 1954; + } } } else @@ -25943,31 +26119,75 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 13) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx0001xxxxxxxxxx - dup. */ - return 149; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx00001xxxxxxxxxx + dup. */ + return 149; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx00001xxxxxxxxxx + fmaxnm. */ + return 292; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx00001xxxxxxxxxx + fminnm. */ + return 308; + } + } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110010xxxxxxx0001xxxxxxxxxx - fmaxnm. */ - return 292; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x00xxxxxx10001xxxxxxxxxx + fmlallbb. */ + return 3402; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x00xxxxxx10001xxxxxxxxxx + fmlalltb. */ + return 3404; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx0001xxxxxxxxxx - fminnm. */ - return 308; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x10xxxxxx10001xxxxxxxxxx + fmlallbt. */ + return 3403; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x10xxxxxx10001xxxxxxxxxx + fmlalltt. */ + return 3405; + } } } } @@ -26176,37 +26396,81 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx1111xxxxxxxxxx - umov. */ - return 152; - } - else + if (((word >> 14) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 0x001110010xxxxxxx1111xxxxxxxxxx - frecps. */ - return 304; + 0x001110x00xxxxxx01111xxxxxxxxxx + umov. */ + return 152; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx1111xxxxxxxxxx - frsqrts. */ - return 316; - } - } - } - } - } - } + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx01111xxxxxxxxxx + frecps. */ + return 304; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx01111xxxxxxxxxx + frsqrts. */ + return 316; + } + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx11111xxxxxxxxxx + fdot. */ + return 3394; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx11111xxxxxxxxxx + fdot. */ + return 3396; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110110xxxxxx11111xxxxxxxxxx + fmlalb. */ + return 3398; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110110xxxxxx11111xxxxxxxxxx + fmlalt. */ + return 3399; + } + } + } + } + } + } + } + } } else { @@ -31639,21 +31903,65 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3013; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111100xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3395; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3013; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3017; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3017; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111101xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3397; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111111xxxxxx0000x0xxxxxxxxxx + fmlalb. */ + return 3400; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111111xxxxxx0000x0xxxxxxxxxx + fmlalt. */ + return 3401; + } + } } } else @@ -32183,21 +32491,65 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3015; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111100xxxxxx1000x0xxxxxxxxxx + fmlallbb. */ + return 3406; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111100xxxxxx1000x0xxxxxxxxxx + fmlalltb. */ + return 3408; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3015; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3019; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3019; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0101111x1xxxxxx1000x0xxxxxxxxxx + fmlallbt. */ + return 3407; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1101111x1xxxxxx1000x0xxxxxxxxxx + fmlalltt. */ + return 3409; + } } } } @@ -33648,10 +34000,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 122: case 123: case 124: - case 182: + case 125: case 183: case 184: case 185: @@ -33665,30 +34016,31 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 195: - case 210: + case 196: case 211: case 212: case 213: - case 222: + case 214: case 223: case 224: case 225: case 226: - case 237: - case 241: - case 245: - case 252: - case 253: - case 260: - case 261: + case 227: + case 239: + case 243: + case 247: + case 254: + case 255: case 262: case 263: + case 264: + case 265: return aarch64_ext_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 295: + case 120: case 297: + case 299: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -33707,18 +34059,17 @@ aarch64_extract_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 299: - return aarch64_ext_reglane (self, info, code, inst, errors); case 39: + case 301: + return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: - case 227: + case 42: case 228: - case 231: - case 264: - case 265: - case 280: - case 281: + case 229: + case 232: + case 266: + case 267: case 282: case 283: case 284: @@ -33730,22 +34081,23 @@ aarch64_extract_operand (const aarch64_operand *self, case 290: case 291: case 292: + case 293: + case 294: return aarch64_ext_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ext_reglist (self, info, code, inst, errors); case 43: - return aarch64_ext_ldst_reglist (self, info, code, inst, errors); + return aarch64_ext_reglist (self, info, code, inst, errors); case 44: - return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ext_lut_reglist (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ext_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -33762,16 +34114,16 @@ aarch64_extract_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 87: + case 77: case 88: case 89: case 90: case 91: - case 117: - case 121: - case 179: - case 181: - case 202: + case 92: + case 118: + case 122: + case 180: + case 182: case 203: case 204: case 205: @@ -33779,104 +34131,104 @@ aarch64_extract_operand (const aarch64_operand *self, case 207: case 208: case 209: - case 266: - case 293: - case 294: + case 210: + case 268: + case 295: case 296: case 298: - case 303: - case 304: + case 300: + case 305: + case 306: return aarch64_ext_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 56: + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); + case 57: return aarch64_ext_shll_imm (self, info, code, inst, errors); - case 59: - case 169: + case 60: + case 170: return aarch64_ext_fpimm (self, info, code, inst, errors); - case 77: - case 177: - return aarch64_ext_limm (self, info, code, inst, errors); case 78: - return aarch64_ext_aimm (self, info, code, inst, errors); + case 178: + return aarch64_ext_limm (self, info, code, inst, errors); case 79: - return aarch64_ext_imm_half (self, info, code, inst, errors); + return aarch64_ext_aimm (self, info, code, inst, errors); case 80: + return aarch64_ext_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ext_fbits (self, info, code, inst, errors); - case 82: case 83: - case 174: - return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 84: - case 173: case 175: - return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 85: + case 174: + case 176: + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ext_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ext_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ext_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ext_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ext_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ext_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ext_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ext_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ext_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ext_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ext_simd_addr_post (self, info, code, inst, errors); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ext_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ext_pstatefield (self, info, code, inst, errors); + return aarch64_ext_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ext_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ext_barrier (self, info, code, inst, errors); + return aarch64_ext_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ext_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ext_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ext_hint (self, info, code, inst, errors); - case 125: case 126: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 127: + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 128: case 129: case 130: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 131: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 132: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 133: + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 134: case 135: case 136: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 137: + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 138: case 139: case 140: @@ -33891,8 +34243,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 149: case 150: case 151: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 152: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: case 154: case 155: @@ -33900,117 +34252,119 @@ aarch64_extract_operand (const aarch64_operand *self, case 157: case 158: case 159: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 160: + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: case 162: case 163: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 164: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 166: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 167: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 168: + return aarch64_ext_sve_aimm (self, info, code, inst, errors); + case 169: return aarch64_ext_sve_asimm (self, info, code, inst, errors); - case 170: - return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 171: - return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 172: + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + case 173: return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 180: + case 181: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 196: case 197: case 198: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 199: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 200: case 201: - case 279: + case 202: + case 281: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 214: case 215: case 216: case 217: - return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 218: + return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 219: case 220: case 221: + case 222: return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); - case 229: case 230: - case 232: + case 231: case 233: case 234: case 235: case 236: - return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 237: case 238: + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 240: return aarch64_ext_sve_index_imm (self, info, code, inst, errors); - case 239: + case 241: return aarch64_ext_sve_index (self, info, code, inst, errors); - case 240: case 242: - case 259: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); - case 243: case 244: + case 261: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); + case 245: case 246: - case 247: case 248: case 249: - case 258: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 250: case 251: + case 260: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); + case 252: + case 253: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 254: case 256: - case 267: + case 258: + case 269: return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); - case 255: case 257: + case 259: return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 268: - case 269: case 270: case 271: case 272: case 273: case 274: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 275: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 276: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 278: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 279: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 280: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 300: - case 301: case 302: + case 303: + case 304: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); - case 305: - case 306: case 307: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 308: case 309: + return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 310: case 311: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 312: + case 313: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 314: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 14dd96af4654ae1f975481de08aeb072a4f71b07..725e9c840b3c6f0d884dd38abddb812722a443c1 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -63,6 +63,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V7"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm1_14}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm2_13}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm3_12}, "a SIMD vector without a type qualifier encoding a bit index"}, @@ -258,6 +259,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, From patchwork Fri Jun 21 18:32:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 92697 Return-Path: X-Original-To: patchwork@sourceware.org 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X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org This includes: - FEAT_SME_F8F32 (+sme-f8f32) - FEAT_SME_F8F16 (+sme-f8f16) The FP16 addition/subtraction instructions originally added by FEAT_SME_F16F16 haven't been added to Binutils yet. They are also required to be enabled if FEAT_SME_F8F16 is present, so they are included in this patch. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index db7741f5915349295e0285e1695b9016779f776a..ea88047a2ae53b2355548ce964f74819b94ab33d 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6807,10 +6807,14 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zn_5_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX2_3: case AARCH64_OPND_SME_Zm_INDEX3_1: case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_3: case AARCH64_OPND_SME_Zm_INDEX3_10: case AARCH64_OPND_SME_Zm_INDEX4_1: + case AARCH64_OPND_SME_Zm_INDEX4_2: + case AARCH64_OPND_SME_Zm_INDEX4_3: case AARCH64_OPND_SME_Zm_INDEX4_10: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: @@ -8021,6 +8025,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; break; + case AARCH64_OPND_SME_ZAda_1b: case AARCH64_OPND_SME_ZAda_2b: case AARCH64_OPND_SME_ZAda_3b: reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier, 0); @@ -10614,6 +10619,10 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURE (SSVE_FP8FMA)}, {"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (SSVE_FP8DOT4)}, + {"sme-f8f32", AARCH64_FEATURE (SME_F8F32), + AARCH64_FEATURES (2, FP8, SME2)}, + {"sme-f8f16", AARCH64_FEATURE (SME_F8F16), + AARCH64_FEATURE (SME_F8F32)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; @@ -10632,6 +10641,8 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = { {AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)}, {AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)}, {AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)}, + /* TODO: Add SME_F16F16->SME_F16F16_F8F16 when SME_F16F16 is added. */ + {AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)}, }; static aarch64_feature_set diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 530d712f55a7e0fc985b7ab04d2dadc18298d189..8434d316f2d3889813210f4616f317d15be20555 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -271,6 +271,10 @@ automatically cause those extensions to be disabled. @tab Enable the SM3 and SM4 cryptographic extensions. @item @code{sme} @tab @code{sve2}, @code{bf16} @tab Enable the Scalable Matrix Extension. +@item @code{sme-f8f16} @tab @code{sme-f8f32} + @tab Enable the SME F8F16 Extension. +@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8} + @tab Enable the SME F8F32 Extension. @item @code{sme-f64f64} @tab @code{sme} @tab Enable SME F64F64 Extension. @item @code{sme-i16i64} @tab @code{sme} diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..58580167f66d30dfa839248151ebc476468632e2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sme-f8f16 +#error_output: fp8-sme-dot-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..3444d738cdc147829550cac851c6cf954477929b --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.l @@ -0,0 +1,87 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]' +[^:]*:2: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]' +[^:]*:3: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:4: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]' +[^:]*:5: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:9: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]' +[^:]*:10: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]' +[^:]*:11: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:12: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[4\]' +[^:]*:13: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:15: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:17: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b' +[^:]*:18: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b' +[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b' +[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b' +[^:]*:21: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b' +[^:]*:23: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b' +[^:]*:24: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b' +[^:]*:25: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b' +[^:]*:26: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b' +[^:]*:27: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b' +[^:]*:29: Error: expected a list of 2 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}' +[^:]*:30: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}' +[^:]*:31: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}' +[^:]*:32: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:33: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:35: Error: expected a list of 4 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}' +[^:]*:36: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}' +[^:]*:37: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}' +[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:39: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:41: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]' +[^:]*:42: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]' +[^:]*:43: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:44: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]' +[^:]*:45: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:46: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:49: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]' +[^:]*:50: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]' +[^:]*:51: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:52: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[8\]' +[^:]*:53: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:54: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:55: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:57: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b' +[^:]*:58: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b' +[^:]*:59: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b' +[^:]*:60: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b' +[^:]*:61: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b' +[^:]*:63: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b' +[^:]*:64: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b' +[^:]*:65: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b' +[^:]*:66: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b' +[^:]*:67: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b' +[^:]*:69: Error: expected a list of 2 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}' +[^:]*:70: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}' +[^:]*:71: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}' +[^:]*:72: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:73: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:75: Error: expected a list of 4 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}' +[^:]*:76: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}' +[^:]*:77: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}' +[^:]*:78: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:79: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:81: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:82: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:83: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:84: Error: start register out of range at operand 2 -- `fvdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]' +[^:]*:85: Error: z0-z15 expected at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]' +[^:]*:86: Error: register element index out of range 0 to 7 at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]' +[^:]*:88: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:89: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:90: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdotb za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:91: Error: start register out of range at operand 2 -- `fvdotb za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]' +[^:]*:92: Error: z0-z15 expected at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]' +[^:]*:93: Error: register element index out of range 0 to 3 at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]' +[^:]*:95: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:96: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:97: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdott za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:98: Error: start register out of range at operand 2 -- `fvdott za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]' +[^:]*:99: Error: z0-z15 expected at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]' +[^:]*:100: Error: register element index out of range 0 to 3 at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]' diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..508bd79e538078ad881a3dec6a2f11633b4938f7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-dot-illegal.s @@ -0,0 +1,100 @@ +fdot za.s[w8, 0], { z0.b-z1.b }, z16.b[0] +fdot za.s[w8, 0], { z1.b-z2.b }, z0.b[0] +fdot za.s[w8, 0, VGx2], { z0.b-z3.b }, z0.b[0] +fdot za.s[w8, 0], { z0.b-z1.b }, z0.b[4] +fdot za.s[w8, 8], { z0.b-z1.b }, z0.b[0] +fdot za.s[w7, 0], { z0.b-z1.b }, z0.b[0] +fdot za.s[w12, 0], { z0.b-z1.b }, z0.b[0] + +fdot za.s[w8, 0], { z0.b-z3.b }, z16.b[0] +fdot za.s[w8, 0], { z2.b-z5.b }, z0.b[0] +fdot za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0] +fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[4] +fdot za.s[w8, 8], { z0.b-z3.b }, z0.b[0] +fdot za.s[w7, 0], { z0.b-z3.b }, z0.b[0] +fdot za.s[w12, 0], { z0.b-z3.b }, z0.b[0] + +fdot za.s[w8, 0], { z0.b-z1.b }, z16.b +fdot za.s[w8, 8], { z0.b-z1.b }, z0.b +fdot za.s[w7, 0], { z0.b-z1.b }, z0.b +fdot za.s[w12, 0], { z0.b-z1.b }, z0.b +fdot za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b + +fdot za.s[w8, 0], { z0.b-z3.b }, z16.b +fdot za.s[w8, 8], { z0.b-z3.b }, z0.b +fdot za.s[w7, 0], { z0.b-z3.b }, z0.b +fdot za.s[w12, 0], { z0.b-z3.b }, z0.b +fdot za.s[w8, 0, VGx2], { z0.b-z3.b }, z0.b + +fdot za.s[w8, 0], { z0.b-z1.b }, { z0.b-z3.b} +fdot za.s[w8, 0], { z0.b-z1.b }, { z1.b-z2.b} +fdot za.s[w8, 0], { z1.b-z2.b }, { z0.b-z1.b} +fdot za.s[w7, 0], { z0.b-z1.b }, { z0.b-z1.b} +fdot za.s[w8, 8], { z0.b-z1.b }, { z0.b-z1.b} + +fdot za.s[w8, 0], { z0.b-z3.b }, { z0.b-z1.b} +fdot za.s[w8, 0], { z0.b-z3.b }, { z2.b-z5.b} +fdot za.s[w8, 0], { z2.b-z5.b }, { z0.b-z3.b} +fdot za.s[w7, 0], { z0.b-z3.b }, { z0.b-z3.b} +fdot za.s[w8, 8], { z0.b-z3.b }, { z0.b-z3.b} + +fdot za.h[w8, 0], { z0.b-z1.b }, z16.b[0] +fdot za.h[w8, 0], { z1.b-z2.b }, z0.b[0] +fdot za.h[w8, 0, VGx2], { z0.b-z3.b }, z0.b[0] +fdot za.h[w8, 0], { z0.b-z1.b }, z0.b[8] +fdot za.h[w8, 8], { z0.b-z1.b }, z0.b[0] +fdot za.h[w7, 0], { z0.b-z1.b }, z0.b[0] +fdot za.h[w12, 0], { z0.b-z1.b }, z0.b[0] + +fdot za.h[w8, 0], { z0.b-z3.b }, z16.b[0] +fdot za.h[w8, 0], { z2.b-z5.b }, z0.b[0] +fdot za.h[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0] +fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[8] +fdot za.h[w8, 8], { z0.b-z3.b }, z0.b[0] +fdot za.h[w7, 0], { z0.b-z3.b }, z0.b[0] +fdot za.h[w12, 0], { z0.b-z3.b }, z0.b[0] + +fdot za.h[w8, 0], { z0.b-z1.b }, z16.b +fdot za.h[w8, 8], { z0.b-z1.b }, z0.b +fdot za.h[w7, 0], { z0.b-z1.b }, z0.b +fdot za.h[w12, 0], { z0.b-z1.b }, z0.b +fdot za.h[w8, 0, VGx4], { z0.b-z1.b }, z0.b + +fdot za.h[w8, 0], { z0.b-z3.b }, z16.b +fdot za.h[w8, 8], { z0.b-z3.b }, z0.b +fdot za.h[w7, 0], { z0.b-z3.b }, z0.b +fdot za.h[w12, 0], { z0.b-z3.b }, z0.b +fdot za.h[w8, 0, VGx2], { z0.b-z3.b }, z0.b + +fdot za.h[w8, 0], { z0.b-z1.b }, { z0.b-z3.b} +fdot za.h[w8, 0], { z0.b-z1.b }, { z1.b-z2.b} +fdot za.h[w8, 0], { z1.b-z2.b }, { z0.b-z1.b} +fdot za.h[w7, 0], { z0.b-z1.b }, { z0.b-z1.b} +fdot za.h[w8, 8], { z0.b-z1.b }, { z0.b-z1.b} + +fdot za.h[w8, 0], { z0.b-z3.b }, { z0.b-z1.b} +fdot za.h[w8, 0], { z0.b-z3.b }, { z2.b-z5.b} +fdot za.h[w8, 0], { z2.b-z5.b }, { z0.b-z3.b} +fdot za.h[w7, 0], { z0.b-z3.b }, { z0.b-z3.b} +fdot za.h[w8, 8], { z0.b-z3.b }, { z0.b-z3.b} + +fvdot za.h[w7, 0], {z0.b-z1.b}, z0.b[0] +fvdot za.h[w12, 0], {z0.b-z1.b}, z0.b[0] +fvdot za.h[w8, 8], {z0.b-z1.b}, z0.b[0] +fvdot za.h[w8, 0], {z1.b-z2.b}, z0.b[0] +fvdot za.h[w8, 0], {z0.b-z1.b}, z16.b[0] +fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[8] + +fvdotb za.s[w7, 0], {z0.b-z1.b}, z0.b[0] +fvdotb za.s[w12, 0], {z0.b-z1.b}, z0.b[0] +fvdotb za.s[w8, 8], {z0.b-z1.b}, z0.b[0] +fvdotb za.s[w8, 0], {z1.b-z2.b}, z0.b[0] +fvdotb za.s[w8, 0], {z0.b-z1.b}, z16.b[0] +fvdotb za.s[w8, 0], {z0.b-z1.b}, z0.b[4] + +fvdott za.s[w7, 0], {z0.b-z1.b}, z0.b[0] +fvdott za.s[w12, 0], {z0.b-z1.b}, z0.b[0] +fvdott za.s[w8, 8], {z0.b-z1.b}, z0.b[0] +fvdott za.s[w8, 0], {z1.b-z2.b}, z0.b[0] +fvdott za.s[w8, 0], {z0.b-z1.b}, z16.b[0] +fvdott za.s[w8, 0], {z0.b-z1.b}, z0.b[4] diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot2.d b/gas/testsuite/gas/aarch64/fp8-sme-dot2.d new file mode 100644 index 0000000000000000000000000000000000000000..8e78b0c8aa2aeb0db152196f896788022dccbcba --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-dot2.d @@ -0,0 +1,50 @@ +#as: -march=armv8-a+sme-f8f16 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: c1d00020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1df0020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\] + *[0-9a-f]+: c1d003e0 fdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d00820 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[4\] + *[0-9a-f]+: c1d00c28 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\] + *[0-9a-f]+: c1d00027 fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d06020 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1109040 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c11f9040 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\] + *[0-9a-f]+: c11093c0 fdot za\.h\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c1109840 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[4\] + *[0-9a-f]+: c1109c48 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\] + *[0-9a-f]+: c1109047 fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c110f040 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c1201008 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c12f1008 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b + *[0-9a-f]+: c12013e8 fdot za\.h\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b + *[0-9a-f]+: c120100f fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1207008 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1301008 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c13f1008 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b + *[0-9a-f]+: c13013e8 fdot za\.h\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b + *[0-9a-f]+: c130100f fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1307008 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1a01020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1be1020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b} + *[0-9a-f]+: c1a013e0 fdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a01027 fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a07020 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a11020 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1bd1020 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b} + *[0-9a-f]+: c1a113a0 fdot za\.h\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a11027 fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a17020 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1d01020 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d07020 fvdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d01027 fvdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d013e0 fvdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c1df1020 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\] + *[0-9a-f]+: c1d01428 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\] + *[0-9a-f]+: c1d01c28 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\] diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot2.s b/gas/testsuite/gas/aarch64/fp8-sme-dot2.s new file mode 100644 index 0000000000000000000000000000000000000000..6da4c3702a1a82cf66358262e1feafffa388d0a8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-dot2.s @@ -0,0 +1,47 @@ +fdot za.h[w8, 0], { z0.b-z1.b }, z0.b[0] +fdot za.h[w8, 0], { z0.b - z1.b }, z15.b[0] +fdot za.h[w8, 0], { z30.b-z31.b }, z0.b[0] +fdot za.h[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[4] +fdot za.h[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[7] +fdot za.h[w8, 7], { z0.b-z1.b }, z0.b[0] +fdot za.h[w11, 0], { z0.b-z1.b }, z0.b[0] + +fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[0] +fdot za.h[w8, 0, VGx4], { z0.b - z3.b }, z15.b[0] +fdot za.h[w8, 0], { z28.b-z31.b }, z0.b[0] +fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[4] +fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[7] +fdot za.h[w8, 7], { z0.b-z3.b }, z0.b[0] +fdot za.h[w11, 0], { z0.b-z3.b }, z0.b[0] + +fdot za.h[w8, 0], { z0.b-z1.b }, z0.b +fdot za.h[w8, 0], { z0.b - z1.b }, z15.b +fdot za.h[w8, 0, VGx2], { z31.b-z0.b }, z0.b +fdot za.h[w8, 7], { z0.b-z1.b }, z0.b +fdot za.h[w11, 0], { z0.b-z1.b }, z0.b + +fdot za.h[w8, 0], { z0.b-z3.b }, z0.b +fdot za.h[w8, 0, VGx4], { z0.b - z3.b }, z15.b +fdot za.h[w8, 0], { z31.b-z2.b }, z0.b +fdot za.h[w8, 7], { z0.b-z3.b }, z0.b +fdot za.h[w11, 0], { z0.b-z3.b }, z0.b + +fdot za.h[w8, 0], { z0.b-z1.b }, {z0.b-z1.b } +fdot za.h[w8, 0], { z0.b - z1.b }, {z30.b - z31.b} +fdot za.h[w8, 0], { z30.b-z31.b }, {z0.b-z1.b} +fdot za.h[w8, 7], { z0.b-z1.b },{ z0.b-z1.b} +fdot za.h[w11, 0, VGx2], { z0.b-z1.b }, {z0.b-z1.b} + +fdot za.h[w8, 0], { z0.b-z3.b }, {z0.b-z3.b } +fdot za.h[w8, 0], { z0.b - z3.b }, {z28.b - z31.b} +fdot za.h[w8, 0], { z28.b-z31.b }, {z0.b-z3.b} +fdot za.h[w8, 7], { z0.b-z3.b }, {z0.b-z3.b} +fdot za.h[w11, 0, VGx4], { z0.b-z3.b }, {z0.b-z3.b} + +fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[0] +fvdot za.h[w11, 0, VGx2], {z0.b-z1.b}, z0.b[0] +fvdot za.h[w8, 7], { z0.b-z1.b }, z0.b[0] +fvdot za.h[w8, 0], {z30.b-z31.b}, z0.b[0] +fvdot za.h[w8, 0], {z0.b-z1.b}, z15.b[0] +fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[3] +fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[7] diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot4.d b/gas/testsuite/gas/aarch64/fp8-sme-dot4.d new file mode 100644 index 0000000000000000000000000000000000000000..d44280ad6cd4d34411512df64afc4a126a81b062 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-dot4.d @@ -0,0 +1,55 @@ +#as: -march=armv8-a+sme-f8f32 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: c1500038 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c15f0038 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\] + *[0-9a-f]+: c15003f8 fdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c1500c38 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\] + *[0-9a-f]+: c150003f fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1506038 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1508008 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c15f8008 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\] + *[0-9a-f]+: c1508388 fdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c1508c08 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\] + *[0-9a-f]+: c150800f fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c150e008 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c1201018 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c12f1018 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b + *[0-9a-f]+: c12013f8 fdot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b + *[0-9a-f]+: c120101f fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1207018 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1301018 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c13f1018 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b + *[0-9a-f]+: c13013f8 fdot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b + *[0-9a-f]+: c130101f fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1307018 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1a01030 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1be1030 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b} + *[0-9a-f]+: c1a013f0 fdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a01037 fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a07030 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a11030 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1bd1030 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b} + *[0-9a-f]+: c1a113b0 fdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a11037 fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a17030 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1d00800 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d06800 fvdotb za\.s\[w11, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d00807 fvdotb za\.s\[w8, 7, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d00bc0 fvdotb za\.s\[w8, 0, vgx4\], {z30\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c1df0800 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z15\.b\[0\] + *[0-9a-f]+: c1d00808 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[1\] + *[0-9a-f]+: c1d00c08 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[3\] + *[0-9a-f]+: c1d00810 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d06810 fvdott za\.s\[w11, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d00817 fvdott za\.s\[w8, 7, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1d00bd0 fvdott za\.s\[w8, 0, vgx4\], {z30\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c1df0810 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z15\.b\[0\] + *[0-9a-f]+: c1d00818 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[1\] + *[0-9a-f]+: c1d00c18 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[3\] diff --git a/gas/testsuite/gas/aarch64/fp8-sme-dot4.s b/gas/testsuite/gas/aarch64/fp8-sme-dot4.s new file mode 100644 index 0000000000000000000000000000000000000000..b405b2610e99ec65d29dc6f8c6120e80c94e742e --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-dot4.s @@ -0,0 +1,53 @@ +fdot za.s[w8, 0], { z0.b-z1.b }, z0.b[0] +fdot za.s[w8, 0], { z0.b - z1.b }, z15.b[0] +fdot za.s[w8, 0], { z30.b-z31.b }, z0.b[0] +fdot za.s[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[3] +fdot za.s[w8, 7], { z0.b-z1.b }, z0.b[0] +fdot za.s[w11, 0], { z0.b-z1.b }, z0.b[0] + +fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[0] +fdot za.s[w8, 0, VGx4], { z0.b - z3.b }, z15.b[0] +fdot za.s[w8, 0], { z28.b-z31.b }, z0.b[0] +fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[3] +fdot za.s[w8, 7], { z0.b-z3.b }, z0.b[0] +fdot za.s[w11, 0], { z0.b-z3.b }, z0.b[0] + +fdot za.s[w8, 0], { z0.b-z1.b }, z0.b +fdot za.s[w8, 0], { z0.b - z1.b }, z15.b +fdot za.s[w8, 0, VGx2], { z31.b-z0.b }, z0.b +fdot za.s[w8, 7], { z0.b-z1.b }, z0.b +fdot za.s[w11, 0], { z0.b-z1.b }, z0.b + +fdot za.s[w8, 0], { z0.b-z3.b }, z0.b +fdot za.s[w8, 0, VGx4], { z0.b - z3.b }, z15.b +fdot za.s[w8, 0], { z31.b-z2.b }, z0.b +fdot za.s[w8, 7], { z0.b-z3.b }, z0.b +fdot za.s[w11, 0], { z0.b-z3.b }, z0.b + +fdot za.s[w8, 0], { z0.b-z1.b }, {z0.b-z1.b } +fdot za.s[w8, 0], { z0.b - z1.b }, {z30.b - z31.b} +fdot za.s[w8, 0], { z30.b-z31.b }, {z0.b-z1.b} +fdot za.s[w8, 7], { z0.b-z1.b },{ z0.b-z1.b} +fdot za.s[w11, 0, VGx2], { z0.b-z1.b }, {z0.b-z1.b} + +fdot za.s[w8, 0], { z0.b-z3.b }, {z0.b-z3.b } +fdot za.s[w8, 0], { z0.b - z3.b }, {z28.b - z31.b} +fdot za.s[w8, 0], { z28.b-z31.b }, {z0.b-z3.b} +fdot za.s[w8, 7], { z0.b-z3.b }, {z0.b-z3.b} +fdot za.s[w11, 0, VGx4], { z0.b-z3.b }, {z0.b-z3.b} + +fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0] +fvdotb za.s[w11, 0, VGx4], { z0.b-z1.b }, z0.b[0] +fvdotb za.s[w8, 7, VGx4], { z0.b-z1.b }, z0.b[0] +fvdotb za.s[w8, 0, VGx4], { z30.b-z31.b }, z0.b[0] +fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z15.b[0] +fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[1] +fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[3] + +fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0] +fvdott za.s[w11, 0, VGx4], { z0.b-z1.b }, z0.b[0] +fvdott za.s[w8, 7, VGx4], { z0.b-z1.b }, z0.b[0] +fvdott za.s[w8, 0, VGx4], { z30.b-z31.b }, z0.b[0] +fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z15.b[0] +fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[1] +fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[3] diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..f5293d6d1899865d96ca22509b528142af7f4a27 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sme-f8f16 +#error_output: fp8-sme-fmlal-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..31551f97ee64afa98df80dcaecb753045d78cddf --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.l @@ -0,0 +1,72 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z16\.b\[0\]' +[^:]*:2: Error: unexpected vector group size at operand 1 -- `fmlal za\.h\[w8,0:1,VGx2\],z0\.b,z0\.b\[0\]' +[^:]*:3: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z0\.b\[16\]' +[^:]*:4: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],z0\.b,z0\.b\[0\]' +[^:]*:5: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],z0\.b,z0\.b\[0\]' +[^:]*:6: Error: immediate offset out of range 0 to 14 at operand 1 -- `fmlal za\.h\[w8,16:17\],z0\.b,z0\.b\[0\]' +[^:]*:7: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],z0\.b,z0\.b\[0\]' +[^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],z0\.b,z0\.b\[0\]' +[^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],z0\.b,z0\.b\[0\]' +[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b\[0\]' +[^:]*:12: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},z0\.b\[0\]' +[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[16\]' +[^:]*:15: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:16: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:17: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:18: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b\[0\]' +[^:]*:23: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},z0\.b\[0\]' +[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[16\]' +[^:]*:26: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:27: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:28: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:29: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z16\.b' +[^:]*:34: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],z0\.b,z0\.b' +[^:]*:35: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],z0\.b,z0\.b' +[^:]*:36: Error: immediate offset out of range 0 to 14 at operand 1 -- `fmlal za\.h\[w8,16:17\],z0\.b,z0\.b' +[^:]*:37: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],z0\.b,z0\.b' +[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],z0\.b,z0\.b' +[^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],z0\.b,z0\.b' +[^:]*:40: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0,VGx4\],z0\.b,z0\.b' +[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b' +[^:]*:43: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b' +[^:]*:44: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b' +[^:]*:45: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b' +[^:]*:46: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b' +[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b' +[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b' +[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b' +[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b' +[^:]*:52: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b' +[^:]*:53: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b' +[^:]*:54: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b' +[^:]*:55: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b' +[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},z0\.b' +[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},z0\.b' +[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b' +[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z0\.b-z3\.b}' +[^:]*:61: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z1\.b-z2\.b}' +[^:]*:62: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},{z0\.b-z1\.b}' +[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:65: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:66: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:67: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:68: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z0\.b-z1\.b}' +[^:]*:71: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z2\.b-z5\.b}' +[^:]*:72: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},{z0\.b-z3\.b}' +[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:75: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:76: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:77: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:78: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}' diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..94c4246e0987f18182669e58c4fa32a431a84562 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal-illegal.s @@ -0,0 +1,78 @@ +fmlal za.h[w8, 0:1], z0.b, z16.b[0] +fmlal za.h[w8, 0:1, VGx2], z0.b, z0.b[0] +fmlal za.h[w8, 0:1], z0.b, z0.b[16] +fmlal za.h[w8, 0], z0.b, z0.b[0] +fmlal za.h[w8, 1:2], z0.b, z0.b[0] +fmlal za.h[w8, 16:17], z0.b, z0.b[0] +fmlal za.h[w8, 0:3], z0.b, z0.b[0] +fmlal za.h[w7, 0:1], z0.b, z0.b[0] +fmlal za.h[w12, 0:1], z0.b, z0.b[0] + +fmlal za.h[w8, 0:1], { z0.b-z1.b }, z16.b[0] +fmlal za.h[w8, 0:1], { z1.b-z2.b }, z0.b[0] +fmlal za.h[w8, 0:1, VGx2], { z0.b-z3.b }, z0.b[0] +fmlal za.h[w8, 0:1], { z0.b-z1.b }, z0.b[16] +fmlal za.h[w8, 0], { z0.b-z1.b }, z0.b[0] +fmlal za.h[w8, 1:2], { z0.b-z1.b }, z0.b[0] +fmlal za.h[w8, 8:9], { z0.b-z1.b }, z0.b[0] +fmlal za.h[w8, 0:3], { z0.b-z1.b }, z0.b[0] +fmlal za.h[w7, 0:1], { z0.b-z1.b }, z0.b[0] +fmlal za.h[w12, 0:1], { z0.b-z1.b }, z0.b[0] + +fmlal za.h[w8, 0:1], { z0.b-z3.b }, z16.b[0] +fmlal za.h[w8, 0:1], { z2.b-z5.b }, z0.b[0] +fmlal za.h[w8, 0:1, VGx4], { z0.b-z1.b }, z0.b[0] +fmlal za.h[w8, 0:1], { z0.b-z3.b }, z0.b[16] +fmlal za.h[w8, 0], { z0.b-z3.b }, z0.b[0] +fmlal za.h[w8, 1:2], { z0.b-z3.b }, z0.b[0] +fmlal za.h[w8, 8:9], { z0.b-z3.b }, z0.b[0] +fmlal za.h[w8, 0:3], { z0.b-z3.b }, z0.b[0] +fmlal za.h[w7, 0], { z0.b-z3.b }, z0.b[0] +fmlal za.h[w12, 0], { z0.b-z3.b }, z0.b[0] + +fmlal za.h[w8, 0:1], z0.b, z16.b +fmlal za.h[w8, 0], z0.b, z0.b +fmlal za.h[w8, 1:2], z0.b, z0.b +fmlal za.h[w8, 16:17], z0.b, z0.b +fmlal za.h[w8, 0:3], z0.b, z0.b +fmlal za.h[w7, 0], z0.b, z0.b +fmlal za.h[w12, 0], z0.b, z0.b +fmlal za.h[w8, 0, VGx4], z0.b, z0.b + +fmlal za.h[w8, 0:1], { z0.b-z1.b }, z16.b +fmlal za.h[w8, 0], { z0.b-z1.b }, z0.b +fmlal za.h[w8, 1:2], { z0.b-z1.b }, z0.b +fmlal za.h[w8, 8:9], { z0.b-z1.b }, z0.b +fmlal za.h[w8, 0:3], { z0.b-z1.b }, z0.b +fmlal za.h[w7, 0:1], { z0.b-z1.b }, z0.b +fmlal za.h[w12, 0:1], { z0.b-z1.b }, z0.b +fmlal za.h[w8, 0:1, VGx4], { z0.b-z1.b }, z0.b + +fmlal za.h[w8, 0:1], { z0.b-z3.b }, z16.b +fmlal za.h[w8, 0], { z0.b-z3.b }, z0.b +fmlal za.h[w8, 1:2], { z0.b-z3.b }, z0.b +fmlal za.h[w8, 8:9], { z0.b-z3.b }, z0.b +fmlal za.h[w8, 0:3], { z0.b-z3.b }, z0.b +fmlal za.h[w7, 0:1], { z0.b-z3.b }, z0.b +fmlal za.h[w12, 0:1], { z0.b-z3.b }, z0.b +fmlal za.h[w8, 0:1, VGx2], { z0.b-z3.b }, z0.b + +fmlal za.h[w8, 0:1], { z0.b-z1.b }, { z0.b-z3.b} +fmlal za.h[w8, 0:1], { z0.b-z1.b }, { z1.b-z2.b} +fmlal za.h[w8, 0:1], { z1.b-z2.b }, { z0.b-z1.b} +fmlal za.h[w7, 0:1], { z0.b-z1.b }, { z0.b-z1.b} +fmlal za.h[w12, 0:1], { z0.b-z1.b }, { z0.b-z1.b} +fmlal za.h[w8, 0], { z0.b-z1.b }, { z0.b-z1.b} +fmlal za.h[w8, 1:2], { z0.b-z1.b }, { z0.b-z1.b} +fmlal za.h[w8, 8:9], { z0.b-z1.b }, { z0.b-z1.b} +fmlal za.h[w8, 0:3], { z0.b-z1.b }, { z0.b-z1.b} + +fmlal za.h[w8, 0:1], { z0.b-z3.b }, { z0.b-z1.b} +fmlal za.h[w8, 0:1], { z0.b-z3.b }, { z2.b-z5.b} +fmlal za.h[w8, 0:1], { z2.b-z5.b }, { z0.b-z3.b} +fmlal za.h[w7, 0:1], { z0.b-z3.b }, { z0.b-z3.b} +fmlal za.h[w12, 0:1], { z0.b-z3.b }, { z0.b-z3.b} +fmlal za.h[w8, 0], { z0.b-z3.b }, { z0.b-z3.b} +fmlal za.h[w8, 1:2], { z0.b-z3.b }, { z0.b-z3.b} +fmlal za.h[w8, 8:9], { z0.b-z3.b }, { z0.b-z3.b} +fmlal za.h[w8, 0:3], { z0.b-z3.b }, { z0.b-z3.b} diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.d new file mode 100644 index 0000000000000000000000000000000000000000..594570205c4e6b235c9a1c2354dbd8b56e06f5a5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.d @@ -0,0 +1,57 @@ +#as: -march=armv8-a+sme-f8f16 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: c1c00000 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[0\] + *[0-9a-f]+: c1c06000 fmlal za\.h\[w11, 0:1], z0\.b, z0\.b\[0\] + *[0-9a-f]+: c1c00007 fmlal za\.h\[w8, 14:15], z0\.b, z0\.b\[0\] + *[0-9a-f]+: c1c003e0 fmlal za\.h\[w8, 0:1], z31\.b, z0\.b\[0\] + *[0-9a-f]+: c1cf0000 fmlal za\.h\[w8, 0:1], z0\.b, z15\.b\[0\] + *[0-9a-f]+: c1c00408 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[3\] + *[0-9a-f]+: c1c08c08 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[15\] + *[0-9a-f]+: c1901030 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1907030 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1901033 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c19013f0 fmlal za\.h\[w8, 0:1, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c19f1030 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\] + *[0-9a-f]+: c1901034 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[1\] + *[0-9a-f]+: c190143c fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\] + *[0-9a-f]+: c1901c3c fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[15\] + *[0-9a-f]+: c1909020 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c190f020 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c1909023 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c19093a0 fmlal za\.h\[w8, 0:1, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c19f9020 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\] + *[0-9a-f]+: c1909024 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[1\] + *[0-9a-f]+: c190942c fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\] + *[0-9a-f]+: c1909c2c fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[15\] + *[0-9a-f]+: c1300c00 fmlal za\.h\[w8, 0:1\], z0\.b, z0\.b + *[0-9a-f]+: c1306c00 fmlal za\.h\[w11, 0:1\], z0\.b, z0\.b + *[0-9a-f]+: c1300c07 fmlal za\.h\[w8, 14:15\], z0\.b, z0\.b + *[0-9a-f]+: c1300fe0 fmlal za\.h\[w8, 0:1\], z31\.b, z0\.b + *[0-9a-f]+: c13f0c00 fmlal za\.h\[w8, 0:1\], z0\.b, z15\.b + *[0-9a-f]+: c1200804 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1206804 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1200807 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1200be4 fmlal za\.h\[w8, 0:1, vgx2\], {z31\.b-z0\.b}, z0\.b + *[0-9a-f]+: c12f0804 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z15\.b + *[0-9a-f]+: c1300804 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1306804 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1300807 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1300be4 fmlal za\.h\[w8, 0:1, vgx4\], {z31\.b-z2\.b}, z0\.b + *[0-9a-f]+: c13f0804 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z15\.b + *[0-9a-f]+: c1a00820 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a06820 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a00823 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a00be0 fmlal za\.h\[w8, 0:1, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1be0820 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b} + *[0-9a-f]+: c1a10820 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a16820 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a10823 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a10ba0 fmlal za\.h\[w8, 0:1, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1bd0820 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b} diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlal.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.s new file mode 100644 index 0000000000000000000000000000000000000000..5455f9e567124c80decbbdd7efad089813134231 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlal.s @@ -0,0 +1,56 @@ +fmlal za.h[w8, 0:1], z0.b, z0.b[0] +fmlal za.h[w11, 0:1], z0.b, z0.b[0] +fmlal za.h[w8, 14:15], z0.b, z0.b[0] +fmlal za.h[w8, 0:1], z31.b, z0.b[0] +fmlal za.h[w8, 0:1], z0.b, z15.b[0] +fmlal za.h[w8, 0:1], z0.b, z0.b[3] +fmlal za.h[w8, 0:1], z0.b, z0.b[15] + +fmlal za.h[w8, 0:1], {z0.b-z1.b }, z0.b[0] +fmlal za.h[w11, 0:1, VGx2], { z0.b-z1.b}, z0.b[0] +fmlal za.h[w8, 6:7], {z0.b - z1.b}, z0.b[0] +fmlal za.h[w8, 0:1], { z30.b-z31.b}, z0.b[0] +fmlal za.h[w8, 0:1], { z0.b - z1.b}, z15.b[0] +fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[1] +fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[7] +fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[15] + +fmlal za.h[w8, 0:1], {z0.b-z3.b }, z0.b[0] +fmlal za.h[w11, 0:1, VGx4], { z0.b-z3.b}, z0.b[0] +fmlal za.h[w8, 6:7], {z0.b - z3.b}, z0.b[0] +fmlal za.h[w8, 0:1], { z28.b-z31.b}, z0.b[0] +fmlal za.h[w8, 0:1], { z0.b - z3.b}, z15.b[0] +fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[1] +fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[7] +fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[15] + +fmlal za.h[w8, 0:1], z0.b, z0.b +fmlal za.h[w11, 0:1], z0.b, z0.b +fmlal za.h[w8, 14:15], z0.b, z0.b +fmlal za.h[w8, 0:1], z31.b, z0.b +fmlal za.h[w8, 0:1], z0.b, z15.b + +fmlal za.h[w8, 0:1], {z0.b -z1.b}, z0.b +fmlal za.h[w11, 0:1], {z0.b-z1.b}, z0.b +fmlal za.h[w8, 6:7], { z0.b - z1.b }, z0.b +fmlal za.h[w8, 0:1, VGx2], {z31.b - z0.b}, z0.b +fmlal za.h[w8, 0:1], {z0.b - z1.b}, z15.b + +fmlal za.h[w8, 0:1], {z0.b -z3.b}, z0.b +fmlal za.h[w11, 0:1], {z0.b-z3.b}, z0.b +fmlal za.h[w8, 6:7], { z0.b - z3.b }, z0.b +fmlal za.h[w8, 0:1, VGx4], {z31.b - z2.b}, z0.b +fmlal za.h[w8, 0:1], {z0.b - z3.b}, z15.b + +fmlal za.h[w8, 0:1], {z0.b -z1.b}, {z0.b-z1.b} +fmlal za.h[w11, 0:1], {z0.b-z1.b}, {z0.b - z1.b} +fmlal za.h[w8, 6:7], { z0.b - z1.b }, {z0.b -z1.b} +fmlal za.h[w8, 0:1, VGx2], {z30.b - z31.b}, {z0.b-z1.b} +fmlal za.h[w8, 0:1], {z0.b - z1.b}, {z30.b -z31.b} + +fmlal za.h[w8, 0:1], {z0.b -z3.b}, {z0.b-z3.b} +fmlal za.h[w11, 0:1], {z0.b-z3.b}, {z0.b - z3.b} +fmlal za.h[w8, 6:7], { z0.b - z3.b }, {z0.b-z3.b} +fmlal za.h[w8, 0:1, VGx4], {z28.b - z31.b}, {z0.b-z3.b} +fmlal za.h[w8, 0:1], {z0.b - z3.b}, {z28.b-z31.b} + diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..b0d20198a648a9a8adb842cbf6d46ef425cd0947 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sme-f8f32 +#error_output: fp8-sme-fmlall-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..12ffda0ad2b2288fc9af1837f7a872dd4038e041 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.l @@ -0,0 +1,72 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z16\.b\[0\]' +[^:]*:2: Error: unexpected vector group size at operand 1 -- `fmlall za\.s\[w8,0:3,VGx2\],z0\.b,z0\.b\[0\]' +[^:]*:3: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z0\.b\[16\]' +[^:]*:4: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],z0\.b,z0\.b\[0\]' +[^:]*:5: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],z0\.b,z0\.b\[0\]' +[^:]*:6: Error: immediate offset out of range 0 to 12 at operand 1 -- `fmlall za\.s\[w8,16:19\],z0\.b,z0\.b\[0\]' +[^:]*:7: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],z0\.b,z0\.b\[0\]' +[^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],z0\.b,z0\.b\[0\]' +[^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],z0\.b,z0\.b\[0\]' +[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b\[0\]' +[^:]*:12: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},z0\.b\[0\]' +[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[16\]' +[^:]*:15: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:16: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:17: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:18: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b\[0\]' +[^:]*:23: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z2\.b-z5\.b},z0\.b\[0\]' +[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]' +[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[16\]' +[^:]*:26: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:27: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:28: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:29: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]' +[^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z16\.b' +[^:]*:34: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],z0\.b,z0\.b' +[^:]*:35: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],z0\.b,z0\.b' +[^:]*:36: Error: immediate offset out of range 0 to 12 at operand 1 -- `fmlall za\.s\[w8,16:19\],z0\.b,z0\.b' +[^:]*:37: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],z0\.b,z0\.b' +[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],z0\.b,z0\.b' +[^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],z0\.b,z0\.b' +[^:]*:40: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0,VGx4\],z0\.b,z0\.b' +[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b' +[^:]*:43: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b' +[^:]*:44: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b' +[^:]*:45: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b' +[^:]*:46: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b' +[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b' +[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b' +[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b' +[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b' +[^:]*:52: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b' +[^:]*:53: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b' +[^:]*:54: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b' +[^:]*:55: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b' +[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z3\.b},z0\.b' +[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z3\.b},z0\.b' +[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b' +[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z3\.b}' +[^:]*:61: Error: start register out of range at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z1\.b-z2\.b}' +[^:]*:62: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},{z0\.b-z1\.b}' +[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:65: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:66: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:67: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:68: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}' +[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},{z0\.b-z1\.b}' +[^:]*:71: Error: start register out of range at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},{z2\.b-z5\.b}' +[^:]*:72: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z2\.b-z5\.b},{z0\.b-z3\.b}' +[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:75: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:76: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:77: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},{z0\.b-z3\.b}' +[^:]*:78: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}' diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..9d4f36a5db52455cf3e72278bb9e9198e3b722dc --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall-illegal.s @@ -0,0 +1,78 @@ +fmlall za.s[w8, 0:3], z0.b, z16.b[0] +fmlall za.s[w8, 0:3, VGx2], z0.b, z0.b[0] +fmlall za.s[w8, 0:3], z0.b, z0.b[16] +fmlall za.s[w8, 0], z0.b, z0.b[0] +fmlall za.s[w8, 2:5], z0.b, z0.b[0] +fmlall za.s[w8, 16:19], z0.b, z0.b[0] +fmlall za.s[w8, 0:1], z0.b, z0.b[0] +fmlall za.s[w7, 0:3], z0.b, z0.b[0] +fmlall za.s[w12, 0:3], z0.b, z0.b[0] + +fmlall za.s[w8, 0:3], { z0.b-z1.b }, z16.b[0] +fmlall za.s[w8, 0:3], { z1.b-z2.b }, z0.b[0] +fmlall za.s[w8, 0:3, VGx2], { z0.b-z3.b }, z0.b[0] +fmlall za.s[w8, 0:3], { z0.b-z1.b }, z0.b[16] +fmlall za.s[w8, 0], { z0.b-z1.b }, z0.b[0] +fmlall za.s[w8, 2:5], { z0.b-z1.b }, z0.b[0] +fmlall za.s[w8, 8:11], { z0.b-z1.b }, z0.b[0] +fmlall za.s[w8, 0:1], { z0.b-z1.b }, z0.b[0] +fmlall za.s[w7, 0:3], { z0.b-z1.b }, z0.b[0] +fmlall za.s[w12, 0:3], { z0.b-z1.b }, z0.b[0] + +fmlall za.s[w8, 0:3], { z0.b-z3.b }, z16.b[0] +fmlall za.s[w8, 0:3], { z2.b-z5.b }, z0.b[0] +fmlall za.s[w8, 0:3, VGx4], { z0.b-z1.b }, z0.b[0] +fmlall za.s[w8, 0:3], { z0.b-z3.b }, z0.b[16] +fmlall za.s[w8, 0], { z0.b-z3.b }, z0.b[0] +fmlall za.s[w8, 2:5], { z0.b-z3.b }, z0.b[0] +fmlall za.s[w8, 8:11], { z0.b-z3.b }, z0.b[0] +fmlall za.s[w8, 0:1], { z0.b-z3.b }, z0.b[0] +fmlall za.s[w7, 0], { z0.b-z3.b }, z0.b[0] +fmlall za.s[w12, 0], { z0.b-z3.b }, z0.b[0] + +fmlall za.s[w8, 0:3], z0.b, z16.b +fmlall za.s[w8, 0], z0.b, z0.b +fmlall za.s[w8, 2:5], z0.b, z0.b +fmlall za.s[w8, 16:19], z0.b, z0.b +fmlall za.s[w8, 0:1], z0.b, z0.b +fmlall za.s[w7, 0], z0.b, z0.b +fmlall za.s[w12, 0], z0.b, z0.b +fmlall za.s[w8, 0, VGx4], z0.b, z0.b + +fmlall za.s[w8, 0:3], { z0.b-z1.b }, z16.b +fmlall za.s[w8, 0], { z0.b-z1.b }, z0.b +fmlall za.s[w8, 2:5], { z0.b-z1.b }, z0.b +fmlall za.s[w8, 8:11], { z0.b-z1.b }, z0.b +fmlall za.s[w8, 0:1], { z0.b-z1.b }, z0.b +fmlall za.s[w7, 0:3], { z0.b-z1.b }, z0.b +fmlall za.s[w12, 0:3], { z0.b-z1.b }, z0.b +fmlall za.s[w8, 0:3, VGx4], { z0.b-z1.b }, z0.b + +fmlall za.s[w8, 0:3], { z0.b-z3.b }, z16.b +fmlall za.s[w8, 0], { z0.b-z3.b }, z0.b +fmlall za.s[w8, 2:5], { z0.b-z3.b }, z0.b +fmlall za.s[w8, 8:11], { z0.b-z3.b }, z0.b +fmlall za.s[w8, 0:1], { z0.b-z3.b }, z0.b +fmlall za.s[w7, 0:3], { z0.b-z3.b }, z0.b +fmlall za.s[w12, 0:3], { z0.b-z3.b }, z0.b +fmlall za.s[w8, 0:3, VGx2], { z0.b-z3.b }, z0.b + +fmlall za.s[w8, 0:3], { z0.b-z1.b }, { z0.b-z3.b} +fmlall za.s[w8, 0:3], { z0.b-z1.b }, { z1.b-z2.b} +fmlall za.s[w8, 0:3], { z1.b-z2.b }, { z0.b-z1.b} +fmlall za.s[w7, 0:3], { z0.b-z1.b }, { z0.b-z1.b} +fmlall za.s[w12, 0:3], { z0.b-z1.b }, { z0.b-z1.b} +fmlall za.s[w8, 0], { z0.b-z1.b }, { z0.b-z1.b} +fmlall za.s[w8, 2:5], { z0.b-z1.b }, { z0.b-z1.b} +fmlall za.s[w8, 8:11], { z0.b-z1.b }, { z0.b-z1.b} +fmlall za.s[w8, 0:1], { z0.b-z1.b }, { z0.b-z1.b} + +fmlall za.s[w8, 0:3], { z0.b-z3.b }, { z0.b-z1.b} +fmlall za.s[w8, 0:3], { z0.b-z3.b }, { z2.b-z5.b} +fmlall za.s[w8, 0:3], { z2.b-z5.b }, { z0.b-z3.b} +fmlall za.s[w7, 0:3], { z0.b-z3.b }, { z0.b-z3.b} +fmlall za.s[w12, 0:3], { z0.b-z3.b }, { z0.b-z3.b} +fmlall za.s[w8, 0], { z0.b-z3.b }, { z0.b-z3.b} +fmlall za.s[w8, 2:5], { z0.b-z3.b }, { z0.b-z3.b} +fmlall za.s[w8, 8:11], { z0.b-z3.b }, { z0.b-z3.b} +fmlall za.s[w8, 0:1], { z0.b-z3.b }, { z0.b-z3.b} diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall.d b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.d new file mode 100644 index 0000000000000000000000000000000000000000..a87d1345a907e77abdcb556fd887d2f42ff04e42 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.d @@ -0,0 +1,57 @@ +#as: -march=armv8-a+sme-f8f32 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: c1400000 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[0\] + *[0-9a-f]+: c1406000 fmlall za\.s\[w11, 0:3], z0\.b, z0\.b\[0\] + *[0-9a-f]+: c1400003 fmlall za\.s\[w8, 12:15], z0\.b, z0\.b\[0\] + *[0-9a-f]+: c14003e0 fmlall za\.s\[w8, 0:3], z31\.b, z0\.b\[0\] + *[0-9a-f]+: c14f0000 fmlall za\.s\[w8, 0:3], z0\.b, z15\.b\[0\] + *[0-9a-f]+: c1400c00 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[3\] + *[0-9a-f]+: c1409c00 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[15\] + *[0-9a-f]+: c1900020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1906020 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c1900021 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\] + *[0-9a-f]+: c19003e0 fmlall za\.s\[w8, 0:3, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c19f0020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\] + *[0-9a-f]+: c1900022 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[1\] + *[0-9a-f]+: c1900426 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\] + *[0-9a-f]+: c1900c26 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[15\] + *[0-9a-f]+: c1108040 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c110e040 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c1108041 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\] + *[0-9a-f]+: c11083c0 fmlall za\.s\[w8, 0:3, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\] + *[0-9a-f]+: c11f8040 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\] + *[0-9a-f]+: c1108042 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[1\] + *[0-9a-f]+: c1108446 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\] + *[0-9a-f]+: c1108c46 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[15\] + *[0-9a-f]+: c1300400 fmlall za\.s\[w8, 0:3\], z0\.b, z0\.b + *[0-9a-f]+: c1306400 fmlall za\.s\[w11, 0:3\], z0\.b, z0\.b + *[0-9a-f]+: c1300403 fmlall za\.s\[w8, 12:15\], z0\.b, z0\.b + *[0-9a-f]+: c13007e0 fmlall za\.s\[w8, 0:3\], z31\.b, z0\.b + *[0-9a-f]+: c13f0400 fmlall za\.s\[w8, 0:3\], z0\.b, z15\.b + *[0-9a-f]+: c1200002 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1206002 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c1200003 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, z0\.b + *[0-9a-f]+: c12003e2 fmlall za\.s\[w8, 0:3, vgx2\], {z31\.b-z0\.b}, z0\.b + *[0-9a-f]+: c12f0002 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z15\.b + *[0-9a-f]+: c1300002 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1306002 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c1300003 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, z0\.b + *[0-9a-f]+: c13003e2 fmlall za\.s\[w8, 0:3, vgx4\], {z31\.b-z2\.b}, z0\.b + *[0-9a-f]+: c13f0002 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z15\.b + *[0-9a-f]+: c1a00020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a06020 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a00021 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1a003e0 fmlall za\.s\[w8, 0:3, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b} + *[0-9a-f]+: c1be0020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b} + *[0-9a-f]+: c1a10020 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a16020 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a10021 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1a103a0 fmlall za\.s\[w8, 0:3, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b} + *[0-9a-f]+: c1bd0020 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b} diff --git a/gas/testsuite/gas/aarch64/fp8-sme-fmlall.s b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.s new file mode 100644 index 0000000000000000000000000000000000000000..a0fa3a4f97fc787b457f50168b534c4154cd424e --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-fmlall.s @@ -0,0 +1,56 @@ +fmlall za.s[w8, 0:3], z0.b, z0.b[0] +fmlall za.s[w11, 0:3], z0.b, z0.b[0] +fmlall za.s[w8, 12:15], z0.b, z0.b[0] +fmlall za.s[w8, 0:3], z31.b, z0.b[0] +fmlall za.s[w8, 0:3], z0.b, z15.b[0] +fmlall za.s[w8, 0:3], z0.b, z0.b[3] +fmlall za.s[w8, 0:3], z0.b, z0.b[15] + +fmlall za.s[w8, 0:3], {z0.b-z1.b }, z0.b[0] +fmlall za.s[w11, 0:3, VGx2], { z0.b-z1.b}, z0.b[0] +fmlall za.s[w8, 4:7], {z0.b - z1.b}, z0.b[0] +fmlall za.s[w8, 0:3], { z30.b-z31.b}, z0.b[0] +fmlall za.s[w8, 0:3], { z0.b - z1.b}, z15.b[0] +fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[1] +fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[7] +fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[15] + +fmlall za.s[w8, 0:3], {z0.b-z3.b }, z0.b[0] +fmlall za.s[w11, 0:3, VGx4], { z0.b-z3.b}, z0.b[0] +fmlall za.s[w8, 4:7], {z0.b - z3.b}, z0.b[0] +fmlall za.s[w8, 0:3], { z28.b-z31.b}, z0.b[0] +fmlall za.s[w8, 0:3], { z0.b - z3.b}, z15.b[0] +fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[1] +fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[7] +fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[15] + +fmlall za.s[w8, 0:3], z0.b, z0.b +fmlall za.s[w11, 0:3], z0.b, z0.b +fmlall za.s[w8, 12:15], z0.b, z0.b +fmlall za.s[w8, 0:3], z31.b, z0.b +fmlall za.s[w8, 0:3], z0.b, z15.b + +fmlall za.s[w8, 0:3], {z0.b -z1.b}, z0.b +fmlall za.s[w11, 0:3], {z0.b-z1.b}, z0.b +fmlall za.s[w8, 4:7], { z0.b - z1.b }, z0.b +fmlall za.s[w8, 0:3, VGx2], {z31.b - z0.b}, z0.b +fmlall za.s[w8, 0:3], {z0.b - z1.b}, z15.b + +fmlall za.s[w8, 0:3], {z0.b -z3.b}, z0.b +fmlall za.s[w11, 0:3], {z0.b-z3.b}, z0.b +fmlall za.s[w8, 4:7], { z0.b - z3.b }, z0.b +fmlall za.s[w8, 0:3, VGx4], {z31.b - z2.b}, z0.b +fmlall za.s[w8, 0:3], {z0.b - z3.b}, z15.b + +fmlall za.s[w8, 0:3], {z0.b -z1.b}, {z0.b-z1.b} +fmlall za.s[w11, 0:3], {z0.b-z1.b}, {z0.b - z1.b} +fmlall za.s[w8, 4:7], { z0.b - z1.b }, {z0.b -z1.b} +fmlall za.s[w8, 0:3, VGx2], {z30.b - z31.b}, {z0.b-z1.b} +fmlall za.s[w8, 0:3], {z0.b - z1.b}, {z30.b -z31.b} + +fmlall za.s[w8, 0:3], {z0.b -z3.b}, {z0.b-z3.b} +fmlall za.s[w11, 0:3], {z0.b-z3.b}, {z0.b - z3.b} +fmlall za.s[w8, 4:7], { z0.b - z3.b }, {z0.b-z3.b} +fmlall za.s[w8, 0:3, VGx4], {z28.b - z31.b}, {z0.b-z3.b} +fmlall za.s[w8, 0:3], {z0.b - z3.b}, {z28.b-z31.b} + diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.d b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..38b71a726d634c0b72837f101ecf42481a3d8005 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sme-f8f16 +#error_output: fp8-sme-mopa-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.l b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..47f3765c0724c28c0e0613c15d97da0b3734e63d --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.l @@ -0,0 +1,7 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: ZA tile number out of range at operand 1 -- `fmopa za2\.h,p0/m,p0/m,z0\.b,z0\.b' +[^:]*:2: Error: p0-p7 expected at operand 2 -- `fmopa za0\.h,p8/m,p0/m,z0\.b,z0\.b' +[^:]*:3: Error: p0-p7 expected at operand 3 -- `fmopa za0\.h,p0/m,p8/m,z0\.b,z0\.b' +[^:]*:5: Error: ZA tile number out of range at operand 1 -- `fmopa za4\.s,p0/m,p0/m,z0\.b,z0\.b' +[^:]*:6: Error: p0-p7 expected at operand 2 -- `fmopa za0\.s,p8/m,p0/m,z0\.b,z0\.b' +[^:]*:7: Error: p0-p7 expected at operand 3 -- `fmopa za0\.s,p0/m,p8/m,z0\.b,z0\.b' diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.s b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..3c0122eb40bab627550cc409bfe4691a1c805c15 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa-illegal.s @@ -0,0 +1,7 @@ +fmopa za2.h, p0/m, p0/m, z0.b, z0.b +fmopa za0.h, p8/m, p0/m, z0.b, z0.b +fmopa za0.h, p0/m, p8/m, z0.b, z0.b + +fmopa za4.s, p0/m, p0/m, z0.b, z0.b +fmopa za0.s, p8/m, p0/m, z0.b, z0.b +fmopa za0.s, p0/m, p8/m, z0.b, z0.b diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa2.d b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.d new file mode 100644 index 0000000000000000000000000000000000000000..c27ff5b6482a223b538591936fe7c3d03ef800b6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.d @@ -0,0 +1,15 @@ +#as: -march=armv8-a+sme-f8f16 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 80a00008 fmopa za0\.h, p0/m, p0/m, z0\.b, z0\.b + *[0-9a-f]+: 80a00009 fmopa za1\.h, p0/m, p0/m, z0\.b, z0\.b + *[0-9a-f]+: 80a01c08 fmopa za0\.h, p7/m, p0/m, z0\.b, z0\.b + *[0-9a-f]+: 80a0e008 fmopa za0\.h, p0/m, p7/m, z0\.b, z0\.b + *[0-9a-f]+: 80a003e8 fmopa za0\.h, p0/m, p0/m, z31\.b, z0\.b + *[0-9a-f]+: 80bf0008 fmopa za0\.h, p0/m, p0/m, z0\.b, z31\.b diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa2.s b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.s new file mode 100644 index 0000000000000000000000000000000000000000..0fa8622cb36669167a6a3b82ff48dce617358e3c --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa2.s @@ -0,0 +1,6 @@ +fmopa za0.h, p0/m, p0/m, z0.b, z0.b +fmopa za1.h, p0/m, p0/m, z0.b, z0.b +fmopa za0.h, p7/m, p0/m, z0.b, z0.b +fmopa za0.h, p0/m, p7/m, z0.b, z0.b +fmopa za0.h, p0/m, p0/m, z31.b, z0.b +fmopa za0.h, p0/m, p0/m, z0.b, z31.b diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa4.d b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.d new file mode 100644 index 0000000000000000000000000000000000000000..c7448e6c165e9d1162123be4d578cabe6e8cf01e --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.d @@ -0,0 +1,15 @@ +#as: -march=armv8-a+sme-f8f32 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 80a00000 fmopa za0\.s, p0/m, p0/m, z0\.b, z0\.b + *[0-9a-f]+: 80a00003 fmopa za3\.s, p0/m, p0/m, z0\.b, z0\.b + *[0-9a-f]+: 80a01c00 fmopa za0\.s, p7/m, p0/m, z0\.b, z0\.b + *[0-9a-f]+: 80a0e000 fmopa za0\.s, p0/m, p7/m, z0\.b, z0\.b + *[0-9a-f]+: 80a003e0 fmopa za0\.s, p0/m, p0/m, z31\.b, z0\.b + *[0-9a-f]+: 80bf0000 fmopa za0\.s, p0/m, p0/m, z0\.b, z31\.b diff --git a/gas/testsuite/gas/aarch64/fp8-sme-mopa4.s b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.s new file mode 100644 index 0000000000000000000000000000000000000000..e68c7562b56e58ce8ae3a2fac8cf5007e46a9578 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sme-mopa4.s @@ -0,0 +1,6 @@ +fmopa za0.s, p0/m, p0/m, z0.b, z0.b +fmopa za3.s, p0/m, p0/m, z0.b, z0.b +fmopa za0.s, p7/m, p0/m, z0.b, z0.b +fmopa za0.s, p0/m, p7/m, z0.b, z0.b +fmopa za0.s, p0/m, p0/m, z31.b, z0.b +fmopa za0.s, p0/m, p0/m, z0.b, z31.b diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.d b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.d new file mode 100644 index 0000000000000000000000000000000000000000..4dcdeb7458d45509afc79f2f135d0cdb040a6edd --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sme-f8f16 +#error_output: sme-fp16-addsub-illegal.l diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.l b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.l new file mode 100644 index 0000000000000000000000000000000000000000..b35c7c98b4064a30164a23ce23557906b75f822a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.l @@ -0,0 +1,19 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w7,0\],{z0\.h-z1\.h}' +[^:]*:2: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w12,0\],{z0\.h-z1\.h}' +[^:]*:3: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.h\[w8,8\],{z0\.h-z1\.h}' +[^:]*:4: Error: start register out of range at operand 2 -- `fadd za\.h\[w8,0\],{z1\.h-z2\.h}' +[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w7,0\],{z0\.h-z3\.h}' +[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w12,0\],{z0\.h-z3\.h}' +[^:]*:8: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.h\[w8,8\],{z0\.h-z3\.h}' +[^:]*:9: Error: start register out of range at operand 2 -- `fadd za\.h\[w8,0\],{z2\.h-z5\.h}' +[^:]*:11: Error: missing braces at operand 2 -- `fadd za\.h\[w0,0\],z0\.h' +[^:]*:13: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w7,0\],{z0\.h-z1\.h}' +[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w12,0\],{z0\.h-z1\.h}' +[^:]*:15: Error: immediate offset out of range 0 to 7 at operand 1 -- `fsub za\.h\[w8,8\],{z0\.h-z1\.h}' +[^:]*:16: Error: start register out of range at operand 2 -- `fsub za\.h\[w8,0\],{z1\.h-z2\.h}' +[^:]*:18: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w7,0\],{z0\.h-z3\.h}' +[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w12,0\],{z0\.h-z3\.h}' +[^:]*:20: Error: immediate offset out of range 0 to 7 at operand 1 -- `fsub za\.h\[w8,8\],{z0\.h-z3\.h}' +[^:]*:21: Error: start register out of range at operand 2 -- `fsub za\.h\[w8,0\],{z2\.h-z5\.h}' +[^:]*:23: Error: missing braces at operand 2 -- `fsub za\.h\[w0,0\],z0\.h' diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.s b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.s new file mode 100644 index 0000000000000000000000000000000000000000..0244546120219982247103078eaf31d13777a22d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub-illegal.s @@ -0,0 +1,24 @@ +fadd za.h[w7, 0], {z0.h-z1.h} +fadd za.h[w12, 0], {z0.h-z1.h} +fadd za.h[w8, 8], {z0.h-z1.h} +fadd za.h[w8, 0], {z1.h-z2.h} + +fadd za.h[w7, 0], {z0.h-z3.h} +fadd za.h[w12, 0], {z0.h-z3.h} +fadd za.h[w8, 8], {z0.h-z3.h} +fadd za.h[w8, 0], {z2.h-z5.h} + +fadd za.h[w0, 0], z0.h + +fsub za.h[w7, 0], {z0.h-z1.h} +fsub za.h[w12, 0], {z0.h-z1.h} +fsub za.h[w8, 8], {z0.h-z1.h} +fsub za.h[w8, 0], {z1.h-z2.h} + +fsub za.h[w7, 0], {z0.h-z3.h} +fsub za.h[w12, 0], {z0.h-z3.h} +fsub za.h[w8, 8], {z0.h-z3.h} +fsub za.h[w8, 0], {z2.h-z5.h} + +fsub za.h[w0, 0], z0.h + diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub.d b/gas/testsuite/gas/aarch64/sme-fp16-addsub.d new file mode 100644 index 0000000000000000000000000000000000000000..81d8f2ed22773ca6915e5b2b12a6bdaeb18726d8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub.d @@ -0,0 +1,25 @@ +#as: -march=armv8-a+sme-f8f16 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: c1a41c00 fadd za\.h\[w8, 0, vgx2\], {z0\.h-z1\.h} + *[0-9a-f]+: c1a47c00 fadd za\.h\[w11, 0, vgx2\], {z0\.h-z1\.h} + *[0-9a-f]+: c1a41c07 fadd za\.h\[w8, 7, vgx2\], {z0\.h-z1\.h} + *[0-9a-f]+: c1a41fc0 fadd za\.h\[w8, 0, vgx2\], {z30\.h-z31\.h} + *[0-9a-f]+: c1a51c00 fadd za\.h\[w8, 0, vgx4\], {z0\.h-z3\.h} + *[0-9a-f]+: c1a57c00 fadd za\.h\[w11, 0, vgx4\], {z0\.h-z3\.h} + *[0-9a-f]+: c1a51c07 fadd za\.h\[w8, 7, vgx4\], {z0\.h-z3\.h} + *[0-9a-f]+: c1a51f80 fadd za\.h\[w8, 0, vgx4\], {z28\.h-z31\.h} + *[0-9a-f]+: c1a41c08 fsub za\.h\[w8, 0, vgx2\], {z0\.h-z1\.h} + *[0-9a-f]+: c1a47c08 fsub za\.h\[w11, 0, vgx2\], {z0\.h-z1\.h} + *[0-9a-f]+: c1a41c0f fsub za\.h\[w8, 7, vgx2\], {z0\.h-z1\.h} + *[0-9a-f]+: c1a41fc8 fsub za\.h\[w8, 0, vgx2\], {z30\.h-z31\.h} + *[0-9a-f]+: c1a51c08 fsub za\.h\[w8, 0, vgx4\], {z0\.h-z3\.h} + *[0-9a-f]+: c1a57c08 fsub za\.h\[w11, 0, vgx4\], {z0\.h-z3\.h} + *[0-9a-f]+: c1a51c0f fsub za\.h\[w8, 7, vgx4\], {z0\.h-z3\.h} + *[0-9a-f]+: c1a51f88 fsub za\.h\[w8, 0, vgx4\], {z28\.h-z31\.h} diff --git a/gas/testsuite/gas/aarch64/sme-fp16-addsub.s b/gas/testsuite/gas/aarch64/sme-fp16-addsub.s new file mode 100644 index 0000000000000000000000000000000000000000..ae64131b2f1ca207d24ef2e16ae9b57c17922fd6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-fp16-addsub.s @@ -0,0 +1,19 @@ +fadd za.h[w8, 0], {z0.h-z1.h} +fadd za.h[w11, 0], {z0.h-z1.h} +fadd za.h[w8, 7], {z0.h-z1.h} +fadd za.h[w8, 0], {z30.h-z31.h} + +fadd za.h[w8, 0], {z0.h-z3.h} +fadd za.h[w11, 0], {z0.h-z3.h} +fadd za.h[w8, 7], {z0.h-z3.h} +fadd za.h[w8, 0], {z28.h-z31.h} + +fsub za.h[w8, 0], {z0.h-z1.h} +fsub za.h[w11, 0], {z0.h-z1.h} +fsub za.h[w8, 7], {z0.h-z1.h} +fsub za.h[w8, 0], {z30.h-z31.h} + +fsub za.h[w8, 0], {z0.h-z3.h} +fsub za.h[w11, 0], {z0.h-z3.h} +fsub za.h[w8, 7], {z0.h-z3.h} +fsub za.h[w8, 0], {z28.h-z31.h} diff --git a/gas/testsuite/gas/aarch64/sme2-18-invalid.l b/gas/testsuite/gas/aarch64/sme2-18-invalid.l index 6a1b77a14942ebd8dc1214d07ba0e0a78a361bb5..ea824cbcf4c259736df63ace4baae3216e56be52 100644 --- a/gas/testsuite/gas/aarch64/sme2-18-invalid.l +++ b/gas/testsuite/gas/aarch64/sme2-18-invalid.l @@ -6,7 +6,7 @@ [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `fvdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h' [^ :]+:[0-9]+: Error: operand mismatch -- `fvdot za\.s\[w8,0\],{z0\.b-z1\.h},z0\.b\[0\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: fvdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\] +[^ :]+:[0-9]+: Info: fvdot za\.h\[w8, 0\], {z0\.b-z1\.b}, z0\.b\[0\] [^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fvdot za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' [^ :]+:[0-9]+: Error: operand 1 must have a vector group size of 2 -- `fvdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]' [^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.s\[w7,0\],{z0\.h-z1\.h},z0\.h\[0\]' diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.l b/gas/testsuite/gas/aarch64/sme2-9-invalid.l index e181f0b73788772178a701e3814235d7d005b9a3..0063e94074203a2151e16a0073a415e2e8642869 100644 --- a/gas/testsuite/gas/aarch64/sme2-9-invalid.l +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.l @@ -172,8 +172,4 @@ [^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} [^ :]+:[0-9]+: Info: other valid variant\(s\): [^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} -[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.h\[w8,0\],{z0\.h-z1\.h}' -[^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} -[^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.h\[w8,0\],{z0\.h-z1\.h}' diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index f2bf994c23651af969f9a37f06144f5e31171519..03e13bfd936ea934557b54ab79639830175027ef 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -252,6 +252,10 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SSVE_FP8DOT4, /* SSVE FP8DOT2 instructions. */ AARCH64_FEATURE_SSVE_FP8DOT2, + /* SME F8F32 instructions. */ + AARCH64_FEATURE_SME_F8F32, + /* SME F8F16 instructions. */ + AARCH64_FEATURE_SME_F8F16, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -261,6 +265,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FP8DOT4_SVE, /* +fp8dot2+sve or +ssve-fp8dot2 */ AARCH64_FEATURE_FP8DOT2_SVE, + /* +sme-f16f16 or +sme-f8f16 */ + AARCH64_FEATURE_SME_F16F16_F8F16, AARCH64_NUM_FEATURES }; @@ -790,6 +796,7 @@ enum aarch64_opnd AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */ AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */ + AARCH64_OPND_SME_ZAda_1b, /* SME .H, 1-bits. */ AARCH64_OPND_SME_ZAda_2b, /* SME .S, 2-bits. */ AARCH64_OPND_SME_ZAda_3b, /* SME .D, 3-bits. */ AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ @@ -820,10 +827,14 @@ enum aarch64_opnd AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */ AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ + AARCH64_OPND_SME_Zm_INDEX2_3, /* Zn.T[index], bits [19:16,10,3]. */ AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */ AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */ + AARCH64_OPND_SME_Zm_INDEX3_3, /* Zn.T[index], bits [19:16,11:10,3]. */ AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */ AARCH64_OPND_SME_Zm_INDEX4_1, /* Zn.T[index], bits [19:16,11:10,2:1]. */ + AARCH64_OPND_SME_Zm_INDEX4_2, /* Zn.T[index], bits [19:16,11:10,3:2]. */ + AARCH64_OPND_SME_Zm_INDEX4_3, /* Zn.T[index], bits [19:16,15,11,10,3]. */ AARCH64_OPND_SME_Zm_INDEX4_10, /* Zn.T[index], bits [19:16,15,12:10]. */ AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 3136e62375c5b9ce13a4abbf097104af2264b0f9..3cc46ec0b20c6db9a508cb800017b30b73942c16 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -60,6 +60,7 @@ enum aarch64_field_kind FLD_SME_V, FLD_SME_VL_10, FLD_SME_VL_13, + FLD_SME_ZAda_1b, FLD_SME_ZAda_2b, FLD_SME_ZAda_3b, FLD_SME_Zdn2, @@ -150,6 +151,7 @@ enum aarch64_field_kind FLD_hw, FLD_imm1_0, FLD_imm1_2, + FLD_imm1_3, FLD_imm1_8, FLD_imm1_10, FLD_imm1_14, @@ -157,6 +159,7 @@ enum aarch64_field_kind FLD_imm1_16, FLD_imm2_0, FLD_imm2_1, + FLD_imm2_2, FLD_imm2_8, FLD_imm2_10, FLD_imm2_12, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 903d3578c2a6822807908ba8a8c53d8de54c96bf..47967303e0645c5fcea952a586170e93df21aa0a 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -256,6 +256,7 @@ const aarch64_field fields[] = { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ { 10, 1 }, /* SME_VL_10: VLx2 or VLx4, bit [10]. */ { 13, 1 }, /* SME_VL_13: VLx2 or VLx4, bit [13]. */ + { 0, 1 }, /* SME_ZAda_1b: tile ZA0-ZA1. */ { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */ { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */ { 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */ @@ -346,6 +347,7 @@ const aarch64_field fields[] = { 21, 2 }, /* hw: in move wide constant instructions. */ { 0, 1 }, /* imm1_0: general immediate in bits [0]. */ { 2, 1 }, /* imm1_2: general immediate in bits [2]. */ + { 3, 1 }, /* imm1_3: general immediate in bits [3]. */ { 8, 1 }, /* imm1_8: general immediate in bits [8]. */ { 10, 1 }, /* imm1_10: general immediate in bits [10]. */ { 14, 1 }, /* imm1_14: general immediate in bits [14]. */ @@ -353,6 +355,7 @@ const aarch64_field fields[] = { 16, 1 }, /* imm1_16: general immediate in bits [16]. */ { 0, 2 }, /* imm2_0: general immediate in bits [1:0]. */ { 1, 2 }, /* imm2_1: general immediate in bits [2:1]. */ + { 2, 2 }, /* imm2_2: general immediate in bits [3:2]. */ { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */ { 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */ { 12, 2 }, /* imm2_12: 2-bit immediate, bits [13:12] */ @@ -1882,10 +1885,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX2_3: case AARCH64_OPND_SME_Zm_INDEX3_1: case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_3: case AARCH64_OPND_SME_Zm_INDEX3_10: case AARCH64_OPND_SME_Zm_INDEX4_1: + case AARCH64_OPND_SME_Zm_INDEX4_2: + case AARCH64_OPND_SME_Zm_INDEX4_3: case AARCH64_OPND_SME_Zm_INDEX4_10: size = get_operand_fields_width (get_operand_from_code (type)) - 4; if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15, @@ -4254,11 +4261,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zn_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX2_3: case AARCH64_OPND_SME_Zm_INDEX3_1: case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_3: case AARCH64_OPND_SME_Zm_INDEX3_10: case AARCH64_OPND_SVE_Zn_5_INDEX: case AARCH64_OPND_SME_Zm_INDEX4_1: + case AARCH64_OPND_SME_Zm_INDEX4_2: + case AARCH64_OPND_SME_Zm_INDEX4_3: case AARCH64_OPND_SME_Zm_INDEX4_10: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: @@ -4275,6 +4286,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, style_imm (styler, "%" PRIi64, opnd->reglane.index)); break; + case AARCH64_OPND_SME_ZAda_1b: case AARCH64_OPND_SME_ZAda_2b: case AARCH64_OPND_SME_ZAda_3b: snprintf (buf, size, "%s", diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index aae87e1f24a21d58ffb6a0e3667b7764d00ba1f7..fa06e424c29cc12b6b4f1bf7ddea0ba8106b1ead 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1703,6 +1703,10 @@ { \ QLF3(S_H,P_M,S_D), \ } +#define OP_SVE_HMMBB \ +{ \ + QLF5(S_H,P_M,P_M,S_B,S_B) \ +} #define OP_SVE_HMS \ { \ QLF3(S_H,P_M,S_S), \ @@ -2806,6 +2810,12 @@ static const aarch64_feature_set aarch64_feature_fp8dot4_sve = AARCH64_FEATURES (2, FP8DOT4_SVE, SVE); static const aarch64_feature_set aarch64_feature_fp8dot2_sve = AARCH64_FEATURES (2, FP8DOT2_SVE, SVE); +static const aarch64_feature_set aarch64_feature_sme_f8f32 = + AARCH64_FEATURES (2, SME_F8F32, SME2); +static const aarch64_feature_set aarch64_feature_sme_f8f16 = + AARCH64_FEATURES (2, SME_F8F32, SME2); +static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = + AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2889,6 +2899,9 @@ static const aarch64_feature_set aarch64_feature_fp8dot2_sve = #define FP8FMA_SVE &aarch64_feature_fp8fma_sve #define FP8DOT4_SVE &aarch64_feature_fp8dot4_sve #define FP8DOT2_SVE &aarch64_feature_fp8dot2_sve +#define SME_F8F32 &aarch64_feature_sme_f8f32 +#define SME_F8F16 &aarch64_feature_sme_f8f16 +#define SME_F16F16_F8F16 &aarch64_feature_sme_f16f16_f8f16 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -3101,6 +3114,12 @@ static const aarch64_feature_set aarch64_feature_fp8dot2_sve = { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define SME_F8F32_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_F8F32, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL } +#define SME_F8F16_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL } +#define SME_F16F16_F8F16_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_F16F16_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -6687,6 +6706,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0), LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0), + /* SME FP16 ZA-targeting addition instructions. */ + SME_F16F16_F8F16_INSNC("fadd", 0xc1a41c00, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0), + SME_F16F16_F8F16_INSNC("fadd", 0xc1a51c00, 0xffff9c78, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD (4), 0), + SME_F16F16_F8F16_INSNC("fsub", 0xc1a41c08, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0), + SME_F16F16_F8F16_INSNC("fsub", 0xc1a51c08, 0xffff9c78, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD (4), 0), + /* FP8 multiplication AdvSIMD instructions. */ FP8DOT4_INSN("fdot", 0x0e00fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), FP8DOT4_INSN("fdot", 0x0f000000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), @@ -6723,6 +6748,41 @@ const struct aarch64_opcode aarch64_opcode_table[] = FP8FMA_SVE_INSNC("fmlalt", 0x64a09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), FP8FMA_SVE_INSNC("fmlalt", 0x64a05000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + /* FP8 multiplication SME instructions. */ + SME_F8F32_INSNC("fdot", 0xc1500038, 0xfff09038, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_VVV_S_B, F_OD (2), 0), + SME_F8F32_INSNC("fdot", 0xc1508008, 0xfff09078, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_VVV_S_B, F_OD (4), 0), + SME_F8F32_INSNC("fdot", 0xc1201018, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (2), 0), + SME_F8F32_INSNC("fdot", 0xc1301018, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (4), 0), + SME_F8F32_INSNC("fdot", 0xc1a01030, 0xffe19c38, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_S_B, F_OD (2), 0), + SME_F8F32_INSNC("fdot", 0xc1a11030, 0xffe39c78, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_S_B, F_OD (4), 0), + SME_F8F16_INSNC("fdot", 0xc1d00020, 0xfff09030, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_VVV_H_B, F_OD (2), 0), + SME_F8F16_INSNC("fdot", 0xc1109040, 0xfff09070, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_VVV_H_B, F_OD (4), 0), + SME_F8F16_INSNC("fdot", 0xc1201008, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (2), 0), + SME_F8F16_INSNC("fdot", 0xc1301008, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (4), 0), + SME_F8F16_INSNC("fdot", 0xc1a01020, 0xffe19c38, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_H_B, F_OD (2), 0), + SME_F8F16_INSNC("fdot", 0xc1a11020, 0xffe39c78, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_H_B, F_OD (4), 0), + SME_F8F16_INSNC("fmlal", 0xc1c00000, 0xfff01010, sme_misc, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX4_3), OP_SVE_VVV_H_B, 0, 0), + SME_F8F16_INSNC("fmlal", 0xc1901030, 0xfff09030, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX4_2), OP_SVE_VVV_H_B, F_OD (2), 0), + SME_F8F16_INSNC("fmlal", 0xc1909020, 0xfff09070, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX4_2), OP_SVE_VVV_H_B, F_OD (4), 0), + SME_F8F16_INSNC("fmlal", 0xc1300c00, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_VVV_H_B, 0, 0), + SME_F8F16_INSNC("fmlal", 0xc1200804, 0xfff09c1c, sme_misc, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (2), 0), + SME_F8F16_INSNC("fmlal", 0xc1300804, 0xfff09c1c, sme_misc, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (4), 0), + SME_F8F16_INSNC("fmlal", 0xc1a00820, 0xffe19c3c, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_VVV_H_B, F_OD (2), 0), + SME_F8F16_INSNC("fmlal", 0xc1a10820, 0xffe39c7c, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_VVV_H_B, F_OD (4), 0), + SME_F8F32_INSNC("fmlall", 0xc1400000, 0xfff0001c, sme_misc, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_VVV_S_B, 0, 0), + SME_F8F32_INSNC("fmlall", 0xc1900020, 0xfff09038, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_VVV_S_B, F_OD (2), 0), + SME_F8F32_INSNC("fmlall", 0xc1108040, 0xfff09078, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_VVV_S_B, F_OD (4), 0), + SME_F8F32_INSNC("fmlall", 0xc1300400, 0xfff09c1c, sme_misc, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm), OP_SVE_VVV_S_B, 0, 0), + SME_F8F32_INSNC("fmlall", 0xc1200002, 0xfff09c1e, sme_misc, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (2), 0), + SME_F8F32_INSNC("fmlall", 0xc1300002, 0xfff09c1e, sme_misc, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (4), 0), + SME_F8F32_INSNC("fmlall", 0xc1a00020, 0xffe19c3e, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_VVV_S_B, F_OD (2), 0), + SME_F8F32_INSNC("fmlall", 0xc1a10020, 0xffe39c7e, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_S_B, F_OD (4), 0), + SME_F8F16_INSNC("fmopa", 0x80a00008, 0xffe0001e, sme_misc, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMBB, 0, 0), + SME_F8F32_INSNC("fmopa", 0x80a00000, 0xffe0001c, sme_misc, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0), + SME_F8F16_INSNC("fvdot", 0xc1d01020, 0xfff09030, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_VVV_H_B, F_OD (2), 0), + SME_F8F32_INSNC("fvdotb", 0xc1d00800, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4), 0), + SME_F8F32_INSNC("fvdott", 0xc1d00810, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4), 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -7268,6 +7328,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx4_STRIDED", \ 4 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt2), \ "a list of SVE vector registers") \ + Y(SVE_REG, regno, "SME_ZAda_1b", 0, F(FLD_SME_ZAda_1b), \ + "an SME ZA tile ZA0-ZA1") \ Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \ "an SME ZA tile ZA0-ZA3") \ Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ @@ -7336,18 +7398,30 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \ F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX2_3", 0, \ + F(FLD_SME_Zm, FLD_imm1_10, FLD_imm1_3), \ + "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_1", 0, \ F(FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_2", 0, \ F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2), \ "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX3_3", 0, \ + F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_3), \ + "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_10", 0, \ F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_1", 0, \ F(FLD_SME_Zm, FLD_imm2_10, FLD_imm2_1), \ "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX4_2", 0, \ + F(FLD_SME_Zm, FLD_imm2_10, FLD_imm2_2), \ + "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX4_3", 0, \ + F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10, FLD_imm1_3), \ + "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_10", 0, \ F(FLD_SME_Zm, FLD_imm1_15, FLD_imm3_10), \ "an indexed SVE vector register") \ From patchwork Fri Jun 21 18:32:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 92696 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C58803830B40 for ; Fri, 21 Jun 2024 18:34:17 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2058.outbound.protection.outlook.com [40.107.103.58]) by sourceware.org (Postfix) with ESMTPS id 80F573830B74 for ; Fri, 21 Jun 2024 18:33:17 +0000 (GMT) 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X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 6c6f983be3f4a9de308f589c718476319d2ba2bc..f8031e09ed2af02edd8bf6b7034238a8da3fd22c 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -682,16 +682,17 @@ aarch64_insert_operand (const aarch64_operand *self, case 247: case 254: case 255: - case 262: + case 256: case 263: case 264: case 265: + case 266: return aarch64_ins_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 297: - case 299: + case 302: + case 304: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -706,7 +707,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 37: case 38: case 39: - case 301: + case 306: return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: @@ -714,9 +715,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 228: case 229: case 232: - case 266: case 267: - case 282: + case 268: case 283: case 284: case 285: @@ -729,6 +729,11 @@ aarch64_insert_operand (const aarch64_operand *self, case 292: case 293: case 294: + case 295: + case 296: + case 297: + case 298: + case 299: return aarch64_ins_simple_index (self, info, code, inst, errors); case 43: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -777,13 +782,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 208: case 209: case 210: - case 268: - case 295: - case 296: - case 298: + case 269: case 300: + case 301: + case 303: case 305: - case 306: + case 310: + case 311: return aarch64_ins_imm (self, info, code, inst, errors); case 52: case 53: @@ -931,7 +936,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 200: case 201: case 202: - case 281: + case 282: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); case 215: case 216: @@ -958,10 +963,10 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sve_index (self, info, code, inst, errors); case 242: case 244: - case 261: - case 307: - case 308: - case 309: + case 262: + case 312: + case 313: + case 314: return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 245: case 246: @@ -969,44 +974,44 @@ aarch64_insert_operand (const aarch64_operand *self, case 249: case 250: case 251: - case 260: + case 261: return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 252: case 253: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 256: - case 258: - case 269: - return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); case 257: case 259: - return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 270: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + case 258: + case 260: + return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 271: case 272: case 273: case 274: case 275: case 276: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 278: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 279: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 280: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 281: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 302: - case 303: - case 304: + case 307: + case 308: + case 309: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 310: - case 311: - case 312: - case 313: + case 315: + case 316: + case 317: + case 318: return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); - case 314: + case 319: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 38cb3a1c52d7922fed9c9f946ed60651bf3b7c4d..da7c223ec502f71290bdfa4591d7ff4d823579c2 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -1116,21 +1116,43 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 4) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000101xxxxxxxxxxxxxxxx0xxxx - sumopa. */ - return 2424; + if (((word >> 3) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000000101xxxxxxxxxxxxxxxx00xxx + fmopa. */ + return 3459; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000000101xxxxxxxxxxxxxxxx01xxx + fmopa. */ + return 3458; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1x00000101xxxxxxxxxxxxxxxx0xxxx - st1w. */ - return 2453; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000101xxxxxxxxxxxxxxxx0xxxx + sumopa. */ + return 2424; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1100000101xxxxxxxxxxxxxxxx0xxxx + st1w. */ + return 2453; + } } } else @@ -1394,13 +1416,13 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 3) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - if (((word >> 4) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 2) & 0x1) == 0) { - if (((word >> 2) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -1412,54 +1434,109 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000010000xxxxxxxxxxxxxxx001xx - usmlall. */ - return 2932; + xx0000010000xxxxxxxxxxxxxxx010xx + smlsll. */ + return 2743; } } else { - if (((word >> 5) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010000xxxxxxxxxxxxxxx0x1xx + usmlall. */ + return 2932; + } + } + else + { + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx0xxxxxxxxx000xxx - smlall. */ - return 2728; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx0xx0xxxxxx000xxx + smlall. */ + return 2728; + } + else + { + if (((word >> 6) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xx0xxxxx0000xxx + smlall. */ + return 2729; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xx0xxxxx1000xxx + fmlall. */ + return 3452; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx1xxxxxxxxx000xxx - smlall. */ - return 2729; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx0xx0xxxxxx001xxx + smlsll. */ + return 2744; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xx0xxxxxx001xxx + smlsll. */ + return 2745; + } } } else { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx0xxxxxxxxx100xxx - usmlall. */ - return 2933; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx1xxxxxxxxx100xxx - usmlall. */ - return 2934; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxxxxx1xxxxxx00xxxx + fdot. */ + return 3437; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx0xxxxxxxxx10xxxx + usmlall. */ + return 2933; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010001xxxx1xxxxxxxxx10xxxx + usmlall. */ + return 2934; } } } - else + } + else + { + if (((word >> 3) & 0x1) == 0) { if (((word >> 20) & 0x1) == 0) { @@ -1522,39 +1599,6 @@ aarch64_opcode_lookup_1 (uint32_t word) } } } - } - else - { - if (((word >> 4) & 0x1) == 0) - { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010000xxxxxxxxxxxxxxx01xxx - smlsll. */ - return 2743; - } - else - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx0xxxxxxxxxx01xxx - smlsll. */ - return 2744; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010001xxxx1xxxxxxxxxx01xxx - smlsll. */ - return 2745; - } - } - } else { if (((word >> 20) & 0x1) == 0) @@ -1785,23 +1829,23 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 3) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - if (((word >> 4) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - if (((word >> 29) & 0x1) == 0) + if (((word >> 30) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000001100xxxxxxxxxxxxxxxx00xxx - bfmopa. */ - return 2411; - } - else + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001100xxxxxxxxxxxxxxxx0xxxx + bfmopa. */ + return 2411; + } + else + { + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { if (((word >> 20) & 0x1) == 0) { @@ -1813,21 +1857,32 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011001xxxx0xx0xxxxxxx00xxx - smlall. */ - return 2965; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx0xx0xxxxxx000xxx + smlall. */ + return 2965; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx1xx0xxxxxx000xxx + smlall. */ + return 2966; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011001xxxx1xx0xxxxxxx00xxx - smlall. */ - return 2966; + x10000011001xxxxxxx0xxxxxx100xxx + fmlall. */ + return 3451; } } } @@ -1837,9 +1892,9 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011000xxxxxxx1xxxxxxx00xxx - fmlal. */ - return 2568; + x10000011000xxxxxxx0xxxxxxx01xxx + smlsll. */ + return 2967; } else { @@ -1847,23 +1902,100 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011001xxxx0xx1xxxxxxx00xxx - fmlal. */ - return 2569; + x10000011001xxxx0xx0xxxxxxx01xxx + smlsll. */ + return 2968; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011001xxxx1xx1xxxxxxx00xxx - fmlal. */ - return 2570; + x10000011001xxxx1xx0xxxxxxx01xxx + smlsll. */ + return 2969; + } + } + } + } + else + { + if (((word >> 20) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011000xxxxxxx1xxxxxxx00xxx + fmlal. */ + return 2568; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011000xxxxxxx1xxxxxxx01xxx + fmlsl. */ + return 2582; + } + } + else + { + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx0xx1xxxxxx000xxx + fmlal. */ + return 2569; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx1xx1xxxxxx000xxx + fmlal. */ + return 2570; + } } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx0xx1xxxxxx001xxx + fmlsl. */ + return 2583; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx1xx1xxxxxx001xxx + fmlsl. */ + return 2584; + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxxxxx1xxxxxx10xxxx + fmlal. */ + return 3444; } } } } - else + } + else + { + if (((word >> 3) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -1871,22 +2003,33 @@ aarch64_opcode_lookup_1 (uint32_t word) usmopa. */ return 2432; } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001100xxxxxxxxxxxxxxxx01xxx + umopa. */ + return 2914; + } } - else + } + else + { + if (((word >> 29) & 0x1) == 0) { - if (((word >> 29) & 0x1) == 0) + if (((word >> 30) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000001100xxxxxxxxxxxxxxxx10xxx - bfmops. */ - return 2412; - } - else + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001100xxxxxxxxxxxxxxxx1xxxx + bfmops. */ + return 2412; + } + else + { + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { if (((word >> 20) & 0x1) == 0) { @@ -1922,9 +2065,9 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011000xxxxxxx1xxxxxxx10xxx - bfmlal. */ - return 2510; + x10000011000xxxxxxx0xxxxxxx11xxx + umlsll. */ + return 2976; } else { @@ -1932,121 +2075,157 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011001xxxx0xx1xxxxxxx10xxx - bfmlal. */ - return 2511; + x10000011001xxxx0xx0xxxxxxx11xxx + umlsll. */ + return 2977; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011001xxxx1xx1xxxxxxx10xxx - bfmlal. */ - return 2512; + x10000011001xxxx1xx0xxxxxxx11xxx + umlsll. */ + return 2978; } } } } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001100xxxxxxxxxxxxxxxx10xxx - usmops. */ - return 2434; - } - } - } - else - { - if (((word >> 4) & 0x1) == 0) - { - if (((word >> 29) & 0x1) == 0) - { - if (((word >> 12) & 0x1) == 0) + else { if (((word >> 20) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011000xxxxxxx0xxxxxxx01xxx - smlsll. */ - return 2967; - } - else - { - if (((word >> 15) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000011001xxxx0xx0xxxxxxx01xxx - smlsll. */ - return 2968; + x10000011000xxxxxxx1xxxxxxx10xxx + bfmlal. */ + return 2510; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000011001xxxx1xx0xxxxxxx01xxx - smlsll. */ - return 2969; + x10000011000xxxxxxx1xxxxxxx11xxx + bfmlsl. */ + return 2518; } } - } - else - { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011000xxxxxxx1xxxxxxx01xxx - fmlsl. */ - return 2582; - } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011001xxxx0xx1xxxxxxx01xxx - fmlsl. */ - return 2583; + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx0xx1xxxxxx010xxx + bfmlal. */ + return 2511; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx1xx1xxxxxx010xxx + bfmlal. */ + return 2512; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx0xx1xxxxxx011xxx + bfmlsl. */ + return 2519; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx1xx1xxxxxx011xxx + bfmlsl. */ + return 2520; + } + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000011001xxxx1xx1xxxxxxx01xxx - fmlsl. */ - return 2584; + x10000011001xxxxxxx1xxxxxx11xxxx + fmlal. */ + return 3443; } } } } + } + else + { + if (((word >> 3) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001100xxxxxxxxxxxxxxxx10xxx + usmops. */ + return 2434; + } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx100001100xxxxxxxxxxxxxxxx01xxx - umopa. */ - return 2914; + xx100001100xxxxxxxxxxxxxxxx11xxx + umops. */ + return 2915; } } - else + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000010100xxxxxxxxxxxxxxxx0xxx + fmlall. */ + return 3450; + } + else + { + if (((word >> 13) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011000xxxxxxx0xxxxxxx11xxx - umlsll. */ - return 2976; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx1000010100xxxx000xxxxxxxxx0xxx + ld1b. */ + return 2603; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx1000010100xxxx100xxxxxxxxx0xxx + ld1b. */ + return 2604; + } } else { @@ -2054,29 +2233,40 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000011001xxxx0xx0xxxxxxx11xxx - umlsll. */ - return 2977; + xx1000010100xxxx010xxxxxxxxx0xxx + ld1w. */ + return 2627; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000011001xxxx1xx0xxxxxxx11xxx - umlsll. */ - return 2978; + xx1000010100xxxx110xxxxxxxxx0xxx + ld1w. */ + return 2628; } } } else { - if (((word >> 20) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011000xxxxxxx1xxxxxxx11xxx - bfmlsl. */ - return 2518; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx1000010100xxxx001xxxxxxxxx0xxx + ld1h. */ + return 2619; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx1000010100xxxx101xxxxxxxxx0xxx + ld1h. */ + return 2620; + } } else { @@ -2084,89 +2274,31 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000011001xxxx0xx1xxxxxxx11xxx - bfmlsl. */ - return 2519; + xx1000010100xxxx011xxxxxxxxx0xxx + ld1d. */ + return 2611; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx0000011001xxxx1xx1xxxxxxx11xxx - bfmlsl. */ - return 2520; + xx1000010100xxxx111xxxxxxxxx0xxx + ld1d. */ + return 2612; } } } } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001100xxxxxxxxxxxxxxxx11xxx - umops. */ - return 2915; - } } - } - } - } - else - { - if (((word >> 23) & 0x1) == 0) - { - if (((word >> 3) & 0x1) == 0) - { - if (((word >> 15) & 0x1) == 0) + else { - if (((word >> 20) & 0x1) == 0) - { - if (((word >> 13) & 0x1) == 0) - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx000xxxxxxxxx0xxx - ld1b. */ - return 2603; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx010xxxxxxxxx0xxx - ld1w. */ - return 2627; - } - } - else - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx001xxxxxxxxx0xxx - ld1h. */ - return 2619; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx011xxxxxxxxx0xxx - ld1d. */ - return 2611; - } - } - } - else + if (((word >> 4) & 0x1) == 0) { - if (((word >> 4) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - if (((word >> 5) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -2178,190 +2310,146 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx000xxx - sdot. */ - return 2697; + xxx000010101xxxx1xx0xxxxxx000xxx + fmla. */ + return 2563; } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx100xxx - svdot. */ - return 2856; + xxx000010101xxxx0xx1xxxxxx000xxx + sdot. */ + return 2697; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx100xxx + xxx000010101xxxx1xx1xxxxxx000xxx sdot. */ - return 2703; + return 2698; } } } else { - if (((word >> 5) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx010xxx - fmls. */ - return 2576; + xxx000010101xxxx0xx0xxxxxx100xxx + svdot. */ + return 2856; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx010xxx - udot. */ - return 2862; + xxx000010101xxxx1xx0xxxxxx100xxx + svdot. */ + return 2857; } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx110xxx - uvdot. */ - return 2943; + xxx000010101xxxx0xx1xxxxxx100xxx + sdot. */ + return 2703; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx110xxx - udot. */ - return 2868; + xxx000010101xxxx1xx1xxxxxx100xxx + sdot. */ + return 2704; } } } } - } - else - { - if (((word >> 20) & 0x1) == 0) - { - if (((word >> 13) & 0x1) == 0) - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx100xxxxxxxxx0xxx - ld1b. */ - return 2604; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx110xxxxxxxxx0xxx - ld1w. */ - return 2628; - } - } - else - { - if (((word >> 14) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx101xxxxxxxxx0xxx - ld1h. */ - return 2620; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010100xxxx111xxxxxxxxx0xxx - ld1d. */ - return 2612; - } - } - } else { - if (((word >> 4) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - if (((word >> 5) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx000xxx - fmla. */ - return 2563; + xxx000010101xxxx0xx0xxxxxx010xxx + fmls. */ + return 2576; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx000xxx - sdot. */ - return 2698; + xxx000010101xxxx1xx0xxxxxx010xxx + fmls. */ + return 2577; } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx100xxx - svdot. */ - return 2857; + xxx000010101xxxx0xx1xxxxxx010xxx + udot. */ + return 2862; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx100xxx - sdot. */ - return 2704; + xxx000010101xxxx1xx1xxxxxx010xxx + udot. */ + return 2863; } } } else { - if (((word >> 5) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx010xxx - fmls. */ - return 2577; + xxx000010101xxxx0xx0xxxxxx110xxx + uvdot. */ + return 2943; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx010xxx - udot. */ - return 2863; + xxx000010101xxxx1xx0xxxxxx110xxx + uvdot. */ + return 2944; } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx110xxx - uvdot. */ - return 2944; + xxx000010101xxxx0xx1xxxxxx110xxx + udot. */ + return 2868; } else { @@ -2476,11 +2564,22 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xxxxxxxxx111xxx - sudot. */ - return 2844; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010101xxxx0xx0xxxxxx111xxx + fdot. */ + return 3430; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010101xxxx0xx1xxxxxx111xxx + sudot. */ + return 2844; + } } } } @@ -2534,11 +2633,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xxxxxxxxx001xxx - fdot. */ - return 2541; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010101xxxx1xx0xxxxxx001xxx + fdot. */ + return 3431; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010101xxxx1xx1xxxxxx001xxx + fdot. */ + return 2541; + } } else { @@ -2600,93 +2710,104 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 3) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001110xxxxx0xx0xxxxxxx00xxx - fmla. */ - return 2980; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001110xxxxx1xx0xxxxxxx00xxx - fmla. */ - return 2981; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011100xxxxxxx0xxxxxxx0xxxx + fmlal. */ + return 3442; } else { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011100xxxxxxx1xxxxxxx00xxx - smlal. */ - return 2719; - } - else + if (((word >> 5) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011101xxxx0xx1xxxxxxx00xxx - smlal. */ - return 2720; + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx00xxxxx000xxx + fmla. */ + return 2980; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx00xxxxx000xxx + fmla. */ + return 2981; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx00xxxxx001xxx + sdot. */ + return 2962; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx00xxxxx001xxx + sdot. */ + return 2963; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011101xxxx1xx1xxxxxxx00xxx - smlal. */ - return 2721; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx01xxxxx00xxxx + fvdotb. */ + return 3461; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx01xxxxx00xxxx + svdot. */ + return 2970; + } } } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxxxxx0xxxxxx10xxxx + fdot. */ + return 3436; + } } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 11) & 0x1) == 0) - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001110xxxxx0xx00xxxxxx01xxx - sdot. */ - return 2962; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001110xxxxx1xx00xxxxxx01xxx - sdot. */ - return 2963; - } - } - else + if (((word >> 3) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx000001110xxxxxxxx01xxxxxx01xxx - svdot. */ - return 2970; + xx0000011100xxxxxxx1xxxxxxx00xxx + smlal. */ + return 2719; } - } - else - { - if (((word >> 20) & 0x1) == 0) + else { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -2694,25 +2815,58 @@ aarch64_opcode_lookup_1 (uint32_t word) smlsl. */ return 2735; } - else + } + else + { + if (((word >> 5) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011101xxxx0xx1xxxxxxx01xxx - smlsl. */ - return 2736; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx1xxxxxx000xxx + smlal. */ + return 2720; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx1xxxxxx000xxx + smlal. */ + return 2721; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000011101xxxx1xx1xxxxxxx01xxx - smlsl. */ - return 2737; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx1xxxxxx001xxx + smlsl. */ + return 2736; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx1xxxxxx001xxx + smlsl. */ + return 2737; + } } } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxxxxx1xxxxxx10xxxx + fvdot. */ + return 3460; + } } } } @@ -2738,30 +2892,74 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 3) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - if (((word >> 29) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx0xx00xxxxxx10xxx + fmls. */ + return 2982; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx1xx00xxxxxx10xxx + fmls. */ + return 2983; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx0xx00xxxxxx11xxx + udot. */ + return 2971; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx1xx00xxxxxx11xxx + udot. */ + return 2972; + } + } + } + else { if (((word >> 15) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx000001110xxxxx0xx0xxxxxxx10xxx - fmls. */ - return 2982; + xx000001110xxxxx0xx01xxxxxx1xxxx + fvdott. */ + return 3462; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx000001110xxxxx1xx0xxxxxxx10xxx - fmls. */ - return 2983; + xx000001110xxxxx1xx01xxxxxx1xxxx + uvdot. */ + return 2979; } } - else + } + else + { + if (((word >> 3) & 0x1) == 0) { if (((word >> 20) & 0x1) == 0) { @@ -2791,79 +2989,46 @@ aarch64_opcode_lookup_1 (uint32_t word) } } } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001110xxxxxxxxxxxxxxxx10xxx - usmops. */ - return 2435; - } - } - else - { - if (((word >> 12) & 0x1) == 0) - { - if (((word >> 11) & 0x1) == 0) - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001110xxxxx0xx00xxxxxx11xxx - udot. */ - return 2971; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001110xxxxx1xx00xxxxxx11xxx - udot. */ - return 2972; - } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001110xxxxxxxx01xxxxxx11xxx - uvdot. */ - return 2979; - } - } - else - { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000011100xxxxxxx1xxxxxxx11xxx - umlsl. */ - return 2898; - } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000011101xxxx0xx1xxxxxxx11xxx + xx0000011100xxxxxxx1xxxxxxx11xxx umlsl. */ - return 2899; + return 2898; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000011101xxxx1xx1xxxxxxx11xxx - umlsl. */ - return 2900; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx1xxxxxxx11xxx + umlsl. */ + return 2899; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx1xxxxxxx11xxx + umlsl. */ + return 2900; + } } } } } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001110xxxxxxxxxxxxxxxx1xxxx + usmops. */ + return 2435; + } } } } @@ -2905,86 +3070,130 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 12) & 0x1) == 0) { - if (((word >> 2) & 0x1) == 0) + if (((word >> 1) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 2) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x10xxxx0xx000xxxxx000xx - smlall. */ - return 2731; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx000xxxxx0000x + smlall. */ + return 2731; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx000xxxxx0000x + smlall. */ + return 2732; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x11xxxx0xx000xxxxx000xx - smlall. */ - return 2732; + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx000xxxx00000x + smlall. */ + return 2733; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx000xxxx00000x + smlall. */ + return 2734; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx000xxxx10000x + fmlall. */ + return 3456; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx000xxxx10000x + fmlall. */ + return 3457; + } + } } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx00xx000xxxxx000xx - smlall. */ - return 2733; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx000xxxxx0010x + usmlall. */ + return 2936; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx000xxxxx0010x + usmlall. */ + return 2937; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx10xx000xxxxx000xx - smlall. */ - return 2734; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx000xxxxx0010x + usmlall. */ + return 2938; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx000xxxxx0010x + usmlall. */ + return 2939; + } } } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x10xxxx0xx000xxxxx001xx - usmlall. */ - return 2936; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x11xxxx0xx000xxxxx001xx - usmlall. */ - return 2937; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xxxx0xx000xxxxx00x1x + fmlall. */ + return 3454; } else { - if (((word >> 16) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx00xx000xxxxx001xx - usmlall. */ - return 2938; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx10xx000xxxxx001xx - usmlall. */ - return 2939; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xxxx0xx000xxxxx00x1x + fmlall. */ + return 3455; } } } @@ -3011,48 +3220,23 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 16) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx00xx100xxxxx00xxx - fdot. */ - return 2544; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx10xx100xxxxx00xxx - fdot. */ - return 2545; - } - } - } - } - else - { - if (((word >> 12) & 0x1) == 0) - { - if (((word >> 22) & 0x1) == 0) - { - if (((word >> 23) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 16) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010010xxxx0xx010xxxxx00xxx - fmlal. */ - return 2572; + x10000011x1xxxx00xx100xxxx000xxx + fdot. */ + return 2544; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010011xxxx0xx010xxxxx00xxx - fmlal. */ - return 2573; + x10000011x1xxxx10xx100xxxx000xxx + fdot. */ + return 2545; } } else @@ -3061,61 +3245,152 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001101xxxx00xx010xxxxx00xxx - fmlal. */ - return 2574; + x10000011x1xxxx00xx100xxxx100xxx + fdot. */ + return 3440; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001101xxxx10xx010xxxxx00xxx - fmlal. */ - return 2575; + x10000011x1xxxx10xx100xxxx100xxx + fdot. */ + return 3441; } } } - else + } + } + else + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 2) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010110xxxx0xx010xxxxx00xxx - smlal. */ - return 2723; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010010xxxx0xx010xxxxx000xx + fmlal. */ + return 2572; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010011xxxx0xx010xxxxx000xx + fmlal. */ + return 2573; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010111xxxx0xx010xxxxx00xxx - smlal. */ - return 2724; + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx00xx010xxxx0000xx + fmlal. */ + return 2574; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx10xx010xxxx0000xx + fmlal. */ + return 2575; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx00xx010xxxx1000xx + fmlal. */ + return 3448; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx10xx010xxxx1000xx + fmlal. */ + return 3449; + } + } } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001111xxxx00xx010xxxxx00xxx - smlal. */ - return 2725; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010110xxxx0xx010xxxxx000xx + smlal. */ + return 2723; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010111xxxx0xx010xxxxx000xx + smlal. */ + return 2724; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001111xxxx10xx010xxxxx00xxx - smlal. */ - return 2726; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx00xx010xxxxx000xx + smlal. */ + return 2725; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx10xx010xxxxx000xx + smlal. */ + return 2726; + } } } } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xxxx0xx010xxxxx001xx + fmlal. */ + return 3446; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xxxx0xx010xxxxx001xx + fmlal. */ + return 3447; + } + } } else { @@ -3168,11 +3443,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 2) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx0xx001xxxxx000xx - smlall. */ - return 2730; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xxxx0xx001xxxxx000xx + smlall. */ + return 2730; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xxxx0xx001xxxxx000xx + fmlall. */ + return 3453; + } } else { @@ -3229,40 +3515,73 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 12) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001x01xxxxx0xx011xxxxx00xxx - fmlal. */ - return 2571; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x010xxxx0xx011xxxxx00xxx + fmlal. */ + return 2571; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x110xxxx0xx011xxxxx00xxx + smlal. */ + return 2722; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001x11xxxxx0xx011xxxxx00xxx - smlal. */ - return 2722; + x1000001xx11xxxx0xx011xxxxx00xxx + fmlal. */ + return 3445; } } else { if (((word >> 16) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xx111xxxxx00xxx - fadd. */ - return 2530; + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx0x00xx111xxxxx00xxx + fadd. */ + return 2530; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx1x00xx111xxxxx00xxx + fadd. */ + return 3394; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xx111xxxxx00xxx - fadd. */ - return 2531; + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx0x10xx111xxxxx00xxx + fadd. */ + return 2531; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx1x10xx111xxxxx00xxx + fadd. */ + return 3395; + } } } } @@ -3360,21 +3679,43 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx00xx100xxxxx10xxx - bfdot. */ - return 2508; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx100xxxx010xxx + bfdot. */ + return 2508; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx100xxxx010xxx + bfdot. */ + return 2509; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx10xx100xxxxx10xxx - bfdot. */ - return 2509; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx100xxxx110xxx + fdot. */ + return 3434; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx100xxxx110xxx + fdot. */ + return 3435; + } } } } @@ -3615,42 +3956,64 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 11) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x10xxxx0xxx00xxxxx01xxx - smlsll. */ - return 2747; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx000xxxxx01xxx + smlsll. */ + return 2747; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx000xxxxx01xxx + smlsll. */ + return 2748; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x11xxxx0xxx00xxxxx01xxx - smlsll. */ - return 2748; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx000xxxxx01xxx + smlsll. */ + return 2749; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx000xxxxx01xxx + smlsll. */ + return 2750; + } } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx00xxx00xxxxx01xxx - smlsll. */ - return 2749; + x1000001xx10xxxx0xx100xxxxx01xxx + fdot. */ + return 3438; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx10xxx00xxxxx01xxx - smlsll. */ - return 2750; + x1000001xx11xxxx0xx100xxxxx01xxx + fdot. */ + return 3439; } } } @@ -3907,19 +4270,41 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 16) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xx111xxxxx01xxx - fsub. */ - return 2598; + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx0x00xx111xxxxx01xxx + fsub. */ + return 2598; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx1x00xx111xxxxx01xxx + fsub. */ + return 3396; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xx111xxxxx01xxx - fsub. */ - return 2599; + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx0x10xx111xxxxx01xxx + fsub. */ + return 2599; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx1x10xx111xxxxx01xxx + fsub. */ + return 3397; + } } } } @@ -3931,42 +4316,64 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 11) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x10xxxx0xxx00xxxxx11xxx - umlsll. */ - return 2910; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx000xxxxx11xxx + umlsll. */ + return 2910; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx000xxxxx11xxx + umlsll. */ + return 2911; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x11xxxx0xxx00xxxxx11xxx - umlsll. */ - return 2911; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx000xxxxx11xxx + umlsll. */ + return 2912; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx000xxxxx11xxx + umlsll. */ + return 2913; + } } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx00xxx00xxxxx11xxx - umlsll. */ - return 2912; + x1000001xx10xxxx0xx100xxxxx11xxx + fdot. */ + return 3432; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx10xxx00xxxxx11xxx - umlsll. */ - return 2913; + x1000001xx11xxxx0xx100xxxxx11xxx + fdot. */ + return 3433; } } } @@ -17268,7 +17675,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0100x1xxxxxxxxxx fdot. */ - return 3413; + return 3417; } } else @@ -17277,7 +17684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0101xxxxxxxxxxxx fmlalb. */ - return 3415; + return 3419; } } else @@ -17318,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 3425; + return 3429; } } else @@ -17351,7 +17758,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xx1xxxxxxxxxx fdot. */ - return 3411; + return 3415; } } else @@ -17422,7 +17829,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx100010xxxxxxxxxx fmlallbb. */ - return 3416; + return 3420; } } else @@ -17431,7 +17838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1000x1xxxxxxxxxx fdot. */ - return 3412; + return 3416; } } else @@ -17440,7 +17847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1100xxxxxxxxxxxx fmlallbb. */ - return 3417; + return 3421; } } else @@ -17449,7 +17856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1x01xxxxxxxxxxxx fmlallbt. */ - return 3418; + return 3422; } } else @@ -17476,7 +17883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx100010xxxxxxxxxx fmlalb. */ - return 3414; + return 3418; } } else @@ -17494,7 +17901,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1100xxxxxxxxxxxx fmlalltb. */ - return 3421; + return 3425; } } else @@ -17503,7 +17910,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 3424; + return 3428; } } else @@ -17536,7 +17943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx100xx1xxxxxxxxxx fdot. */ - return 3410; + return 3414; } } else @@ -17545,7 +17952,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx110xxxxxxxxxxxxx fmlallbt. */ - return 3419; + return 3423; } } else @@ -17577,7 +17984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx110xxxxxxxxxxxxx fmlalltt. */ - return 3423; + return 3427; } } else @@ -17891,7 +18298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1010xxxxxxxxxxxx fmlalltb. */ - return 3420; + return 3424; } else { @@ -17899,7 +18306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1011xxxxxxxxxxxx fmlalltt. */ - return 3422; + return 3426; } } else @@ -26159,7 +26566,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx10001xxxxxxxxxx fmlallbb. */ - return 3402; + return 3406; } else { @@ -26167,7 +26574,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx10001xxxxxxxxxx fmlalltb. */ - return 3404; + return 3408; } } else @@ -26178,7 +26585,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x10xxxxxx10001xxxxxxxxxx fmlallbt. */ - return 3403; + return 3407; } else { @@ -26186,7 +26593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x10xxxxxx10001xxxxxxxxxx fmlalltt. */ - return 3405; + return 3409; } } } @@ -26434,7 +26841,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x00xxxxxx11111xxxxxxxxxx fdot. */ - return 3394; + return 3398; } else { @@ -26444,7 +26851,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxx11111xxxxxxxxxx fdot. */ - return 3396; + return 3400; } else { @@ -26454,7 +26861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110110xxxxxx11111xxxxxxxxxx fmlalb. */ - return 3398; + return 3402; } else { @@ -26462,7 +26869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110110xxxxxx11111xxxxxxxxxx fmlalt. */ - return 3399; + return 3403; } } } @@ -31911,7 +32318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3395; + return 3399; } else { @@ -31941,7 +32348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3397; + return 3401; } else { @@ -31951,7 +32358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx0000x0xxxxxxxxxx fmlalb. */ - return 3400; + return 3404; } else { @@ -31959,7 +32366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx0000x0xxxxxxxxxx fmlalt. */ - return 3401; + return 3405; } } } @@ -32501,7 +32908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x010111100xxxxxx1000x0xxxxxxxxxx fmlallbb. */ - return 3406; + return 3410; } else { @@ -32509,7 +32916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x110111100xxxxxx1000x0xxxxxxxxxx fmlalltb. */ - return 3408; + return 3412; } } else @@ -32540,7 +32947,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111x1xxxxxx1000x0xxxxxxxxxx fmlallbt. */ - return 3407; + return 3411; } else { @@ -32548,7 +32955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111x1xxxxxx1000x0xxxxxxxxxx fmlalltt. */ - return 3409; + return 3413; } } } @@ -34031,16 +34438,17 @@ aarch64_extract_operand (const aarch64_operand *self, case 247: case 254: case 255: - case 262: + case 256: case 263: case 264: case 265: + case 266: return aarch64_ext_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 297: - case 299: + case 302: + case 304: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -34060,7 +34468,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 37: case 38: case 39: - case 301: + case 306: return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: @@ -34068,9 +34476,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 228: case 229: case 232: - case 266: case 267: - case 282: + case 268: case 283: case 284: case 285: @@ -34083,6 +34490,11 @@ aarch64_extract_operand (const aarch64_operand *self, case 292: case 293: case 294: + case 295: + case 296: + case 297: + case 298: + case 299: return aarch64_ext_simple_index (self, info, code, inst, errors); case 43: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -34132,13 +34544,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 208: case 209: case 210: - case 268: - case 295: - case 296: - case 298: + case 269: case 300: + case 301: + case 303: case 305: - case 306: + case 310: + case 311: return aarch64_ext_imm (self, info, code, inst, errors); case 52: case 53: @@ -34288,7 +34700,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 200: case 201: case 202: - case 281: + case 282: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); case 215: case 216: @@ -34315,7 +34727,7 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sve_index (self, info, code, inst, errors); case 242: case 244: - case 261: + case 262: return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 245: case 246: @@ -34323,48 +34735,48 @@ aarch64_extract_operand (const aarch64_operand *self, case 249: case 250: case 251: - case 260: + case 261: return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 252: case 253: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 256: - case 258: - case 269: - return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); case 257: case 259: - return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 270: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + case 258: + case 260: + return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 271: case 272: case 273: case 274: case 275: case 276: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 278: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 279: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 280: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 281: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 302: - case 303: - case 304: - return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); case 307: case 308: case 309: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); - case 310: - case 311: + return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); case 312: case 313: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 314: + return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); + case 315: + case 316: + case 317: + case 318: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 319: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 725e9c840b3c6f0d884dd38abddb812722a443c1..c714f84a64d692fc239836b3460e2c97746a41ab 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -278,6 +278,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_1b}, "an SME ZA tile ZA0-ZA1"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, @@ -308,10 +309,14 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm1_3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm1_3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm2_1}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm2_2}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10, FLD_imm1_3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm3_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"},