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Fri, 21 Jun 2024 15:50:21 +0000 Received: from smtpav02.fra02v.mail.ibm.com (smtpav02.fra02v.mail.ibm.com [10.20.54.101]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 45LFoGw256033562 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 21 Jun 2024 15:50:18 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EFA4D20043; Fri, 21 Jun 2024 15:50:15 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C21EA2004F; Fri, 21 Jun 2024 15:50:15 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 21 Jun 2024 15:50:15 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org, Richard Earnshaw , Marcus Shawcroft Cc: Jens Remus , Andreas Krebbel , Claudio Bantaloukas Subject: [PATCH 1/2] aarch64: Treat operand Rt_IN_SYS_ALIASES as register number (PR 31919) Date: Fri, 21 Jun 2024 17:50:12 +0200 Message-Id: <20240621155013.1423979-2-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240621155013.1423979-1-jremus@linux.ibm.com> References: <20240621155013.1423979-1-jremus@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: dpaJ41yzATH3HWFQeh9IPOZg1XBKWnPQ X-Proofpoint-ORIG-GUID: dpaJ41yzATH3HWFQeh9IPOZg1XBKWnPQ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-21_07,2024-06-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 phishscore=0 suspectscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 clxscore=1011 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406210112 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org The AArch64 instruction table (aarch64-tbl.h) defines the operand Rt_IN_SYS_ALIASES as register number. During assembly it is correctly encoded as register number (reg.regno) in parse_operands. During disassembly it is first correctly decoded as register number (reg.regno) in aarch64_ext_regno called by aarch64_extract_operand, but then erroneously treated as immediate value (imm.value) in aarch64_print_operand. This resolves the assembler test case "gas/aarch64/brbe-brb-inst" to erroneously fail on s390. On AArch64 - being little-endian - the struct aarch64_opnd_info union fields reg.regno and imm.value share their least-significant bits. On s390 - being big-endian - they do not. opcodes/ PR binutils/31919 * aarch64-opc.c: Treat operand Rt_IN_SYS_ALIASES as register number. Bug: https://sourceware.org/PR31919 Fixes: 72476aca8f58 ("aarch64: add Branch Record Buffer extension instructions") Signed-off-by: Jens Remus --- opcodes/aarch64-opc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ea278bfdfe5f..991b71804bf4 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3987,7 +3987,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, { /* Avoid printing an invalid additional value for Rt in SYS aliases such as BRB, provide a helpful comment instead */ - snprintf (comment, comment_size, "unpredictable encoding (Rt!=31): #%" PRIi64, opnd->imm.value); + snprintf (comment, comment_size, "unpredictable encoding (Rt!=31): #%u", opnd->reg.regno); break; } /* Omit the operand, e.g. RET. */ From patchwork Fri Jun 21 15:50:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 92683 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 34EFD3830B53 for ; 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Fri, 21 Jun 2024 15:50:15 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org, Richard Earnshaw , Marcus Shawcroft Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 2/2] aarch64: Treat operand ADDR_SIMPLE as address with base register Date: Fri, 21 Jun 2024 17:50:13 +0200 Message-Id: <20240621155013.1423979-3-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240621155013.1423979-1-jremus@linux.ibm.com> References: <20240621155013.1423979-1-jremus@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: zS1CfCosWEQeUcwBT5rJzm6mDJqTjGuq X-Proofpoint-ORIG-GUID: zS1CfCosWEQeUcwBT5rJzm6mDJqTjGuq X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-21_07,2024-06-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=946 phishscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406210112 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org The AArch64 instruction table (aarch64-tbl.h) defines the operand ADDR_SIMPLE as "address with base register (no offset)". During assembly it is correctly encoded as address with base register (addr.base_regno) in parse_operands. In warn_unpredictable_ldst it is erroneously treated as register number (reg.regno). This resolves the assembler test case "Diagnostics Quality" to erroneously fail when changing the union in struct aarch64_opnd_info from union to struct for debugging purposes. gas/ * config/tc-aarch64.c: Treat operand ADDR_SIMPLE as address with base register. Signed-off-by: Jens Remus --- Notes (jremus): I ran into two issues where union members of struct aarch64_opnd_info were erroneously used interchangeably: - https://sourceware.org/PR31561 - https://sourceware.org/PR31919 This got me the idea to change the union to struct for debugging purposes to check whether there were further instances. gas/config/tc-aarch64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 885ea65b8eb0..ed238a05c9fc 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8415,7 +8415,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) (_("unpredictable: identical transfer and status registers" " --`%s'"),str); - if (opnds[0].reg.regno == opnds[2].reg.regno) + if (opnds[0].reg.regno == opnds[2].addr.base_regno) { if (!(opcode->opcode & (1 << 21))) /* Store-Exclusive is unpredictable if Rn == Rs. */ @@ -8432,8 +8432,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) /* Store-Exclusive pair is unpredictable if Rn == Rs. */ if ((opcode->opcode & (1 << 21)) - && opnds[0].reg.regno == opnds[3].reg.regno - && opnds[3].reg.regno != REG_SP) + && opnds[0].reg.regno == opnds[3].addr.base_regno + && opnds[3].addr.base_regno != REG_SP) as_warn (_("unpredictable: identical base and status registers" " --`%s'"),str); }