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Date: Tue, 4 Jun 2024 19:09:52 +0800 Message-Id: <20240604110952.989717-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: qwCowADXb5sN9l5mEatVCQ--.20061S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtF4rtF15ArWktr4xCr48JFb_yoWxZF1rpr s5uF1v9FZ3XFn7Jrn3GFyjgF47Zwsa9r1Ykr4xuw17Aws2qrWxXFWDtw15JF48XF4UKr1S ga1agrW5Zw4UG3JanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyv14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxG rwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAF wI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbrMaUUUUUU== X-Originating-IP: [47.106.160.38] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBwkSAGZe85ULIAAAsp X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org This patch support RISC-V Zfbfmin extension with two new instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zfbfmin.d: New test. * testsuite/gas/riscv/zfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): New opcode. (MASK_FCVT_BF16_S): Ditto. (MATCH_FCVT_S_BF16): Ditto. (MASK_FCVT_S_BF16): Ditto. (DECLARE_INSN): New instructions. * opcode/riscv.h (enum riscv_insn_class): New extension. opcodes/ChangeLog: * riscv-opc.c: New instructions. --- bfd/elfxx-riscv.c | 7 +++++++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++ gas/testsuite/gas/riscv/zfbfmin.s | 4 ++++ include/opcode/riscv-opc.h | 6 ++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 5 +++++ 7 files changed, 35 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index dfacb87eda0..f203237420a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1226,6 +1226,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"d", "f", check_implicit_always}, {"zfh", "zfhmin", check_implicit_always}, {"zfhmin", "f", check_implicit_always}, + {"zfbfmin", "zfhmin", check_implicit_always}, + {"zfbfmin", "f", check_implicit_always}, {"f", "zicsr", check_implicit_always}, {"zqinx", "zdinx", check_implicit_always}, {"zdinx", "zfinx", check_implicit_always}, @@ -1362,6 +1364,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2579,6 +2582,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "q")) || (riscv_subset_supports (rps, "zhinxmin") && riscv_subset_supports (rps, "zqinx"))); + case INSN_CLASS_ZFBFMIN: + return riscv_subset_supports (rps, "zfbfmin"); case INSN_CLASS_ZFA: return riscv_subset_supports (rps, "zfa"); case INSN_CLASS_D_AND_ZFA: @@ -2827,6 +2832,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zhinxmin"; else return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); + case INSN_CLASS_ZFBFMIN: + return "zfbfmin"; case INSN_CLASS_ZFA: return "zfa"; case INSN_CLASS_D_AND_ZFA: diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index c5754837e05..ee5a3f03d90 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -28,6 +28,7 @@ All available -march extensions for RISC-V: zfa 1.0 zfh 1.0 zfhmin 1.0 + zfbfmin 1.0 zfinx 1.0 zdinx 1.0 zqinx 1.0 diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d new file mode 100644 index 00000000000..b04e6e030db --- /dev/null +++ b/gas/testsuite/gas/riscv/zfbfmin.d @@ -0,0 +1,11 @@ +#as: -march=rv64i_zfbfmin +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s new file mode 100644 index 00000000000..ddf873f611a --- /dev/null +++ b/gas/testsuite/gas/riscv/zfbfmin.s @@ -0,0 +1,4 @@ +target: + fcvt.s.bf16 fa0, fa1 + fcvt.bf16.s fa0, fa1 + fcvt.bf16.s fa0, fa1, rne diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ae14e14d427..e33b81bf4fb 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -821,8 +821,12 @@ #define MASK_FMIN_H 0xfe00707f #define MATCH_FMAX_H 0x2c001053 #define MASK_FMAX_H 0xfe00707f +#define MATCH_FCVT_BF16_S 0x44800053 +#define MASK_FCVT_BF16_S 0xfff0007f #define MATCH_FCVT_H_S 0x44000053 #define MASK_FCVT_H_S 0xfff0007f +#define MATCH_FCVT_S_BF16 0x40600053 +#define MASK_FCVT_S_BF16 0xfff0007f #define MATCH_FCVT_S_H 0x40200053 #define MASK_FCVT_S_H 0xfff0007f #define MATCH_FSQRT_H 0x5c000053 @@ -3675,6 +3679,8 @@ DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fcvt_s_bf16, MATCH_FCVT_S_BF16 MASK_FCVT_S_BF16) +DECLARE_INSN(fcvt_bf16_s, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 5f516a1026e..e10b2b890b5 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -446,6 +446,7 @@ enum riscv_insn_class INSN_CLASS_ZFHMIN_INX, INSN_CLASS_ZFHMIN_AND_D_INX, INSN_CLASS_ZFHMIN_AND_Q_INX, + INSN_CLASS_ZFBFMIN, INSN_CLASS_ZFA, INSN_CLASS_D_AND_ZFA, INSN_CLASS_Q_AND_ZFA, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1ef4eaddf4d..f73d2c7a81d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -764,6 +764,11 @@ const struct riscv_opcode riscv_opcodes[] = {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, {"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, +/* BF16 floating-point instruction subset. */ +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, + /* Half-precision floating-point instruction subset. */ {"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE }, {"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO },