From patchwork Tue May 21 09:01:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 90558 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A967D3858C32 for ; Tue, 21 May 2024 09:02:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by sourceware.org (Postfix) with ESMTPS id 2B6A73858C35 for ; Tue, 21 May 2024 09:01:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2B6A73858C35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2B6A73858C35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716282082; cv=none; b=cRJ5Lg1bUxBoYMBB6jxcJ18TicjXHsIIHbWTbfzbMrZ+x5SuGBQDiP4kLro9n/a8BA/U+dgqJorHs+j93aBPHSD75mviyUTLfJObhcPpqxzECxXj0I4G2UWih694+CR4856tRWOhVMwPcdVhGyNqpJwELNNK7Z1soul/8pDI+F0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716282082; c=relaxed/simple; bh=BUVlW6ZKcQwX0pTruukZwmzcasbeGlF4/OXgPupzJC0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=W2qfNE3iv4q0O/OuANVdl5ebYn+kgZRKXKKEIH3WXjjuVNc56GumPZYkrbWjqiLVBlXPUe/j+xeLTnx43ffREm7xEk/2x7S0AjvkntZFagz2V7OoxKO+odUIWyTBVI24mAwMAoae6dlFw+W1PCQZLfCqgtlDEhoqU1Y9h6BZO6g= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716282077; x=1747818077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BUVlW6ZKcQwX0pTruukZwmzcasbeGlF4/OXgPupzJC0=; b=Py/ko5D5UEogQYHU2pZTOC9HuBVU70cdXHvEL0VtBCVVrPQUpkIeAf9R L/AznrBVdEJSWuO3+/h1BdfYQQD6T1STh5yIUJGKe4MztN44s7U03uDQJ BbaGNGYwaj1GFP+t6Lt/KwXSGD1AgW9A1EZVyi7UdA2f4bymmiYeoQtPF MHoWVraw8mVDbE5W0u8NJDGCOEdE4C3MY5kDN9qzp+FPPDQxp2V3Tyie5 GaX5F+uZ7H8hE/y0knXj9swROAD65LoqJ9dy6qIefdK6GrvlxI27/e57h urt3P1ex6t+fzFrJ/wUciugKTH6/wplhV560uKVk8v5IHJyX4Nw597S6J w==; X-CSE-ConnectionGUID: SXQvOot1QiiqN8GU23CJbA== X-CSE-MsgGUID: VMRxTG/+SiS3FxdnwVuiew== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="23862903" X-IronPort-AV: E=Sophos;i="6.08,177,1712646000"; d="scan'208";a="23862903" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2024 02:01:15 -0700 X-CSE-ConnectionGUID: SlM6u6ElSq6Arv9Tbv6zDQ== X-CSE-MsgGUID: 3vYSIq8ESnuS2wzjq/TuWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,177,1712646000"; d="scan'208";a="32969934" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa010.fm.intel.com with ESMTP; 21 May 2024 02:01:10 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id E8FF91008F73; Tue, 21 May 2024 17:01:09 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH v3] i386: Disable ix86_expand_vecop_qihi2 when !TARGET_AVX512BW Date: Tue, 21 May 2024 17:01:09 +0800 Message-Id: <20240521090109.2436971-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Hi all, This is the v3 patch to fix PR115069. The new testcase has passed. Changes in v3: - Simplify the testcase. Changes in v2: - Add a testcase. - Change the comment for the early exit. Thx, Haochen Since vpermq is really slow, we should avoid using it for permutation when vpmovwb is not available (needs AVX512BW) for ix86_expand_vecop_qihi2 and fall back to ix86_expand_vecop_qihi. gcc/ChangeLog: PR target/115069 * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Do not enable the optimization when AVX512BW is not enabled. gcc/testsuite/ChangeLog: PR target/115069 * gcc.target/i386/pr115069.c: New. --- gcc/config/i386/i386-expand.cc | 7 +++++++ gcc/testsuite/gcc.target/i386/pr115069.c | 10 ++++++++++ 2 files changed, 17 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr115069.c diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index a6132911e6a..f7939761879 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -24323,6 +24323,13 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2) bool op2vec = GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT; bool uns_p = code != ASHIFTRT; + /* Without VPMOVWB (provided by AVX512BW ISA), the expansion uses the + generic permutation to merge the data back into the right place. This + permutation results in VPERMQ, which is slow, so better fall back to + ix86_expand_vecop_qihi. */ + if (!TARGET_AVX512BW) + return false; + if ((qimode == V16QImode && !TARGET_AVX2) || (qimode == V32QImode && (!TARGET_AVX512BW || !TARGET_EVEX512)) /* There are no V64HImode instructions. */ diff --git a/gcc/testsuite/gcc.target/i386/pr115069.c b/gcc/testsuite/gcc.target/i386/pr115069.c new file mode 100644 index 00000000000..7f1ff209f26 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr115069.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-final { scan-assembler-not "vpermq" } } */ + +typedef char v16qi __attribute__((vector_size(16))); + +v16qi foo (v16qi a, v16qi b) { + return a * b; +} +